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MOBILE PENTIUM® PROCESSOR MHz, MHz,
Available MHz, Supports Intel Architecture with Dynamic Execution Dual Independent (DIB) architecture Integrated primary 16-Kbyte instruction cache 16-Kbyte write back data Integrated second level cache (512-Kbyte) Integrated thermal diode sensor Mini-cartridge packaging technology Supports thin form factor notebook designs Exposed enables more efficient heat dissipation Intel Mobile Pentium processor introduces higher level performance today's mobile computing environment, including multimedia enhancements improved Internet communications capabilities. provides improved performance available applications running advanced operating systems such Windows 98*. built-in power management capabilities, Mobile Pentium processor takes advantage software designed Intel's MMXtechnology unleash enhanced color, smoother graphics other multimedia communications enhancements. Mobile Pentium processor contain design defects errors know errata which cause product deviate from published specifications. Current characterized errata available upon request.
Refer Mobile Pentium® Processor Performance Brief.
Fully compatible with previous Intel microprocessors Binary compatible with applications Support MMXtechnology
Power Management Features Quick Start Deep Sleep modes provide extremely power dissipation
Low-Power GTL+ processor system interface Integrated math co-processor High Reliability error detection with 64-bit system with Error Correction Code
ORDER NUMBER: 243669-002
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document sale Intel products. Except provided Intel's terms conditions sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving life sustaining applications. Intel retains right make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Contact your local sales office your distributor obtain latest specifications before placing your product order. Mobile Pentium processors contain design defects errors known errata, which cause product deviate from published specifications. Current characterized errata available upon request. Copies documents which have ordering number referenced this document, other Intel literature, obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com call 1-800-879-4683 visit Intel's site http:\\www.intel.com Copyright Intel Corporation 1998 two-wire communications bus/protocol developed Philips. SMBus subset bus/protocol developed Intel. Implementations bus/protocol SMBus bus/protocol require licenses from various entities, including Philips Electronics N.V. North American Philips Corporation. Third party brands names property their respective
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
CONTENTS
PAGE 3.1.6. INTRODUCTION 1.1. Architecture Overview. 1.2. Terminology. 1.3. References MOBILE PENTIUM PROCESSOR FEATURES. 2.1. Differences Between Mobile Pentium Processor Pentium Processor 2.2. Power Management. 2.2.1. MOBILE PENTIUM PROCESSOR CLOCK CONTROL ARCHITECTURE NORMAL STATE. AUTO HALT STATE. STOP GRANT STATE QUICK START STATE. HALT/GRANT SNOOP STATE. SLEEP STATE. DEEP SLEEP STATE. CURRENTLY SUPPORTED CLOCK STATES
PAGE SMBUS PINS UNUSED PINS.14 STATE POWER STATES.14
3.1.7. 3.1.8.
3.1.8.1. System Signals.14 3.1.8.2. Compatibility Sideband Signals.14 3.1.8.3. Other Signals.14 3.2. Decoupling Requirements.15 3.3. System Clock Processor Clocking.15 3.4. Maximum Ratings 3.5. Specifications 3.6. Specifications.19 3.6.1. SYSTEM BUS, CLOCK, APIC, COMPATIBILITY SPECIFICATIONS
2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.2.6. 2.2.7. 2.2.8. 2.2.9.
SYSTEM SIGNAL SIMULATIONS.32 4.1. System Clock (BCLK) Signal Quality Specifications.32 4.2. Power GTL+ Signal Quality Specifications.32 4.3. Non-Low Power GTL+ Signal Quality Specifications.36 4.3.1. 4.3.2. 4.3.3. OVERSHOOT/UNDERSHOOT GUIDELINES.36 RINGBACK SPECIFICATION.37 SETTLING LIMIT GUIDELINE.37
2.2.10. OPERATING SYSTEM IMPLICATIONS QUICK START SLEEP STATES 2.3. Power GTL+. 2.3.1. POWER GTL+ PINS.
2.4. Mobile Pentium Processor CPUID. MECHANICAL SPECIFICATIONS.39 ELECTRICAL SPECIFICATIONS. 3.1. Mobile Pentium Processor System Signals. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.5. POWER SEQUENCING REQUIREMENTS. VOLTAGE SENSE PINS TEST ACCESS PORT (TAP) CONNECTION. THERMAL SENSOR CATASTROPHIC THERMAL PROTECTION
5.1. Connector Mechanical Specifications 5.2. Mechanical Specification Mobile Pentium Processor 5.3. Mobile Pentium Processor Lists THERMAL SPECIFICATIONS PROCESSOR INITIALIZATION CONFIGURATION 7.1. Description.54 7.1.1. QUICK START ENABLE.54
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
7.1.2. 7.1.3.
SYSTEM FREQUENCY APIC ENABLE.54
INDEX
7.2. Clock Frequencies Ratios APPENDIX SIGNAL REFERENCE.
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
LIST FIGURES
PAGE Figure Mobile Pentium Processor Clock Control States. Figure Ramp Rate Requirement Figure BCLK Connector Core Offset. Figure Generic Clock Waveform Figure Valid Delay Timings. Figure Setup Hold Timings Figure Cold/Warm Reset Configuration Timings Figure Power-On Reset Timings Figure Test Timings (Boundary Scan). Figure Test Reset Timings Figure Quick Start/Deep Sleep Timing Figure 3.10 Stop Grant/Sleep/Deep Sleep Timing. Figure BCLK Generic Clock Waveform Processor Core. Figure BCLK Generic Clock Waveform Processor Connector Figure Low-to-High, Power GTL+ Receiver Ringback Tolerance. Figure Non-GTL+ Overshoot/Undershoot Ringback. Figure Mini-Cartridge Assembly Connector Keepout Location, View Figure Mobile Pentium Processor Crosssectional View Figure Mini-Cartridge Assembly, Cover mm). Figure Mini-Cartridge Assembly, Bottom Cover Sides mm). Figure Standoff Connector Location, View mm). Figure Cross Sectional View with Vertical Dimensions Figure PWRGOOD Relationship Power-On
PAGE
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
LIST TABLES
PAGE Table Pins Mobile Pentium Processor.5 Table Mobile Pentium Processor Clock State Characteristics Table Low-Power Clock States Supported Processor.10 Table Mobile Pentium Processor CPUID Table System Signal Groups Table Recommended Pull-Up Resistors Open Drain Signals Table Mobile Pentium Processor Absolute Maximum Ratings.16 Table Mobile Pentium Processor Power Specifications Table Power GTL+ Specifications Table Power GTL+ Signal Group Specifications Table Clock, APIC, Compatibility Signal Group Specifications.19 Table System Clock Specifications Table Valid Mobile Pentium Processor Frequencies Table 3.10 Power GTL+ Signal Groups Specifications Table 3.11 Compatibility Signal Group Specifications Table 3.12 Reset Configuration Specifications Table 3.13 APIC Signal Specifications.23 Table 3.14 Signal Specifications Processor Connector Pins Table 3.15 Quick Start/Deep Sleep Specifications25 Table 3.16 Stop Grant/Sleep/Deep Sleep Specifications Table BCLK Signal Quality Specifications Processor Core Table BCLK Signal Quality Guidelines Processor Connector Table Power GTL+ Signal Group Ringback Specification Processor Core Table Power GTL+ Signal Group Ringback Guideline Processor Connector.36 Table Signal Ringback Specifications NonGTL+ Signals Processor Core Table Signal Ringback Guidelines Non-GTL+ Signals Processor Connector.38
PAGE Table Mobile Pentium Processor Mechanical Specifications Table Mobile Pentium Processor Vertical Dimensions Table Mobile Pentium Processor Dimension Definitions Table Mobile Pentium Processor Pinout Table Mobile Pentium Processor Listing. Table Mobile Pentium Processor Listing (Continued). Table Mobile Pentium Processor Listing (Continued). Table Mobile Pentium Processor Listing (Continued). Table Mobile Pentium Processor Power Specifications Table Voltage Identification Definition Table Input Signals Table Output Signals Table Input/Output Signals (Single Driver). Table Input/Output Signals (Multiple Driver)
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
INTRODUCTION
Mobile Pentium processor first implementation Pentium Processor family that optimized mobile platform. will initially offered three speeds: MHz, MHz, MHz, with system speed MHz. consists Mobile Pentium processor core with integrated cache controller 64-bit high performance system bus. Mobile Pentium processor private cache that allows high performance 64-bit wide cache subsystem gluelessly implemented using TagRAM PBSRAM (Pipeline Burst SRAM) devices. Mobile
Pentium processor able cache first Mbytes memory using 512-Kbyte cache data array composed PBSRAMs. private cache complements system providing critical data faster, improving performance, reducing total system power consumption. Mobile Pentium processor's 64-bit wide Power GTL+ (Gunning Transceiver Logic) system compatible with 440BX AGPset provides glueless, point-to-point interface bridge/memory controller. Figure shows various parts Mobile Pentium processor-based system Mobile Pentium processor connects them.
Thermal Sensor
TagRAM APIC Mobile Pentium Processor Core PBSRAMs
System
Mobile Pentium® Processor
SMBus
443BX North Bridge Compatibility
DRAM
System Controller IOAPIC (optional) ISA/EIO
PIIX4E South Bridge
Figure Signal Groups Mobile Pentium® Processor-based System
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
1.1.
Architecture Overview
Architectural enhancements improve performance Supports Intel Architecture with Dynamic Execution Supports Intel Architecture technology Integrated Intel Floating-Point Unit compatible with IEEE
Integrated primary (L1) instruction data caches 4-way associative, 32-byte line size, line sector 16-Kbyte instruction cache 16-Kbyte writeback data cache Cacheable range programmable processor programmable registers Dedicated 64-bit wide high speed data transfers 512-Kbyte, protected cache data array Uses Intel designed TagRAM Clock PBSRAMs turns when processor power states 64-bit data bus, 66-MHz operation Uni-processor, loads only (processor bridge/memory controller) Short trace length capacitance allows single ended termination
when signal asserted (based name signal) electrical state. Otherwise, signals driven electrical high state when they asserted. state machine diagrams, signal name condition indicates condition that signal being asserted. signal name preceded symbol, then indicates condition that signal being asserted. example, condition `!STPCLK# equivalent `the active signal STPCLK# unasserted (i.e., 2.5V) condition true.' symbols refer respectively electrical electrical high signal levels. symbols refer respectively logical logical high signal levels. example, BD[3:0] `1010' `HLHL' refers hexadecimal `A', D[3:0]# `1010' `LHLH' also refers hexadecimal `A'.
1.3.
References
Integrated second level (L2) cache
Pentium Processor MHz, MHz, (Order Number 243335) Pentium Processor Developer's Manual (Order Number 243341) CKDM66-M Clock Driver Specification (Contact your Intel Field Sales Representative) Intel Architecture Software Developer's Manual (Order Number 243193) Volume Basic Architecture (Order Number 243190-001) Volume Instruction Reference (Order Number 243191-001) Volume III: System Programming Guide (Order Number 243192-001 Mobile Pentium Processor Buffer Models, IBIS Format (Available electronic format; contact your Intel Field Sales Representative) Mobile Pentium Processor System Layout Guideline (Order Number 243672-001) Mobile Pentium Processor Mini-cartridge Processor Mechanical Thermal User's Guide (Order Number 243671-001)
Power GTL+ system interface
Voltage reduction technology Pentium processor family clock control Quick Start power, exit latency clock "throttling" Deep Sleep mode extremely power dissipation
Accurate processor temperature sensor
1.2.
Terminology
this document symbol following signal name indicates that signal active low. This means that
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
System Management Specification, Revision (Available World Wide Web; contact your Intel Field Sales Representative) Mobile Pentium Processor Pentium Processor Mobile Module Thermal Power Consumption (Order Number 243670-001) Mobile Pentium Processor/440BX AGPset Datasheet (Order Number 290633-001) Mobile Pentium Processor Pentium Processor Mobile Module Thermal Sensor Programming Interface Specification (Contact your Intel Field Sales Representative)
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
MOBILE PENTIUM® PROCESSOR FEATURES Differences Between Mobile Pentium® Processor Pentium Processor
Thermal Sensor
2.1.
Fault Tolerance (FRC)
Pentium processor supports master/checker processor configuration high integrity, fault tolerant operation. This mode supported Mobile Pentium processor there FRCERR pin. Local APIC
Mobile Pentium processor core thermal diode with impedance connection anode cathode package pins. Mobile Pentium processor there thermal sensor attached diode that communicates processor core temperature system logic through system management (SMBus) interface. Having thermal sensor integrated onto processor core allows better thermal management Mobile Pentium processor system. THERM-TRIP# Mobile Pentium processor does have THERMTRIP# pin. Cache Clock Stopping
Pentium processor requires that PICCLK driven with valid APIC clock signal even when APIC used. APIC clock signal required Mobile Pentium processor PICD0 strapped ground reset. Voltage Reduction Technology
Pentium processor uses single voltage core cache buffers while Mobile Pentium processor permits core voltage lower than voltage. This allows processor achieve much lower power consumption while maintaining 1.8V interface. Both processors have 2.5V tolerant buffers non-GTL+ system logic signals (clocks, APIC, compatibility). Power GTL+
Pentium processor turns clocks cache cache only when Deep Sleep state leaves them running other times. Mobile Pentium processor core turns clocks PBSRAMs when Quick Start Sleep states. TagRAM clock left running except Deep Sleep state. Quick Start
Pentium processor GTL+ uses termination both ends limits stub lengths allow three loads long GTL+ bus. Mobile Pentium processor supports Power GTL+ with short, point-topoint, load with possibility socketed CPU. recommended termination under Power GTL+ single-ended termination resistors. Uniprocessor
Mobile Pentium processor clock control state that similar Stop Grant state consumes less power. Stop Grant state supports snooping transactions generated priority device (usually bridge) symmetric processors. Quick Start state only snoops priority device transactions, thus only usable uniprocessor systems. Stop Grant state supports recognition changes input signals latching edgetriggered interrupts (e.g., NMI, SMI#). Quick Start state input signal transitions allowed (see Section 2.2.5).
Pentium processor supports 2-way multiprocessing Mobile Pentium processor only used uniprocessor systems.
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
Clock Ratio Selection Pentium processor clock ratio programmed into processor reset time LINT[1:0], IGNNE# A20M# pins according encoding scheme Pentium Processor Developer's Manual. This requires logic system board multiplex clock ratio code onto these pins during reset. Mobile Pentium processor clock ratio preprogrammed during manufacturing. LINT[1:0], IGNNE# A20M# pins ignored Reset Mobile Pentium processor.
msec, exit latency Deep Sleep state been reduced µsec Mobile Pentium processor. Stop Grant Sleep states shown Figure intended "Deep Green" desktop server systems mobile systems. Performing state transitions shown Figure neither recommended supported. clock control architecture consists seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant Snoop, Sleep Deep Sleep states. Stop Grant Quick Start clock states mutually exclusive, i.e., strapping option A15# chooses which state entered when STPCLK# signal asserted. Quick Start state enabled strapping A15# ground Reset; otherwise, asserting STPCLK# signal puts processor into Stop Grant state. Stop Grant state higher power level than Quick Start state designed platforms. Quick Start state much lower power level, only used uniprocessor platforms. Table provides clock state characteristics (power numbers based estimates Mobile Pentium processor running MHz), which described detail following sections. 2.2.2. NORMAL STATE
2.2.
2.2.1.
Power Management
MOBILE PENTIUM PROCESSOR CLOCK CONTROL ARCHITECTURE
Mobile Pentium processor clock control architecture (Figure 2.1) been optimized leading edge deep green desktop mobile computer designs. Auto Halt state provides power clock state that controlled through software execution instruction. Quick Start state provides very power, exit latency clock state that used hardware controlled "idle" computer states. Deep Sleep state provides extremely power state that used "Power-on Suspend" computer states, which alternative shutting processor's power. Compared Pentium processor exit latency
Normal state processor normal operating mode where processor's internal clock running processor actively executing instructions.
Table Pins Mobile Pentium Processor Name SMBALERT# SMBCLK SMBDATA Type Thermal sensor attention signal. SMBus clock signal. Refer System Management Specification descriptions specifications three SMBus signals. SMBus data signal. Refer System Management Specification descriptions specifications three SMBus signals. Description
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
Normal State
HS=false
STPCLK# stop grant cycle (!STPCLK# !HS) RESET# halt cycle halt break STPCLK# stop grant cycle !STPCLK#
Quick Start
BCLK stopped BCLK
STPCLK# !QSS stop grant cycle (!STPCLK# !HS) stop break !STPCLK#
Auto Halt
HS=true
Snoop serviced
Snoop occurs
Deep Sleep
Snoop occurs Snoop serviced
STPCLK# !QSS stop grant cycle Snoop occurs Snoop serviced SLP# !SLP# RESET#
Stop Grant
HALT/Grant Snoop
BCLK stopped
BCLK !QSS
Sleep
halt break BINIT#, FLUSH#, SMI#, NMI, INTR, INIT#, RESET#, A20M# stop break BINIT#, FLUSH#, RESET# Quick Start Strapping option Processor Halt State instruction executed
Figure Mobile Pentium Processor Clock Control States
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
Table Mobile Pentium Processor Clock State Characteristics Clock State Normal Auto Halt Stop Grant Quick Start Approximately clocks clocks Exit Latency Power Varies Snooping? System Uses Normal program execution controlled entry idle mode controlled entry/exit mobile throttling controlled entry/exit mobile throttling
Through snoop, HALT/Grant Snoop state: immediate Through STPCLK#, Normal state: clocks
HALT/ Grant Snoop Sleep
clocks after snoop activity. Stop Grant state clocks
specified
Supports snooping power states controlled entry/exit desktop idle mode support controlled entry/exit Mobile powered-on suspend support
Deep Sleep
µsec
NOTE:
100% tested. Specified design/characterization. STPCLK#, system logic return processor Auto Halt state without issuing Halt cycle. SMI# interrupt recognized Auto Halt state. return from System Management Interrupt (SMI) handler either Normal state Auto Halt state. Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide more information. Halt cycle issued when returning Auto Halt state from SMM.
2.2.3.
AUTO HALT STATE
This power mode entered processor through execution instruction. power level this mode similar Stop Grant state. transition Normal state made halt break event (one following signals going active: NMI, INTR, BINIT#, INIT#, RESET#, FLUSH# SMI#). Asserting STPCLK# signal while Auto Halt state will cause processor transition Stop Grant Quick Start state, where Stop Grant Acknowledge cycle will issued. deasserting
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
FLUSH# signal serviced Auto Halt state. After on-chip off-chip caches have been flushed, processor will return Auto Halt state without issuing Halt cycle. Transitions A20M# recognized while Auto Halt state. 2.2.4. STOP GRANT STATE
snooping behavior, Quick Start only used Uniprocessor (UP) configuration. transition Deep Sleep state (see Section 2.2.8) made stopping clock input processor. transition back Normal state (from Quick Start state) made only STPCLK# signal deasserted. While this state processor limited ability respond input. incapable latching interrupt, servicing snoop transactions from symmetric masters responding FLUSH# BINIT# assertions. While processor Quick Start state, will respond properly input signal other than STPCLK#, RESET# BPRI#. other input signal changes, then behavior processor will unpredictable. serial interrupt messages begin progress while processor Quick Start state. thermal sensor will respond normally SMBus transactions when processor Quick Start state. RESET# assertion will cause processor immediately initialize itself, processor will stay Quick Start state after initialization until STPCLK# deasserted. Asserting SLP# signal when processor configured Quick Start will result unpredictable behavior recommended. 2.2.6. HALT/GRANT SNOOP STATE
processor enters this mode with assertion STPCLK# signal when configured Stop Grant state (via A15# strapping option). processor still able respond snoop requests latch interrupts. Latched interrupts will serviced when processor returns Normal state. Only occurrence each interrupt event will latched. transition back Normal state made de-assertion STPCLK# signal, occurrence stop break event BINIT#, FLUSH# RESET# assertion). While Stop Grant state, SMI#, INIT# LINT[1:0] will latched processor, only serviced when processor returns normal state. Only occurrence each event will recognized upon return normal state. processor will return Stop Grant state after completion BINIT# initialization unless STPCLK# been de-asserted. RESET# assertion will cause processor immediately initialize itself, processor will stay Stop Grant state after initialization until STPCLK# deasserted. FLUSH# signal asserted, processor will flush on-chip off-chip caches return Stop Grant state. transition Sleep state made assertion SLP# signal (see Section 2.2.7 description). 2.2.5. QUICK START STATE
This mode entered processor with assertion STPCLK# signal when configured Quick Start state (via A15# strapping option). Quick Start state processor only capable acting snoop transactions generated system priority device. Because
Mobile Pentium processor will respond snoop transactions system while Auto Halt, Stop Grant Quick Start state. When snoop transaction presented system processor will enter HALT/Grant Snoop state. processor will remain this state until snoop system been serviced system quiet. After snoop been serviced, processor will return previous Auto Halt, Stop Grant Quick Start state. HALT/Grant Snoop state entered from Quick Start state, then input signal restrictions Quick Start state still apply HALT/Grant Snoop state, except those signal transitions that required perform snoop.
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
2.2.7.
SLEEP STATE
Sleep state very power state which processor maintains context phase-locked loop (PLL) maintains phase lock. Sleep state only entered from Stop Grant state. After entering Stop Grant state, SLP# signal asserted, causing processor enter Sleep state. SLP# recognized Normal Auto Halt states. processor reset RESET# while Sleep state. RESET# driven active while processor Sleep state then SLP# STPCLK# must immediately driven inactive ensure that processor correctly executes Reset sequence. Input signals (other than RESET#) change while processor Sleep state transitioning into Sleep state. Input signal changes these times will cause unpredictable behavior. Thus, processor incapable snooping latching events Sleep state. thermal sensor will respond normally SMBus transactions when processor Sleep state. While Sleep state, processor capable entering lowest power state, Deep Sleep state, removing processor's input clock. PICCLK removed Sleep state. 2.2.8. DEEP SLEEP STATE
input signal restrictions Deep Sleep state same Sleep state, except that RESET# assertion will result unpredictable behavior. thermal sensor will respond normally SMBus transactions when processor Deep Sleep state. 2.2.9. CURRENTLY SUPPORTED CLOCK STATES Table shows low-power clock states supported Pentium processor family product line. 2.2.10. OPERATING SYSTEM IMPLICATIONS QUICK START SLEEP STATES There number architectural features Mobile Pentium processor that available when Quick Start state enabled function Quick Start Sleep state they Stop Grant state. These features part APIC, time-stamp counter performance monitor counters. local APIC timer does behave properly when processor Quick Start Sleep state. There guarantee that local APIC timer will count down Quick Start Sleep state. timer counts down zero when processor about enter Quick Start Sleep state, processor's behavior will unpredictable. InterProcessor Interrupts (IPIs)
Deep Sleep state lowest power mode processor enter while maintaining context. Deep Sleep state entered stopping BCLK input processor, while Sleep Quick Start state. proper operation, BCLK input should stopped state. re-enter either Sleep Quick Start state from Deep Sleep state, BCLK input must restarted. processor will return Sleep Quick Start state, appropriate, after msec. PICCLK removed Deep Sleep state. PICCLK should designed turn when BCLK turns when transitioning Deep Sleep state.
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
Table Low-Power Clock States Supported Processor Processor Stop Grant Pentium Processor Pentium Processor Mobile Pentium Processor
Auto Halt
Clock State Quick Start
Sleep
Deep Sleep
should used Mobile Pentium processor systems. software generates just before processor enters Quick Start Sleep state, then message APIC will generated. This violates requirement stated Section 2.2.5 that input signals toggle Quick Start Sleep state. software-generated Mobile Pentium processor system (uniprocessor system) will always result error. time-stamp counter performance monitor counters guaranteed count Quick Start Sleep states. software sets APIC interrupt enable either performance counters, then resulting behavior will unpredictable.
based capacitive derating. Analog signal simulation system including trace lengths highly recommended ensure that there significant transmission line effects. Contact your field sales representative receive IBIS models Mobile Pentium processor. GTL+ system Pentium processor designed support high speed data transfers with multiple loads long that behaves like transmission line. However, mobile system, system only loads (the processor chipset) traces short enough that transmission line effects significant. possible change layout termination system take advantage mobile environment using same GTL+ buffers. benefit that reduces number terminating resistors half substantially reduces power dissipation system bus. Power GTL+ uses GTL+ buffers, although only loads allowed. trace length limited terminated only. Since system small lightly loaded, behaves like capacitor, GTL+ buffers behave like high speed open-drain buffers. With 66-MHz frequency, pull-up would 120. been increased from 1.5V processor core eliminate need 1.5V power plane. termination resistors used rather than 120, then percent more power will dissipated termination resistors. termination recommended conserve power. Refer Mobile Pentium Processor System Layout Guideline details laying Power GTL+ system bus.
2.3.
Power GTL+
Mobile Pentium processor system signals variation low-voltage (Gunning Transceiver Logic) signaling technology. Mobile Pentium processor system specification similar Pentium processor system specification, which itself version with enhanced noise margins less ringing. Mobile Pentium processor system specification reduces system cost power consumption raising termination voltage termination resistance changing termination from dual ended single ended. Because specification different from standard specification from Pentium processor GTL+ specification, referred Power GTL+. Pentium processor GTL+ system depends incident wave switching uses flight time timing calculations GTL+ signals. Power GTL+ system short lightly loaded. With Power GTL+ signals, timing calculations
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
2.3.1.
POWER GTL+ PINS
simulations show that signal quality specifications Section met.
signals system will potentially meet Power GTL+ layout requirements: PRDY# RESET#. These signals connect debug port described Section thus cannot meet maximum length requirements. Also, RESET# potentially used generate reset configuration selection signal. PRDY# RESET# meet layout requirements Power GTL+, then they must terminated using dual-ended termination 120. Higher resistor values used
2.4.
Mobile Pentium® Processor CPUID
CPUID instruction does distinguish between Mobile Pentium Pentium processors. After power-on RESET, when CPUID instruction executed, register contains values shown Table 2.4.
Table Mobile Pentium Processor CPUID Reserved [31:14] Type [13:12] Family [11:8] Model [7:4] Stepping [3:0]
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
3.1.
ELECTRICAL SPECIFICATIONS Mobile Pentium Processor System Signals
TRST#. Compatibility signals (CMOS inputs) applied asynchronously. CMOS, Clock, APIC inputs driven from ground 2.5V. FERR#, IERR#, APIC outputs open drain should pulled 2.5V using resistors with values shown Table 3.2. open drain drivers used input signals, then they should also pulled 2.5V using resistors with values shown Table 3.2.
Table lists Mobile Pentium processor system signals type. Power GTL+ signals synchronous with BCLK signal. signals synchronous with signal except
Table System Signal Groups Group Name Power GTL+ Input Power GTL+ Output Power GTL+ Signals BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# PRDY# A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD, SLP#, SMI#, STPCLK#
CMOS Input
Open Drain Output Thermal Sensor Clock
FERR#, IERR# SMBALERT#, SMBCLK, SMBDATA BCLK PICCLK PICD[1:0]
APIC Clock APIC
Input
TCK, TDI, TMS, TRST#
Output
VCC, VCC_S, VCCP, VCCP_S, VCC3, VID[3:0], VSS, VSS_S
Power/Other NOTES:
Section Appendix information PWRGOOD signal. These signals tolerant 2.5V only. power supply Mobile Pentium processor core. VCCP power supply Cache voltage. VCC3 power supply PBSRAM cores. system ground. VCC_S, VCCP_S VSS_S voltage sense pins VCC, VCCP VSS, respectively.
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
Table Recommended Pull-Up Resistors Open Drain Signals Recommended Resistor Value 4.7K NOTES: TRST# should pulled ground with resistor. PICD[1:0], TDI, STPCLK# INIT#, TCK, Open Drain Signal
A20M#, FERR#, FLUSH#, IERR#, IGNNE#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD, SLP#, SMI#
Refer Section 3.1.7 required pull-up pull-down resistors signals that being used. 3.1.1. POWER SEQUENCING REQUIREMENTS Mobile Pentium processor power sequencing requirements. recommended that processor power planes rise their specified values within second each other. power plane must rise fast. least µsec (TR) must pass from time that nominal value until time that nominal value (see Figure
processor installed. these pins used voltage sense processor presence sense, then they should connected VCC, VCCP VSS, respectively. 3.1.3. TEST ACCESS PORT (TAP) CONNECTION interface implementation IEEE 1149.1 ("JTAG") standard. voltage levels supported interface, recommended that Mobile Pentium processor other 2.5V JTAG specification compliant devices last JTAG chain after devices with 3.3V JTAG interfaces within system. translation buffer should used reduce output voltage last 3.3/5V device down 2.5V range that Mobile Pentium processor tolerate. Multiple copies TRST# must provided, each voltage level. Debug Port connector been defined Section placed start JTAG chain containing processor, with first component coming from Debug Port from last component going Debug Port. There requirements placement Mobile Pentium processor JTAG chain, except those dictated voltage requirements signals.
(nominal) Volts (nominal) Time
Figure Ramp Rate Requirement 3.1.2. VOLTAGE SENSE PINS
Mobile Pentium processor three voltage sense pins allow VCCP power regulators sense VCCP voltage levels processor after voltage drop connector. These pins VCC_S, VCCP_S VSS_S. VSS_S also used generate system shutdown signal system turned with
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
3.1.4.
THERMAL SENSOR
then they should connected with resistor. local APIC hardware disabled, then PICCLK PICD[1:0] should tied with resistor. Otherwise PICCLK must driven with clock that meets specification (see Table 3.13) PICD[1:0] pins must pulled 2.5V with resistors, even local APIC used. 3.1.8. 3.1.8.1. STATE POWER STATES System Signals
Within Mobile Pentium processor, there thermal sensor connected SMBus pins. programming interface thermal sensor described Mobile Pentium Processor Pentium Processor Mobile Module Thermal Sensor Programming Interface Specification. Mobile Pentium processor thermal sensor supports ACPI-compliant system implementation monitoring temperature processor. thermal sensor only provides accurate reading processor temperature when processor fully powered. address thermal sensor processor SMBus 1001101. 3.1.5. CATASTROPHIC THERMAL PROTECTION Mobile Pentium processor does support catastrophic thermal protection. thermal sensor must used protect processor system against excessive temperatures. 3.1.6. SMBUS PINS
system pins have Power GTL+ input, output input/output drivers. Except when servicing snoops, system pins tri-stated pulled termination resistors. Snoops permitted Sleep Deep Sleep states. 3.1.8.2. Compatibility Sideband Signals
SMBus subset bus/protocol developed Intel. two-wire communications bus/protocol developed Philips*. Contact your Intel Field Sales Representative copy System Management specification. 3.1.7. UNUSED PINS
compatibility input pins allowed either logic high state when processor power state. Auto Halt Stop Grant states these signals allowed toggle. These input buffers have internal pull-up pull-down resistors system logic CMOS open-drain drivers drive them. compatibility output pins have open drain drivers external pull-up resistors required. output pins (IERR#) catastrophic error indicator tri-stated (and pulled-up) when processor functioning normally. FERR# output either tri-stated driven when processor power state depending condition floating point unit. Since this current path when driven VSS, recommended that software clear mask floating point error condition before putting processor into Deep Sleep state. 3.1.8.3. Other Signals
RESERVED pins must unconnected. Unused Power GTL+ inputs, outputs bi-directional signals should individually connected with pull-up resistors. Unused CMOS active inputs should connected 2.5V unused active high inputs should connected VSS. Unused open-drain outputs should unconnected. processor configured enter Quick Start state rather than Stop Grant state, then SLP# should connected 2.5V. When tying signal power ground, resistor will allow system testability. unused pins, suggested that resistors used pull-ups resistors used pull-downs. VID[3:0] pins used
system clock (BCLK) must driven power states except Deep Sleep state. APIC clock (PICCLK) must driven whenever BCLK
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
driven unless APIC hardware disabled processor Sleep State. Otherwise, permitted turn PICCLK holding VSS. system clock should held when stopped Deep Sleep state. Auto Halt Stop Grant states APIC data pins (PICD[1:0]) toggle APIC messages. These pins required tri-stated pulled-up when processor Quick Start, Sleep Deep Sleep states unless APIC hardware disabled. state SMBus pins determined policy embodied SMBus host controller. thermal sensor accessed processor states long power applied processor.
rising edge BCLK input. Mobile Pentium processor core frequency multiple BCLK frequency. ratio between core frequency BCLK frequency configured when processor manufactured. Multiplying clock frequency necessary increase performance while allowing easier distribution signals within system. Clock multiplication within processor provided internal Phase Lock Loop (PLL), which requires constant frequency BCLK input. During Reset, exit from Deep Sleep state, requires some amount time acquire phase BCLK. This time called lock latency, which specified Section 3.6.
3.4. 3.2. Decoupling Requirements
Maximum Ratings
Mobile Pentium processor high frequency decoupling capacitors three power planes, additional bulk decoupling capacitance required. amount bulk decoupling required meet processor voltage tolerance requirement strong function power supply design. Contact your Intel Field Sales Representative tools help determine much decoupling required. cache power plane (VCCP) requires decoupling. cache Mobile Pentium processor requires decoupling 3.3V power plane (VCC3) addition decoupling required other 3.3V system components. Power GTL+ pull-up resistors, 0.1µF high frequency decoupling capacitor recommended resistor pack. There should more than eight pull-up resistors resistor pack.
Table contains Mobile Pentium processor stress ratings. Functional operation absolute maximum minimum neither implied guaranteed. processor should receive clock while subjected these conditions. Functional operating conditions provided tables. Extended exposure maximum ratings affect device reliability. Furthermore, although processor contains protective circuitry resist damage from static electric discharge, should always take precautions avoid high static voltages electric fields.
3.5.
Specifications
3.3.
System Clock Processor Clocking
Table through Table list specifications Mobile Pentium processor. Specifications valid only while meeting specifications case temperature, clock frequency input voltages. Care should taken read notes associated with each parameter.
2.5V BCLK input directly controls operating speed system interface. system timing parameters specified with respect
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
Table Mobile Pentium Processor Absolute Maximum Ratings Symbol TStorage VCC(Abs) Parameter Storage Temperature Supply Voltage with respect -0.5 voltage Unit Notes
VCCP VCC3 VIN25 VSMB IVID IVSS_S NOTES:
cache voltage PBSRAM core voltage Power GTL+ Buffer Input Voltage with respect 2.5V Buffer Input Voltage with respect SMBus Buffer Input Voltage with respect current sense current
-0.3 -0.3 -0.3 -0.3 -0.3
Parameter applies Power GTL+ signal groups only. Parameter applies Compatibility, APIC signal groups only. Parameter applies SMBCLK, SMBDATA SMBALERT# signals. When used processor presence detect signal.
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Table Mobile Pentium Processor Power Specifications Symbol core frequency when cache buffers PBSRAM cores core frequency Parameter 1.48 1.48 1.48 1.48 1.48 1.48 1.71 3.135 1.72 1.72 1.72 1.79 1.79 1.79 1.89 3.465 7.91 7.03 6.15 0.75
TPROC (processor core temperature) 1.6V ±120mV, VCCP 1.8V ±90mV, VCC3 3.3V ±165mV Unit Notes ±120
VCC,LP
-120 +190
VCCP VCC3
1.8V 3.3V
ICCP ICC3 ICC,DSLP ICCP,DSLP ICC3,DSLP dICC/dt dICC3/dt NOTES:
VCCP cache buffers) VCC3 (Tag PBSRAM cores) Processor core Deep Sleep leakage current Processor cache Deep Sleep leakage current Processor cache core thermal sensor Deep Sleep leakage current Core power supply current slew rate core power supply current slew rate
A/µs A/µs
VCC, 95°C core temperature VCCP, 115°C core temperature VCC3, 115°C core temperature
Unless otherwise noted, specifications this table apply processor frequencies. higher VCC,MAX allowed when processor power state enable high efficiency, current modes power regulator. ICCx,max specifications specified VCC,max, VCCP,max VCC3,max TCASE,max under maximum signal loading conditions. ICCx,max specifications specified VCC,LP,max. that voltage specification used then slightly higher current expected. ICCP current supply Mobile Pentium processor cache buffers buffers TagRAM PBSRAMs. ICC3 current supply PBSRAM cores. These currents specified processor with cache. 100% tested. Specified design/characterization. ICCx,DSLP specifications specified maximum voltages temperatures under maximum signal loading conditions. Based simulations averaged over duration change current. Used compute maximum inductance reaction time voltage regulator. This parameter tested. Maximum values specified design/characterization nominal VCC3.
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signals Mobile Pentium processor system included Power GTL+ signal group. These signals specified terminated VCC. termination reference voltage specifications these signals listed Table 3.5. Mobile Pentium processor requires external termination generates VREF; information Table provided system design.
specifications Power GTL+ signals listed Table 3.6. Refer Mobile Pentium Processor System Layout Guideline full details system VREF requirements. Clock, Compatibility pins designed interface 2.5V CMOS levels allow connection other devices. specifications these 2.5V tolerant pins listed Table 3.7.
Table Power GTL+ Specifications TPROC 1.6V ±120mV, VCCP 1.8V ±90mV, VCC3 3.3V ±165mV Symbol VREF NOTES: intent same power supply VTT. VREF system logic should created from voltage divider. Table Power GTL+ Signal Group Specifications TPROC 1.6V ±120mV, VCCP 1.8V ±90mV, VCC3 3.3V ±165mV Symbol NOTES: VREF worst case, nominal. Noise VREF should accounted for. VCC). VOUT VCC). Parameter Input Voltage Input High Voltage Output High Voltage Output Drive Strength Leakage Current Output Leakage Current
Parameter Termination Voltage Input Reference Voltage
VCC,MIN /9VTT
VCC,MAX
Units
Notes
/9VTT
/9VTT
-0.3 /9VTT
/9VTT
Unit
Notes Table
Table
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Table Clock, APIC, Compatibility Signal Group Specifications TPROC 1.6V ±120mV, VCCP 1.8V ±90mV, VCC3 3.3V ±165mV Symbol VIL,BCLK VIH,BCLK Parameter Input Voltage Input Voltage, BCLK connector Input High Voltage Input High Voltage, BCLK connector Output Voltage Output High Voltage -0.3 -0.3 2.625 2.625 2.625 Unit
Notes
outputs opendrain
NOTES:
Output Current Input Leakage Current
BCLK connector 0.6V. timing specification that relative BCLK connector uses this voltage specification. Parameter measured 2.625V). frequencies cache frequencies; Table 3.10 contains Power GTL+ specifications; Table 3.11 contains Compatibility signal group specifications; Table 3.12 contains timings reset conditions; Table 3.13 contains APIC specifications; Table 3.14 contains specifications; Tables 3.15 3.16 contain power management timing specifications. system specifications Power GTL+ signal group relative rising edge BCLK input VIL,BCLK. Power GTL+ timings referenced VREF both logic levels unless otherwise specified.
3.6.
3.6.1.
Specifications
SYSTEM BUS, CLOCK, APIC, COMPATIBILITY SPECIFICATIONS
system timings specified this section defined Mobile Pentium processor connector. Table through Table 3.16 provide Mobile Pentium processor specifications. specifications divided into following categories: Tables contains system clock specifications; Table contains processor core
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Table System Clock Specifications Symbol Parameter System Frequency NOTES: BCLK Period BCLK offset from connector processor core BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time 4.84 0.52 0.52 1.43 1.43 0.45 66.67 0.70 Unit
TPROC 1.6V ±120mV, VCCP 1.8V ±90mV, VCC3 3.3V ±165mV Figure Notes
@>1.8V @<0.6V (0.6V 1.8V) (1.8V 0.6V)
timings Power GTL+ CMOS signals referenced BCLK rising edge VIL,BCLK processor connector pins. This reference account trace length capacitance processor substrate, allowing processor core receive signal with reference 1.25V. Power GTL+ signals referenced VREF processor connector pins. CMOS signals referenced 1.25V processor connector pins. BCLK period allows +0.5 tolerance clock driver variation. BCLK offset time absolute difference needed between BCLK signal arriving connector 0.6V arriving processor core 1.25V. positive offset needed account delay between connector processor core. positive offset ensures that both processor core system logic receive BCLK edge concurrently. 100% tested. Specified design/characterization. Measured rising edge adjacent BCLKs 1.25V. jitter present must accounted component BCLK skew between devices. Table Valid Mobile Pentium Processor Frequencies TPROC 1.6V ±120mV, VCCP 1.8V ±90mV, VCC3 3.3V ±165mV BCLK Frequency (MHz) 66.67 66.67 66.67 Frequency Multiplier Core Frequency (MHz) 233.33 266.67 300.00 Second Level Cache (MHz) 116.67 133.33 150.00
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Table 3.10 Power GTL+ Signal Groups Specifications TPROC 1.6V ±120mV, VCCP 1.8V ±90mV, VCC3 3.3V ±165mV terminated VCC, VREF VCC, load Symbol Parameter system board signal trace length NOTES: Power GTL+ Output Valid Delay Power GTL+ Input Setup Time Power GTL+ Input Hold Time RESET# Pulse Width 2.54 10.67 Unit
Figure
Notes guideline
timings Power GTL+ signals referenced BCLK rising edge VIL,BCLK processor connector pins. Power GTL+ signals referenced VREF processor connector pins. 100% tested. Specified design characterization. Equivalent specifications tested processor core. RESET# asserted (active) asynchronously, must de-asserted synchronously. Specification minimum 0.40V swing. Specification maximum 1.0V swing. After VCC, VCCp, VCC3 BCLK become stable, PWRGOOD must asserted. Table 3.11 Compatibility Signal Group Specifications TPROC 1.6V ±120mV, VCCP 1.8V ±90mV, VCC3 3.3V ±165mV Symbol T14B NOTES: timings Compatibility signals referenced BCLK rising edge VIL,BCLK processor connector pins. CMOS signals referenced 1.25V processor connector pins. 100% tested. Specified design characterization. Equivalent specifications tested processor core. Valid delay timings these signals specified into 2.5V Valid delay timings these signals specified 2.5V Table pull-up resistor values. Parameter 2.5V Output Valid Delay 2.5V Input Setup Time 2.5V Input Hold Time 2.5V Input Pulse Width, except PWRGOOD LINT[1:0] LINT[1:0] Input Pulse Width PWRGOOD Inactive Pulse Width 10.4 Unit BCLKs BCLKs BCLKs Figure
Notes
Active Inactive states
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These inputs driven asynchronously. However, guarantee recognition specific clock, setup hold times with respect BCLK must met. A20M#, IGNNE#, INIT# FLUSH# asynchronous inputs, guarantee recognition these signals following write instruction, they must valid with TRDY# assertion corresponding transaction. INTR function Compatibility signals only when APIC disabled; otherwise, they function LINT[1:0] signals. Compatibility signal specifications apply either case. instruction restart feature Mobile Pentium processor, SMI# signal must meet these setup hold specifications clock edge system clocks before RS[2:0]# assertion transaction instruction. This specification only applies when APIC enabled LINT1 LINT0 configured edge-triggered interrupt with fixed delivery; otherwise specification applies. When driven inactive, after VCC, VCCP, VCC3 BCLK become stable. PWRGOOD must remain below VIL,max from Table until voltage planes meet voltage tolerance specifications Table BCLK BCLK specifications Table least clock cycles. PWRGOOD must rise glitch-free monotonically 2.5V. BCLK signal meets specification within turning then PWRGOOD Inactive Pulse Width specification (T15) waived BCLK start after PWRGOOD asserted. PWRGOOD must still remain below VIL,max until voltage planes meet voltage tolerance specifications. Table 3.12 Reset Configuration Specifications Symbol Parameter Reset Configuration Signals (A[15:5]#, BR0#, FLUSH#, INIT#, PICD0) Setup Time Reset Configuration Signals (A[15:5]#, BR0#, FLUSH#, INIT#, PICD0) Hold Time Reset Lock Latency Unit
TPROC 1.6V ±120mV, VCCP 1.8V ±90mV, VCC3 3.3V ±165mV Figure Notes Before deassertion RESET# After clock that deasserts RESET# Before deassertion RESET# BCLKs
BCLKs
NOTE:
T20, although valid other systems, relevant mobile systems.
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Table 3.13 APIC Signal Specifications Symbol NOTES: Parameter PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Time PICCLK Rise Time PICCLK Fall Time PICD[1:0] Setup Time PICD[1:0] Hold Time PICD[1:0] Valid Delay 12.0 12.0 12.0 33.3 Unit
TPROC 1.6V ±120mV, VCCP 1.8V ±90mV, VCC3 3.3V ±165mV Figure
Notes
timings APIC signals referenced PICCLK rising edge processor connector pins. CMOS signals referenced 1.25V processor connector pins. minimum frequency when PICD0 2.5V reset. PICD0 strapped reset then minimum frequency MHz. Referenced PICCLK Rising Edge. open drain signals, Valid Delay synonymous with Float Delay. Valid delay timings these signals specified into 2.5V
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Table 3.14 Signal Specifications Processor Connector Pins TPROC 1.6V ±120mV, VCCP 1.8V ±90mV, VCC3 3.3V ±165mV Symbol NOTES: Parameter Frequency Period High Time Time Rise Time Fall Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time 13.0 40.0 14.0 25.0 25.0 16.67 Unit Figure
Notes
1.7V 0.7V
(0.7V-1.7V) (1.7V-0.7V)
Asynchronous
timings signals referenced rising edge processor connector pins. CMOS signals referenced 1.25V processor connector pins. 100% tested. Specified design/characterization. added maximum rise fall times every below MHz. Referenced rising edge. Referenced falling edge. Valid delay timing this signal specified into terminated 2.5V Non-Test Outputs Inputs normal output input signals (except TCK, TRST#, TDI, TMS). These timings correspond response these signals boundary scan operations. During Debug Port operation normal specified timings rather than signal timings.
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Table 3.15 Quick Start/Deep Sleep Specifications TPROC 1.6V ±120mV, VCCP 1.8V ±90mV, VCC3 3.3V ±165mV Symbol NOTE: Input signals other than SMBus, RESET# BPRI# must held constant Quick Start state. Table 3.16 Stop Grant/Sleep/Deep Sleep Specifications TPROC 1.6V ±120mV, VCCP 1.8V ±90mV, VCC3 3.3V ±165mV Symbol NOTE: Input signals other than SMBus RESET# must held constant Sleep state. Parameter SLP# Signal Hold Time from Stop Grant Cycle Completion SLP# Assertion Input Signals Stable SLP# Assertion Clock Stop Clock Start Lock SLP# Hold Time from Lock STPCLK# Hold Time from SLP# Deassertion Input Signal Hold Time from SLP# Deassertion Unit BCLKs BCLKs BCLKs BCLKs Figure 3.10 3.10 3.10 3.10 3.10 3.10 3.10
Parameter Stop Grant Cycle Completion Clock Stop Stop Grant Cycle Completion Input Signals Stable Clock Start Lock STPCLK# Hold Time from Lock Input Signal Hold Time from STPCLK# Deassertion
Unit BCLKs
Figure
Notes
BCLKs
Notes
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Figures through 3.10 used conjunction with Tables through 3.16.
BCLK Connector BCLK Core
VIL,BCLK
1.25V
Figure BCLK Connector Core Offset
1.25V
Figure Generic Clock Waveform NOTES: T34, Rise Time T35, Fall Time T32, High Time T33, Time T31, Period
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Signal Valid Valid
Figure Valid Delay Timings NOTES: T11, Valid Delay T14, T14B Pulse Width VREF Power GTL+ signal group; 1.25V Compatibility, APIC signal groups
Signal
Valid
Figure Setup Hold Timings NOTES: T12, Setup Time T13, Hold Time VREF Power GTL+ signals; 1.25V Compatibility, APIC signals
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BCLK
RESET#
Configuration (A[15:5], BR0#, FLUSH#, INIT#, PICD0)
Valid
Figure Cold/Warm Reset Configuration Timings NOTES: (Low Power GTL+ Input Hold Time) (Low Power GTL+ Input Setup Time) (RESET# Pulse Width) (Reset Lock Latency) (Reset Configuration Signals (A[15:5]#, BR0#, FLUSH#, INIT#, PICD0) Setup Time) (Reset Configuration Signals (A[15:5]#, BR0#, FLUSH#, INIT#, PICD0) Hold Time)
BCLK
VCCP, VCC, VREF
PWRGOOD
VIL,max
VIH,min
RESET#
D0007-00
Figure Power-On Reset Timings NOTES: (PWRGOOD Inactive Pulse Width) (RESET# pulse width) (Reset Lock Latency)
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TDI,
1.25V
Input Signals
Output Signals
Figure Test Timings (Boundary Scan) NOTES: (All Non-Test Inputs Setup Time) (All Non-Test Inputs Hold Time) (TDO Float Delay) (TDI, Setup Time) (TDI, Hold Time) (TDO Valid Delay) (All Non-Test Outputs Valid Delay) (All Non-Test Outputs Float Delay)
TRST#
1.25V
Figure Test Reset Timings NOTE: (TRST# Pulse Width)
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Normal BCLK
Running
Quick Start
Deep Sleep
Quick Start
Running
Normal
STPCLK#
stpgnt
SLP#
Frozen
Compatibility Signals
Changing
Figure Quick Start/Deep Sleep Timing NOTES: (Stop Grant Acknowledge Cycle Completion Clock Shut Delay) (Setup Time Input Signal Hold Requirement) (PLL Lock Latency After Clocks Restart) (PLL Lock STPCLK# Hold Time) (Input Signal Hold Time)
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Normal BCLK
Running
Stop Grant Sleep
Deep Sleep
Sleep
Running
Stop Grant Normal
STPCLK#
stpgnt
SLP#
Frozen Changing
Compatibility Signals
Changing
Figure 3.10 Stop Grant/Sleep/Deep Sleep Timing NOTES: (Stop Grant Acknowledge Cycle Completion SLP# Assertion Delay) (Setup Time Input Signal Hold Requirement) (SLP# Assertion Clock Shut Delay) (PLL Lock Latency after Clocks Restart) (SLP# Hold Time) (STPCLK# Hold Time) (Input Signal Hold Time)
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SYSTEM SIGNAL SIMULATIONS
Many scenarios have been simulated generate Power GTL+ layout guidelines which available Mobile Pentium Processor System Layout Guideline. waveforms described this section simulated processor core. Systems must simulated using IBIS model determine they compliant with this specification. signal quality guidelines also provided. Violations these guidelines allowed; they occur, then simulations signal quality processor core should performed ensure that violations signal quality specifications occur. Meeting guideline does guarantee meeting specification.
signal quality BCLK measured processor connector. timings illustrated Figure taken from Tables 3.8. BCLK 2.5V clock.
4.2.
Power GTL+ Signal Quality Specifications
Table Figure illustrate Power GTL+ signal quality specifications Mobile Pentium processor, simulated core. Table shows Power GTL+ signal quality guidelines Mobile Pentium processor, measured connector. Refer Pentium Processor Developer's Manual GTL+ buffer specification.
4.1.
System Clock (BCLK) Signal Quality Specifications
Table Figure show signal quality system clock (BCLK) signal simulated processor core. Table Figure show
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Table BCLK Signal Quality Specifications Processor Core Symbol VIL,BCLK VIH,BCLK Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback BCLK rising/falling slew rate NOTES: core, BCLK must rise/fall monotonically between VIL,BCLK VIH,BCLK. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK signal back after passing (rising) (falling) voltage limits. -0.7 Parameter Unit V/ns Figure
Notes
Undershoot, Overshoot Absolute Value Absolute Value
Figure BCLK Generic Clock Waveform Processor Core
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Table BCLK Signal Quality Guidelines Processor Connector Symbol NOTE: rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK signal back after passing VIH,BCLK (rising) VIL,BCLK (falling) voltage limits. VIL,BCLK VIH,BCLK Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback Tline Ledge Voltage Tline Ledge Oscillation -0.5 Parameter Unit Figure Overshoot, Undershoot Absolute Value Absolute Value
Notes
Figure BCLK Generic Clock Waveform Processor Connector
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Table Power GTL+ Signal Group Ringback Specification Processor Core Symbol
Overshoot Minimum Time High Amplitude Ringback Final Settling Voltage Duration Sequential Ringback
Parameter
-100
Unit
Figure
Notes
NOTES: Specified edge rate V/ns. Figure generic waveform. values determined design/characterization. Ringback below VREF +100 authorized during low-to-high transitions. Ringback above VREF -100 authorized during high-to-low transitions.
VREF+0.2V VREF Vstart VIL,BCLK Clock
VREF-0.2V
Time Note: High case analogous.
Figure Low-to-High, Power GTL+ Receiver Ringback Tolerance
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Table Power GTL+ Signal Group Ringback Guideline Processor Connector Symbol
Overshoot Minimum Time High Amplitude Ringback Final Settling Voltage Duration Sequential Ringback
Parameter
-250
Unit
Figure
Notes
NOTES: Greek letter symbols Figure refer values Table Table 4.4. Specified edge rate V/ns. Figure generic waveform. values determined design/characterization. Ringback below VREF +250 authorized during low-to-high transitions. Ringback above VREF -250 authorized during high-to-low transitions.
4.3.
Non-Low Power GTL+ Signal Quality Specifications
Signals driven Mobile Pentium processor system should meet signal quality specifications ensure that components read data properly that incoming signals affect long term reliability component. There three signal quality parameters defined: overshoot/undershoot, ringback settling limit. three signal quality parameters shown Figure non-GTL+ signal groups. 4.3.1. OVERSHOOT/UNDERSHOOT GUIDELINES Overshoot undershoot) absolute value maximum voltage above nominal high voltage below VSS. overshoot/undershoot guideline limits transitions beyond fast signal
edge rates. (See Figure non-GTL+ signals.) processor damaged repeated overshoot events 2.5V tolerant buffers charge large enough (i.e., overshoot great enough). However, excessive ringback dominant detrimental system timing effect resulting from overshoot/undershoot (i.e., violating overshoot/ undershoot guideline will make difficult satisfy ringback specification). overshoot/undershoot guideline 0.8V assumes absence diodes input. These guidelines should verified simulations without on-chip protection diodes present because diodes will begin clamping 2.5V tolerant signals beginning approximately 1.25V above 0.5V below VSS. signals reaching clamping voltage, this will issue. system should rely diodes overshoot/undershoot protection this will negatively affect life components make meeting ringback specification very difficult.
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Settling Limit Overshoot VHI=2.5V Rising-Edge Ringback
Falling-Edge Ringback Settling Limit
Time Undershoot
Figure Non-GTL+ Overshoot/Undershoot Ringback 4.3.2. RINGBACK SPECIFICATION
4.3.3.
SETTLING LIMIT GUIDELINE
Ringback refers amount reflection seen after signal switched. ringback specification voltage that signal rings back after achieving maximum absolute value. Excessive ringback cause false signal detection extend propagation delay. ringback specification applies input each receiving agent. Violations signal Ringback specification allowed under circumstances non-GTL+ signals. Ringback simulated with without input protection diodes that added input buffer model. However, signals that reach clamping voltage should evaluated further. Table Table provide signal ringback specifications non-GTL+ signals processor core processor connector, respectively.
Settling limit defines maximum amount ringing receiving that signal reach before next transition. amount allowed percent total signal swing (VHI-VLO) above below final value. signal should within settling limits final value, when either high state state, before next transition. Signals that within their settling limit before transitioning risk unwanted oscillations which could jeopardize signal integrity. Simulations verify settling limit done either with without input protection diodes present. Violation settling limit guideline acceptable simulations successive transitions show amplitude ringing increasing subsequent transitions.
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Table Signal Ringback Specifications Non-GTL+ Signals Processor Core Input Signal Group Non-GTL+ Signals Non-GTL+ Signals Transition Maximum Ringback (with Input Diodes Present) Figure
Table Signal Ringback Guidelines Non-GTL+ Signals Processor Connector Input Signal Group Non-GTL+ Signals Non-GTL+ Signals Transition Maximum Ringback (with Input Diodes Present) Figure
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5.1.
MECHANICAL SPECIFICATIONS Connector Mechanical Specifications
Mobile Pentium processor board-to-board stacking connector consists plug receptacle. plug surface mounts processor mates receptacle, which surface mounts motherboard. Each half connector uses ball grid array (BGA) technology surface mount. processor connector pins array. solder ball attached tail each contact surface mount center-to-center distance between solder balls (pitch) 1.27 plug mounted processor will available height. receptacle mounted motherboard will available from outside vendor heights allow component placement flexibility within package keepout line system electronics. board-to-board spacing defined spacing between processor substrate system electronics substrate after both halves connector reflowed onto their respective boards mated. board-to-board spacing confused with bottom clearance which space below cartridge. Mobile Pentium processor available board-toboard spacings These spacings dependent height receptacle, which function system manufacturer's mounting technique. system manufacturer chooses board-to-board spacing particular system design.
connector processor exposed order accommodate installation into system. shown Figure 5.1, overall footprint area reserved processor 56.00 60.00 Note that bottom cover metallic, caution should taken prevent shorting when placing components under processor. Components placed within package keepout line should contact processor. receptacle outline shown Figure that silk screened onto system electronics substrate, assist manual placement receptacle. actual shape receptacle assembly more complicated than rectangle, rectangle sufficient purpose manual placement. large small rectangles Figure show position large small keys connector. processor should securely mounted system board prevent potential damage shock vibration. Four mounting holes provided order facilitate mounting fasteners screws recommended) through processor into standoffs system board. concerns, mounting system that provides impedance ground between processor system board recommended. noted previously, processor exposed order accommodate system thermal interface. Table contains specification bond-line thickness, which distance between surface surface processor. facilitate this solution, cover recessed around (see Figure 5.3). More information about EMI, mounting, stand-offs thermal solution attachment provided Mobile Pentium Processor Mini-cartridge Mechanical Thermal User's Guide.
5.2.
Mechanical Specification Mobile Pentium® Processor
Mobile Pentium processor enclosed stainless steel (300-series) covers; however,
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56.0 2.25 4.56 2.04 42.5
12.9
15.0
LARGE
60.0
RECEPTACLE OUTLINE
PLUG KEEPOUT OUTLINE PACKAGE KEEPOUT OUTLINE
V0034-00
Figure Mini-Cartridge Assembly Connector Keepout Location, View
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important that processor disassembled permanently altered (e.g., adding extra holes) order facilitate system thermal solution attachment. Functionality processor guaranteed cover been removed. addition adhesives greases exterior surfaces product considered permanent.
Figure shows cross-sectional view Mobile Pentium processor. Figure through Figure illustrate Mobile Pentium processor assembly bottom cover dimensions standoff locations.
Thermal Plate
Cover (recess)
Processor Core
Processor Substrate
System Electronics Substrate Bottom Cover
Figure Mobile Pentium Processor Cross-sectional View
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Figure Mini-Cartridge Assembly, Cover
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Figure Mini-Cartridge Assembly, Bottom Cover Sides
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-L46.89 41.91 1.27 1.27
1.02
LARGE
50.80
STANDOFF LOCATION PLACES
V0035-00
Figure Standoff Connector Location, View
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Table Mobile Pentium Processor Mechanical Specifications Symbol X,YDIE FINS FEXT PDIE PTOP Shock Vibration NOTES: long edge processor core parallel long edge processor enclosure. These distances approximate will change from stepping stepping processor core. dimensions approximate likely change. Table Mobile Pentium Processor Vertical Dimensions Symbol NOTES: Table Figure definitions illustration processor height, plug height, bottom cover height bond-line thickness. Processor height, plug height, bond-line thickness only guaranteed vertical dimensions. other dimensions shown Figure dependent receptacle height. Refer Mobile Pentium Processor Mini-cartridge Mechanical Thermal User's Guide information effect receptacle mounting technique these dimensions. Bottom Cover Height reference proposes only. Table defines Mobile Pentium processor dimensions illustrated Figure 5.6. assembly stack height (SH), board-to-board spacing (BS) bottom clearance (BC) dimensions dependent receptacle height. Refer Mobile Pentium Processor Mini-cartridge Mechanical Thermal User's Guide information effect receptacle mounting technique these dimensions.
Parameter Processor Core Dimensions Processor Insertion Force Processor Extraction Force Allowable Pressure Thermal Attach Plate (TAP) Allowable Pressure Recessed Part Cover Mechanical Shock Under Nonoperating Conditions Mechanical Vibration Under Nonoperating Conditions Sine Sweep Random
10.84, 11.97
Unit
Notes
810E Method 810E Method
Parameter Processor Height Plug Height Bottom Cover Height
4.40 0.91
4.55 1.03 2.81
4.70 1.15
Units
Figure
Bond-Line Thickness
0.01
0.12
0.23
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V0030-00
Figure Cross Sectional View with Vertical Dimensions
Table Mobile Pentium Processor Dimension Definitions Symbol Parameter Processor Height Plug Height Bottom Cover Height Bond-Line Thickness Assembly Stack Height Board-to-Board Spacing Bottom Clearance Definition Distance from surface processor mating surface plug. Distance from bottom processor substrate mating surface plug. Distance from bottom side processor substrate bottom outer surface processor. Distance between surface surface processor. Distance from surface processor system electronics substrate. Distance from processor substrate system electronics substrate. Distance from bottom surface processor system electronics substrate.
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5.3.
Mobile Pentium® Processor Lists
Table shows Mobile Pentium processor signals location. Table lists signals name.
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Table Mobile Pentium Processor Pinout VCC3 BINIT# D40# D34# D38# D17# D14# VID3 RSVD RSVD FERR# IERR# A24# A20# DBSY# REQ3# AP0# VCC3 VCC3 BP3# D41# D52# D39# D44# D33# D31# D25# D16# D12# RSVD RSVD STPCLK# SMI# A32# A26# A27# A28# A21# A19# AERR# SMBDATA SMBCLK PREQ# SMBALERT# BPM1# VCCP_S D42# D45# D47# D36# D35# D26# D22# D20# D10# RSVD RSVD A20M# BERR# A34# A30# A22# A23# REQ4# RSP# VID2 VSS_S VID0 D49# D46# D48# D43# D27# D19# D21# D15# RSVD SLP# INIT# A31# A15# A17# A16# A18# DRDY# AP1# PRDY# VCC_S D57# D53# D51# D54# D37# DEP0# D32# D29# D18# D23# PWRGOOD IGNNE# RESET# A35# A29# A25# RSVD LOCK# A13# A11# A12# A14# BR0# HITM# BP2# INTR D55# D62# D59# D28# D24# D11# TRST# RS0# A33# BPRI# A10# RS2# HIT# BPM0# PICD0 DEP6# D56# D63# D58# D61# D60# D50# D30# PICD1 D13# FLUSH# RS1# TRDY# RSVD BCLK VCCP PICCLK VID1 DEP2# DEP1# DEP4# DEP7# DEP3# DEP5# BNR# REQ2# REQ0# RSVD ADS# DEFER# REQ1# VCCP
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Table Mobile Pentium Processor Listing Name A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# Signal Type Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Name A32# A33# A34# A35# A20M# ADS# AERR# AP0# AP1# BCLK BERR# BINIT# BNR# BP2# BP3# BPM0# BPM1# BPRI# BR0# Signal Type Power GTL+ Power GTL+ Power GTL+ Power GTL+ CMOS Input Power GTL+ Power GTL+ Power GTL+ Power GTL+ System Clock Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Input Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+
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Table Mobile Pentium Processor Listing (Continued) Name D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# Signal Type Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Name D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DEP0# DEP1# DEP2# DEP3# Signal Type Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Input Power GTL+ Power GTL+ Power GTL+ Power GTL+
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Table Mobile Pentium Processor Listing (Continued) Name DEP4# DEP5# DEP6# DEP7# DRDY# FERR# FLUSH# HIT# HITM# IERR# IGNNE# INIT# INTR LOCK# PICCLK PICD0 PICD1 PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESET# RS0# RS1# RS2# Signal Type Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ CMOS Output CMOS Input Power GTL+ Power GTL+ CMOS Output CMOS Input CMOS Input CMOS Input Power GTL+ CMOS Input APIC Clock Input CMOS CMOS Power GTL+ Output CMOS Input CMOS Input Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Input Power GTL+ Power GTL+ Input Power GTL+ Input Power GTL+ Input Name RSP# RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SLP# SMBALERT# SMBCLK SMBDATA SMI# STPCLK# TRDY# TRST# Signal Type Power GTL+ Input Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CMOS Input Thermal Alert SMBus Clock SMBus CMOS Input CMOS Input Clock Input Input Output Input Power GTL+ Input Input Core Core Core Core Core Core Core Core
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Table Mobile Pentium Processor Listing (Continued) Name VCC_S VCC3 VCC3 VCC3 VCCP VCCP VCCP_S VID0 VID1 VID2 VID3 Signal Type Core Core Core Core Core Core Core Core Core Core Core Sense Cache Core Cache Core Cache Core Cache Cache Cache Sense Voltage Identification Voltage Identification Voltage Identification Voltage Identification Ground Ground Ground Ground Ground Ground Ground Ground Ground Name VSS_S Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Sense Signal Type
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THERMAL SPECIFICATIONS
processor must clean before thermal solution attached processor damaged. During operational environments, processor core temperature, TPROC, must within range thermal sensor used measure processor core temperature. Section 3.1.4 description thermal sensor. thermal sensor measures temperature processor core with accuracy Note that this measurement 100% tested specified design/characterization.
Mobile Pentium processor contains enclosure which allows number different thermal management solutions system manufacturer. This section contains thermal characteristics processor. order achieve proper cooling processor, thermal solution (e.g., heat spreader, heat pipe, other heat transfer system) must securely attached processor's cover. Since processor exposed, thermal solutions must attach cover exposed processor.
Table Mobile Pentium Processor Power Specifications Symbol TDPPROC Parameter Thermal Design Power (Processor) Thermal Transfer Power
11.6 10.3
Unit
Notes Processor (core cache)
TDPTT
Core only
PSGNT PDSLP NOTES:
Stop Grant Auto Halt power Quick Start Sleep power Deep Sleep power
Processor, 50°C Processor, 50°C Processor, 50°C
TDPPROC,TYP TDPTT,TYP recommendations based power dissipation processor processor core, respectively, while executing publicly-available software under normal operating conditions nominal voltages. Contact your Intel Field Sales Representative further information. TDPPROC,MAX specification total power dissipation processor while executing worst-case instruction under normal operating conditions nominal voltages. includes power dissipated components within processor. 100% tested. Specified design/characterization. 100% tested guaranteed. Deep Sleep power specification composed leakage current various components processor VCC, VCCP VCC3 voltage planes. These leakages measured specified high temperatures. This Deep Sleep power specification determined characterization component leakage currents higher temperatures.
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PROCESSOR INITIALIZATION CONFIGURATION Description
7.1.3.
APIC ENABLE
7.1.
Mobile Pentium processor some configuration options that determined hardware some that determined software. processor samples hardware configuration reset, active-to-inactive transition RESET#. Most configuration options Mobile Pentium processor identical those Pentium processor. Pentium Processor Developer's Manual describes these configuration options. configuration options Mobile Pentium processor described remainder this section. 7.1.1. QUICK START ENABLE
PICD0 sampled active-toinactive transition RESET# signal then PICCLK tied VSS. Otherwise PICD[1:0] pins must pulled 2.5V PICCLK must supplied. Driving PICD0 reset also effect clearing APIC Global Enable APIC Base MSR. This normally when processor reset, when cleared APIC completely disabled until next reset.
7.2.
Clock Frequencies Ratios
Mobile Pentium processor uses clock design which clock multiplied ratio produce processor's internal "core") clock. ratio used programmed into processor when manufactured.
processor normally enters Stop Grant state when STPCLK# signal asserted will enter Quick Start state instead A15# sampled active RESET# signal's active-to-inactive transition. Quick Start state supports snoops from priority device like Stop Grant state does support symmetric master snoops latching interrupts supported. position Power-On Configuration register indicates that Quick Start state been enabled. 7.1.2. SYSTEM FREQUENCY
current generation Mobile Pentium processor will only function with system frequency MHz. position Power-On Configuration register indicates which speed processor will run. indicates 66-MHz frequency indicates 100-MHz frequency.
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APPENDIX SIGNAL REFERENCE Alphabetical Signal Reference
both agents Mobile Pentium processor system bus. AERR# (I/O Power GTL+) AERR# (Address Parity Error) signal observed driven both Mobile Pentium processor system agents, used, must connected appropriate pins both agents Mobile Pentium processor system bus. AERR# observation optionally enabled during power-on configuration; enabled, valid assertion AERR# aborts current transaction. AERR# observation disabled during power-on configuration, central agent handle assertion AERR# appropriate error handling architecture system. AP[1:0]# (I/O Power GTL+) AP[1:0]# (Address Parity) signals driven request initiator along with ADS#, A[35:3]#, REQ[4:0]# RP#. AP1# covers A[35:24]#. AP0# covers A[23:3]#. correct parity signal high even number covered signals number covered signals low. This allows parity high when covered signals high. AP[1:0]# should connected appropriate pins both agents Mobile Pentium processor system bus. BCLK 2.5V tolerant) BCLK (Bus Clock) signal determines system frequency. Both Mobile Pentium processor system agents must receive this signal drive their outputs latch their inputs BCLK rising edge. external timing parameters specified with respect BCLK signal. BERR# (I/O Power GTL+) BERR# (Bus Error) signal asserted indicate unrecoverable error without protocol violation. driven either Mobile Pentium processor system agents, must connected appropriate pins both agents, used. However,
A[35:3]# (I/O Power GTL+) A[35:3]# (Address) signals define -byte physical memory address space. When ADS# active, these pins transmit address transaction; when ADS# inactive, these pins transmit transaction information. These signals must connected appropriate pins both agents Mobile Pentium processor system bus. A[35:24]# signals protected with AP1# parity signal, A[23:3]# signals protected with AP0# parity signal. active-to-inactive transition RESET#, each processor agent samples A[35:3]# signals determine power-on configuration. Section details. A20M# 2.5V tolerant) A20M# (Address-20 Mask) input signal asserted, processor masks physical address (A20#) before looking line internal cache before driving read/write transaction bus. Asserting A20M# emulates 8086 processor's address wrap-around 1-Mbyte boundary. Assertion A20M# only supported real mode. A20M# asynchronous input. However, guarantee recognition this signal following write instruction, A20M# must valid with TRDY# assertion corresponding Write transaction. ADS# (I/O Power GTL+) ADS# (Address Strobe) signal asserted indicate validity transaction address A[35:3]# pins. Both agents observe ADS# activation begin parity checking, protocol checking, address decode, internal snoop deferred reply match operations associated with transaction. This signal must connected appropriate pins
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Mobile Pentium processors assertions BERR# signal.
observe
simultaneous edge transitions driven multiple drivers, BNR# activated specific clock edges sampled specific clock edges. BP[3:2]# (I/O Power GTL+) BP[3:2]# (Breakpoint) signals System Support group Breakpoint signals. They outputs from processor that indicate status breakpoints. BPM[1:0]# (I/O Power GTL+) BPM[1:0]# (Breakpoint Monitor) signals breakpoint performance monitor signals. They outputs from processor that indicate status breakpoints programmable counters used monitoring processor performance. BPRI# Power GTL+) BPRI# (Bus Priority Request) signal used arbitrate ownership Mobile Pentium processor system bus. must connected appropriate pins both agents system bus. Observing BPRI# active asserted priority agent) causes processor stop issuing requests, unless such requests part ongoing locked operation. priority agent keeps BPRI# asserted until requests completed, then releases deasserting BPRI#. BR0# (I/O Power GTL+)
BERR# assertion conditions defined system configuration. Configuration options enable BERR# driver follows: Enabled disabled Asserted optionally internal errors along with IERR# Asserted optionally request initiator transaction after observes error Asserted agent when observes error transaction
BINIT# (I/O Power GTL+) BINIT# (Bus Initialization) signal observed driven both Mobile Pentium processor system agents, must connected appropriate pins both agents, used. BINIT# driver enabled during power-on configuration, BINIT# asserted signal condition that prevents reliable future information. BINIT# enabled during power-on configuration, BINIT# sampled asserted, state machines reset data which transit lost. agents reset their rotating arbitration state after reset, internal count information lost. caches affected. BINIT# disabled during power-on configuration, central agent handle assertion BINIT# appropriate Machine Check Architecture (MCA) system. BNR# (I/O Power GTL+) BNR# (Block Next Request) signal used assert stall agent that unable accept transactions. During stall, current owner cannot issue transactions. Since multiple agents need request stall simultaneously, BNR# wired-OR signal which must connected appropriate pins both agents Mobile Pentium processor system bus. order avoid wire-OR glitches associated with
BR0# (Bus Request) signal processor Arbitration signal. Mobile Pentium processor indicates that wants ownership system asserting BR0# signal. During power-up configuration, central agent must assert BR0# signal. processor samples BR0# active-to-inactive transition RESET#. D[63:0]# (I/O Power GTL+) D[63:0]# (Data) signals data signals. These signals provide 64-bit data path between both Mobile Pentium processor system agents, must connected appropriate pins both agents. data driver asserts DRDY# indicate valid data transfer.
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DBSY# (I/O Power GTL+) DBSY# (Data Busy) signal asserted agent responsible driving data Mobile Pentium processor system indicate that data use. data released after DBSY# deasserted. This signal must connected appropriate pins both agents system bus. DEFER# Power GTL+) DEFER# (Defer) signal asserted agent indicate that transaction cannot guaranteed inorder completion. Assertion DEFER# normally responsibility addressed memory agent agent. This signal must connected appropriate pins both agents Mobile Pentium processor system bus. DEP[7:0]# (I/O Power GTL+) DEP[7:0]# (Data Protection) signals provide optional protection data bus. They driven agent responsible driving D[63:0]#, must connected appropriate pins both agents Mobile Pentium processor system they used. During poweron configuration, DEP[7:0]# signals enabled checking disabled checking. DRDY# (I/O Power GTL+)
FLUSH# 2.5V tolerant) When FLUSH# (Flush) input signal asserted, processor writes back internal cache lines Modified state invalidates internal cache lines. completion flush operation, processor issues Flush Acknowledge transaction processor stops caching data while FLUSH# signal remains asserted. FLUSH# asynchronous input. However, guarantee recognition this signal following write instruction, FLUSH# must valid along with TRDY# assertion corresponding Write transaction. active-to-inactive transition RESET#, each processor agent samples FLUSH# determine power-on configuration. HIT# (I/O Power GTL+), HITM# (I/O Power GTL+) HIT# (Snoop Hit) HITM# (Hit Modified) signals convey transaction snoop operation results, must connected appropriate pins both agents Mobile Pentium processor system bus. Either agent assert both HIT# HITM# together indicate that requires snoop stall, which continued reasserting HIT# HITM# together. IERR# 2.5V tolerant open-drain)
DRDY# (Data Ready) signal asserted data driver each data transfer, indicating valid data data bus. multi-cycle data transfer, DRDY# deasserted insert idle clocks. This signal must connected appropriate pins both agents Mobile Pentium processor system bus. FERR# 2.5V tolerant open-drain) FERR# (Floating-point Error) signal asserted when processor detects unmasked floatingpoint error. FERR# similar ERROR# signal Intel387 coprocessor, included compatibility with systems using DOS-type floatingpoint error reporting.
IERR# (Internal Error) signal asserted processor result internal error. Assertion IERR# usually accompanied SHUTDOWN transaction Mobile Pentium processor system bus. This transaction optionally converted external error signal (e.g., NMI) system core logic. processor will keep IERR# asserted until handled software with assertion RESET#, BINIT INIT#. IGNNE# 2.5V tolerant) IGNNE# (Ignore Numeric Error) signal asserted force processor ignore numeric error continue execute non-control floating-point instructions. IGNNE# deasserted, processor freezes non-control floating-point instruction
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previous instruction caused error. IGNNE# effect when control register set. IGNNE# asynchronous input. However, guarantee recognition this signal following write instruction, IGNNE# must valid along with TRDY# assertion corresponding Write transaction. INIT# 2.5V tolerant) INIT# (Initialization) signal asserted reset integer registers inside processor without affecting internal caches floating-point registers. processor begins execution power-on reset vector configured during power-on configuration. processor continues handle snoop requests during INIT# assertion. INIT# asynchronous input. INIT# sampled active RESET#'s active-toinactive transition, then processor executes built-in self test (BIST). INTR 2.5V tolerant) INTR (Interrupt) signal indicates that external interrupt been generated. INTR becomes LINT0 signal when APIC enabled. interrupt maskable using EFLAGS register. set, processor vectors interrupt handler after completing current instruction execution. Upon recognizing interrupt request, processor issues single Interrupt Acknowledge (INTA) transaction. INTR must remain active until INTA transaction guarantee recognition. INTR sampled every rising BCLK edge. INTR asynchronous input recognition INTR guaranteed specific clock asserted synchronously meets setup hold times. INTR must deasserted minimum clocks guarantee inactive recognition. APIC enabled Reset, then LINT[1:0] default configuration. LINT[1:0] 2.5V tolerant) LINT[1:0] (Local APIC Interrupt) signals must connected appropriate pins APIC agents, including processor core logic
APIC component. When APIC disabled, LINT0 signal becomes INTR, maskable interrupt request signal, LINT1 becomes NMI, nonmaskable interrupt. INTR backward compatible with same signals Pentium processor. Both signals asynchronous inputs. Both these signals must software configured programming APIC register space used either NMI/INTR LINT[1:0] BIOS. APIC enabled reset, then LINT[1:0] default configuration. LOCK# (I/O Power GTL+) LOCK# (Lock) signal indicates system that sequence transactions must occur atomically. This signal must connected appropriate pins both agents Mobile Pentium processor system bus. locked sequence transactions, LOCK# asserted from beginning first transaction through last transaction. When priority agent asserts BPRI# arbitrate ownership, waits until observes LOCK# deasserted. This enables processor retain ownership throughout locked operation guarantee atomicity lock. 2.5V tolerant) (Non-Maskable Interrupt) indicates that external interrupt been generated. becomes LINT1 signal when APIC enabled. Asserting causes interrupt with internally supplied vector value external interrupt-acknowledge transaction generated. asserted during execution service routine, remains pending recognized after IRET executed service routine. most, assertion held pending. rising-edge sensitive. Recognition guaranteed specific clock asserted synchronously meets setup hold times. asserted asynchronously, active inactive pulse widths must minimum clocks.
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PICCLK 2.5V tolerant) PICCLK (APIC Clock) signal input clock processor core logic APIC that required operation processor, core logic APIC components APIC bus. PICD[1:0] (I/O 2.5V tolerant open-drain) PICD[1:0] (APIC Data) signals used bidirectional serial message passing APIC bus. They must connected appropriate pins APIC agents, including processor core logic APIC components. PICD0 signal sampled active-to-inactive transition RESET# signal, then APIC hardware disabled. PRDY# Power GTL+) PRDY# (Probe Ready) signal processor output used debug tools determine processor debug readiness. Section instructions this signal. PREQ# 2.5V tolerant) PREQ# (Probe Request) signal used debug tools request debug operation processor. Section instructions this signal.
BCLK VCC, VCCP, VREF
PWRGOOD 2.5V tolerant) PWRGOOD (Power Good) 2.5V tolerant input. processor requires this signal clean indication that clocks power supplies (Vcc, Vccp, etc.) stable within their specifications. Clean implies that signal will remain low, (capable sinking leakage current) without glitches, from time that power supplies turned until they come within specification. signal will then transition monotonically high (2.5V) state. Figure illustrates relationship PWRGOOD other system signals. PWRGOOD driven inactive time, clocks power must again stable before rising edge PWRGOOD. must also meet minimum inactive pulse width specified Table 3.11 (Section 3.6) followed RESET# pulse. PWRGOOD signal, which must supplied processor, used protect internal circuits against voltage sequencing issues. PWRGOOD signal should driven high throughout boundary scan operation.
PWRGOOD
VIH,min msec
RESET#
Figure PWRGOOD Relationship Power-On REQ[4:0]# (I/O Power GTL+) REQ[4:0]# (Request Command) signals must connected appropriate pins both agents Mobile Pentium processor system bus. They asserted current owner when drives A[35:3]# define currently active transaction type.
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RESET# Power GTL+) Asserting RESET# signal resets processor known state invalidates caches without writing back Modified state) lines. RESET# must remain active millisecond "warm" reset. power-on type reset, RESET# must stay active least millisecond after BCLK have reached their proper specifications after PWRGOOD been asserted. When observing active RESET#, agents will deassert their outputs within clocks. number signals sampled active-toinactive transition RESET# power-on configuration. configuration options described Section every signal description this appendix. Unless outputs tristated during power-on configuration, after active-to-inactive transition RESET#, processor optionally executes built-in self-test (BIST) begins program execution reset-vector 0_000F_FFF0H 0_FFFF_FFF0H. RESET# must connected appropriate pins both agents Mobile Pentium processor system bus. (I/O Power GTL+) (Request Parity) signal driven request initiator, provides parity protection ADS# REQ[4:0]#. should connected appropriate pins both agents Mobile Pentium processor system bus. correct parity signal high even number covered signals number covered signals low. This definition allows parity high when covered signals high. RS[2:0]# Power GTL+) RS[2:0]# (Response Status) signals driven response agent (the agent responsible completion current transaction), must connected appropriate pins both agents Mobile Pentium processor system bus.
RSP# Power GTL+) RSP# (Response Parity) signal driven response agent (the agent responsible completion current transaction) during assertion RS[2:0]#. RSP# provides parity protection RS[2:0]#. RSP# should connected appropriate pins both agents Mobile Pentium processor system bus. correct parity signal high even number covered signals number covered signals low. During Idle state RS[2:0]# (RS[2:0]#=000), RSP# also high since driven agent guaranteeing correct parity. SLP# 2.5V tolerant) SLP# (Sleep) signal, when asserted Stop Grant state, causes processor enter Sleep state. During Sleep state, processor stops providing internal clock signals units, leaving only Phase-Locked Loop (PLL) still running. processor will recognize snoops interrupts Sleep state. processor will only recognize changes SLP#, STPCLK# RESET# signals while Sleep state. SLP# deasserted, processor exits Sleep state returns Stop Grant state which restarts internal clock APIC processor core units. SMBALERT# tolerant) SMBALERT# (SMBus Alert) signal used thermal sensor processor indicate that requires attention. compliant with SMBALERT# signal System Management Specification. processor's thermal sensor, this must connected appropriate SMBus host controller. SMBCLK (I/O tolerant) SMBCLK (SMBus Clock) signal compliant with SMBCLK signal System Management Specification. processor's thermal sensor, this must connected appropriate SMBus host controller.
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SMBDATA (I/O tolerant) SMBDATA (SMBus Data) signal compliant with SMBDATA signal System Management Specification. processor's thermal sensor, this must connected appropriate SMBus host controller. SMI# 2.5V tolerant) SMI# (System Management Interrupt) asserted asynchronously system logic. accepting System Management Interrupt, processor saves current state enters System Management Mode (SMM). Acknowledge transaction issued, processor begins program execution from handler. SMI# asynchronous input. However, guarantee recognition this signal following instruction, SMI# must valid system clocks before RS[2:0]# assertion corresponding transaction. STPCLK# 2.5V tolerant) STPCLK# (Stop Clock) signal, when asserted, causes processor enter low-power Stop Grant state. processor issues Stop Grant Acknowledge special transaction, stops providing internal clock signals units except APIC units. processor continues snoop transactions service interrupts while Stop Grant state. When STPCLK# deasserted, processor restarts internal clock units resumes execution. assertion STPCLK# effect clock. STPCLK# asynchronous input. However, guarantee recognition this signal following write instruction, STPCLK# must valid along with TRDY# assertion corresponding Write transaction. 2.5V tolerant) (Test Clock) signal provides clock input test (also known test access port).
2.5V tolerant) (Test Data signal transfers serial test data processor. provides serial input needed JTAG support. 2.5V tolerant open-drain) (Test Data Out) signal transfers serial test data from processor. provides serial output needed JTAG support. 2.5V tolerant) (Test Mode Select) signal JTAG support signal used debug tools. TRDY# Power GTL+) TRDY# (Target Ready) signal asserted target indicate that target ready receive write implicit writeback data transfer. TRDY# must connected appropriate pins both agents Mobile Pentium processor system bus. TRST# 2.5V tolerant) TRST# (Test Reset) signal resets Test Access Port (TAP) logic. Mobile Pentium processors self-reset during power-on; therefore, necessary drive this signal during power-on reset. VID[3:0] open drain) VID[3:0] (Voltage pins used support automatic selection power supply voltages. These pins signals, either open circuit short circuit processor. combination opens shorts defines voltage required processor. pins needed cleanly support voltage specification changes Mobile processors. These pins (VID3 Pentium through VID0) defined Table A.1. this table refers open refers short ground. power supply must supply voltage that requested disable itself.
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these pins, attach pull-up resistors each connected power supply that guaranteed stable when supply core power supply
stable. pull-up voltage resistance specified, current through pins must exceed value shown Table 3.3.
Table Voltage Identification Definition VID[3:0] 0000 0001 0010 0011 2.00 1.95 1.90 1.85 VID[3:0] 0100 0101 0110 0111 1.80 1.75 1.70 1.65 VID[3:0] 1000 1001 1010 1011 1.60 1.55 1.50 1.45 VID[3:0] 1100 1101 1110 1111 1.40 1.35 1.30
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Signal Summaries
Tables through list attributes processor input, output, signals. Table Input Signals Name A20M# BCLK BPRI# DEFER# FLUSH# IGNNE# INIT# INTR LINT[1:0] PICCLK PREQ# PWRGOOD RESET# RS[2:0]# RSP# SLP# SMI# STPCLK# TRDY# TRST# NOTES: Synchronous assertion with active TRDY# guarantees synchronization. Synchronous assertion clocks before active RS[2:0]# guarantees synchronization instruction trapping. Active Level High High High High High High High High High Clock Asynch BCLK BCLK Asynch Asynch Asynch Asynch Asynch Asynch Asynch Asynch BCLK BCLK BCLK Asynch Asynch Asynch BCLK Asynch Signal Group compatibility System System System compatibility compatibility System compatibility APIC compatibility APIC Implementation Implementation System System System Implementation compatibility Implementation JTAG JTAG JTAG System JTAG Always Always Always Always Always Always Always
Qualified
APIC disabled mode APIC enabled mode APIC disabled mode Always Always Always Always Always Always Stop Grant state Always Always Always Always Always Response phase Always
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
Table Output Signals Name FERR# IERR# PRDY# SMBALERT# VID[3:0] Active Level High Clock Asynch Asynch BCLK Asynch Asynch Signal Group compatibility Implementation Implementation Implementation JTAG Implementation
Table Input/Output Signals (Single Driver) Name A[35:3]# ADS# AP[1:0]# BR0# BP[3:2]# BPM[1:0]# D[63:0]# DBSY# DEP[7:0]# DRDY# LOCK# REQ[4:0]# Active Level Clock BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK Signal Group System System System System System System System System System System System System System Qualified ADS#, ADS#+1 Always ADS#, ADS#+1 Always Always Always DRDY# Always DRDY# Always Always ADS#, ADS#+1 ADS#, ADS#+1
A-10
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
Table Input/Output Signals (Multiple Driver) Name AERR# BERR# BINIT# BNR# HIT# HITM# PICD[1:0] SMBCLK SMBDATA Active Level High High High Clock BCLK BCLK BCLK BCLK BCLK BCLK PICCLK SMBCLK Signal Group System System System System System System APIC SMBus SMBus Qualified ADS#+3 Always Always Always Always Always Always Always Always
A-11
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
INDEX
reference voltage termination voltage
specifications .19-31 APIC specifications specifications hardware disable auto halt specifications
HALT/GRANT SNOOP STATE
instruction restart IBIS.
BCLK signal quality specifications system clock
leakage specifications. power GTL+. power power states state.
clock specifications CONTROL .5-10 specifications latency ratio configuration ratios.15 connector specification.39 CPUID
maximum ratings. mechanical specifications 39-52
overshoot
specifications .15-19 debug port decoupling.15 deep sleep specifications specifications
compatibility. specifications. specifications. pinout power specifications. PWRGOOD
fault tolerance (FRC).4
quick start specifications. configuration specifications.
GTL+ specifications specifications GTL+.10 power .18,
reset
MOBILE PENTIUM PROCESSOR MHZ, MHZ,
specifications. ringback.
specifications specifications thermal sensor THERMTRIP#.
shutdown signal signals reference summary 9-11 sleep specifications. specifications. SMBus. stop grant specifications. specifications.
undershoot unused pins
voltage voltage reduction technology. voltage sense pins
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