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MOBILE PENTIUM® II PROCESSOR AT 233 MHz, 266 MHz, AND 300 MHz

Refer to the Mobile Pentium® II Processor Performance Brief.

MOBILE PENTIUM® II PROCESSOR AT 233 MHz, 266 MHz, AND 300 MHz
Refer to the Mobile Pentium® II Processor Performance Brief.
Fully compatible with previous Intel microprocessors - Binary compatible with all applications - Support for MMX technology
Power Management Features - Quick Start and Deep Sleep modes provide extremely low power dissipation
Low-Power GTL+ processor system bus interface Integrated math co-processor High Reliability error detection with 64-bit system bus with Error Correction Code
ORDER NUMBER: 243669-002
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
CONTENTS
PAGE 3.1.6. 1. INTRODUCTION ......................... 1 1.1. Architecture Overview.................. 2 1.2. Terminology.......................... 2 1.3. References .......................... 2 2. MOBILE PENTIUM II PROCESSOR FEATURES............................. 4 2.1. Differences Between the Mobile Pentium II Processor and the Pentium II Processor .... 4 2.2. Power Management.................... 5 2.2.1. THE MOBILE PENTIUM II PROCESSOR CLOCK CONTROL ARCHITECTURE ................ 5 NORMAL STATE................ 5 AUTO HALT STATE.............. 7 STOP GRANT STATE ............ 8 QUICK START STATE............ 8 HALT / GRANT SNOOP STATE..... 8 SLEEP STATE.................. 9 DEEP SLEEP STATE............. 9 CURRENTLY SUPPORTED CLOCK STATES ....................... 9
PAGE SMBUS PINS ..................14 UNUSED PINS.................14 PIN STATE IN LOW POWER STATES.......................14
3.1.8.1. System Bus Signals...........14 3.1.8.2. PC Compatibility / Sideband Signals.....................14 3.1.8.3. Other Signals................14 3.2. Decoupling Requirements..............15 3.3. System Bus Clock and Processor Clocking.15 3.4. Maximum Ratings ....................15 3.5. DC Specifications ....................15 3.6. AC Specifications.....................19 3.6.1. SYSTEM BUS, CLOCK, APIC, TAP AND PC COMPATIBILITY AC SPECIFICATIONS ..............19
4. SYSTEM SIGNAL SIMULATIONS..........32 4.1. System Bus Clock (BCLK) Signal Quality Specifications........................32 4.2. Low Power GTL+ Signal Quality Specifications........................32 4.3. Non-Low Power GTL+ Signal Quality Specifications........................36 4.3.1. 4.3.2. 4.3.3. OVERSHOOT / UNDERSHOOT GUIDELINES...................36 RINGBACK SPECIFICATION......37 SETTLING LIMIT GUIDELINE.....37
2.2.10. OPERATING SYSTEM IMPLICATIONS OF THE QUICK START AND SLEEP STATES ...... 9 2.3. Low Power GTL+..................... 10 2.3.1. LOW POWER GTL+ PINS........ 11
2.4. Mobile Pentium II Processor CPUID..... 11 5. MECHANICAL SPECIFICATIONS..........39 3. ELECTRICAL SPECIFICATIONS........... 12 3.1. The Mobile Pentium II Processor System Signals............................. 12 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.5. POWER SEQUENCING REQUIREMENTS............... 13 VOLTAGE SENSE PINS ......... 13 TEST ACCESS PORT (TAP) CONNECTION................. 13 THERMAL SENSOR ............ 14 CATASTROPHIC THERMAL PROTECTION ................. 14
5.1. Connector Mechanical Specifications .....39 5.2. Mechanical Specification of the Mobile ® Pentium II Processor .................39 5.3. Mobile Pentium II Processor Pin Lists ....47 6. THERMAL SPECIFICATIONS .............53 7. PROCESSOR INITIALIZATION AND CONFIGURATION .......................54 7.1. Description..........................54 7.1.1. QUICK START ENABLE..........54
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
SYSTEM BUS FREQUENCY ......54 APIC ENABLE..................54
INDEX ................................... I-1
7.2. Clock Frequencies and Ratios ...........54 APPENDIX A. SIGNAL REFERENCE......... A-1
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
LIST OF FIGURES
PAGE Figure 2.1 Mobile Pentium II Processor Clock Control States........................... 6 Figure 3.0 VCC Ramp Rate Requirement ......... 13 Figure 3.1 BCLK Connector to Core Offset....... 26 Figure 3.2 Generic Clock Waveform ............ 26 Figure 3.3 Valid Delay Timings................ 27 Figure 3.4 Setup and Hold Timings ............. 27 Figure 3.5 Cold / Warm Reset and Configuration Timings ......................... 28 Figure 3.6 Power-On Reset Timings ............ 28 Figure 3.7 Test Timings (Boundary Scan)........ 29 Figure 3.8 Test Reset Timings ................ 29 Figure 3.9 Quick Start / Deep Sleep Timing ....... 30 Figure 3.10 Stop Grant / Sleep / Deep Sleep Timing.. 31 Figure 4.1 BCLK Generic Clock Waveform at the Processor Core................... 33 Figure 4.2 BCLK Generic Clock Waveform at the Processor Connector .............. 34 Figure 4.3 Low-to-High, Low Power GTL+ Receiver Ringback Tolerance............... 35 Figure 4.4 Non-GTL+ Overshoot / Undershoot and Ringback........................ 37 Figure 5.1 Mini-Cartridge Assembly and Connector Keepout Location, Top View (in mm) .. 40 ® Figure 5.2 Mobile Pentium II Processor Crosssectional View .................... 41 Figure 5.3 Mini-Cartridge Assembly, Top Cover (in mm)............................ 42 Figure 5.4 Mini-Cartridge Assembly, Bottom Cover and Sides (in mm)................. 43 Figure 5.5 Standoff and Connector Location, Top View (in mm)..................... 44 Figure 5.6 Cross Sectional View with Vertical Dimensions ...................... 46 Figure A.1 PWRGOOD Relationship at Power-On .. 5
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
LIST OF TABLES
PAGE Table 2.1 New Pins in the Mobile Pentium II Processor........................5 ® Table 2.2 Mobile Pentium II Processor Clock State Characteristics ....................7 Table 2.3 Low-Power Clock States Supported by Processor.......................10 ® Table 2.4 Mobile Pentium II Processor CPUID ...11 Table 3.1 System Signal Groups ...............12 Table 3.2 Recommended Pull-Up Resistors for Open , 2 Drain Signals ...................13 ® Table 3.3 Mobile Pentium II Processor Absolute Maximum Ratings.................16 ® Table 3.4 Mobile Pentium II Processor Power 1 Specifications ...................17 Table 3.5 Low Power GTL+ Bus DC Specifications 18 Table 3.6 Low Power GTL+ Signal Group DC Specifications ....................18 Table 3.7 Clock, APIC, TAP and PC Compatibility Signal Group DC Specifications......19 Table 3.8 System Bus Clock AC Specifications ...20 ® Table 3.9 Valid Mobile Pentium II Processor Frequencies .....................20 Table 3.10 Low Power GTL+ Signal Groups AC Specifications ....................21 Table 3.11 PC Compatibility Signal Group AC Specifications ....................21 Table 3.12 Reset Configuration AC Specifications .22 Table 3.13 APIC Bus Signal AC Specifications....23 Table 3.14 TAP Signal AC Specifications at the Processor Connector Pins ..........24 Table 3.15 Quick Start / Deep Sleep AC Specifications25 Table 3.16 Stop Grant / Sleep / Deep Sleep AC Specifications ....................25 Table 4.1 BCLK Signal Quality Specifications at the Processor Core ...................33 Table 4.2 BCLK Signal Quality Guidelines at the Processor Connector ..............34 Table 4.3 Low Power GTL+ Signal Group Ringback Specification at the Processor Core ...35 Table 4.4 Low Power GTL+ Signal Group Ringback Guideline at the Processor Connector..36 Table 4.5 Signal Ringback Specifications for NonGTL+ Signals at the Processor Core ..38 Table 4.6 Signal Ringback Guidelines for Non-GTL+ Signals at the Processor Connector...38
PAGE Table 5.1 Mobile Pentium II Processor Mechanical Specifications .................... 45 ® Table 5.2 Mobile Pentium II Processor Vertical Dimensions ..................... 45 ® Table 5.3 Mobile Pentium II Processor Dimension Definitions ....................... 46 ® Table 5.4 Mobile Pentium II Processor Pinout .... 48 ® Table 5.5 Mobile Pentium II Processor Pin Listing. 49 ® Table 5.5 Mobile Pentium II Processor Pin Listing (Continued)................ 50 ® Table 5.5 Mobile Pentium II Processor Pin Listing (Continued)................ 51 ® Table 5.5 Mobile Pentium II Processor Pin Listing (Continued)................ 52 ® Table 6.1 Mobile Pentium II Processor Power Specifications .................... 53 Table A.1 Voltage Identification Pin Definition ...... 8 Table A.2 Input Signals ....................... 9 Table A.3 Output Signals .................... 10 Table A.4 Input / Output Signals (Single Driver).... 10 Table A.5 Input / Output Signals (Multiple Driver) ... 11
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
INTRODUCTION
The Mobile Pentium II processor is the first implementation of the Pentium II Processor family that is optimized for the mobile platform. It will initially be offered at three speeds: 300 MHz, 266 MHz, and 233 MHz, with a system bus speed of 66 MHz. It consists of a Mobile Pentium II processor core with an integrated L2 cache controller and a 64-bit high performance system bus. The Mobile Pentium II processor has a private cache bus that allows a high performance 64-bit wide cache subsystem to be gluelessly implemented using a TagRAM and two PBSRAM (Pipeline Burst SRAM) devices. The Mobile
Thermal Sensor
TagRAM APIC Bus Mobile Pentium II Processor Core PBSRAMs
System Bus
Mobile Pentium® II Processor
SMBus
443BX North Bridge Compatibility
System Controller IOAPIC (optional) ISA / EIO
PIIX4E South Bridge
Figure 1.1 Signal Groups of a Mobile Pentium® II Processor-based System
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Architecture Overview
Architectural enhancements to improve performance · · · Supports the Intel Architecture with Dynamic Execution Supports the Intel Architecture MMX technology Integrated Intel Floating-Point Unit compatible with the IEEE Std 754
Integrated primary (L1) instruction and data caches · · · 4-way set associative, 32-byte line size, 1 line per sector 16-Kbyte instruction cache and 16-Kbyte writeback data cache Cacheable range programmable by processor programmable registers Dedicated 64-bit wide bus for high speed data transfers 512-Kbyte, ECC protected cache data array Uses Intel designed TagRAM Clock to PBSRAMs turns off when processor is in low power states 64-bit data bus, 66-MHz operation Uni-processor, two loads only (processor and I / O bridge / memory controller) Short trace length and low capacitance allows for single ended termination
References
Integrated second level (L2) cache · · · ·
Low Power GTL+ system bus interface · · ·
Voltage reduction technology New Pentium II processor family clock control · · Quick Start for low power, low exit latency clock "throttling" Deep Sleep mode for an extremely low power dissipation
Accurate processor temperature sensor
Terminology
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
System Management Bus Specification, Revision 1.0 (Available on the World Wide Web contact your Intel Field Sales Representative) Mobile Pentium II Processor and Pentium II Processor Mobile Module Thermal Power Consumption (Order Number 243670-001) Mobile Pentium II Processor / 440BX AGPset Datasheet (Order Number 290633-001) Mobile Pentium II Processor and Pentium II Processor Mobile Module Thermal Sensor Programming Interface Specification (Contact your Intel Field Sales Representative)
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
MOBILE PENTIUM® II PROCESSOR FEATURES Differences Between the Mobile Pentium® II Processor and the Pentium II Processor
Thermal Sensor
Fault Tolerance (FRC)
The Pentium II processor supports a master / checker processor configuration for high integrity, fault tolerant operation. This mode is not supported in the Mobile Pentium II processor and there is no FRCERR pin. · Local APIC
The Mobile Pentium II processor core has a thermal diode with a low impedance connection to anode and cathode package pins. On the Mobile Pentium II processor there is a thermal sensor attached to the diode that communicates the processor core temperature to the system logic through a system management bus (SMBus) interface. Having a thermal sensor integrated onto the processor core allows for better thermal management of the Mobile Pentium II processor system. · THERM-TRIP# The Mobile Pentium II processor does not have a THERMTRIP# pin. · L2 Cache Clock Stopping
The Pentium II processor requires that the PICCLK pin be driven with a valid APIC clock signal even when the APIC is not used. No APIC clock signal is required in the Mobile Pentium II processor if the PICD0 pin is strapped to ground at reset. · Voltage Reduction Technology
The Pentium II processor uses a single voltage for the core and the L2 cache I / O buffers while the Mobile Pentium II processor permits the core voltage to be lower than the L2 I / O voltage. This allows the processor to achieve a much lower power consumption while maintaining a 1.8V L2 interface. Both processors have 2.5V tolerant buffers for non-GTL+ system logic signals (clocks, APIC, TAP and PC compatibility). · Low Power GTL+
The Pentium II processor turns off the clocks to the L2 cache on the cache bus only when it is in the Deep Sleep state and leaves them running at all other times. The Mobile Pentium II processor core turns off the clocks to the PBSRAMs when it is in the Quick Start and Sleep states. The TagRAM clock is left running except in the Deep Sleep state. · Quick Start
The Pentium II processor GTL+ bus uses 56 termination at both ends or one end of the bus and limits on stub lengths to allow three loads on the long GTL+ bus. The Mobile Pentium II processor supports Low Power GTL+ with a short, point-topoint, two load bus with the possibility of a socketed CPU. The recommended termination under Low Power GTL+ is single-ended and 120 termination resistors. · Uniprocessor
The Mobile Pentium II processor has a new clock control state that is similar to the Stop Grant state but consumes less power. The Stop Grant state supports snooping of bus transactions generated by the priority bus device (usually the PCI bridge) and by symmetric processors. The Quick Start state only snoops bus priority device transactions, thus it is only usable in uniprocessor systems. The Stop Grant state supports the recognition of changes in input signals and the latching of edgetriggered interrupts (e.g., NMI, SMI#). In the Quick Start state input signal transitions are not allowed (see Section 2.2.5).
The Pentium II processor supports 2-way multiprocessing but the Mobile Pentium II processor can only be used in uniprocessor systems.
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
msec, the exit latency of the Deep Sleep state has been reduced to 30 µsec in the Mobile Pentium II processor. The Stop Grant and Sleep states shown in Figure 2.1 are intended for use in "Deep Green" desktop and server systems - not in mobile systems. Performing state transitions not shown in Figure 2.1 is neither recommended nor supported. The clock control architecture consists of seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT / Grant Snoop, Sleep and Deep Sleep states. The Stop Grant and Quick Start clock states are mutually exclusive, i.e., a strapping option on pin A15# chooses which state is entered when the STPCLK# signal is asserted. The Quick Start state is enabled by strapping the A15# pin to ground at Reset otherwise, asserting the STPCLK# signal puts the processor into the Stop Grant state. The Stop Grant state has a higher power level than the Quick Start state and is designed for SMP platforms. The Quick Start state has a much lower power level, but it can only be used in uniprocessor platforms. Table 2.2 provides clock state characteristics (power numbers based on estimates for a Mobile Pentium II processor running at 266 MHz), which are described in detail in the following sections. 2.2.2. NORMAL STATE
Power Management
THE MOBILE PENTIUM II PROCESSOR CLOCK CONTROL ARCHITECTURE
Table 2.1 New Pins in the Mobile Pentium II Processor Pin Name SMBALERT# SMBCLK SMBDATA O I / O I / O Type Thermal sensor attention signal. SMBus clock signal. Refer to the System Management Bus Specification for descriptions and specifications of the three SMBus signals. SMBus data signal. Refer to the System Management Bus Specification for descriptions and specifications of the three SMBus signals. Description
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Normal State
Quick Start
BCLK stopped BCLK on and QSS
Auto Halt
Snoop serviced
Snoop occurs
Deep Sleep
Snoop occurs Snoop serviced
Stop Grant
HALT / Grant Snoop
BCLK stopped
Sleep
halt break - BINIT#, FLUSH#, SMI#, NMI, INTR, INIT#, RESET#, A20M# stop break - BINIT#, FLUSH#, RESET# QSS - Quick Start Strapping option HS - Processor Halt State HLT - HLT instruction executed
Figure 2.1 Mobile Pentium II Processor Clock Control States
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Through snoop, to HALT / Grant Snoop state: immediate Through STPCLK#, to Normal state: 10 bus clocks
HALT / Grant Snoop Sleep
A few bus clocks after the end of snoop activity. To Stop Grant state 10 bus clocks
Not specified 0.5 W
Supports snooping in the low power states H / W controlled entry / exit desktop idle mode support H / W controlled entry / exit Mobile powered-on suspend support
Deep Sleep
30 µsec
100 mW
NOTE:
AUTO HALT STATE
This is a low power mode entered by the processor through the execution of the HLT instruction. The power level of this mode is similar to the Stop Grant state. A transition to the Normal state is made by a halt break event (one of the following signals going active: NMI, INTR, BINIT#, INIT#, RESET#, FLUSH# or SMI#). Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition to the Stop Grant or Quick Start state, where a Stop Grant Acknowledge bus cycle will be issued. By deasserting
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
The FLUSH# signal is serviced in the Auto Halt state. After the on-chip and off-chip caches have been flushed, the processor will return to the Auto Halt state without issuing a Halt bus cycle. Transitions in the A20M# pin are recognized while in the Auto Halt state. 2.2.4. STOP GRANT STATE
snooping behavior, Quick Start can only be used in a Uniprocessor (UP) configuration. A transition to the Deep Sleep state (see Section 2.2.8) can be made by stopping the clock input to the processor. A transition back to the Normal state (from the Quick Start state) is made only if the STPCLK# signal is deasserted. While in this state the processor is limited in its ability to respond to input. It is incapable of latching any interrupt, servicing snoop transactions from symmetric bus masters or responding to FLUSH# or BINIT# assertions. While the processor is in the Quick Start state, it will not respond properly to any input signal other than STPCLK#, RESET# or BPRI#. If any other input signal changes, then the behavior of the processor will be unpredictable. No serial interrupt messages may begin or be in progress while the processor is in the Quick Start state. The thermal sensor will respond normally to SMBus transactions when the processor is in the Quick Start state. RESET# assertion will cause the processor to immediately initialize itself, but the processor will stay in the Quick Start state after initialization until STPCLK# is deasserted. Asserting the SLP# signal when the processor is configured for Quick Start will result in unpredictable behavior and is not recommended. 2.2.6. HALT / GRANT SNOOP STATE
The processor enters this mode with the assertion of the STPCLK# signal when it is configured for Stop Grant state (via the A15# strapping option). The processor is still able to respond to snoop requests and latch interrupts. Latched interrupts will be serviced when the processor returns to the Normal state. Only one occurrence of each interrupt event will be latched. A transition back to the Normal state can be made by the de-assertion of the STPCLK# signal, or the occurrence of a stop break event (a BINIT#, FLUSH# or RESET# assertion). While in the Stop Grant state, SMI#, INIT# and LINT1:0 will be latched by the processor, and only serviced when the processor returns to the normal state. Only one occurrence of each event will be recognized upon return to the normal state. The processor will return to the Stop Grant state after the completion of a BINIT# bus initialization unless STPCLK# has been de-asserted. RESET# assertion will cause the processor to immediately initialize itself, but the processor will stay in the Stop Grant state after initialization until STPCLK# is deasserted. If the FLUSH# signal is asserted, the processor will flush the on-chip and off-chip caches and return to the Stop Grant state. A transition to the Sleep state can be made by the assertion of the SLP# signal (see Section 2.2.7 for a description). 2.2.5. QUICK START STATE
This is a mode entered by the processor with the assertion of the STPCLK# signal when it is configured for the Quick Start state (via the A15# strapping option). In the Quick Start state the processor is only capable of acting on snoop transactions generated by the system bus priority device. Because of its
The Mobile Pentium II processor will respond to snoop transactions on the system bus while in the Auto Halt, Stop Grant or Quick Start state. When a snoop transaction is presented on the system bus the processor will enter the HALT / Grant Snoop state. The processor will remain in this state until the snoop on the system bus has been serviced and the system bus is quiet. After the snoop has been serviced, the processor will return to the previous Auto Halt, Stop Grant or Quick Start state. If the HALT / Grant Snoop state is entered from the Quick Start state, then the input signal restrictions of the Quick Start state still apply in the HALT / Grant Snoop state, except for those signal transitions that are required to perform the snoop.
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
SLEEP STATE
The Deep Sleep state is the lowest power mode the processor can enter while maintaining its context. The Deep Sleep state is entered by stopping the BCLK input to the processor, while it is in the Sleep or Quick Start state. For proper operation, the BCLK input should be stopped in the low state. To re-enter either the Sleep or Quick Start state from the Deep Sleep state, the BCLK input must be restarted. The processor will return to the Sleep or Quick Start state, as appropriate, after 30 msec. PICCLK may be removed in the Deep Sleep state. PICCLK should be designed to turn on when BCLK turns on when transitioning out of the Deep Sleep state.
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Table 2.3 Low-Power Clock States Supported by Processor Processor Stop Grant Pentium Pro Processor ® Pentium II Processor ® Mobile Pentium II Processor
Auto Halt
Clock State Quick Start
Sleep
Deep Sleep
should not be used in Mobile Pentium II processor systems. If software generates an IPI just before the processor enters the Quick Start or Sleep state, then a message on the APIC bus will be generated. This violates the requirement stated in Section 2.2.5 that no input signals toggle in the Quick Start or Sleep state. Any software-generated IPI in a Mobile Pentium II processor system (uniprocessor system) will always result in an error. The time-stamp counter and the performance monitor counters are not guaranteed to count in the Quick Start or Sleep states. If software sets the APIC interrupt enable bit of either of the performance counters, then the resulting behavior will be unpredictable.
based on capacitive derating. Analog signal simulation of the system bus including trace lengths is highly recommended to ensure that there are no significant transmission line effects. Contact your field sales representative to receive the IBIS models for the Mobile Pentium II processor. The GTL+ system bus of the Pentium II processor was designed to support high speed data transfers with multiple loads on a long bus that behaves like a transmission line. However, in a mobile system, the system bus only has two loads (the processor and the chipset) and the bus traces are short enough that transmission line effects are not significant. It is possible to change the layout and termination of the system bus to take advantage of the mobile environment using the same GTL+ I / O buffers. The benefit is that it reduces the number of terminating resistors in half and substantially reduces the AC and DC power dissipation of the system bus. Low Power GTL+ uses GTL+ I / O buffers, although only two loads are allowed. The trace length is limited and the bus is terminated at one end only. Since the system bus is small and lightly loaded, it behaves like a capacitor, and the GTL+ I / O buffers behave like high speed open-drain buffers. With a 66-MHz bus frequency, the pull-up would be 120. VTT has been increased from 1.5V to processor core VCC to eliminate the need for a 1.5V power plane. If 100 termination resistors are used rather than 120, then 20 percent more power will be dissipated in the termination resistors. 120 termination is recommended to conserve power. Refer to the Mobile Pentium II Processor System Bus Layout Guideline for details on laying out the Low Power GTL+ system bus.
Low Power GTL+
The Mobile Pentium II processor system bus signals use a variation of the low-voltage GTL (Gunning Transceiver Logic) signaling technology. The Mobile Pentium II processor system bus specification is similar to the Pentium II processor system bus specification, which is itself a version of GTL with enhanced noise margins and less ringing. The Mobile Pentium II processor system bus specification reduces system cost and power consumption by raising the termination voltage and termination resistance and changing the termination from dual ended to single ended. Because the specification is different from the standard GTL specification and from the Pentium II processor GTL+ specification, it is referred to as Low Power GTL+. The Pentium II processor GTL+ system bus depends on incident wave switching and uses flight time for timing calculations of the GTL+ signals. The Low Power GTL+ system bus is short and lightly loaded. With Low Power GTL+ signals, timing calculations are
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
LOW POWER GTL+ PINS
simulations show that the signal quality specifications in Section 4 are met.
Two signals of the system bus will potentially not meet the Low Power GTL+ layout requirements: PRDY# and RESET#. These two signals connect to the debug port described in Section 7 and thus cannot meet the maximum length requirements. Also, RESET# is potentially used to generate a reset configuration selection signal. If PRDY# or RESET# do not meet the layout requirements for Low Power GTL+, then they must be terminated using dual-ended termination at 120. Higher resistor values can be used if
Mobile Pentium® II Processor CPUID
The CPUID instruction does not distinguish between ® the Mobile Pentium II and Pentium II processors. After a power-on RESET, or when the CPUID instruction is executed, the EAX register contains the values shown in Table 2.4.
Table 2.4 Mobile Pentium II Processor CPUID Reserved 31:14 X Type 13:12 0 Family 11:8 6 Model 7:4 5 Stepping 3:0 X
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
ELECTRICAL SPECIFICATIONS The Mobile Pentium II Processor System Signals
TRST#. All PC Compatibility signals (CMOS inputs) can be applied asynchronously. The CMOS, Clock, APIC and TAP inputs can be driven from ground to 2.5V. The FERR#, IERR#, APIC and TAP outputs are open drain and should be pulled up to 2.5V using resistors with the values shown in Table 3.2. If open drain drivers are used for input signals, then they should also be pulled up to 2.5V using resistors with the values shown in Table 3.2.
Table 3.1 lists the Mobile Pentium II processor system signals by type. All Low Power GTL+ signals are synchronous with the BCLK signal. All TAP signals are synchronous with the TCK signal except
Table 3.1 System Signal Groups Group Name Low Power GTL+ Input Low Power GTL+ Output Low Power GTL+ I / O Signals BPRI#, DEFER#, RESET#, RS2:0#, RSP#, TRDY# PRDY# A35:3#, ADS#, AERR#, AP1:0#, BERR#, BINIT#, BNR#, BP3:2#, BPM1:0#, BR0#, D63:0#, DBSY#, DEP7:0#, DRDY#, HIT#, HITM#, LOCK#, REQ4:0#, RP# A20M#, FLUSH#, IGNNE#, INIT#, LINT0 / INTR, LINT1 / NMI, PREQ#, PWRGOOD, SLP#, SMI#, STPCLK#
CMOS Input
Open Drain Output Thermal Sensor Clock
FERR#, IERR# SMBALERT#, SMBCLK, SMBDATA BCLK PICCLK PICD1:0
APIC Clock APIC I / O
TAP Input
TCK, TDI, TMS, TRST#
TAP Output
Power / Other NOTES:
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Table 3.2 Recommended Pull-Up Resistors for Open Drain Signals Recommended Resistor Value () 150 680 1K 4.7K NOTES: 1. TRST# should be pulled to ground with a 680 to 1k resistor. PICD1:0, TDI, TDO STPCLK# INIT#, TCK, TMS Open Drain Signal
A20M#, FERR#, FLUSH#, IERR#, IGNNE#, LINT0 / INTR, LINT1 / NMI, PREQ#, PWRGOOD, SLP#, SMI#
processor installed. If these pins are not used for voltage sense or processor presence sense, then they should be connected to VCC, VCCP and VSS, respectively. 3.1.3. TEST ACCESS PORT (TAP) CONNECTION The TAP interface is an implementation of the IEEE 1149.1 ("JTAG") standard. Due to the voltage levels supported by the TAP interface, it is ® recommended that the Mobile Pentium II processor and the other 2.5V JTAG specification compliant devices be last in the JTAG chain after any devices with 3.3V or 5V JTAG interfaces within the system. A translation buffer should be used to reduce the TDO output voltage of the last 3.3 / 5V device down to the 2.5V range that the Mobile Pentium II processor can tolerate. Multiple copies of TMS and TRST# must be provided, one for each voltage level. A Debug Port and connector has been defined in Section 7. It may be placed at the start and end of the JTAG chain containing the processor, with TDI to the first component coming from the Debug Port and TDO from the last component going to the Debug Port. There are no requirements for placement of the Mobile Pentium II processor in the JTAG chain, except for those dictated by voltage requirements of the TAP signals.
Figure 3.0 VCC Ramp Rate Requirement 3.1.2. VOLTAGE SENSE PINS
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
THERMAL SENSOR
then they should be connected to VSS with a 1k resistor. If the local APIC is hardware disabled, then PICCLK and PICD1:0 should be tied to VSS with a 1k resistor. Otherwise PICCLK must be driven with a clock that meets specification (see Table 3.13) and the PICD1:0 pins must be pulled up to 2.5V with 150 resistors, even if the local APIC is not used. 3.1.8. 3.1.8.1. PIN STATE IN LOW POWER STATES System Bus Signals
Within the Mobile Pentium II processor, there is a thermal sensor connected to the SMBus pins. The programming interface for the thermal sensor is ® described in the Mobile Pentium II Processor and ® Pentium II Processor Mobile Module Thermal Sensor Programming Interface Specification. The Mobile Pentium II processor thermal sensor supports an ACPI-compliant system implementation for monitoring the temperature of the processor. The thermal sensor only provides an accurate reading of the processor temperature when the processor is fully powered. The address of the thermal sensor on the processor SMBus is 1001101. 3.1.5. CATASTROPHIC THERMAL PROTECTION The Mobile Pentium II processor does not support catastrophic thermal protection. The thermal sensor must be used to protect the processor and the system against excessive temperatures. 3.1.6. SMBUS PINS
All of the system bus pins have Low Power GTL+ input, output or input / output drivers. Except when servicing snoops, the system bus pins are tri-stated and pulled up by the termination resistors. Snoops are not permitted in the Sleep and Deep Sleep states. 3.1.8.2. PC Compatibility / Sideband Signals
SMBus is a subset of the I C bus / protocol developed 2 by Intel. I C is a two-wire communications bus / protocol developed by Philips. Contact your Intel Field Sales Representative for a copy of the System Management Bus specification. 3.1.7. UNUSED PINS
The PC compatibility input pins are allowed to be in either the logic high or low state when the processor is in a low power state. In the Auto Halt and Stop Grant states these signals are allowed to toggle. These input buffers have no internal pull-up or pull-down resistors and system logic can use CMOS or open-drain drivers to drive them. The PC compatibility output pins have open drain drivers and external pull-up resistors are required. One of the two output pins (IERR#) is a catastrophic error indicator and is tri-stated (and pulled-up) when the processor is functioning normally. The FERR# output can be either tri-stated or driven to VSS when the processor is in a low power state depending on the condition of the floating point unit. Since this pin is a DC current path when it is driven to VSS, it is recommended that the software clear or mask any floating point error condition before putting the processor into the Deep Sleep state. 3.1.8.3. Other Signals
All RESERVED pins must be unconnected. Unused Low Power GTL+ inputs, outputs and bi-directional signals should be individually connected to VCC with 120 pull-up resistors. Unused CMOS active low inputs should be connected to 2.5V and unused active high inputs should be connected to VSS. Unused open-drain outputs should be unconnected. If the processor is configured to enter the Quick Start state rather than the Stop Grant state, then the SLP# pin should be connected to 2.5V. When tying any signal to power or ground, a resistor will allow for system testability. For unused pins, it is suggested that 10k resistors be used for pull-ups and 1k resistors be used for pull-downs. If the VID3:0 pins are not used
The system bus clock (BCLK) must be driven in all of the low power states except the Deep Sleep state. The APIC clock (PICCLK) must be driven whenever BCLK
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
is driven unless the APIC is hardware disabled or the processor is in the Sleep State. Otherwise, it is permitted to turn off PICCLK by holding it at VSS. The system bus clock should be held at VSS when it is stopped in the Deep Sleep state. In the Auto Halt and Stop Grant states the APIC bus data pins (PICD1:0) may toggle due to APIC bus messages. These pins are required to be tri-stated and pulled-up when the processor is in the Quick Start, Sleep or Deep Sleep states unless the APIC is hardware disabled. The state of the SMBus pins is determined by the policy embodied in the SMBus host controller. The thermal sensor can be accessed in all processor states as long as power is applied to the processor.
rising edge of the BCLK input. The Mobile Pentium II processor core frequency is a multiple of the BCLK frequency. The ratio between the core frequency and the BCLK frequency is configured when the processor is manufactured. Multiplying the bus clock frequency is necessary to increase performance while allowing for easier distribution of signals within the system. Clock multiplication within the processor is provided by the internal Phase Lock Loop (PLL), which requires a constant frequency BCLK input. During Reset, or on exit from the Deep Sleep state, the PLL requires some amount of time to acquire the phase of BCLK. This time is called the PLL lock latency, which is specified in Section 3.6.
3.4. 3.2. Decoupling Requirements
Maximum Ratings
The Mobile Pentium II processor has high frequency decoupling capacitors on all three power planes, but additional bulk decoupling capacitance is required. The amount of bulk decoupling required to meet the processor voltage tolerance requirement is a strong function of power supply design. Contact your Intel Field Sales Representative for tools to help determine how much decoupling is required. The cache bus power plane (VCCP) requires 50 to 100 µF of decoupling. The L2 cache of the Mobile Pentium II processor requires 100 µF of decoupling on the 3.3V power plane (VCC3) in addition to the decoupling required by the other 3.3V system components. For the Low Power GTL+ pull-up resistors, one 0.1µF high frequency decoupling capacitor is recommended per resistor pack. There should be no more than eight pull-up resistors per resistor pack.
Table 3.3 contains the Mobile Pentium II processor stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating conditions are provided in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields.
DC Specifications
System Bus Clock and Processor Clocking
Table 3.4 through Table 3.7 list the DC specifications ® for the Mobile Pentium II processor. Specifications are valid only while meeting specifications for case temperature, clock frequency and input voltages. Care should be taken to read all notes associated with each parameter.
The 2.5V BCLK input directly controls the operating speed of the system bus interface. All system bus timing parameters are specified with respect to the
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Table 3.3 Mobile Pentium II Processor Absolute Maximum Ratings Symbol TStorage VCC(Abs) Parameter Storage Temperature Supply Voltage with respect to VSS Min -40 -0.5 Max 85 VID voltage + 1.0 3.0 4.0 VCC + 0.7 3.3 6.0 5 5 Unit °C V Notes
L2 cache I / O voltage Tag RAM and PBSRAM core voltage Low Power GTL+ Buffer DC Input Voltage with respect to VSS 2.5V Buffer DC Input Voltage with respect to VSS SMBus Buffer DC Input Voltage with respect to VSS VID pin current VSS sense pin current
1. Parameter applies to the Low Power GTL+ signal groups only. 2. Parameter applies to PC Compatibility, APIC and TAP bus signal groups only. 3. Parameter applies to SMBCLK, SMBDATA and SMBALERT# signals. 4. When used as a processor presence detect signal.
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
VCC, LP
-120 mV +190 mV
VCCP VCC3 ICC
ICCP ICC3 ICC, DSLP ICCP, DSLP ICC3, DSLP dICC / dt dICC3 / dt NOTES:
ICC for VCCP (L2 cache I / O buffers) ICC for VCC3 (Tag RAM and PBSRAM cores) Processor core Deep Sleep leakage current Processor L2 cache bus I / O Deep Sleep leakage current Processor L2 cache core and thermal sensor Deep Sleep leakage current Core power supply current slew rate L2 core power supply current slew rate
VCC, max and 95°C 6 core temperature VCCP, max and 115°C 6 core temperature VCC3, max and 115°C 6 core temperature
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
The signals on the Mobile Pentium II processor system bus are included in the Low Power GTL+ signal group. These signals are specified to be terminated to VCC. The termination and reference voltage specifications for these signals are listed in ® Table 3.5. The Mobile Pentium II processor requires external termination and generates its own VREF the information in Table 3.5 is provided for system design.
The DC specifications for the Low Power GTL+ signals are listed in Table 3.6. Refer to the Mobile ® Pentium II Processor System Bus Layout Guideline for full details of system VTT and VREF requirements. The Clock, PC Compatibility and TAP pins are designed to interface at 2.5V CMOS levels to allow connection to other devices. The DC specifications for these 2.5V tolerant pins are listed in Table 3.7.
Parameter Bus Termination Voltage Input Reference Voltage
Nom VCC
Max VCC, MAX
Units V V
Notes
Min -0.3 / 9VTT + 0.2 -
Notes See Table 3.5
See VTT max in Table 3.5
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Notes
All outputs are opendrain
IOL ILI NOTES:
Output Low Current Input Leakage Current
AC Specifications
SYSTEM BUS, CLOCK, APIC, TAP AND PC COMPATIBILITY AC SPECIFICATIONS
The system bus timings specified in this section are ® defined at the Mobile Pentium II processor connector. Table 3.8 through Table 3.16 provide Mobile Pentium II processor AC specifications. The AC specifications are divided into the following categories: Tables 3.8 contains the system bus clock specifications Table 3.9 contains the processor core
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Figure
Notes guideline
Notes
Active and Inactive states
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5. These inputs may be driven asynchronously. However, to guarantee recognition on a specific clock, the setup and hold times with respect to BCLK must be met. 6. A20M#, IGNNE#, INIT# and FLUSH# can be asynchronous inputs, but to guarantee recognition of these signals following an I / O write instruction, they must be valid with the TRDY# assertion of the corresponding bus transaction. 7. INTR and NMI function as PC Compatibility signals only when the APIC is disabled otherwise, they function as LINT1:0 signals. The PC Compatibility signal AC specifications apply in either case. 8. To use the I / O instruction restart feature of the Mobile Pentium II processor, the SMI# signal must meet these setup and hold specifications at the clock edge two system bus clocks before the RS2:0# assertion of the bus transaction for the I / O instruction. 9. This specification only applies when the APIC is enabled and the LINT1 or LINT0 pin is configured as an edge-triggered interrupt with fixed delivery otherwise specification T14 applies. 10. When driven inactive, or after VCC, VCCP, VCC3 and BCLK become stable. PWRGOOD must remain below VIL, max from Table 3.7 until all the voltage planes meet the voltage tolerance specifications in Table 3.4 and BCLK has met the BCLK AC specifications in Table 3.8 for at least 10 clock cycles. PWRGOOD must rise glitch-free and monotonically to 2.5V. 11. If the BCLK signal meets its AC specification within 150 ns of turning on then the PWRGOOD Inactive Pulse Width specification (T15) is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD must still remain below VIL, max until all the voltage planes meet the voltage tolerance specifications. Table 3.12 Reset Configuration AC Specifications Symbol T16 Parameter Reset Configuration Signals (A15:5#, BR0#, FLUSH#, INIT#, PICD0) Setup Time Reset Configuration Signals (A15:5#, BR0#, FLUSH#, INIT#, PICD0) Hold Time Reset PLL Lock Latency Min 4 Max Unit
BCLKs 3.5
T18 NOTE:
1. T19 and T20, although valid for other systems, are not relevant in mobile systems.
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Table 3.13 APIC Bus Signal AC Specifications Symbol T21 T22 T23 T24 T25 T26 T27 T28 T29 NOTES: Parameter PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Low Time PICCLK Rise Time PICCLK Fall Time PICD1:0 Setup Time PICD1:0 Hold Time PICD1:0 Valid Delay Min 2 30 12.0 12.0 1 1 8.5 3.0 3.0 12.0 5 5 Max 33.3 500 Unit MHz ns ns ns ns ns ns ns ns
Notes
1. All AC timings for APIC signals are referenced to the PICCLK rising edge at VIL at the processor connector pins. All CMOS signals are referenced at 1.25V at the processor connector pins. 2. The minimum frequency is 2 MHz when PICD0 is at 2.5V at reset. If PICD0 is strapped to VSS at reset then the minimum frequency is 0 MHz. 3. Referenced to PICCLK Rising Edge. 4. For open drain signals, Valid Delay is synonymous with Float Delay. 5. Valid delay timings for these signals are specified into 150 to 2.5V and 50 pF.
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Notes
1.7V 0.7V
(0.7V-1.7V) (1.7V-0.7V)
Asynchronous
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Parameter Stop Grant Cycle Completion to Clock Stop Stop Grant Cycle Completion to Input Signals Stable Clock Start to PLL Lock STPCLK# Hold Time from PLL Lock Input Signal Hold Time from STPCLK# Deassertion
Min 100
Unit BCLKs
Figure 3.9 3.9 3.9 3.9 3.9
Notes
ns µs ns BCLKs
Notes
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Figures 3.1 through 3.10 are to be used in conjunction with Tables 3.8 through 3.16.
BCLK at Connector T1B BCLK at Core
VIL, BCLK
1.25V
Figure 3.1 BCLK Connector to Core Offset
Th Tr VIH CLK VIL Tf Tl Tp 1.25V
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
CLK Tx Signal V Valid Tpw Valid Tx
CLK Ts Th
Signal
V Valid
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RESET#
Configuration (A15:5, BR0#, FLUSH#, INIT#, PICD0)
Tw Valid
VCCP, , VCC, VREF
PWRGOOD
VIL, max Ta
VIH, min Tb
RESET#
D0007-00
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
TDI, TMS
1.25V Tr Ts
Input Signals
Output Signals
TRST#
1.25V Tq
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Normal BCLK
Running
Quick Start
Deep Sleep
Quick Start
Running
Normal
STPCLK#
CPU bus
stpgnt
Tw Tz Frozen
Compatibility Signals
Changing
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Normal BCLK
Running
Stop Grant Sleep
Deep Sleep
Sleep
Running
Stop Grant Normal
STPCLK#
CPU bus
stpgnt Tt Tw Tx
Tu Tz Frozen Changing
Compatibility Signals
Changing
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SYSTEM SIGNAL SIMULATIONS
Many scenarios have been simulated to generate a set of Low Power GTL+ layout guidelines which are ® available in the Mobile Pentium II Processor System Bus Layout Guideline. All waveforms described in this section are simulated at the pad on the processor core. Systems must be simulated using the IBIS model to determine if they are compliant with this specification. A set of signal quality guidelines are also provided. Violations of these guidelines are allowed but if they occur, then simulations of signal quality at the processor core should be performed to ensure that no violations of the signal quality specifications occur. Meeting the guideline does not guarantee meeting the specification.
signal quality for BCLK as measured at the processor connector. The timings illustrated in Figure 4.2 are taken from Tables 3.8. BCLK is a 2.5V clock.
Low Power GTL+ Signal Quality Specifications
System Bus Clock (BCLK) Signal Quality Specifications
Table 4.1 and Figure 4.1 show the signal quality for the system bus clock (BCLK) signal as simulated at the processor core. Table 4.2 and Figure 4.2 show the
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Table 4.1 BCLK Signal Quality Specifications at the Processor Core Symbol V1 V2 V3 V4 V5 VIL, BCLK VIH, BCLK VIN Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback BCLK rising / falling slew rate NOTES: 1. At the core, BCLK must rise / fall monotonically between VIL, BCLK and VIH, BCLK. 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. 0.8 1.8 -0.7 1.8 0.7 4.4 3.5 Parameter Min Max 0.7 Unit V V V V V V / ns Figure 4.1 4.1 4.1 4.1 4.1
Notes
Undershoot, Overshoot Absolute Value Absolute Value
Figure 4.1 BCLK Generic Clock Waveform at the Processor Core
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Table 4.2 BCLK Signal Quality Guidelines at the Processor Connector Symbol V1 V2 V3 V4 V5 V6 V7 NOTE: 1. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH, BCLK (rising) or VIL, BCLK (falling) voltage limits. VIL, BCLK VIH, BCLK VIN Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback Tline Ledge Voltage Tline Ledge Oscillation 0.7 1.8 -0.5 1.8 0.6 1.8 0.1 3.3 Parameter Min Max 0.6 Unit V V V V V V V Figure 4.2 4.2 4.2 4.2 4.2 4.2 4.2 Overshoot, Undershoot Absolute Value Absolute Value
Notes
Figure 4.2 BCLK Generic Clock Waveform at the Processor Connector
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Table 4.3 Low Power GTL+ Signal Group Ringback Specification at the Processor Core Symbol
Overshoot Minimum Time at High Amplitude of Ringback Final Settling Voltage Duration of Sequential Ringback
Parameter
Figure
Notes
NOTES: 1. Specified for the edge rate of 0.3 - 0.8 V / ns. See Figure 4.3 for the generic waveform. 2. All values determined by design / characterization. 3. Ringback below VREF +100 mV is not authorized during low-to-high transitions. Ringback above VREF -100 mV is not authorized during high-to-low transitions.
Clk Ref VREF+0.2V VREF Vstart VIL, BCLK Clk Ref Clock
VREF-0.2V
Time Note: High to Low case is analogous.
Figure 4.3 Low-to-High, Low Power GTL+ Receiver Ringback Tolerance
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Table 4.4 Low Power GTL+ Signal Group Ringback Guideline at the Processor Connector Symbol
Overshoot Minimum Time at High Amplitude of Ringback Final Settling Voltage Duration of Sequential Ringback
Parameter
100 1.5 -250 250 N / A mV ns mV mV ns
Figure
Notes
NOTES: 1. Greek letter symbols in Figure 4.3 refer to the values in Table 4.3 and Table 4.4. 2. Specified for the edge rate of 0.3 - 0.8 V / ns. See Figure 4.3 for the generic waveform. 3. All values determined by design / characterization. 4. Ringback below VREF +250 mV is not authorized during low-to-high transitions. Ringback above VREF -250 mV is not authorized during high-to-low transitions.
Non-Low Power GTL+ Signal Quality Specifications
Signals driven on the Mobile Pentium II processor system bus should meet signal quality specifications to ensure that the components read data properly and that incoming signals do not affect the long term reliability of the component. There are three signal quality parameters defined: overshoot / undershoot, ringback and settling limit. All three signal quality parameters are shown in Figure 4.4 for non-GTL+ signal groups. 4.3.1. OVERSHOOT / UNDERSHOOT GUIDELINES Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage or below VSS. The overshoot / undershoot guideline limits transitions beyond VCC or VSS due to the fast signal
edge rates. (See Figure 4.4 for non-GTL+ signals.) The processor can be damaged by repeated overshoot events on 2.5V tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). However, excessive ringback is the dominant detrimental system timing effect resulting from overshoot / undershoot (i.e., violating the overshoot / undershoot guideline will make it difficult to satisfy the ringback specification). The overshoot / undershoot guideline is 0.8V and assumes the absence of diodes on the input. These guidelines should be verified in simulations without the on-chip ESD protection diodes present because the diodes will begin clamping the 2.5V tolerant signals beginning at approximately 1.25V above VCC and 0.5V below VSS. If the signals are not reaching the clamping voltage, this will not be an issue. A system should not rely on the diodes for overshoot / undershoot protection as this will negatively affect the life of the components and make meeting the ringback specification very difficult.
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Falling-Edge Ringback Settling Limit
VSS Time Undershoot
Figure 4.4 Non-GTL+ Overshoot / Undershoot and Ringback 4.3.2. RINGBACK SPECIFICATION
SETTLING LIMIT GUIDELINE
Ringback refers to the amount of reflection seen after a signal has switched. The ringback specification is the voltage that the signal rings back to after achieving its maximum absolute value. Excessive ringback can cause false signal detection or extend the propagation delay. The ringback specification applies to the input pin of each receiving agent. Violations of the signal Ringback specification are not allowed under any circumstances for the non-GTL+ signals. Ringback can be simulated with or without the input protection diodes that can be added to the input buffer model. However, signals that reach the clamping voltage should be evaluated further. Table 4.5 and Table 4.6 provide signal ringback specifications for non-GTL+ signals at the processor core and at the processor connector, respectively.
Settling limit defines the maximum amount of ringing at the receiving pin that a signal may reach before its next transition. The amount allowed is 10 percent of the total signal swing (VHI-VLO) above and below its final value. A signal should be within the settling limits of its final value, when either in its high state or low state, before its next transition. Signals that are not within their settling limit before transitioning are at risk of unwanted oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be done either with or without the input protection diodes present. Violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing increasing in the subsequent transitions.
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Table 4.5 Signal Ringback Specifications for Non-GTL+ Signals at the Processor Core Input Signal Group Non-GTL+ Signals Non-GTL+ Signals Transition 01 10 Maximum Ringback (with Input Diodes Present) 1.7 V 0.7 V 4.4 4.4 Figure
Table 4.6 Signal Ringback Guidelines for Non-GTL+ Signals at the Processor Connector Input Signal Group Non-GTL+ Signals Non-GTL+ Signals Transition 01 10 Maximum Ringback (with Input Diodes Present) 1.7 V 0.7 V 4.4 4.4 Figure
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
MECHANICAL SPECIFICATIONS Connector Mechanical Specifications
Mechanical Specification of the Mobile Pentium® II Processor
The Mobile Pentium II processor is enclosed by stainless steel (300-series) covers however, the
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PIN A1
LARGE KEY
RECEPTACLE AND CAP OUTLINE
PLUG KEEPOUT OUTLINE PACKAGE KEEPOUT OUTLINE
V0034-00
Figure 5.1 Mini-Cartridge Assembly and Connector Keepout Location, Top View (in mm)
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
It is important that the processor not be disassembled or permanently altered in any way (e.g., adding extra holes) in order to facilitate system thermal solution attachment. Functionality of a processor is not guaranteed if its cover has been removed. The addition of adhesives and greases to the exterior surfaces of the product is not considered to be permanent.
Figure 5.2 shows a cross-sectional view of the Mobile Pentium II processor. Figure 5.3 through ® Figure 5.5 illustrate the Mobile Pentium II processor assembly top and bottom cover dimensions and standoff locations.
OEM Thermal Plate
Top Cover (recess)
Processor Core
Processor Substrate
System Electronics Substrate Bottom Cover
Figure 5.2 Mobile Pentium II Processor Cross-sectional View
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Figure 5.3 Mini-Cartridge Assembly, Top Cover (in mm)
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Figure 5.4 Mini-Cartridge Assembly, Bottom Cover and Sides (in mm)
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-L46.89 41.91 29X 1.27 7X 1.27
LARGE KEY
V0035-00
Figure 5.5 Standoff and Connector Location, Top View (in mm)
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Parameter Processor Core Die Dimensions Processor Insertion Force Processor Extraction Force Allowable Pressure On Die For Thermal Attach Plate (TAP) Allowable Pressure on Recessed Part of the Top Cover Mechanical Shock Under Nonoperating Conditions Mechanical Vibration Under Nonoperating Conditions Sine Sweep Random
Max 10.84, 11.97 133 100 411 411 50 1.0 3.1
Unit mm N N kPa kPa G G rms G rms
Notes
Mil Std 810E Method 516 Mil Std 810E Method 514
Parameter Processor Height Plug Height Bottom Cover Height
Min 4.40 0.91
Nom 4.55 1.03 2.81 REF
Max 4.70 1.15
Units mm mm mm
Figure 5.6 5.6 5.6 5.6
Bond-Line Thickness
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V0030-00
Figure 5.6 Cross Sectional View with Vertical Dimensions
Table 5.3 Mobile Pentium II Processor Dimension Definitions Symbol H M P BLT SH BS BC Parameter Processor Height Plug Height Bottom Cover Height Bond-Line Thickness Assembly Stack Height Board-to-Board Spacing Bottom Clearance Definition Distance from the top surface of the processor to the mating surface of the plug. Distance from the bottom of the processor substrate to the mating surface of the plug. Distance from the bottom side of the processor substrate to the bottom outer surface of the processor. Distance between the top surface of the die and the top surface of the processor. Distance from the top surface of the processor to the system electronics substrate. Distance from the processor substrate to the system electronics substrate. Distance from the bottom surface of the processor to the system electronics substrate.
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Mobile Pentium® II Processor Pin Lists
Table 5.4 shows the Mobile Pentium II processor signals by pin location. Table 5.5 lists the signals by pin name.
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Table 5.5 Mobile Pentium II Processor Pin Listing Pin Name A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# Pin G21 G25 G22 G23 F27 F25 G24 F24 E25 E26 E24 E27 D22 D25 D24 D27 B25 A24 B24 C22 C23 A22 E21 B21 B22 B23 E20 C21 D21 Signal Type Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Pin Name A32# A33# A34# A35# A20M# ADS# AERR# AP0# AP1# BCLK BERR# BINIT# BNR# BP2# BP3# BPM0# BPM1# BPRI# BR0# D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# Pin B20 F19 C20 E19 C18 H25 B28 A29 D30 G29 C19 A3 H21 F1 B3 G1 C3 F21 E29 E15 D15 G15 B15 C14 F15 F14 G14 D14 E14 Signal Type Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O CMOS Input Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O System Bus Clock Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ Input Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O
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Table 5.5 Mobile Pentium II Processor Pin Listing (Continued) Pin Name D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# Pin C13 F13 B13 G13 A13 D13 B12 A12 E12 D11 C12 D12 C11 E13 F12 B11 C10 D10 F10 E11 G11 B10 E10 B9 A7 C9 C8 E8 A9 B7 Signal Type Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Pin Name D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DEP0# DEP1# DEP2# DEP3# Pin A6 B5 C5 D9 B8 C6 D6 C7 D7 D4 G10 E6 B6 E5 E7 F4 G5 E4 G7 F7 G9 G8 F6 G6 A27 H26 E9 H6 H5 H9 Signal Type Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ Input Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
Table 5.5 Mobile Pentium II Processor Pin Listing (Continued) Pin Name DEP4# DEP5# DEP6# DEP7# DRDY# FERR# FLUSH# HIT# HITM# IERR# IGNNE# INIT# INTR LOCK# NMI PICCLK PICD0 PICD1 PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESET# RP# RS0# RS1# RS2# Pin H7 H10 G4 H8 D28 A18 G17 F30 E30 A19 E17 D18 F3 E23 C30 H2 G2 G12 E1 C1 E16 H23 H27 H22 A28 C25 E18 G19 F18 G18 F28 Signal Type Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O CMOS Output CMOS Input Low Power GTL+ I / O Low Power GTL+ I / O CMOS Output CMOS Input CMOS Input CMOS Input Low Power GTL+ I / O CMOS Input APIC Clock Input CMOS I / O CMOS I / O Low Power GTL+ Output CMOS Input CMOS Input Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ I / O Low Power GTL+ Input Low Power GTL+ I / O Low Power GTL+ Input Low Power GTL+ Input Low Power GTL+ Input Pin Name RSP# RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SLP# SMBALERT# SMBCLK SMBDATA SMI# STPCLK# TCK TDI TDO TMS TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC Pin C26 A16 A17 B14 B16 C15 C16 D16 E22 G27 H24 D17 C2 B30 B29 B19 B18 F17 C17 G16 B17 G26 F16 A4 A10 A21 A25 B27 C27 D19 F9 Signal Type Low Power GTL+ Input Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CMOS Input Thermal Alert SMBus Clock SMBus I / O CMOS Input CMOS Input TAP Clock Input TAP Input TAP Output TAP Input Low Power GTL+ Input TAP Input Core VCC Core VCC Core VCC Core VCC Core VCC Core VCC Core VCC Core VCC
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MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
THERMAL SPECIFICATIONS
Table 6.1 Mobile Pentium II Processor Power Specifications Symbol TDPPROC Parameter Thermal Design Power (Processor) Thermal Transfer Power @ 300 MHz @ 266 MHz @ 233 MHz @ 300 MHz @ 266 MHz @ 233 MHz Typ -
Notes Processor (core & L2 cache)
TDPTT
Core only
PSGNT PQS PDSLP NOTES:
Stop Grant and Auto Halt power Quick Start and Sleep power Deep Sleep power
Processor, at 50°C Processor, at 50°C Processor, at 50°C
REV 2.0
INTEL CORP.
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
PROCESSOR INITIALIZATION AND CONFIGURATION Description
APIC ENABLE
If the PICD0 pin is sampled low on the active-toinactive transition of the RESET# signal then the PICCLK pin can be tied to VSS. Otherwise the PICD1:0 pins must be pulled up to 2.5V and PICCLK must be supplied. Driving PICD0 low at reset also has the effect of clearing the APIC Global Enable bit in the APIC Base MSR. This bit is normally set when the processor is reset, but when it is cleared the APIC is completely disabled until the next reset.
Clock Frequencies and Ratios
MOBILE PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, AND 300 MHZ
APPENDIX A. SIGNAL REFERENCE A.1 Alphabetical Signal Reference
on both agents on the Mobile Pentium II processor system bus. AERR# (I / O - Low Power GTL+) The AERR# (Address Parity Error) signal is observed ® and driven by both Mobile Pentium II processor system bus agents, and if used, must be connected to the appropriate pins of both agents on the Mobile Pentium II processor system bus. AERR# observation is optionally enabled during power-on configuration if enabled, a valid assertion of AERR# aborts the current transaction. If AERR# observation is disabled during power-on configuration, a central agent may handle an assertion of AERR# as appropriate to the error handling architecture of the system. AP1:0# (I / O - Low Power GTL+) The AP1:0# (Address Parity) signals are driven by the request initiator along with ADS#, A35:3#, REQ4:0# and RP#. AP1# covers A35:24#. AP0# covers A23:3#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP1:0# should be connected to the appropriate pins on both agents on the Mobile Pentium II processor system bus. BCLK (I - 2.5V tolerant) The BCLK (Bus Clock) signal determines the system ® bus frequency. Both Mobile Pentium II processor system bus agents must receive this signal to drive their outputs and latch their inputs on the BCLK rising edge. All external timing parameters are specified with respect to the BCLK signal. BERR# (I / O - Low Power GTL+) The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by either Mobile Pentium II processor system bus agents, and must be connected to the appropriate pins of both agents, if used. However,