MH16D72AKLB-10,75 1,207.959,552-BIT (16,777,216-WORD 72-BIT) Doub

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MH16D72AKLB-10,75 1,207.959,552-BIT (16,777,216-WORD 72-BIT) Doub

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MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
DESCRIPTION
MH16D72AKLB 16777216 word 72-bit Double Data Rate(DDR) nchronous DRAM mounted module. This consists industry standard nchronous DRAMs TSOP with SSTL_2 interf which achiev high speed data rate 133MHz. This socket-ty memory odule suitable main memory computer systems easy interchange modules.
93pin
1pin
FEATURES
Max. Frequency Access Time [component level]
Type name
MH16D72AKLB-75 MH16D72AKLB-10
133MHz 100MHz
0.75ns 0.8ns
Utilizes industry standard Synchronous DRAMs TSOP package industry standard Registered Buffer TSSOP package industry standard TSSOP package. Vdd=Vddq=2.5v ±0.2V
144pin 145pin
52pin 53pin
Double data rate architecture; data transf clock Bidirectional, data strobe (DQS) transmitted/receiv with data erential clock inputs (CK0 /CK0) data data mask erenced both edges /CAS latency 2.0/2.5 (programmable) Burst length- 2/4/8 (programmable) Auto precharge bank precharge controlled 4096 resh /64ms Auto resh Self resh address A0-11 Column address A0-9 SSTL_2 Interf Module 1bank Conf igration Burst sequential/interleav e(programmable) Commands entered each positiv edge
184pin
92pin
APPLICATION
Main memory unit PCserver
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
CONFIGURATION
NAME VREF DQS0 RESET DQS1 VDDQ DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 DQ18 VDDQ DQ19 DQ24 DQ25 DQS3 DQ26 DQ27 DQ32 VDDQ DQ33 DQS4 DQ34 DQ35 DQ40 VDDQ DQ41 /CAS DQS5 DQ42 DQ43 DQ48 DQ49 VDDQ DQS6 DQ50 DQ51 VDDID DQ56 NAME DQS8 NAME DQ57 DQS7 DQ58 DQ59 VDDQ VDDQ DQ12 DQ13 DQ14 DQ15 CKE1 VDDQ DQ20 DQ21 DQ22 DQ23 DQ36 DQ37 DQ38 DQ39 DQ44 /RAS DQ45 VDDQ DQ46 DQ47 VDDQ DQ52 DQ53 NAME DQ28 DQ29 VDDQ DQ30 DQ31 VDDQ /CK0 VDDQ NAME DQ54 DQ55 VDDQ DQ60 DQ61 DQ62 DQ63 VDDQ VDDSPD
Connected
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21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
Block Diagram
/RS0 DQS0 DQS1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8
BA0-BA1 A0-A11 /RAS /CAS CKE0 /PCK /RS0 SDRAMs D0-D8 RBA0-RBA1 SDRAMs D0-D8 RA0-RA11 SDRAMs D0-D8 /RRAS SDRAMs D0-D8 /RCAS SDRAMs D0-D8 /RCKE0 SDRAMs D0-D8 /RWE SDRAMs D0-D8
DQS4
DQ32 DQ33 DQ34 DQ35
DQ36 DQ37 DQ38 DQ39 DQS5 DQ40 DQ41 DQ42 DQ43
DQ44 DQ45 DQ46 DQ47
SERIAL
DQS6
DQ48 DQ49 DQ50 DQ51
VDDQ
DQ52 DQ53 DQ54 DQ55 DQS7 DQ56 DQ57 DQ58 DQ59
VREF VDDID
VDDID: OPEN VDDQ VDDQ
PCK0 SDRAMs D0-D8, Registered Buffer /PCK0 SDRAMs D0-D8, Registered Buffer
DQ60 DQ61 DQ62 DQ63
/CK0
/RESET
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION
SYMBOL TYPE DESCRIPTION
Clock: /CK0 erential clock inputs. address control input signals sampled crossing positiv edge negativ edge /CK0. Output (read) data erenced crossings /CK0 (both directions rossing). Clock Enable: CKE0 controls SDRAM internal clock. When CKE0 low, internal clock ollowing ceased. CKE0 also used select auto self resh. After self resh mode started, CKE0 becomes nchronous input. Self resh maintained long CKE0 low. ical Bank Select: When high, command means Operation.
CK0,/CK0
Input
CKE0
Input
/RAS, /CAS,
Input Input
Combination /RAS, /CAS, defines basic commands.
A0-11 specif Column Address conjunction with BA0,1. Address specif A0-11. Column Address specif A0-9. also used indicate precharge option. When high read write command, auto precharge perf ormed. When high precharge command, banks precharged.
Bank Address: BA0,1 specifies four banks SDRAM which command applied. BA0,1 must with ACT, PRE, READ, WRITE commands.
A0-11
Input
BA0,1 0-64 DQS0-8 DM0-8 Vdd, VddQ, VssQ Vddspd Vref RESET SA0-2 VDDID
Input Input Output Input Output Input Power Supply Power Supply Power Supply Input Input
Data Input/Output: Data
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered write data. Used capture write data.
Masks write data when high, issued concurrently with input data. Both have write latency clock once write command registered into SDRAM.
Power Supply memory array peripheral circuitry. VddQ VssQ supplied Output Buffers only. Power Supply SSTL_2 reference voltage.
This signal nchronous driv register order guarantee register outputs low. This bidirectional used transf data into EEPROM. resistor must connected line pullup. This signal used clock data into EEPROM. resistor connected time pullup. These signals tied system planar either conf igure serial EEPROM address range. identif ication
Input Output
Input Input
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
BASIC FUNCTIONS
MH16D72AKLB provides basic functions, bank (row) activate, burst read write, bank (row) precharge, auto self refresh. Each command defined control signals /RAS, /CAS rising edge. addition signals, ,CKE0 used chip select, refresh option, precharge option, respectively. know detailed definition commands, please command truth table.
/CK0 /RAS /CAS CKE0
Chip Select L=select, H=deselect Command Command Command resh Option @ref resh command Precharge Option @precharge read/write command basic commands
Activate (ACT) [/RAS /CAS =/WE command activates idle bank indicated Read (READ) [/RAS /CAS READ command starts burst read from active bank indicated First output data appears after /CAS latency. When this command, bank deactivated after burst read (auto-precharge,READA) Write (WRITE) [/RAS /CAS =/WE WRITE command starts burst write active bank indicated Total data length written burst length. When this command, bank deactivated after burst write (auto-precharge, WRITEA). Precharge (PRE) [/RAS /CAS command deactivates active bank indicated This command also terminates burst read /write operation. When this command, banks deactivated (precharge all, PREA). Auto-Refresh (REFA) [/RAS =/CAS =CKE0 REFA command starts auto-refresh cycle. Refresh address including bank address generated internally. After this command, banks precharged automatically.
MIT-DS-0397-1.3 21.Mar.2001
MITSUBISHI ELECTRIC
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
TRUTH TABLE
COMMAND Deselect Operation Address Entry Bank Activate Single Bank Precharge Precharge Banks Column Address Entry Write Column Address Entry Write with Auto-Precharge Column Address Entry Read Column Address Entry Read with Auto-Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register MNEMONIC DESEL PREA WRIT CKE0 CKE0 /RAS /CAS BA0,1 A0-9, note
WRITEA
READ
READA REFA REFS REFSX TERM
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: Applies only read bursts with autoprecharge disabled; this command undefined (and should used) read bursts with autoprecharge enabled, write bursts. BA0-BA1 select either Base Extended Mode Register (BA0 selects Mode Register; selects Extended Mode Register; other combinations BA0-BA1 reserved; A0-A11 provide op-code written selected Mode Register.
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE
Current State IDLE ACTIVE READ (AutoPrecharge Disabled) /RAS /CAS Op-Code, Mode-Add Op-Code, Mode-Add Address Command DESEL TERM ILLEGAL Action Notes
READ WRITE ILLEGAL PREA REFA DESEL TERM READ READA WRITE WRITEA PREA REFA DESEL TERM Bank Active, Latch Auto-Refresh Mode Register Begin Read, Latch Determine Auto-Precharge Begin Write, Latch Determine Auto-Precharge Bank Active ILLEGAL Precharge Precharge ILLEGAL ILLEGAL (Continue Burst END) (Continue Burst END) Terminate Burst Terminate Burst, Latch READ READA Begin Read, Determine Auto-Precharge WRITE WRITEA PREA REFA
Op-Code, Mode-Add
ILLEGAL Bank Active ILLEGAL Terminate Burst, Precharge ILLEGAL ILLEGAL
MIT-DS-0397-1.3
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21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State WRIT (AutoPrecharge Disabled) /RAS /CAS Address Command DESEL TERM Action (Continue Burst END) (Continue Burst END) ILLEGAL Terminate Burst, Latch READ READA Begin Read, Determine AutoPrecharge WRITE WRITEA PREA REFA DESEL TERM Terminate Burst, Latch Begin Write, Determine AutoPrecharge Bank Active ILLEGAL Terminate Burst, Precharge ILLEGAL ILLEGAL (Continue Burst END) (Continue Burst END) ILLEGAL Notes
READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE MIT-DS-0397-1.3
Op-Code, Mode-Add Op-Code, Mode-Add Op-Code, Mode-Add
READ READA ILLEGAL WRITE WRITEA PREA REFA DESEL TERM ILLEGAL Bank Active ILLEGAL PRECHARGE/ILLEGAL ILLEGAL ILLEGAL (Continue Burst END) (Continue Burst END) ILLEGAL
READ READA ILLEGAL WRITE WRITEA PREA REFA ILLEGAL Bank Active ILLEGAL PRECHARGE/ILLEGAL ILLEGAL ILLEGAL 21.Mar.2001
MITSUBISHI ELECTRIC
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State CHARGING ACTIVATING WRITE RECOVERING /RAS /CAS Op-Code, Mode-Add Op-Code, Mode-Add Op-Code, Mode-Add Address Command DESEL TERM Action (Idle after tRP) (Idle after tRP) ILLEGAL Notes
READ WRITE ILLEGAL PREA REFA DESEL TERM ILLEGAL (Idle after tRP) ILLEGAL ILLEGAL (Row Active after tRCD) (Row Active after tRCD) ILLEGAL
READ WRITE ILLEGAL PREA REFA DESEL TERM ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
READ WRITE ILLEGAL PREA REFA ILLEGAL ILLEGAL ILLEGAL ILLEGAL
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State REFRESHING MODE REGISTER SETTING /RAS /CAS Op-Code, Mode-Add Op-Code, Mode-Add Address Command DESEL TERM Action (Idle after tRC) (Idle after tRC) ILLEGAL Notes
READ WRITE ILLEGAL PREA REFA DESEL TERM ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Idle after tRSC) (Idle after tRSC) ILLEGAL
READ WRITE ILLEGAL PREA REFA ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation NOTES: entries assume that CKE0 High during preceding clock cycle current clock cycle. ILLEGAL bank specified state; function legal bank indicated depending state that bank. Must satisfy contention, turn around, write recovery requirements. bank precharging idle state. precharge bank indicated ILLEGAL bank idle. ILLEGAL Device operation and/or data-integrity guaranteed.
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE
Current State SELFREFRESH CKE0 CKE0 POWER DOWN BANKS IDLE STATE other than listed above ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: CKE0 High transition will re-enable other inputs asynchronously minimum setup time must satisfied before command other than EXIT. Power-Down Self-Refresh entered only from Banks Idle State. Must legal command. /RAS /CAS INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL (Maintain Self-Refresh) INVALID Exit Power Down Idle (Maintain Self-Refresh) Refer Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer Current State =Power Down Refer Function Truth Table Begin Suspend Next Cycle Exit Suspend Next Cycle Maintain Suspend Action Notes
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
SIMPLIFIED STATE DIAGRAM
POWER APPLIED
POWER
PREA
CHARGE
REFS
SELF REFRESH
REFSX REFA
MODE REGISTER
IDLE
AUTO REFRESH
CKEL CKEH
Active Power Down
CKEH
POWER DOWN
CKEL
ACTIVE
WRITE WRITE WRITEA READA READ READ READ
BURST STOP
WRIT
READ
TERM
WRITEA READA
READA
WRITEA
READA
CHARGE Automatic Sequence Command Sequence MIT-DS-0397-1.3 21.Mar.2001
MITSUBISHI ELECTRIC
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
POWER SEQUENCE
Before starting normal operation, following power sequence necessary prevent SDRAM from damaged multifunctioning. Apply before same time VDDQ Apply VDDQ before same time Vref Maintain stable condition 200us after stable power CLK, apply DSEL Issue precharge command banks device Issue EMRS Issue Mode Register reset Issue more Auto Refresh commands Maintain stable condition cycle After these sequence, SDRAM idle state ready normal operation.
MODE REGISTER
Burst Length, Burst Type /CAS Latency programmed setting mode register (MRS). mode register stores these data until next command, which issued when banks discrete idle state. After tMRD from command, DIMM ready command. /CK0 /RAS /CAS LTMODE A11-A0 /CAS Latency Burst Length
Latency Mode
Burst Type
Sequential Interleaved
Reset
Reserved Future
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
EXTENDED MODE REGISTER
disable enable mode programmed setting extended mode register (EMRS). extended mode register stores these data until next EMRS command, which issued when banks discrete idle state. After tMRD from EMRS command, DIMM ready command.
/CK0 /RAS /CAS
A11-A0
Disable
enable disable
Drive Strength
Normal Weak
Disable Enable
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
Componennt Level /CLK Command Address /CAS Latency
Read
Write
Burst Length
Burst Length
Initial Address
Sequential
Column Addressing Interleaved
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
ABSOLUTE AXIMUM RATINGS
Symbol VddQ Topr Tstg Parameter Supply Voltage Supply Voltage Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature 25°C Conditions with respect with respect VssQ with respect with respect VssQ Ratings -0.5 -0.5 -0.5 Vdd+0.5 -0.5 VddQ+0.5 Unit
OPERATING CONDITIONS
(Ta=0 70°C
Symbol VddQ Vref VIH(DC) VIL(DC) VIN(DC)
unless otherwise noted)
Limits Parameter Supply Voltage Supply Voltage Output Input Reference Voltage High-Level Input Voltage Low-Level Input Voltage Input Voltage Level, /CK0 Min. 1.15 Vref 0.18 -0.3 -0.3 0.36 Vref 0.04 Typ. 1.25 Max. 1.35 VddQ+0.3 Vref 0.18 VddQ VddQ Vref 0.04 Unit Notes
VID(DC) Input Differential Voltage, /CK0 Termination Voltage
CAPACITANCE
(Ta=0 70°C Symbol CI(A) CI(C) CI(K) CI/O VddQ 0.2V, VssQ unless otherwise noted) Parameter Input Capacitance, address Input Capacitance, control Input Capacitance, Input Capacitance, Test Condition
1.25V =100MHz 25mVrm
Limits(max.) 15.3 13.3
Unit Notes
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
AVERAGE SUPPLY CURRENT from
(Ta=0 70°C
VddQ 0.2V, VssQ Output Open, unless otherwise noted)
Parameter/Test Conditions Limits(max) Unit Notes
IDD0
OPERATING CURRENT: Bank; Activ e-Precharge; MIN; MIN; inputs changing twice clock address control inputs changing once clock OPERATING CURRENT: Bank; Activ e-Read-Precharge; Burst MIN; 2.5; MIN; IOUT= mA;Address control inputs changing once clock PRECHARGE POWER-DOWN STANDBY CURRENT: banks idle; power-down mode; (MAX); IDLE STANDBY CURRENT: (MIN); banks idle; (MIN); MIN; Address other control inputs changing once clock ACTIVE POWER-DOWN STANDBY CURRENT: bank activ power-down mode; (MAX); ACTIVE STANDBY CURRENT: (MIN); (MIN); bank; Activ e-Precharge; MAX; MIN; DQ,DM inputs changing twice clock address other control inputs changing once clock OPERATING CURRENT: Burst Reads; Continuous burst;One bank activ Address control inputs changing once clock 2.5; MIN; IOUT
1390
1273
IDD1
1435
1318
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
1930
1768
OPERATING CURRENT: Burst Writes; Continuous burst; bank activ Address control inputs changing once clock IDD4W 2.5; MIN; inputs changing twice clock IDD5 IDD6 AUTO REFRESH CURRENT: (MIN) SELF REFRESH CURRENT: 0.2V
1885
1723
2110
1948
OPERATING CONDITIONS CHARACTERISTICS
(Ta=0 70°C Symbol VddQ 0.2V, VssQ unless otherwise noted) Parameter/Test Conditions Limits Min. Vref 0.35 Vref 0.35 0.5*V DDQ-0.2 0.5*V DDQ+0.2 Max. Unit Notes 21.Mar.2001
VIH(AC) High-Level Input Voltage (AC) VIL(AC) Low-Level Input Voltage (AC) VID(AC) Input Differential Voltage, /CLK VIX(AC) Input Crossing Point Voltage, /CLK Off-state Output Current floating Vo=0~V Input Current VIN=0 VddQ
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
TIMING REQUIREMENTS (Component Level)
(Ta=0 70°C VddQ 0.2V, VssQ unless otherwise noted)
Characteristics Parameter Output Valid data delay time CLK//CLK Min. -0.75 -0.75 0.45 0.45 min(tCL, CL=2.5 time CL=2 tDIPW tDQSQ tDQSQA tDQSS tDQSH tDQSL tDSS tDSH tMRD Input Setup time (DQ,DM) Input Hold time(DQ,DM) input pulse width each input) Data-out-high impedance time CLK//CLK Data-out-low impedance time CLK//CLK DQS-DQ Skew(f associated signals) DQS-DQ Skew(f signals) data Valid window DQ/DQS output hold time Write command irst latching transition input High width input width alling edge setup time alling edge hold time Mode Register command time 0.35
tHP-0.75
Max. +0.75 +0.75 0.55 0.55 Min. -0.8 -0.8 0.45 0.45
Max. +0.8 +0.8 0.55 0.55 Unit +0.8 +0.8 +0.6 +0.6 0.35
tHP-1.0
Notes
tDQSCK Output Valid data delay time CLK//CLK High width width half period
min(tCL, +0.75 +0.75 +0.5 +0.5 -0.8 -0.8
1.75 -0.75 -0.75
0.75 0.35 0.35 0.25
1.25
0.75 0.35 0.35
1.25
tWPRES Write preamble setup time tWPST tWPRE tRPST tRPRE Write postamble Write preamble Input Setup time (address control) Input Hold time (address control) Read postamble Read preamble
0.25
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MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
TIMING REQUIREMENTS(Continues)
(Ta=0 70°C VddQ 0.2V, VssQ unless otherwise noted) Characteristics Symbol tRAS tRFC tRCD tRRD tDAL tXSNR tXSRD tXPNR tXPRD tREFI Active time Cycle time(operation) Auto Ref. Active/Auto Ref. command period Column Delay Precharge time Delay time Write Recovery time Auto Precharge write recovery precharge time Internal Write Read Command Delay Exit Self Ref. non-Read command Exit Self Ref. -Read command Exit Power down command Exit Power down -Read command Average Periodic Refresh interval Parameter Min. 15.6 Max. 120,000 Min. 15.6 Max. 120,000 Unit Notes
Output Load Condition
component measurement)
VREF
10cm
50ohm
VREF
Zo=50 30pF
Output Timing Measurement Reference Point
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
Notes
voltages referenced Vss. Tests timing, IDD, electrical, characteristics, conducted nominal reference/supply voltage levels, related specifications device operation guaranteed full voltage range specified. timing tests swing 1.5V test environment, input timing still referenced VREF crossing point CK//CK), parameter specifications guaranteed specified input levels under normal conditions. minimum slew rate input signals 1V/ns range between VIL(AC) VIH(AC). input level specifications defined SSTL_2 Standard (i.e. receiver will effectively switch result signal crossing input level, will remain that state long signal does ring back above (below) input (HIGH) level. VREF expected equal 0.5*VddQ transmitting device, track variations level same. Peak-to-peak noise VREF exceed +/-2% value. applied directly device. system supply signal termination resistors, expected equal VREF, must track variations level VREF. magnitude difference between input level input level /CLK. value expected equal 0.5*VddQ transmitting device must track variations level same. Enables on-chip refresh address counters. specification tested after device properly initialized. This parameter sampled. VddQ +2.5V+/-0.2V, +2.5V+/-0.2V, =100MHz, VOUT(DC)= VddQ/2, VOUT(PEAK PEAK) 25mV, inputs grouped with pins reflecting fact that they matched laoding faciliate trace matching board level). CLK//CLK input reference level (for signals other than CLK//CLK) point which /CLK cross; input reference level signals other than CLK//CLK, VREF. Inputs recognized valid until VREF stabilized. Exception: during period before VREF stabilizes, CKE=< 0.3VddQ recognized LOW. transitions occur same access time windows valid data transitions. These parameters referenced specific voltage level, specify when device output longer driving (HZ), begins driving (LZ). maximum limit this parameter device limit. device will operate with greater value this parameter, system performance (bus turnaround) will degrade accordingly. specific requirement that valid (HIGH, LOW, some point valid transition) before this edge. valid transition defined monotonic, meeting input slew rate specifications device. When writes were previously progress bus, will transitioning from High-Z logic LOW. previous write progress, could HIGH, LOW, transitioning from HIGH this time, depending tDQSS. maximum eight AUTO REFRESH commands posted given SDRAM device. tXPRD should tCLK condition unstable operation during power down mode. command/address /CLK slew rate >1.0V/ns. Min(tCL, tCH)refers smaller actual clock time actualclock high time provided device.
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
(Component Level) Read Operation /CLK Add.
tDQSCK tRPRE Valid Data tRPST VREF
tDQSQ
Write Operation tDQSS=max. /CLK
tDQSS tWPRES tWPRE tDSS
tWPST
tDQSL
tDQSH
Write Operation tDQSS=min. /CLK
tDQSS tWPRES tWPRE tDQSL tDQSH tDSH tWPST
MIT-DS-0397-1.3 21.Mar.2001
MITSUBISHI ELECTRIC
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
OPERATIONAL DESCRIPTION
BANK ACTIVATE SDRAM four independent banks. Each bank activated command with bank addresses (BA0,1). indicated address A11-0. minimum activation interval between bank other bank tRRD. aximum commands allowed within tRC,although number banks which active concurrently limited. PRECHARGE command deactivates bank indicated BA0,1. When multiple banks active, precharge command (PREA,PRE+A10=H) available deactivate them same time. After from precharge, command same bank issued. Bank Activation Precharge (BL=8, CL=2 (Discrete level))
Module input output timing. /CLK
command tRCmin tRCmin tRAS tRCD BL/2
Command
tRRD
READ
A0-9,11-12
BA0,1
Precharge
precharge command issued BL/2(Discrete) from read command without data loss.
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
READ After tRCD from bank activation, READ command issued. Output data available after /CAS Latency from READ, followed (BL-1) consecutive data when Burst Length start address specified A11,A9-A0, address sequence burst data defined Burst Type. READ command applied active bank, precharge time (tRP) hidden behind continuous output data interleaving multiple banks. When high READ command, auto-precharge(READA) performed. command(READ,WRITE,PRE,ACT) same bank inhibited till internal precharge complete. internal precharge starts BL/2 after READA. next command issued after (BL/2+tRP) from previous READA. Multi Bank Interleaving READ (BL=8, CL=2(Discrete level))
Module input output timing. /CLK Command A0-9,11 BA0,1
tRCD
READ
READ
Burst Length Module /CAS latency (Discrete
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
READ with Auto-Precharge (BL=8, CL=2(Discrete))
Module input output timing. /CLK Command A0-9,11-12 BA0,1
BL/2 tRCD READ BL/2
Internal precharge start (BL/2+1 case Module)
READ Auto-Precharge Timing (BL=8)
Module input output timing. /CLK Command Module CL=3.5 Discrete CL=2.5
READ BL/2
CL=3
CL=2
Internal Precharge Start Timing case module, Precharge start BL/2+1)
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
WRITE After tRCD from bank activation, WRITE command issued. input data from WRITE command with data strobe input, following (BL-1) data written into when Burst Length start address specified A11,A9-A0, address sequence burst data defined Burst Type. WRITE command applied active bank, precharge time (tRP) hidden behind continuous input data interleaving multiple banks. From last data command, write recovery time (tWRP) required. When high WRITE command, auto-precharge(WRITEA) performed. command(READ,WRITE,PRE,ACT) same bank inhibited till internal precharge complete. next command issued after tDAL from last input data cycle.
Module input output timing. /CLK Command A0-9,11 BA0,1
Multi Bank Interleaving WRITE (BL=8)
WRITE
WRITE
Module input output timing. /CLK Command A0-9,11 BA0,1
WRITE with Auto-Precharge (BL=8)
WRITE tDAL
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
BURST INTERRUPTION [Read Interrupted Read] Burst read operation interrupted read bank. Random column access allowed. READ READ interval minimum 1CLK.
Module input output timing. /CLK Command A0-9,11 BA0,1
READ READ
Read Interrupted Read (BL=8, CL=2(Discrete))
READ
READ
Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 5Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7
[Read Interrupted precharge] Burst read operation interrupted precharge same bank. READ interval minimum CLK. command output disable latency equivalent /CAS Latency. result, READ interval determines valid data length output. figure below shows examples BL=8.
Module input output timing. /CLK Command
READ
Read Interrupted Precharge (BL=8)
Module CL=3.5 Discrete CL=2.5
Command Command
READ READ
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
Read Interrupted Precharge (BL=8)
Module input output timing. /CLK Command
READ
Module CL=3.0 Discrete CL=2.0
Command Command
READ READ
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
[Read Interrupted Burst Stop] Burst read operation interrupted burst stop command(TERM READ TERM interval minimum CLK. TERM command output disable latency equivalent /CAS Latency. result, READ TERM interval determines valid data length output. figure below shows examples BL=8.
Read Interrupted TERM (BL=8)
Module input output timing. /CLK Command
READ
TERM
Module CL=3.5 Discrete CL=2.5
Command Command Command
READ
TERM
READ
TERM
READ TERM
Module CL=3.0 Discrete CL=2.0
Command Command
READ TERM READ
TERM
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
[Read Interrupted Write with TERM]
Read Interrupted TERM (BL=8)
/CLK Command
READ
TERM
WRITE
CL=2.5
Command
READ
TERM
WRITE
CL=2.0
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
[Write interrupted Write] Burst write operation interrupted write bank. Random column access allowed. WRITE WRITE interval minimum CLK. Write Interrupted Write (BL=8) Module input output timing.
/CLK Command A0-9,11 BA0,1
Dai0 Dai1 Daj0 Daj1 Daj2 Daj3 Dal0 Dal1 Dal2 Dal3 Dal4 Dal5 Dal6 Dal7
WRITE WRITE
WRITE
WRITE
[Write interrupted Read] Burst write operation interrupted read same other bank. Random column access allowed. Internal WRITE READ command interval(tWTR) minimum CLK. input data interrupting READ cycle "don't care". tWTR referenced from first positive edge after last data input.
Module input output timing. /CLK Command A0-9,11 BA0,1
WRITE
Write Interrupted Read (BL=8, CL=2.5(Discrete))
READ
Dai0 Dai1
tWTR
Qaj0 Qaj1 Qaj2 Qaj3 Qaj4 Qaj5 Qaj6 Qaj7
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
[Write interrupted Precharge] Burst write operation interrupted precharge same bank. Random column access allowed. referenced from first positive edge after last data input.
Write Interrupted Precharge (BL=8, CL=2.5)
Module input output timing. /CLK Command A0-9,11 BA0,1
Dai0 Dai1
WRITE
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
[Initialize Mode Register sets]
/CLK
Command A0-9,11 BA0,1
EMRS
Code
Code
Code
Code
Code
Code
tMRD
tMRD
tRFC
tRFC
tMRD
[AUTO REFRESH] Single cycle auto-refresh initiated with REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. refresh address generated internally. 4096 REFA cycles within 64ms refresh 128M bits memory cells. auto-refresh performed banks concurrently. Before performing auto refresh, banks must idle state. Auto-refresh auto-refresh interval minimum tRFC command must supplied device before tRFC from REFA command. Auto-Refresh
/CLK /RAS /CAS A0-11 BA0,1
tRFC DESELECT
Auto Refresh Banks
MIT-DS-0397-1.3
Auto Refresh Banks
21.Mar.2001
MITSUBISHI ELECTRIC
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
REFRESH] Self -refresh mode entered issuing REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L). Once self-refresh initiated, maintained long kept low. During self-refresh mode, asynchronous only enable input, other inputs including disabled ignored, that power consumption synchronous inputs saved. exit self-refresh, supplying stable inputs, asserting DESEL command then asserting longer than tXSNR/tXSRD.
Self-Refresh
/CLK /RAS /CAS A0-11 BA0,1
tXSNR Self Refresh Exit tXSRD
Read
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21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
[Asynchronous REFRESH] Asynchronous Self -refresh mode entered CKE=L within tCLK after issuing REFA command (/CS=/RAS=/CAS=L,/WE=H). Once self-refresh initiated, maintained long kept low. During self-refresh mode, asynchronous only enable input, other inputs including disabled ignored, that power consumption synchronous inputs saved. exit self-refresh, supplying stable inputs, asserting DESEL command then asserting longer than tXSNR/tXSRD.
Asynchronous Self-Refresh
/CLK /RAS /CAS A0-11 BA0,1
tCLK
tXSNR Self Refresh Exit
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
[Power DOWN] purpose suspend power down. synchronous input except during self-refresh mode. command cycle ignored. From CKE=H normal function, recovery time required condition stable operation during power down mode. Power Down
/CLK Command
Standby Power Down
Valid
Command
Active Power Down
tXPNR/ tXPRD
Valid
CONTROL] defined data mask writes. During writes,DM masks input data word word. write mask latency Function(BL=8,CL=2(Discrete))
Module input output timing. /CLK Command
Write READ
Don't Care
masked DM=H
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MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table
Byte Function described Number Serial Bytes Written during Production Total bytes memory device Fundamental memory type Addresses this assembly Column Addresses this assembly Module Banks this assembly Data Width this assembly. Data Width continuation Voltage interface standard this assembly
SDRAM Cycletime Max. Supported Latency (CL).
enrty data Bytes SDRAM 1BANK SSTL2.5V 7.5ns 8.0ns +0.75ns +0.8
DATA(hex)
Cycle time CL=2.5 SDRAM Access from Clock CL=2.5 DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type SDRAM width,Primary DRAM Error Checking SDRAM data width
MIimum Clock Delay, Random Column Access
15.625uS/SR clock 4bank 2.0,
Registered with Differential Clock 0.2V
Burst Lengths Supported Number Device Banks CAS# Latency Latency Latency SDRAM Module Attributes SDRAM Device Attributes:General SDRAM Cycle time(2nd highest latency) Cycle time CL=2
SDRAM Access form Clock(2nd highest latency)
10ns 10ns +0.75ns +0.8ns Undefined Undefined Undefined Undefined 20ns 15ns 20ns
CL=2
SDRAM Cycle time(3rd highest latency)
SDRAM Access form Clock(3rd highest latency)
Minimum Precharge Time (tRP) Minimum Active Active Delay (tRRD) Delay Minv (tRCD)
45ns 50ns
Active Precharge (tRAS)
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table
Density each bank module
128MByte
0.9nS 1.1nS 0.9nS 1.1nS 0.5nS 0.6nS 0.5nS 0.6nS
1CFFFFFFFFFFFFFF
Command Address signal input setup time Command Address signal input hold time
36-61
Data signal input setup time Data signal input hold time Superset Information (may used future) Revision
option Check
Checksum bytes 0-62 Check
64-71
Manufactures Jedec code JEP-108E
MITSUBISHI
Manufacturing location
Manufacturing Location
73-90
Manufactures Part Number
MH16D72AKLB-75 MH16D72AKLB-10
91-92 93-94 95-98 99-127 128-255
Revision Code Manufacturing date Assembly Serial Number Reserved Open Customer
revision year/week code serial number Undefined Undefined
rrrr yyww ssssssss
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MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
EEPROM Components A.C. D.C. Characteristics
Symbol Parameter Supply Voltage Supply Voltage Input High Voltage Input Voltage Output Voltage Min. Vccx0.7 Limits Typ. Max. Vcc+0.5 Vccx0.3 Units
EEPROM A.C.Timing Parameters (Ta=0 70°C
Symbol fSCL TBUF THD:STA TLOW THIGH TSU:STA THD:DAT TSU:DAT TSU:STO Parameter Clock Frequency Noise Supression Time Constant SCL, inputs Data Valid
Time Must Free before Transmission Start
Limits Min. Max.
Units
Start Condition Hold Time Clock Time Clock High Time Start Condition Setup Time Data Hold Time Data Setup Time Rise Time Fall Time Stop Condition Setup Time Data Hold Time Write Cycle Time
time from valid stop condition write sequence EEPROM internal erase/program cycle.
HIGH
SU:STO SU:STA HD:STA HD:DAT SU:DAT
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MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module 133.35 3.00 3.00
4-R2
1.27 6.35 64.77 73.295
6.35 49.53 128.95
2.50
3.9Max
1.27
MIT-DS-0397-1.3
MITSUBISHI ELECTRIC
21.Mar.2001
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD 72-BIT) Double Data Rate Synchronous DRAM Module
Keep safety first your circuit designs!
Mitsubishi Electric Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) nonflammable material (iii) prevention against malfunction mishap.
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MH16D72AKLB-10,75 1,207.959,552-BIT (16,777,216-WORD 72-BIT) Doub

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