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Pentium Processor Mobile Module: Mobile Module Connector (MMC-2) Featuring Intel SpeedStep Technology
Mobile Pentium processor featuring Intel SpeedStep technology with processor speeds 850/700 MHz, 800/650 MHz, 750/600 MHz, 700/550 MHz, 650/500 MHz, 600/500 On-die, primary 16-K Instruction cache 16-K Write Back Data cache On-die, 256-K cache Eight-way associative Runs speed processor core Fully compatible with previous Intel mobile microprocessors Binary compatible with applications Support technology Supports streaming SIMD Power management features that provide low-power dissipation Quick Start mode Deep Sleep mode Integrated math co-processor Integrated active thermal feedback (ATF) system Programmable trip point interrupt poll mode temperature reading
Intel 82443BX Host Bridge system controller DRAM controller supports 3.3-V SDRAM Supports CLKRUN# protocol SDRAM clock enable support selfrefresh SDRAM during Suspend mode control 3.3V only, Specification, Revision compliant Supports single 66-MHz, 3.3-V device Two-piece thermal transfer plate (TTP) heat dissipation made nickel-plated copper made aluminum Mobile Pentium processor core voltage regulation supports input voltages from 7.5V 21.0V Above peak efficiency Integrated solution
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Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium processor mobile module featuring Intel SpeedStep technology contain design defects errors known errata, which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2000 *Other brands names property their respective owners.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Content1.0 Introduction. References Architecture Overview Signal Information Signal Definitions. 3.1.1 Signal List.6 3.1.2 Memory Signal Description 3.1.3 Signals 3.1.4 Signals.10 3.1.5 Intel SpeedStep Technology Signals 3.1.6 Processor PIIX4E/M Sideband Signals 3.1.7 Power Management Signals 3.1.8 Clock Signals.14 3.1.9 Voltage Signals 3.1.10 JTAG Pins.16 3.1.11 Miscellaneous Pins.16 Connector Assignments Assignments Pentium Processor Mobile Module Featuring Intel SpeedStep Technology Cache 82443BX Host Bridge System Controller 4.3.1 Memory Organization 4.3.2 Reset Strap Options 4.3.3 Interface 4.3.4 Interface.23 Intel SpeedStep Technology Power Management 4.5.1 Clock Control Architecture.23 4.5.1.1 Normal State 4.5.1.2 Auto Halt State 4.5.1.3 Stop Grant State.26 4.5.1.4 Quick Start State 4.5.1.5 HALT/Grant Snoop State 4.5.1.6 Sleep State 4.5.1.7 Deep Sleep State Power Consumption Power Management Modes System Clock Signal Quality Specifications.31 5.1.1 BCLK Specifications.31 5.1.2 BCLK Specifications.31 System Power Requirements.33 Processor Core Voltage Regulation
Functional Description.21
Electrical Specifications.31
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Voltage Regulator Efficiency Voltage Regulator Control Power Planes: Bulk Capacitance Requirements. System Power Supply Circuit Protection. 5.3.4.1 Power System Protection. 5.3.4.2 V_DC Power Supply. 5.3.4.3 Overcurrent Protection 5.3.4.4 Current Limit Shift Point 5.3.4.5 Slew Rate Control 5.3.4.6 Undervoltage Lockout 5.3.4.7 Overvoltage Lockout Active Thermal Feedback Thermal Sensor Configuration Register. Mobile Module Dimensions 6.1.1 Location MMC-2 Connector 6.1.2 Printed Circuit Board 6.1.3 Height Restrictions Thermal Transfer Plate Mobile Module Physical Support. 6.3.1 Mobile Module Mounting Requirements. 6.3.2 Weight Thermal Design Power. 5.3.1 5.3.2 5.3.3 5.3.4
Mechanical Specifications.
Thermal Specification. Labeling Information. Environmental Standards.
Figure1 Block Diagram. MMC-2 Connector Footprint Clock Control States BCLK Waveform Processor Core Pins Efficiency Chart Vcore 1.60V Efficiency Chart Vcore 1.35V Power Sequence Timing V_DC Ripple Current V_DC Power System Protection Block Diagram. Overcurrent Protection Circuit. Current Shift Model Undervoltage Lockout Undervoltage Lockout Model Overvoltage Lockout Overvoltage Lockout Model Recommended Power Supply Protection Circuit System Electronics Simulation V_DC Voltage Skew. Board Dimensions MMC-2 Connector Orientation.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Board Dimensions MMC-2 Connector-Pin Orientation Printed Circuit Board Thickness Height Restrictions 82443BX Thermal Transfer Plate (Reference Only) 82443BX Thermal Transfer Plate Detail.56 Thermal Transfer Plate (Reference Only).57 Standoff Holes, Board Edge Clearance, Containment Ring Product Tracking Code.61
Table1 Connector Signal Summary Memory Signal Descriptions. Signal Descriptions Signal Descriptions.10 Intel SpeedStep Technology Signal Description Processor PIIX4E/M Sideband Signal Descriptions Power Management Signal Descriptions Clock Signal Descriptions.14 Voltage Descriptions JTAG Pins.16 Miscellaneous Descriptions.16 Connector Assignment.17 Connector Specifications.20 Configuration Straps 82443BX Host Bridge System Controller Clock State Characteristics Power Consumption Values Power Consumption Values Power Consumption Values Power Consumption Values IV.30 BCLK Specifications.31 BCLK Specifications Processor Core Pins.31 BCLK Signal Quality Specifications Processor Core.32 System Power Requirements.33 Vcore Power Conversion Efficiency 1.60V.34 Vcore Power Conversion Efficiency 1.35V.34 Voltage Signal Definitions Sequences VR_ON In-rush Current.37 Bulk Capacitance Requirements Power Plane Thermal Sensor SMBus Address Thermal Sensor Configuration Register Thermal Design Power (TDPMODULE) Specification Environmental Standards
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Revision History
Date January 2000 February 2000 Revision Update
Initial Release Revision contains following updates: Section 4.6, which contains power consumption values power management modes Sections accuracy clarity name Section 5.3.4 "System Power Supply Circuit Guidelines" Figure "PW" references were changed "V_DC" note Figure clarification note Figure clarification clarifications were made Section clarifications were made Section 6.3.1 Revision contains following updates: 700/550-MHz processor speed Table "Power Consumption Values Table "BCLK Signal Quality Specifications Processor Core" note updated clarification Table "System Power Requirements" Vcpupu minimal, nominal, maximum values were corrected maximum minimum designators Figure "BCLK Waveform Processor Core Pins" clarity Section 5.3.3, "Power Planes: Bulk Capacitance Requirements" clarity 700/550 TDPmodule values Table "Thermal Design Power Specifications Revision contains following updates: product tracking codes (PTCs) conversion modules. Table "Power Consumption Values Revision contains following updates: 750/600 Table "Power Consumption Values III", which contains power management data C-step. Revision contains following updates: processor speeds 850/700 800/650 Table Table Figure
April 2000
April 2000
2000
September 2000
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Introduction
This document provides technical specifications integrating Intel Pentium processor mobile module with Intel SpeedStep technology connector (MMC-2) into latest notebook systems today's notebook market. Building around this design gives system manufacturer these advantages:
Avoids complexities associated with designing high-speed processor core logic boards. standard interface provides upgrade path from previous Intel mobile modules.
ReferenceRefer following documents additional information relating Pentium processor mobile module with featuring Intel SpeedStep technology.
Mobile Pentium® Processor BGA2 Micro-PGA2 Packages Datasheet (Order
Number 245302)
Intel 440BX AGPSet: 82443BX Host Bridge/Controller Datasheet (Order Number: 290633001)
82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) (Order Number: 290562-001) Intel 82371MB (PIIX4E/M) Specification Update CK97 Clock Synthesizer/Driver Specification (OR-1089) IntelPentium Processor Mobile Module MMC-2 Simulation Validation Rev. (OR-1781) Rev. (OR-1780)
Intel Pentium Processor Mobile Module System Electronics 100-MHz Layout Guidelines Mobile Pentium Processor/440BX AGPset Recommended Design Debug Practice(RDDP-A) Rev. (SC-2760)
66/100MHz SDRAM Unbuffered SO-DIMM Specification Intel Mobile Module Design Guide (AP-590) Pentium® Processor Mobile Module MMC-2 Insertion Extraction User Manual Mobile Pentium Processor Mobile Module 400-Pin Connector Assembly Development Guide Rev. 1.0* Customers Rev. (OR-1385)
Focused Discussion Intel Mobile Modules Design Mfg. Best Methods MHPG
Design Guide (ORMD6-0859) Intel Mobile Module Newsletters Intel Mobile Module Thermal Diode Temperature Sensor Application Note Geyserville Hardware Technical Specification, Revision (OR-1728) Geyserville Software Architecture Specification, Revision (SC-2364) Intel MMC-2 Standoff/Receptacle Height Spreadsheet
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Interface Specification Revision
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Architecture Overview
highly integrated assembly, Pentium processor mobile module featuring Intel SpeedStep technology contains mobile Pentium processor core that runs speeds 850/700 MHz, 800/650 MHz, 750/600 MHz, 700/550 MHz, 650/500, 600/500 with 100-MHz processor system speed (PSB). Intel 440BX AGPset provides immediate system-level support includes PIIX4E/M PCI/ISA Bridge 82443BX Host Bridge. PIIX4E/M provides extensive power management capabilities supports Intel 82443BX Host Bridge. notebook's system electronics must include PIIX4E/M device connect mobile module. features Intel 82443BX Host Bridge include: DRAM controller supporting SDRAM 3.3Vwith burst read 4-1-1-1; CLKRUN# signal request PIIX4E/M regulate clock bus; 82443BX clock enables Self-Refresh mode SDRAM during Suspend mode compatible with SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM) modes power management; E_SMRAM mode supports write-back cacheable SMRAM TTPs mobile Pentium processor 82443BX Host Bridge provide heat dissipation thermal attach points manufacturer's thermal solution. on-board voltage regulator converts system voltage processor's core voltage. Isolating processor voltage requirements allows system manufacturer incorporate different processor variants into single notebook system. Supporting input voltages from 7.5V 21.0V, integrated module voltage regulator enables above peak efficiency de-couples processor voltage requirements from system. Also incorporated active thermal feedback (ATF) sensing, compliant ACPI Specification 1.0. integrated system management (SMBus) compliant thermal sensor supports internal external temperature sensing with programmable trip points. Figure illustrates block diagram Pentium processor mobile module featuring Intel SpeedStep technology.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure Block Diagram
Processor Core Voltage
Mobile Pentium Processor Core
PIIX4E/M Sidebands HI/LO#
SpeedStep Control Logic (V_3)
Voltage Regulator
Control
Sense
PIIX4E/M Sideband
Sideband Pullup (V_CPUPU)
V_DC (7.5V~21.0V
Clock Driver (V_CLK)
HCLK0
82443BX "Northbridge" (V_3)
Memory DCLKWR SMBUS
GCLKO
400-Pin, Board-to-Board Connector
GCLKI
PCLK
DCLKO
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SpeedStep
Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Signal Information
This section provides information signal groups Pentium processor mobile module featuring Intel SpeedStep technology. signals defined compatibility with future Intel mobile modules.
Signal DefinitionTable provides list signals category corresponding number signals each category. proper signal termination, please contact your Intel Field Representative further information.
Table
Connector Signal Summary
Signal Group Memory Processor/PIIX4E/M Sideband SpeedStep Technology Power Management Clocks Voltage: V_DC Voltage: V_3S Voltage: Voltage: Voltage: VCCAGP Voltage: V_CPUPU Voltage: V_CLK ITP/JTAG Module Ground Reserved Total Number Pins
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3.1.1
Signal List
following notations used denote signal type: Input Output Open-drain output requiring pullup resistor Open-drain input requiring pullup resistor Input/Open-drain output requiring pullup resistor Bi-directional input/output
signal description also includes type buffer used particular signal: GTL+ CMOS Open-drain GTL+ interface signal interface signals interface signals CMOS signals, depending functional group, 1.5V, 2.5V, 3.3V.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
3.1.2
Memory Signal Description
Table provides descriptions memory interface signals.
Table
Memory Signal DescriptionName Type CMOS CMOS CMOS Voltage Description Memory Data: These signals carry Memory data during access DRAM. supported Intel mobile modules. Chip Select (SDRAM): These pins activate SDRAMs. SDRAM accepts command when active low. Input/Output Data Mask (SDRAM): These pins synchronized output enables during read cycle byte mask during write cycle. Memory Address (SDRAM): This column address DRAM. 82443BX Host Bridge system controller identical sets address lines (MAA MAB#). mobile module supports only address lines. additional addressing features, please refer Intel 440BX AGPSet: 82443BX Host Bridge/ Controller Datasheet (Order Number: 290633-001). Memory Write Enable (SDRAM): MWEA# should used write enable memory data bus. SDRAM Address Strobe (SDRAM): When active low, this signal latches Address positive edge clock. SRASA# also allows access pre-charge. SDRAM Column Address Strobe (SDRAM): When active low, this signal latches Column Address positive edge clock. SCASA# also allows Column access. SDRAM Clock Enable (SDRAM): SDRAM clock enable pin. When these signals deasserted, SDRAM enters power-down mode. Each individually controlled clock enable. Memory Data: These signals connected DRAM data and, they terminated mobile module.
MECC[7:0]
CSA[5:O]#
DQMA[7:0]
MAB[9:0]# MAB[10] MAB[12:11]# MAB[13] MWEA# CMOS CMOS CMOS CMOS CMOS CMOS
SRASA#
SCASA#
CKE[5:0]
MD[63:0]
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3.1.3
SignalTable provides descriptions interface signals.
Table
Signal DescriptionName Type Voltage Description Address/Data: standard address data lines. This functions same AD[31:0] bus. address driven with FRAME# assertion, data driven received following clocks. Command/Byte Enable: This carries command information during cycles when PIPE# used. During write, this contains byte enable information. command driven with FRAME# assertion, byte enables corresponding supplied requested data driven following clocks. Frame: This signal used during transactions remains deasserted internal pullup resistor. Assertion indicates address phase transfer. Negation indicates that cycle initiator desires more data transfer. Device Select: This signal provides same function DEVSEL#. used during transactions. 82443BX Host Bridge system controller drives this signal when initiator attempting access DRAM. DEVSEL# asserted medium decode time. Initiator Ready: Indicates compliant target ready provide write data current transaction. signal asserted when initiator ready data transfer. Target Ready: This signal indicates compliant master ready provide write data current transaction. signal asserted when target ready data transfer. Stop: This signal provides same function STOP#. used during transactions. Asserted target request master stop current transaction. Request: master requests AGP. Grant: This signal provides same function PCI. Additional information provided ST[2:0] bus. Grant: Permission given master PCI. Parity: single parity provided over GAD[31:0] BE[3:0]. This signal used during transactions. Pipelined Request: This signal asserted current master indicate full width address that queued target. master queues request each rising clock edge while PIPE# asserted. Sideband Address: This provides additional conduit pass address commands 82443BX Host Bridge System Controller from master. Read Buffer Full: This signal Indicates master ready accept previously requested, low-priority read data.
GAD[31:0]
GC/BE[3:0]#
GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GREQ#
GGNT#
GPAR
PIPE#
SBA[7:0]
RBF#
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Table Signal DescriptionName ST[2:0] Type Voltage Description Status Bus: Provides information from arbiter Master what These bits only have meaning when GGNT asserted. Strobes: Provides timing double-clocked data bus. agent providing data drives these signals. These signals identical copies each other. Sideband Strobe: Provides timing sideband bus. SBA[7:0] (AGP master) drives sideband strobe.
ADSTB[B:A]
SBSTB
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3.1.4
SignalTable provides descriptions signals.
Table
Signal DescriptionName AD[31:0] Type Voltage Description Address/Data: standard address data lines. address driven with FRAME# assertion, data driven received following clocks. Command/Byte Enable: command driven with FRAME# assertion, byte enables corresponding supplied requested data driven following clocks. Frame: Assertion indicates address phase transfer. Negation indicates that cycle initiator desires more data transfer. Device Select: 82443BX Host Bridge drives this signal when initiator attempting access DRAM. DEVSEL# asserted medium decode time. Initiator Ready: Asserted when initiator ready data transfer. Target Ready: Asserted when target ready data transfer. Stop: Asserted target request master stop current transaction. Lock: Indicates exclusive operation require multiple transactions complete. When LOCK# asserted, nonexclusive transactions proceed. 82443BX supports lock initiated cycles only. initiated locked cycles supported. Request: master requests PCI. Grant: Permission given master PCI. Hold: This signal comes from expansion bridge. bridge request PCI. 82443BX Host Bridge will drain DRAM write buffers, drain processor-to-PCI posting buffers, acquire host before granting request PHLDA#. This ensures that timing masters. PHOLD# protocol been modified include support passive release. Hold Acknowledge: This signal driven 82443BX Host Bridge grant expansion bridge. PHLDA# protocol been modified include support passive release. Parity: single parity provided over AD[31:0] C/BE[3:0]#.
C/BE[3:0]
FRAME#
DEVSEL#
IRDY# TRDY# STOP#
PLOCK#
REQ[4:0]# GNT[4:0]#
PHOLD#
PHLDA#
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Table Signal DescriptionName Type Voltage Description System Error: 82443BX asserts this signal indicate error condition. further information, refer Intel 440BX AGPSet: 82443BX Host Bridge/Controller Datasheet (Order Number: 290633001). Clock Run: open-drain output input. 82443BX Host Bridge requests central resource, PIIX4E/M, start maintain clock asserting CLKRUN#. 82443BX Host Bridge tristates CLKRUN# upon deassertion reset (since running upon deassertion reset). Reset: When asserted, this signal asynchronously resets 82443BX Host Bridge. signals also tri-state, compliant with Revision Specifications.
SERR#
CLKRUN#
PCI_RST#
CMOS
3.1.5
Intel SpeedStep Technology SignalTable provides Intel speedstep technology signal descriptions.
Table
Intel SpeedStep Technology Signal Description
Name G_LOHI# Type CMOS CMOS Voltage V_3S Description SpeedStep State Transition: Generated system electronics, this signal defines SpeedStep state change SpeedStep state machine. This signal must high rising edge VR_ON. SpeedStep CPU_STP#: CPU_STP# signal must gated system electronics VRCHGNG# then routed G_CPU_STP# connector clock generator. Voltage Changing: SpeedStep state machine signal that indicates that actual state change progress setpoint changed settling. When this signal deasserts, SpeedStep state will settle processor. system electronics will this signal generate force transition deep sleep. Also used gate CPU_STP# system electronics. G_SUS_STAT1#: system electronics uses this signal gate SUS_STAT1# from PIIX4E/M.
G_CPU_STP#
V_3S
VRCHGNG#
CMOS
V_3S
G_SUS_STAT1#
CMOS
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3.1.6
Processor PIIX4E/M Sideband SignalTable provides descriptions processor PIIX4E/M sideband signals.
Table
Processor PIIX4E/M Sideband Signal DescriptionName Type CMOS CMOS CMOS CMOS Voltage Description Numeric Coprocessor Error: This functions FERR# signal supporting coprocessor errors. This signal tied coprocessor error signal processor pulled active processor PIIX4E/M. Ignore Error: This open-drain signal connected Ignore Error processor driven PIIX4E/M. Initialization: INIT# asserted PIIX4E/M processor system initialization. This signal open-drain. Processor Interrupt: INTR driven PIIX4E/M signal processor that interrupt request pending needs serviced. This signal open-drain. Non-Maskable Interrupt: used force non-maskable interrupt processor. PIIX4E/M bridge generates when either SERR# IOCHK# asserted, depending Status Control Register programmed. This signal opendrain. Address Mask: When enabled, this open-drain signal causes processor emulate address wraparound which occurs Intel 8086 processor. System Management Interrupt: SMI# active-low synchronous output from PIIX4E/M that asserted response many enabled hardware software events. SMI# open-drain signal asynchronous input processor. However, this chipset SMI# synchronous PCLK. Stop Clock: STPCLK# active-low, synchronous open-drain output from PIIX4E/M that asserted response many hardware software events. STPCLK# connects directly processor synchronous PCICLK. When processor samples STPCLK# asserted, processor responds entering low-power state (Quick Start). processor will only exit this mode when this signal deasserted.
FERR#
V_CPUPU
IGNNE# INIT#
V_CPUPU V_CPUPU
INTR
V_CPUPU
CMOS
V_CPUPU
A20M#
CMOS
V_CPUPU
SMI#
CMOS
V_CPUPU
STPCLK#
CMOS
V_CPUPU
NOTE: Table V_CPUPU definition.
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3.1.7
Power Management SignalTable provides descriptions power management signals. SM_CLK SM_DATA signals refer two-wire serial SMBus interface. Although this interface currently used solely digital thermal sensor, SMBus contains reserved serial addresses future use.
Table
Power Management Signal DescriptionName SUS_STAT1# Type CMOS Voltage V_3ALWAYS Description Suspend Status: This signal connects SUS_STAT1# output PIIX4E/M. SUS_STAT1# provides information host clock status asserted during suspend states. VR_ON: Voltage regulator This 3.3-V (5.0-V tolerant) signal controls operation voltage regulator. VR_ON should generated function PIIX4E/M SUSB# signal, which used controlling "Suspend State voltage planes. This signal should driven digital signal with rise/fall time less than equal (VIL,max =0.4V, VIH,min =3.0V.) VR_PWRGD: This signal driven high mobile module indicate that voltage regulator stable pulled using 100-K resistor when inactive. used some combinations generate system PWRGOOD signal. Power This signal must active least after power rail stable prior deassertion PCIRST#. Serial Clock: This clock signal used SMBus interface digital thermal sensor. Serial Data: open-drain data signal SMBus interface digital thermal sensor. Interrupt: open-drain output signal digital thermal sensor.
VR_ON
CMOS
VR_PWRGD
BXPWROK
CMOS CMOS CMOS CMOS
SM_CLK SM_DATA ATF_INT#
NOTE: V_3ALWAYS 3.3-V supply generated whenever V_DC available supplied PIIX4E/M resume well.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
3.1.8
Clock SignalTable provides descriptions clock signals.
Table
Clock Signal DescriptionName Type Voltage Description Clock PCLK, input mobile module, system's clocks. This clock used 82443BX Host Bridge logic clock domain. This clock stopped when PIIX4E/M PCI_STP# signal asserted "and/or" during suspend states. Host Clock This clock input mobile module from CK100-M/CK100-SM clock source. processor 82443BX Host Bridge system controller HCLK0. This clock stopped when PIIX4E/M CPU_STP# signal asserted "and/or" during suspend states. Note: signal names HCLK0 BCLK used interchangeably. HCLK1 CMOS CMOS V_CLK Host Clock This clock input mobile module from CK100-M/CK100-SM clock source. HCLK1 implemented mobile module. SDRAM Clock Out: 66-MHz SDRAM clock reference generated internally 82443BX Host Bridge system controller onboard PLL. feeds external buffer that produces multiple copies SODIMMs. SDRAM Read Clock: feedback reference from SDRAM clock buffer. 82443BX Host Bridge System Controller uses this clock when reading data from SDRAM array. DCLKRD implemented mobile module. DCLKWR CMOS CMOS SDRAM Write Clock: feedback reference from SDRAM clock buffer. 82443BX Host Bridge system controller uses this clock when writing data SDRAM array. Clock GCLKIN input feedback reference from GCLKO signal. Clock Out: This signal generated 82443BX Host Bridge system controller onboard from HCLK0 host clock reference. frequency GCLKO MHz. GCLKO output used feed both reference input pins 82443BX Host Bridge system controller device. board layout must maintain complete symmetry loading trace geometry minimize clock skew. Frequency Select: This output indicates desired host clock frequency mobile module.
PCLK
HCLK0
CMOS
V_CLK
DCLK0
DCLKRD
CMOS
GCLKIN
GCLKO
CMOS
CMOS
V_3S
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3.1.9
Voltage SignalTable provides descriptions voltage signals.
Table
Voltage DescriptionName V_DC V_3S Type Number pins Input: 7.5V 21.0V SUSB# controlled 3.3V: power managed 3.3-V supply, output voltage regulator system electronics. This rail during STR, STD, Soff. SUSC# controlled 5.0V: power managed 5.0-V supply. output voltage regulator system electronics. This rail during Soff. SUSC# controlled 3.3V: power managed 3.3-V supply. output voltage regulator system electronics. This rail during Soff. Voltage: This voltage rail implemented mobile module defined upgrade purposes only. Intel recommends that this voltage rail connected system electronics. Processor Ring: mobile module drives V_CPUPU power processor interface signals, such PIIX4E/M opendrain pullups processor/PIIX4E/M sideband signals. V_CPUPU tied 3.3V mobile module. Processor Clock Rail: mobile module drives V_CLK power CK100-M VDDCPU rail. Description
VCCAGP
V_CPUPU
V_CLK
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3.1.10
JTAG PinTable provides descriptions JTAG signals, which system manufacturer implement JTAG chain port desired.
Table JTAG PinName TCLK TRST# FS_PREQ# FS_PRDY# FS_RESET# Type Voltage V_CPUPU Description JTAG Test Data Out: serial output port. instructions data shifted processor from this port. JTAG Test Data serial input port. instructions data shifted into processor from this port. JTAG Test Mode Select: This controls controller change sequence. JTAG Test Clock: testability clock clocking JTAG boundary scan sequence. JTAG Test Reset: This signal asynchronously resets controller processor. Debug Mode Request: This signal driven makes request enter debug mode. Debug Mode Ready: This signal driven processor informs that processor debug mode. Processor Reset: processor reset status ITP. GTL+ Termination Voltage: This used POWERON debug port determine when target system POWERON pulled using resistor VTT. Other signals might this power rail pullup.
NOTE: FS_RESET# FS_PRDY# pulled inside mobile processor core.
3.1.11
Miscellaneous PinTable provides descriptions miscellaneous signal pins.
Table Miscellaneous DescriptionName Module ID[3:0] Ground Reserved Type CMOS RSVD Number Description Module Revision These pins track revision level mobile module. 100-K pullup resistor V_3S must placed system electronics these signals. Section more detail. Ground Unallocated Reserved pins. Reserved pins must connected.
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Connector AssignmentTable lists signals each connector system electronics. Refer Section assignments.
Table Connector Assignment
Number SBA5 GAD25 GAD30 RBF# BXPWROK MD36 MD41 MD43 MD14 MECC4 SCASA# CSA1# SRASA# RESERVED RESERVED RESERVED MAB8# RESERVED MAB13 CKE1 CKE5 RESERVED FS_RESET# FS_PRDY# G_SUS_STAT1# RESERVED ADSTBB GAD24 GAD29 VCCAGP GAD1 RESERVED MD33 MD38 MD42 MD11 MD45 MECC0 MWEA# MID1 DQMA4 CSA2# CSA5# RESERVED MAB4# RESERVED RESERVED MAB11# MID2 CKE2 G_LO/HI# SMCLK SMDAT SBA6 GAD26 GAD4 GAD3 GAD2 MD37 MD40 MD44 ND15 MECC5 DQMA0 MID0 CSA4# MAB0# MAB2# MAB5# RESERVED MAB12# CKE3 MID3 DQMA2 RESERVED MD26 MD58 GAD31 SBA4 GAD27 GAD6 GAD5 ADSTBA CLKRUN# MD32 MD35 MD39 MD10 MD13 ND47 RESERVED DQMA1 DQMA5 CSA3# MAB1# RESERVED RESERVED RESERVED MSB9# RESERVED CKE0 C_CPU_STP# DCLKWR FS_PREQ# MD57 TCLK SBA7 SBA0 GDA8 GC/BE0# GAD7 MD34 MD34 MD12 ND46 RESERVED CSA# RESERVED MAB3# MAB6# MAB7# MAB10 DCLK0 DCLKRD VRCHGNG# DQMA3 MD25 MD60 FERR# IGNNE#
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Table Connector Assignment
Number RESERVED RESERVED V_CPUPU V_CLK RESERVED V_DC V_DC RESERVED V_DC V_DC RESERVED V_3S V_3S V_3S RESERVED V_DC V_DC TRST# V_3S V_3S V_3S RESERVED V_DC V_DC ATF_INT# V_3S V_3S V_3S RESERVED V_DC V_DC
Number
GREQ# GGNT# GAD13 GAD12 GAD10 GAD11 GAD9 VCCAGP MECC1 SERR# AD16 AD19 AD23 AD27 PCI_RST# RESERVED IRDY# GNT1# DQMA6 MECC2
GSTOP# GPAR GAD15 GC/BE1# GAD14 VCCAGP C/BE0# AD10 AD13 TRDY# AD30 AD22 PHOLD# FRAME# GNT2# GNT4# PHLDA# MECC7 MD48
PIP# SBA1 SBA2 GAD16 GAD18 GFRAME# GTRDY# GDEVESEL# AD15 STOP# AD17 AD24 C/BE3# AD20 AD31 REQ2# GNT0# MD50 MD18
SBA3 SBSTB GAD20 GAD17 GC/BE2# GIRDY# VCCAGP AD12 C/BE1# DEVSEL# C/BE2# AD26 AD28 AD29 REQ1# REQ3# REQ4# MD51 MD52
GCLKI CGLK0 GAD23 GC/BE3# GAD22 GAD21 GAD19 GAD28 AD11 AD14 PLOCK# AD18 AD21 PCLK AD25 REQ0# GNT3# MD59 MD54 MD24
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
DQMA7 MECC6 MECC3 MD27 DMI# A20M# RESERVED V_DC V_DC
MD16 MD17 MD49 MD28 MD29 INTR SUS_STAT1# STPCLK# RESERVED V_DC V_DC
MD19 MD21 MD20 MD61 VR_ON VR_PWRGD INIT# RESERVED V_DC V_DC
MD53 MD22 MD62 MD30 RESERVED V_DC V_DC
MD23 MD55 MD56 MD63 MD31 HCLK0 HCLK1 RESERVED V_DC V_DC
AssignmentThe 400-pin MMC-2 connector 1.27-mm pitch style surface mount. Refer Section 6.1.3 size information. Figure shows MMC-2 connector assignments.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure MMC-2 Connector Footprint
400-Pin Connector Footprint Assignment
Table summarizes some connector specifications. Table Connector SpecificationParameter Contact Material Housing Current Voltage Electrical Insulation Resistance Termination Resistance Capacitance Mating Cycles Mechanical Connector Mating Force Contact Unmating Force Thermo-Plastic Molded Compound: 0.5A 20-m maximum 20-mV open circuit with 5-pF maximum contact cycles 50-lbs (22.7 maximum 30-lbs (13.6 maximum Condition Copper Alloy Specification
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Functional Description
Pentium Processor Mobile Module Featuring Intel SpeedStep Technology
Pentium processor mobile module featuring Intel SpeedStep technology runs speeds 850/700 MHz, 800/650 MHz, 750/600 MHz, 700/550 MHz, 650/500 MHz, 600/500 MHz, offers 100-MHz PSB.
Cache
on-die cache eight-way associative, runs speed processor core.
82443BX Host Bridge System Controller
Intel's 82443BX Host Bridge system controller highly integrated device that combines controller, DRAM controller, controller into component. 82443BX Host Bridge multiple power management features designed specifically notebook systems such
CLKRUN#, feature that enables controlling clock off. 82443BX Host Bridge suspend modes, which include Suspend-To-RAM (STR), SuspendTo-Disk (STD), Power-On-Suspend (POS).
System Management (SMRAM) power management modes, which include Compatible
SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM). C_SMRAM traditional SMRAM feature implemented Intel chipsets. E_SMRAM feature that supports write-back cacheable SMRAM space minimize power consumption while system idle, internal 82443BX Host Bridge clock turned (gated off) when there processor activity. This accomplished setting G_CLK enable 82443BX power management register through system BIOS.
4.3.1
Memory Organization
memory interface 82443BX Host Bridge available connector. This allows following:
memory control signals, sufficient support three SO-DIMM sockets
banks SDRAM
signal each bank
Memory features supported 82443BX Host Bridge system controller this product are:
Eight banks memory 256-Mb memory device
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Second memory address lines (MAA[13:0]) Extended Data (EDO) DRAM 66-MHz memory buThe clocking architecture supports SDRAM. tight timing requirements 100-MHz SDRAM clocks, clocking mode SDRAM memory configurations allows host SDRAM clocks generated from same clocking architecture system electronics. complete details about memory device support, organization, size, addressing when using SDRAM memory trace length guidelines, refer Intel® Pentium® Processor Mobile Module System Electronics 100-MHz Layout Guidelines Revision (OR-1780).
4.3.2
Reset Strap OptionSeveral strap options memory address define behavior mobile module after reset. Other straps allowed override default settings. Table shows various straps their implementation.
Table Configuration Straps 82443BX Host Bridge System Controller
Signal MAB[12]# MAB[11]# MAB[10]# MAB[9]# MAB[7]# MAB[6]# Function Host Frequency Select Order Queue Depth Quick Start Select Disable Configuration Host Buffer Mode Select Module Default Setting Strapped high module strap, maximum queue depth Strapped high module Quick Start mode strap (AGP enabled) strap (standard MMC-2 mode) Strapped high mobile module mobile buffers Optional Override System Electronics None None None Strap high disable None None
4.3.3
Interface
interface 82443BX Host Bridge available MMC-2 connector. 82443BX Host Bridge supports Clockrun protocol power management. this protocol, devices assert CLKRUN# open-drain signal when they require interface. Refer Mobile Design Guide complete details Clockrun protocol. 82443BX Host Bridge responsible arbitrating bus. 82443BX Host Bridge support five masters. There five Request/Grant pairs (REQ[4:0]# GNT[4:0]#) available connector. Note: interface MMC-2 connector 3.3V only. devices that 5.0V supported. 82443BX Host Bridge system controller compliant with Specification, which improves worst case access latency from earlier specifications. 82443BX Host Bridge supports only Mechanism accessing configuration space. This implies that signals AD[31:11] available IDSEL signals. However, since 82443BX Host Bridge
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology always device AD11 will never asserted during configuration cycles IDSEL. 82443BX reserves AD12 AGPbus. Thus, AD13 first available address line usable IDSEL. Intel recommends that AD18 used PIIX4E/M.
4.3.4
Interface
82443BX Host Bridge system controller compliant with Interface Specification Revision 2.0, which supports asynchronous interface coupling 82443BX core frequency. interface achieve real data throughput excess second using graphics device. Actual bandwidth vary depending specific hardware software implementations.
Intel SpeedStep Technology
Intel Speedstep technology allows processor switch between core frequencies without resetting processor changing system frequency. processor ratios programmed instead one. lower frequency mode maximizes battery life, higher frequency mode provides processor performance similar desktop Pentium processor systems. high performance mode should used when system connected external power source because this mode requires more power. More cooling required well. example, necessary switch from passive active cooling when using high performance mode. more detailed technical information regarding Intel SpeedStep technology, refer Geyserville Hardware Technical Specification Rev. (OR-1728) Geyserville Software Architecture Specification (SC-2364).
4.5.1
Power Management
Clock Control Architecture
clock control architecture been optimized notebook designs. clock control architecture consists seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant Snoop, Sleep, Deep Sleep. Auto Halt state provides low-power clock state that controlled through software execution instruction. Quick Start state provides very low-power, low-exit latency clock state that used hardware controlled "idle" states. Deep Sleep state provides extremely low-power state that used Power-On-Suspend states, which alternative shutting processor's power. exit latency Deep Sleep state Stop Grant state Quick Start clock states mutually exclusive. example, strapping option signal A15# chooses which state entered when STPCLK# signal asserted. Strapping A15# signal ground Reset enables Quick Start state. Otherwise, asserting STPCLK# signal puts processor into Stop Grant state. Table provides information clock control states, Figure illustrates clock control architecture. Performing state transitions shown Figure neither recommended supported.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Table Clock State CharacteristicClock State Normal Auto Halt Stop Grant Approximately clocks clocks Through Snoop, HALT/Grant Snoop state: immediate Through STPCLK#, Normal state: clocks clocks after snoop activity Stop Grant state clocks Exit Latency Snooping System Uses Normal program execution Software controlled entryidle mode Hardware controlled entry/exit mobile throttling Hardware controlled entry/exit mobile throttling Supports snooping low-power states Hardware controlled entry/exit desktop idle mode support Hardware controlled entry/exit mobile support Notes Note Note Notes
Quick Start
Note
HALT/Grant Snoop Sleep
Note
Notes
Deep Sleep
Note
NOTES: Intel mobile modules support Sleep Stop Grant states. These values 100% tested specified 50°C design characterization. This value 100% tested specified 35°C design characterization. Specifications labeled available.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure Clock Control StateSTPCLK#
Normal State
HS=false
(!STPCLK# !HS) RESET# halt cycle halt break STPCLK# !STPCLK#
Quick Start
BCLK stopped BCLK
STPCLK# !QSE (!STPCLK# !HS) stop break !STPCLK# STPCLK# !QSE
Auto Halt
HS=true
Snoop serviced
Snoop occur
Deep Sleep
Snoop occurs Snoop serviced Snoop occurs Snoop serviced
Stop Grant
HALT/Grant Snoop
SLP# !SLP# RESET# BCLK stopped
BCLK !QSE
Sleep
NOTES: Halt break A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI# instruction executed Processor Halt State Quick Start State Enabled Stop Grant Acknowledge cycle issued Stop break BINIT#, FLUSH#, RESET# Intel mobile modules support shaded clock control state
4.5.1.1
Normal State
Normal state normal operating mode where processor's core clock running, processor actively executing instructions.
4.5.1.2
Auto Halt State
This low-power mode entered processor through execution instruction. power level this mode similar Stop Grant state. transition Normal state made halt break event (one following signals going active: NMI, INTR, BINIT#, INIT#, RESET#, FLUSH#, SMI#).
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Asserting STPCLK# signal while Auto Halt state will cause processor transition Stop Grant state Quick Start state, where Stop Grant Acknowledge cycle will issued. Deasserting STPCLK# will cause processor return Auto Halt state without issuing Halt cycle. SMI# (System Management Interrupt) recognized Auto Halt state. return from handler either Normal state Auto Halt state. Intel® Architecture Software Developer's Manual, Volume III: System Programmer's Guide more information. Halt cycle issued when returning Auto Halt state from System Management Mode (SMM). FLUSH# signal serviced Auto Halt state. After flushing on-chip, processor will return Auto Halt state without issuing Halt cycle. Transitions A20M# PREQ# signals recognized while Auto Halt state.
4.5.1.3
Stop Grant State
Intel mobile modules support Stop Grant state. desktop systems, processor enters this mode with assertion STPCLK# signal when configured Stop Grant state (via A15# strapping option). processor still able respond snoop requests latch interrupts. Latched interrupts will serviced when processor returns Normal state. Only occurrence each interrupt event will latched. transition back Normal state made deassertion STPCLK# signal, occurrence stop break event BINIT#, FLUSH#, RESET# assertion). processor will return Stop Grant state after completion BINIT# initialization unless STPCLK# been deasserted. RESET# assertion will cause processor immediately initialize itself. However, processor will stay Stop Grant state after initialization until STPCLK# deasserted. FLUSH# signal asserted, processor will flush on-chip caches return Stop Grant state. transition Sleep state made assertion SLP# signal. While Stop Grant state, assertions SMI#, INIT#, INTR, LINT[1:0]) will latched processor. These latched events will serviced until processor returns Normal state. Only each event will recognized upon return Normal state.
4.5.1.4
Quick Start State
processor enters this mode with assertion STPCLK# signal when processor configured Quick Start state (via A15# strapping option). Quick Start state processor only capable acting snoop transactions generated priority device. Because snooping behavior, Quick Start only used single processor configurations. transition Deep Sleep state made stopping clock input processor. transition back Normal state (from Quick Start state) made only STPCLK# signal deasserted. While this state, processor limited ability respond input. incapable latching interrupts, servicing snoop transactions from symmetric masters, responding FLUSH# BINIT# assertions. Quick Start state, processor will respond properly input signal other than STPCLK#, RESET#, BPRI#. other input signal changes, then behavior processor will unpredictable. serial interrupt messages begin progress while processor Quick Start state.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology RESET# assertion will cause processor immediately initialize itself, processor will stay Quick Start state after initialization until STPCLK# deasserted.
4.5.1.5
HALT/Grant Snoop State
processor will respond snoop transactions while Auto Halt, Stop Grant, Quick Start state. When snoop transaction presented system bus, processor will enter HALT/Grant Snoop state. processor will remain this state until snoop been serviced quiet. After snoop been serviced, processor will return previous state. HALT/Grant Snoop state entered from Quick Start state, then input signal restrictions Quick Start state still apply HALT/Grant Snoop state (except those signal transitions that required perform snoop).
4.5.1.6
Sleep State
Intel mobile modules support Sleep state. desktop systems, Sleep state very low-power state which processor maintains context phase locked loop (PLL) maintains phase lock. Sleep state only entered from Stop Grant state. After entering Stop Grant state SLP# signal asserted, causing processor enter Sleep state. SLP# signal recognized Normal state Auto Halt state. processor reset RESET# signal while Sleep state. RESET# driven active while processor Sleep state, then SLP# STPCLK# must immediately driven inactive ensure that processor correctly initializes itself. Input signals (other than RESET#) change while processor transitioning into Sleep state. Input signal changes these times will cause unpredictable behavior. Thus, processor incapable snooping latching events Sleep state. While Sleep state processor enter lowest power state, Deep Sleep state. Removing processor's input clock puts processor Deep Sleep state. PICCLK removed Sleep state.
4.5.1.7
Deep Sleep State
Deep Sleep state lowest power mode processor enter while maintaining context. processor enters Deep Sleep state stopping BCLK input while processor Sleep state Quick Start state. proper operation, BCLK input should stopped state. processor will return Sleep state Quick Start state from Deep Sleep state when BCLK input restarted. lock latency, there 30.0-µS delay after clocks have started before this state transition happens. PICCLK removed Deep Sleep state. PICCLK should designed turn when BCLK turns while transitioning Deep Sleep state. input signal restrictions Deep Sleep state same Sleep state, except that RESET# assertion will result unpredictable behavior.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Power Consumption Power Management ModeThe power data divided each power rail. Each power rail supplied mobile module through MMC-2 connector. total power values based typical power consumption. data captured Tamb 25°C, V_DC 18.0V. Note: power consumption values 100% tested have been characterized design. Table Table Table provide module power consumption values various power management modes. Because mobile modules with same frequencies have different printed circuit board (PCB) revisions, refer product tracking code (PTC) lists before each table below match correct power consumption information with correct mobile module. Table applies mobile modules with following PTCs.
PMM65002001AA PMM60002001AA
Table Power Consumption Values
V_DC State 1.60V Auto Halt Quick Start Deep Sleep 2.19W 1.77W 1.29W 1.35V 1.36W 1.06W 0.82W 1.60V 0.08W 0.08W 0.08W 1.35V 0.06W 0.07W 0.08W 1.60V 2.27W 2.04W 0.24W 1.35V 2.16W 1.89W 0.24W 1.60V 0.57W 0.62W 0.45W 1.35V 0.41W 0.43W 0.29W 1.60V 4.17W 3.43W 1.35W 1.35V 3.50W 2.99W 1.05W V_3S Total Power
0.04W
0.01W
0.01W
0.00W
0.05W
NOTE: These power values should used power supply guidelines power management modes. They have some guardband added design margin. Therefore, total power does necessarily each power rail. "Total Power" individual "raw" power requirements with guardband added.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Table applies mobile modules with following PTCs.
PMM70002101AA PMM65002101AB PMM60002101AB PMM70002201AB PMM65002201AC PMM60002201AC
Table Power Consumption Values
V_DC State 1.60V Auto Halt Quick Start Deep Sleep 2.56W 2.10W 1.64W 1.35V 1.94W 1.72W 1.47W 1.60V 0.06W 0.06W 0.05W 1.35V 0.06W 0.06W 0.06W 1.60V 2.31W 2.00W 0.26W 1.35V 2.29W 2.00W 0.26W 1.60V 0.03W 0.03W 0.04W 1.35V 0.01W 0.04W 0.04W 1.60V 4.93W 4.13W 1.96W 1.35V 4.22W 3.74W 1.79W V_3S Total Power
0.03W
0.01W
0.02W
0.00W
0.05W
NOTE: These power values should used power supply guidelines power management modes. They have some guardband added design margin. Therefore, total power does necessarily each power rail. "Total Power" individual "raw" power requirements with guardband added.
Table applies mobile modules with following PTCs.
PMM75002101AA PMM75002201AB
Table Power Consumption Values
V_DC State 1.60V Auto Halt Quick Start Deep Sleep 2.92W 3.12W 1.74W 1.35V 2.04W 1.75W 1.29W 1.60V 0.24W 0.24W 0.29W 1.35V 0.22W 0.22W 0.25W 1.60V 2.21W 1.98W 0.27W 1.35V 2.22W 2.00W 0.26W 1.60V 0.03W 0.04W 0.03W 1.35V 0.02W 0.04W 0.04W 1.60V 5.18W 5.20W 2.25W 1.35V 4.29W 3.75W 1.76W V_3S Total Power
0.03
0.00
0.01
0.00
0.04
NOTE: These power values should used power supply guidelines power management modes. They have some guardband added design margin. Therefore, total power does necessarily each power rail. "Total Power" individual "raw" power requirements with guardband added.
Table applies mobile modules with following PTCs.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
PMM85002101AA PMM80002201AA
Table Power Consumption Values
V_DC State 1.60V Auto Halt Quick Start Deep Sleep 2.81W 2.35W 1.46W 1.35V 1.98W 1.67W 1.14W 1.60V 0.18W 0.18W 0.22W 1.35V 0.16W 0.16W 0.19W 1.60V 2.23W 1.97W 0.25W 1.35V 2.18W 1.91W 0.25W 1.60V 0.02W 0.04W 0.04W 1.35V 0.22W 0.24W 0.04W 1.60V 5.05W 4.37W 1.88W 1.35V 4.02W 3.52W 1.54W V_3S Total Power
0.05
0.01
0.02
0.00
0.06
NOTE: These power values should used power supply guidelines power management modes. They have some guardband added design margin. Therefore, total power does necessarily each power rail. "Total Power" individual "raw" power requirements with guardband added.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Electrical SpecificationThe following section provides electrical specifications Pentium processor mobile module featuring Intel SpeedStep technology.
System Clock Signal Quality SpecificationThe HCLK0 BCLK signal names used interchangeably.
5.1.1
BCLK Specification
Table BCLK SpecificationSymbol VIL,BCLK VIH,BCLK Parameter Input Voltage, BCLK Input High Voltage, BCLK 2.625 Unit
NOTE: VILX,min VIH,max only apply when BCLK stopped. BCLK should stopped state. Table BCLK voltage range specifications when BCLK running.
5.1.2
BCLK Specification
Table BCLK Specifications Processor Core PinT# Parameter System Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time 2.85 2.55 0.175 0.175 100.0 10.0
Unit
Note Notes Notes Notes 1.7V, Notes 0.7V, Notes 0.9V 1.6V, Notes 1.6V 0.9V, Notes
0.875 0.875
NOTES: timings GTL+ CMOS signals referenced BCLK rising edge 1.25V. CMOS signals referenced 0.75V. internal core clock frequency derived from clock. clock core clock ratio determined during initialization predetermined Intel mobile module. BCLK period allows +0.5 tolerance clock driver variation. This value measured rising edge adjacent BCLKs 1.25V. jitter present must accounted component BCLK skew between devices. clock driver's closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. attenuation point, measured into 10-pF 2-pF load, should less than kHz. This specification ensured design characterization and/or measured with spectrum analyzer. CK97 Clock Synthesizer/Driver Specification (OR-1089) further details. These values 100% tested specified design characterization clock driver requirement. Specifications labeled available.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Table describes signal quality specifications processor core clock (BCLK) signal. Figure describes signal quality waveforms clock processor core pins proper signal termination, refer "Clocking Guidelines" section Mobile Pentium Processor/440BX AGPset Recommended Design Debug Practices (RDDP-A) Rev. (SC-2760). Table BCLK Signal Quality Specifications Processor Core
VIL,BCLK VIH,BCLK Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback BCLK Rising/Falling Slew Rate Parameter -0.3 -0.7 2.625 Unit V/nS Notes Notes Undershoot, Overshoot, Note Absolute Value, Notes Absolute Value, Notes Note
NOTES: rising edge BCLK, there must minimum overshoot 2.0V. clock must rise monotonically between VIL,BCLK 2.0V fall monotonically between VIH,BCLK VIL,BCLK. These specifications apply only when BCLK running. Table specifications when BCLK stopped. BCLK above VIH,BCLK,MAX below VIL,BCLK,MIN more than clock cycle. rising edge ringback voltage minimum absolute voltage that BCLK signal back after passing VIH,BCLK,MIN voltage limits. falling edge ringback voltage maximum absolute voltage that BCLK signal back after passing VIL,BCLK,MAX voltage limits. Specifications labeled available.
Figure BCLK Waveform Processor Core PinT3
V3MAX
V2MIN
V1MAX
V3MIN
V0012-00
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
System Power RequirementTable provides power supply design criteria.
Table System Power RequirementSymbol IDC_RMS IDC_Surge I5_Surge I3_Surge VCPUPU ICPUPU VCLK ICLK Parameter Input Voltage Input Current Ripple Current Maximum Surge Current Power Managed 5.0-V Supply Power Managed 5.0-V Current, Operating Maximum Surge Current Power Managed 3.3-V Supply Power Managed 3.3-V Current Maximum Surge Current Processor Ring Voltage Processor Ring Current Processor Clock Rail Voltage Processor Clock Rail Current 4.75 20.0 3.135 3.135 2.375 24.0 12.0 50.0 10.0 35.0 21.0 20.0 5.25 100.0 3.465 3.465 20.0 2.625 80.0 Unit Note Notes Notes Notes Notes Notes Note
NOTES: V_DC 12.0V order determine typical V_DC current. V_DC 7.5V order determine maximum V_DC current. 20-µS duration. This V_DC dependent. Figure data IDC-RMS V_DC. These values system dependent. Specifications labeled applicable.
Processor Core Voltage Regulation
voltage regulator (DC/DC converter) designed support core voltage ring voltage current future Intel mobile processors. voltage regulator provides appropriate mobile processor core voltage, GTL+ termination voltage, processor sideband signal pull-up voltage, clock driver buffer voltage. these voltages, only processor sideband pullup voltage (V_CPUPU) clock driver buffer voltage (V_CLK) delivered system electronics. mobile module supports input voltage range 7.5V 21.0V from system battery power supply.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
5.3.1
Voltage Regulator Efficiency
There three voltage regulators mobile module. voltage regulators generate core voltage ring voltage. core voltage regulator provides required current from V_DC supply. Intel SpeedStep technology single frequency Vcore efficiencies shown Table Table Figure Figure provide charts efficiency values. V_CLK voltage regulators plane.
Table Vcore Power Conversion Efficiency 1.60V
Vcore 1.60V Icore Efficiency V_DC 7.50V Efficiency V_DC 12.0V Efficiency V_DC 21.0V
Table Vcore Power Conversion Efficiency 1.35V
Vcore 1.35 Icore Efficiency V_DC 7.50V 77.1% 84.4% 86.2% 85.7% 84.6% 83.2% 81.8% 80.3% 78.8% Efficiency V_DC 12.0V 70.8% 82.0% 84.5% 84.9% 84.3% 83.4% 82.2% 81.1% 79.9% Efficiency V_DC 21.0V 62.2% 76.8% 80.4% 81.0% 81.4% 80.9% 80.4% 79.5% 78.7%
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure Efficiency Chart Vcore 1.60V
Efficiency Vcore 1.60V
Efficiency
V_DC 7.5V
V_DC 12.0V V_DC 21.0V
Icore
Figure Efficiency Chart Vcore 1.35V
Efficiency Vcore 1.35V
Efficiency(%)
V_DC 7.5V V_DC V_DC
Icore(A)
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
5.3.2
Voltage Regulator Control
VR_ON connector allows 3.3-V signal control voltage regulator. system manufacturer this signal turn voltage regulator OFF. VR_ON should controlled function same signal (SUSB#) used control system's switched 5.0-V 3.3-V power planes. PIIX4E/M defines Suspend Power Management state which power physically removed from processor voltage regulator. this state, SUSB# PIIX4E/M controls these power planes. mobile module provides VR_PWRGD signal, which indicates that voltage regulator power operating stable voltage level. system manufacturer should this signal system electronics control power inputs gate PWROK PIIX4E/M South Bridge. Table provides detailed definitions sequences voltage signals.
Table Voltage Signal Definitions SequenceSignal Source Definitions Sequences V_DC required between 7.5V 21.0V driven system electronics' power supply. V_DC powers mobile module DC-to-DC converter processor core voltages. mobile module cannot inserted removed while V_DC powered V_3S System Electronics System Electronics System Electronics system electronics supplies voltage regulator. system electronics supplies 82443BX powers mobile module's linear regulators generating V_CLK V_CPUPU voltage rails. stays during suspend. system electronics supplies V_3S shut during suspend. VR_ON 3.3-V signal that enables voltage regulator circuit. When driven active high voltage regulator circuit activated. signal driving VR_ON should digital signal with rise/fall time less than equal (VIL,max= 0.4V, VIH,min 3.0V.) result VR_ON being asserted, V_CORE output DCDC regulator mobile module driven core voltage processor. Upon sampling voltage level V_CORE (minus tolerances ripple), VR_PWRGD driven active high. VR_PWRGD sampled active within second assertion VR_ON, then system electronics should deassert VR_ON. After V_CORE stabilized, VR_PWRGD will assert logic high (3.3V). This signal must pulled system electronics. VR_PWRGD should "logically ANDed" with V_3S generate PIIX4E/M input signal, PWROK. system electronics should monitor VR_PWRGD verify that asserted high prior active high assertion PIIX4E/M PWROK. V_CPUPU 3.3V. system electronics uses this voltage power PIIX4E/M-to-processor interface circuitry. V_CLK 2.5V. system electronics uses this voltage power HCLK[0:1] drivers processor clock.
V_DC
System Electronic
VR_ON
System Electronic
V_CORE
Module
VR_PWRGD
Module
V_CPUPU V_CLK
Module Module
following list includes additional specifications clarifications power sequence timing Figure provides illustration.
VR_ON signal only asserted logical high digital signal after V_DC
7.5V, 4.5V, 3.0V.
Rise Time Fall Time VR_ON must less than equal
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
VR_ON VILmax 0.4V VIHmin +3.0V. VR_PWRGD will asserted logic high (3.3V) after V_CORE stabilized V_DC
reaches 7.5V. This signal should pulled system electronics.
power-on process, Intel recommends raise higher voltage power plane first
(V_DC), followed lower power planes (V_5, V_3), finally assert VR_ON after above voltage levels rails. power-off process should reverse, example VR_ON gets deasserted, followed lower power planes, finally higher power planes.
VR_ON must monotonically rise through fall through points.
sign slope change between rising VILin falling. listed Table Table VR_ON In-rush Current
Instantaneous Maximum Typical 41.0 Operating
VR_ON must provide instantaneous in-rush current mobile module with value
VR_ON Valid-Low Time: This specifies long VR_ON needs valid
before VR_ON turned back again. going from valid then back following conditions must prevent damage system mobile module: VR_ON must original voltage level requirements turn-on must before assertion VR_ON (i.e. V_DC 7.5V, 4.5V, 3.0V).
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure Power Sequence Timing
V_DC V_3S G_LO/HI# VR_ON VR_PWRGD V_CPUPU V_CLK NOTE NOTE NOTE NOTE NOTE NOTE
NOTES: PWROK board should active when VR_PWRGD active V_3S good. CPU_RST from board should active minimum after PWROK active PLL_STP# CPU_STP# inactive. Note that PLL_STP# condition RSMRST# SUSB# PIIX4E/M. This 5.0-V power supplied MMC-2 connector. This should first 5.0-V plane power Stays during suspend. G_LO/HI# must high rising edge VR_ON. not, BIOS must assert this signal very early core execution. V_DC 7.5V, V_5>= 4.5V, V_3S>= 3.0V. VR_PWRGD specified active module regulator within less than equal 6.0-mS maximum after assertion VR_ON. V_CPUPU V_CLK generated mobile module.
5.3.3
Power Planes: Bulk Capacitance RequirementThe placement sufficient bulk capacitance system electronics board critical operation mobile module ensure that system design accommodate future high frequency modules. Intel provided maximum possible bulk capacitance mobile module. However, order achieve proper filtering in-rush current protection, imperative that additional filtering provided system electronics board. Table details bulk capacitance requirements system electronics. Note: Observe voltage rating requirement capacitors each respective voltage rail.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Table Bulk Capacitance Requirements Power Plane
Bulk Capacitance Requirements Power Plane V_DC V_3S VCC_AGP V_CPUPU V_CLK Total Capacitance 100.0 100.0 470.0 100.0 22.0 10.0 20.0 100.0 100.0 100.0 100.0 Ripple Current 3.0A~ 5.0A 1.0A 1.0A 1.0A High Frequency Capacitance Requirements 0.01 0.01 0.01 0.01 0.01 8200.0 8200.0
Note
Notes 1,3,4,5,6 Notes 1,4,5,6 Notes 1,4,5,6 Notes 1,4,5,6 Notes 1,4,5,6 Notes 1,5,6,7 Notes 1,2,5,6,7
NOTES: Placement above capacitance requirements should located near connector. V_CLK filtering should located next system clock synthesizer. ripple current specification depends V_DC input module. Figure Tantalum* capacitors used, voltage derating practice must observed. example, 5.0-V rail requires 10.0-V rated capacitor. order reduce ESR, Intel recommends multiple bulk capacitors rather than single large capacitor. Intel strongly recommends that system designers close attention capacitor design recommendations. Specifically, "Capacitance Temperature De-rating Curve," "Capacitance Applied Voltage Derating Curve," "Capacitance Frequency De-rating Curve." Some capacitor dielectrics particularly susceptible these conditions, example ceramic capacitors. Specifications labeled available.
Figure shows dependence V_DC ripple current V_DC.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure V_DC Ripple Current
V_DC Input Ripple Current V_DC Voltage
8.00 7.50 7.00 6.50 6.00 5.50 5.00 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00
Input Ripple Current(A)
V_DC(V)
5.3.4
5.3.4.1
System Power Supply Circuit Protection
Power System Protection
recommended Power System Protection consists following:
Power Supply capable delivering 7.5V 21.0V mobile module Overcurrent Protection circuit providing means limit maximum current available
system
Slew Rate Control circuit providing controlled voltage slew rate turn which provideprotection components sensitive fast voltage rise time
Undervoltage Lockout circuit that protects against potentially damaging high currents,
which might encountered Power Supply voltage
Overvoltage Lockout circuit providing protection from potentially damaging high
Power Supply voltage
Bulk Decoupling Capacitors providing filtering reservoir energy, which provide
faster transient response than power supply
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure V_DC Power System Protection Block Diagram
V_DC Power Supply
(See Table
Overcurrent Protection
(See Section 5.3.4.3)
Slew Rate Control
(See Section 5.3.4.5)
Bulk Decoupling Capacitor
Module
Undervoltage Lockout
(See Section 5.3.4.6)
Overvoltage Lockout
(See Section 5.3.4.7)
5.3.4.2
V_DC Power Supply
power supply must able deliver 7.5V 21.0V mobile module, measured mobile module.
5.3.4.3
Overcurrent Protection
Overcurrent Protection circuit provides limit current drawn mobile module. Under normal operating conditions, I_DC should expected exceed 3.0A V_DC 7.5V. allow component variations margining issues, reasonable I_DC Current Limit would 6.0A.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure Overcurrent Protection Circuit
V_DC Power Supply 2.5V 2N2222A LM4040
NOTE: must able operate with inputs near V_DC rail. Consider LMC6762.
Over Current Protection
Slew Rate Control Si4435DY
V_DC
2N7000
V_DC
other V_DC input range, current will somewhat less. 14.0V, example, corresponding power could produced with only 3.0A. this example, comparator, U1A, will used sense when V_DC over 14.0V will shift current limit from 6.0A 3.0A.
Delimited)= 6.0A I_DC(limit2)= 3.0A b(Q1)= 0.005 R12= 100.0 R13= 100.0 V(R14) 1.8V I(R20) 100.0 C36= 2.0K
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure Current Shift Model
V_DC
5.3.4.4
Current Limit Shift Point
Comparator should switch when non-inverting input equal 2.5-V reference inverting input, when voltage applied V_DC equal selected switch point voltage dropped across 2.5V. this example, change should occur when V_DC= 14.0V.
Equation
V_DC Vref) Vref 2.5)
2000
(The nearest standard value 9.01 Comparator will pull output when V_DC falls below 14.0V, which will effectively parallel with R14. When power initially applied circuit, charges 2.5V through R20. This slowly rising voltage applied base current source, voltage approximately 2.5V minus base-emitter drop about 0.7V 25°C): V(R14) 1.8V. 2N2222A with moderate about 100. Therefore, current through approximately equal current through R14. charging C18, provides small increment delay will allow pull Gate until pulled non-inverting input down slightly. voltage developed across function load. Equation V(R1)= I_DC*R1
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology maximum I_DC expected 3.0A, consider setting I_DC Current Limit 6.0A. Current Sense resistor, selected (0.005), maximum voltage developed across this resistor calculated. Consider case where V_DC above 14.0V. Equation I_DC(limit)*Rsense= 3.0A*5E-3= 15.0 Offset voltage applied inverting input comparator, U1B, should then 15.0 selected 100.0, current then calculated shown Equation below. Equation Ioffset= 15.0 mV/100.0= 150.0 Note: successful design, input offset comparator should also considered. option that design offset least times greater than device offsets. value calculated with Equation Equation R14= 1.8V/150.0 12.0 (The nearest value 12.1K.) Consider case when V_DC drops below 14.0V current limits shift 6.0A. Equation I_DC(limit)*Rsense= 6.0A*5E-3= 30.0 Offset voltage applied inverting input comparator, U1B, should then 30.0 selected 100.0, current then calculated shown Equation below. Equation Ioffset= 30.0 mV/100= 300.0 value parallel combination calculated shown Equation below. Equation Rcombo= 1.8V/300.0 12.0-K resistor. also 12.0K, parallel combination will 6.0K. R20, LM4040-2.5 very wide operating current range from 60.0 15.0 order provide current source base drive will need Equation Equation Ibase Ic/b= 300.0 µA/100
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology selected I(R20), would adequate reference current source base drive. Since both these currents must satisfied power supply margin, V_DC 7.5V will assumed. Equation (V_DC-Vref)/I(R20) 7.5-2.50)/100.0 50.0 allow component tolerances, 51.0 recommended.)
5.3.4.5
Slew Rate Control
slew rate control regulates rate that power supply voltage applied system.
Threshold voltage -1.0V VGS(sat) -2.4V, also denoted Vsat 100.0 t_delay 500.0 Ctotal Bulk capacitors module capacitors 22.0 119.4
RDS(on) P-Channel MOSFET such Siliconix* Si4435DY. When power supply voltage applied increased value that exceeds Lockout value, (7.5V will used this example), Undervoltage Lockout circuit, allows pull gate start turn-on sequence. pulls drain toward ground, forcing current flow through will start source current until after t_delay, with t_delay defined shown Equation Equation below. Equation
t_delay R2.C9.ln V_DC
Equation
V_DC
published minimum threshold Si4435DY -1.0V, i.e. must charge 1.0V before starts turn delay, t_delay, time required charge 1.0V. Assuming negligible voltage drop across when voltage Gate with respect ground, voltage developed across V(R2). minimum steady-state bias desired -4.5V, this will voltage dropped across R16. V_DC margin, i.e. 7.5V, then derived from Equation below. Equation V_DC+VGS 7.5V- 4.5V 3.0V (with respect ground)
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Equation Vg.R16 V_DC 66.67
(The nearest standard value 66.5 example will continue with 66.5 Rearranging Equation solve yields Equation Equation
R2.ln t_delay V_DC
value calculated. Equation 0.354 close standard value 0.33 will yield t_delay 466.0 µS.) ramp-up time, t_ramp, defined shown Equation Equation
t_ramp R2.C9.ln Vsat t_delay
VGS(sat) -2.4V, then Equation applies. Equation t_ramp 948.8 maximum current during power-up ramp shown Equation below. Equation
V_DC Imax Ctotal Ctotal t_ramp
total capacitance, Ctotal V_DC bus, 119.4 then Equation below. Equation Imax 0.944A From values assumed calculated, t_delay 466.0 t_ramp 949.0 Imax 944.0
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
5.3.4.6
Undervoltage Lockout
circuit below shows Undervoltage Lockout portion V_DC Supply circuit. This circuit protects locks applied voltage mobile module prevent accidental turn-on V_DC supply voltages.
Warning:
voltage applied mobile module could result destructive current levels.
Figure Undervoltage Lockout
V_DC_A V_DC_UVlock=7.5V R17=10 R25=1 VCEsat= 0.3V Vref=2.5V Gate V_DC Vref 2.5V
V_DC LM339
Undervoltage Lockout
output LM339 comparator open-collector when applied voltage V_DC less than 7.5V, which holds Gate low. Consequently, Slew Rate Controller allowed turn-on. 2.5-V reference, Vref, voltage derived from Figure When non-inverting input comparator exceeds Vref, 2.5V, comparator trips allows output High state. gate then pulled starting controlled Power-up Slew. model Figure will used calculate Undervoltage Lockout trip point.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure Undervoltage Lockout Model
V_DC
2.5V VCEsat Undervoltage Lockout Model
VCEsat saturation voltage comparator output transistor. comparator trip point voltage calculated with Equation Equation
V_DC_UVlock Vref Vref Vref VCEsat
power mobile module held until V_DC exceeds 7.5V, Equation rearranged solve R18. Equation
Vref.R17.R25 R25.( V_DC_UVlock Vref) R17.( Vref VCEsat)
value determined plugging these values into Equation Equation 5.022 (4.99 standard resistor value, which would provide lockout below 7.532V.)
5.3.4.7
Overvoltage Lockout
mobile module operates with maximum input voltage 21.0V. This circuit lock input voltage exceeds desired input.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure Overvoltage Lockout
V_DC_A R4=100 R24=100K R26=1 R27=1
Gate
Vref 2.5V
V_DC V_DC LM339 Overvoltage Lockout
LM339 comparator open-collector output pulled when applied voltage V_DC high, thus disabling Slew-rate circuit. model Figure below will used component calculations. Figure Overvoltage Lockout Model
V_DC_A V_DC
Vinv Vnoninv Vref Overvoltage Lockout Model
Assume that desired V_DC Overvoltage Lockout 21.0V. Using Equation input non-inverting input Lockout comparator calculated with following equations.
243356-006
Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Equation
Vnoninv Vref R27.( V_DC_OVlock Vref)
Equation Vnoninv= 2.517V Equation
Vinv V_DC_OVlockR23)
output Lockout comparator will become active pull down when inverting input becomes greater than 2.517V input non-inverting input. Equation rearranged solve R23. Equation
R24.Vinv V_DC_OVlock Vinv
Lockout comparator trip point defined Vinv Vnoninv 2.517V. Equation provides solution R23. Equation R23= 13.618 (The nearest standard value 13.7 V_DC exceeds 6.0V, voltage Lockout comparator inverting input will exceed 2.517V causing comparator trip, pulling output disabling Power Skew Control circuit which, turn, will disconnect V_DC from mobile module.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure Recommended Power Supply Protection Circuit System ElectronicV_DC Adaptor 27uF 2.5V LM339 2N2222A LM4040 V_DC V_DC LM339 LM339 V_DC 2N7000 V_DC 27uF 27uF 27uF 27uF 4.7uF 4.7uF V_DC
Over Current Protection
Slew Rate Control
Si4435DY
Input Bulk Decoupling Capacitor
Processor Module
Components values assumed calculated
5.62K, 100K, 100, 100, 12.1K, 100K, 10K, 11K, 0.33µF 0.1µF 20K, 71.5K, 100K, 12.1K, 9.1K,
2.5V
Under Voltage Lockout
V_DC V_DC LM339
Over Voltage Lockout
Figure Simulation V_DC Voltage Skew
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Active Thermal Feedback
Table Thermal Sensor SMBus AddresFunction Thermal Sensor SMBus Address 1001
Thermal Sensor Configuration Register
configuration register thermal sensor controls operating mode (Auto Convert Standby) device. Since processor temperature varies dynamically during normal operation, Auto Convert mode should used exclusively monitor processor temperature. Table shows format configuration register. RUN/STOP low, then thermal sensor enters Auto Convert mode. RUN/STOP high, then thermal sensor immediately stops converting enters Standby mode. thermal sensor will still perform temperature conversions Standby mode when receives one-shot command. However, result one-shot command during Auto Convert mode guaranteed. Intel does recommend using one-shot command monitor temperature when processor active, only Auto Convert mode should used. thermal sensor configured various interface modes temperature sampling. Intel recommends interfacing thermal sensor using Interrupt mode. more detailed information regarding interface methods, please Intel Mobile Module Thermal Diode Temperature Sensor Application Note available through your Intel Field Representative.
Table Thermal Sensor Configuration Register
Name MASK Reset State Function Masks SMBALERT# when high Standby mode control bit. low, then device enters Auto Convert mode. high, then device immediately stops converting enters Standby mode where one-shot command performed. Reserved future
RUN/STOP
Reserved
NOTE: Reserved bits should written read "don't care" programming purposes.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Mechanical SpecificationThis section provides physical dimensions Pentium processor mobile module featuring Intel SpeedStep technology.
Mobile Module DimensionFigure shows mobile module board dimensions connector orientation.
Figure Board Dimensions MMC-2 Connector Orientation
Module Mechanical X-Y-Z Dimensions Thermal Attach Points Unless otherwise specified: Tolerances Angles 0.5° 0.15 .XXX 0.075 Dimensions
6.1.1
Location MMC-2 Connector
Figure shows location 400-pin connector.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure Board Dimensions MMC-2 Connector-Pin Orientation
6.1.2
Printed Circuit Board
Figure shows minimum maximum thickness printed circuit board (PCB). range thickness allows different technologies used with current future Intel mobile modules. Note: system manufacturer must ensure that mechanical restraining method and/or system-level contacts able support this range compatibility with future Intel mobile modules.
Figure Printed Circuit Board ThicknesMin: 0.90 Max: 1.10
Printed Circuit Board
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
6.1.3
Height RestrictionFigure shows height restrictions mobile module. keep-out zone also illustrated. Three mating connectors available heights approximately three sizes provide flexibility choosing system electronics components between boards. Information these connectors obtained from your Intel Field Representative.
Figure Height Restriction
Note
Note
NOTES: values nominal unless otherwise specified. model (PRO/E Native) Available upon request. These dimensions have changed.
Thermal Transfer Plate
TTPs provide heat dissipation processor 82443BX, they vary different generations Intel mobile modules. TTPs provide thermal attach point where system manufacturer transfer heat through notebook system using heat pipe, heat spreader plate, thermal solution. Attachment dimensions thermal interface block TTPs provided Figure Figure Figure mobile module designed high efficiency spreader. fully take advantage mobile module thermal design optimize system thermal performance, contact area (Ac) needs minimum While crucial maximize contact area, equally important ensure that contact area and/or mobile module free from warpage assembled configuration.
Warning:
warpage occurs, thermal resistance mobile module could adversely affected. When attaching mating block either TTPs, Intel recommends that thermal elastomer should used interface material. This material reduces thermal resistance. thermal interface block should secured with screws using maximum torque Kg*cm Kg*cm (equivalent 0.147 to.197 N*m). thread length screws should 2.25-mm gageable thread (2.25-mm minimum 2.80-mm maximum).
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology mobile module designed ensure that thermal resistance between processor center point directly above surface 0.35° C/W, under following conditions.
RTTP-a (center point) ambient ~2.4° Contact area centered between attach points
Figure 82443BX Thermal Transfer Plate (Reference Only)
Rivets Mounting
Figure 82443BX Thermal Transfer Plate Detail
3.150
1.000 0.89 1.050 3.569 6.280
NOTE: tolerances 0.015 unless otherwise noted.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure Thermal Transfer Plate (Reference Only)
6.3.1
Mobile Module Physical Support
Mobile Module Mounting RequirementThree mounting holes available securing mobile module system base system electronics. Figure mounting hole locations. These hole locations board edge clearances will remain fixed Intel mobile modules. three mounting holes should used ensure long term mechanical reliability integrity system. board edge clearance includes 0.762-mm (0.030 inches) wide containment ring around perimeter mobile module. This ring each layer mobile module grounded. hole patterns also have plated surrounding ring metal standoff shielding purposes. Standoffs should used provide support installed mobile module. However, warpage baseboard vary should calculated into final dimensions standoffs used. calculations made with Intel MMC-2 Standoff/Receptacle Height Spreadsheet. Information this spreadsheet obtained from your Intel Field Representative. Figure shows standoff support hole details, board edge clearance, dimensions containment ring. components placed board keep-out area.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure Standoff Holes, Board Edge Clearance, Containment Ring
Hole detail, place
3.81+/-0.19
2.413
0.050 0.025 hole diameter
4.45 diameter grounded ring
1.27+/- 0.19 board edge ring
0.762 width containment ring
2.54+/-0.19 keep-out area
3.81+/-0.19 board edge hole centerline
6.3.2
Weight
Pentium processor mobile module featuring Intel SpeedStep technology weighs approximately grams.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Thermal Specification
Thermal Design Power
Table provides typical thermal design power (TDP) specifications. typical typical power dissipation under normal operating conditions nominal V_CORE (CPU power supply) while executing worst case power instruction mix. This includes power dissipated relevant components. During operating environments, processor junction temperature, must within specified range power handling capability system thermal solution reduced less than recommended typical with implementation firmware/software control "throttling" that reduces power consumption dissipation.
Table Thermal Design Power (TDPMODULE) Specification
Typical 850/700 1.60V 22.5 1.35V 15.1 Typical 800/650 1.60V 21.6 1.35V 14.6 Typical 750/600 1.60V 20.0W 1.35V 13.9W Typical 700/550 1.60V 19.1W 1.35V 13.4W Typical 650/500 1.60V 17.8W 1.35V 12.2W Typical 600/500 1.60V 16.6W 1.35V 12.2W
NOTES: processor temperature, must within special range 100°C. TDPModule thermal-solution design reference point system thermal solution readiness total module power. Module equals core 82443BX
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Labeling Information
Intel mobile modules tracked methods. first method product tracking code (PTC), which Intel uses determine assembly level mobile module. Figure shows where found mobile module. contains characters provides following information. Example: PMM75002101AA Key: AABCCCDDEEEFF
Definition: AABCCCDDEEEFFProcessor Module Pentium Processor Mobile Module Featuring Intel SpeedStep Technology Speed Identity 850/700 MHz, 800/650 MHz, 750/600 MHz, 700/550 MHz, 650/500 MHz, 600/500 Cache Size (256K) Notifiable Design Revision (Start 001) Notifiable Processor Revision (Start
Note: other Intel mobile modules, second field defined
Pentium Processor Mobile Module (MMC-1) Pentium Processor Mobile Module (MMC-2) Pentium Processor Mobile Module With On-die Cache (MMC-1) Pentium Processor Mobile Module With On-die Cache (MMC-2) Celeron Processor Mobile Module (MMC-1) Celeron Processor Mobile Module (MMC-2) Pentium Processor Mobile Module (MMC-2) Celeron Processor (0.18µ) Mobile Module (MMC-2)
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology Figure Product Tracking Code
Intel Assembly Identification Intel Serial Number
ISYWW6666
XXXXXX-XXX XXXXXXXXXXXXX
Product Tracking Code Secondary Side Module
second tracking method system designer generated software utility. Four strapping resistors located mobile module determine production level. connected terminated properly, module-revision levels determined. system designer generated software utility then read these bits with stepping provide complete module manufacturing revision level. current module information, please refer latest Intel mobile module product change notification (PCN) letter, which obtained from your local Intel Field Representative.
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Pentium Processor Mobile Module MMC-2 Featuring Intel SpeedStep Technology
Environmental StandardThe environmental standards defined Table
Table Environmental StandardParameter Temperature Cycle Humidity Voltage Condition Non-operating Operating Unbiased Non-operating Shock Unpackaged Packaged Packaged Unpackaged Vibration Packaged Packaged Damage Human Body Model relative humidity 55°C 5.0V 3.3V Half Sine, Trapezoidal, 50G, Inclined impact feet/S Half Sine, inches simulated free fall 2.2-gRMS random gRMS 11,800 impacts (low frequency) Non-powered test mobile module only noncatastrophic failure. mobile module tested then inserted system functional test. Specification
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