3.3V 128K 32/36 pipeline burst synchronous SRAM Features Organiza

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3.3V 128K 32/36 pipeline burst synchronous SRAM Features Organiza

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7C33128PFS32A 7C33128PFS36A
3.3V 128K 32/36 pipeline burst synchronous SRAM Features
Organization: 131,072 words bits Fast clock speeds LVTTL/LVCMOS Fast clock data access: 3.5/3.8/4.0/5.0 Fast access time: 3.5/3.8/4.0/5.0 Fully synchronous register-to-register operation Single register "Flow-through" mode Single-cycle deselect Dual-cycle deselect also available (AS7C33128PFD32A/ AS7C33128PFD36A) Pentium®* compatible architecture timing Asynchronous output enable control Economical 100-pin TQFP package Byte write enables Multiple chip enables easy expansion core power supply 2.5V 3.3V operation with separate VDDQ typical standby power power down mode NTDTM* pipeline architecture available (AS7C33128NTD32A/ AS7C33128NTD36A)
Logic block diagram
ADSC ADSP A[16:0] Address register Burst logic
arrangement
ADSC ADSP 128K 32/36 Memory array
Byte write registers Byte write registers Byte write registers Byte write registers Enable register Power down Enable delay register
36/32
36/32
DATA [35:0] DATA [31:0]
Note: Pins 1,30,51,80
Selection guide
AS7C33128PFS32A AS7C33128PFS32A AS7C33128PFS32A AS7C33128PFS32A -166 -150 -133 -100 Units Minimum cycle time Maximum clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)
Output registers
Input registers
DQPc/NC VDDQ VSSQ VSSQ VDDQ VDDQ VSSQ VSSQ VDDQ DQPd/NC
TQFP
DQPb/NC VDDQ VSSQ VSSQ VDDQ VDDQ VSSQ VSSQ VDDQ DQPa/NC
Pentium registered trademark Intel Corporation. NTDis trademark Alliance Semiconductor Corporation. trademarks mentioned this document property their respective owners.
2/1/01; V.0.9
Alliance Semiconductor
Copyright Alliance Semiconductor. rights reserved.
7C33128PFS32A 7C33128PFS36A
Functional description
AS7C33128PFS32A AS7C33128PFS36A high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) devices organized 131,072 words bits, incorporate two-stage register-register pipeline highest frequency given technology. Timing these devices compatible with existing Pentium® synchronous cache specifications. This architecture suited ASIC, (TMS320C6X), PowerPCTM*-based systems computing, datacomm, instrumentation, telecommunications systems. Fast cycle times 6/6.7/7.5/10 with clock access times (tCD) 3.5/3.8/4.0/5.0 enable 166, 150, frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation initiated ways: controller address strobe (ADSC), processor address strobe (ADSP). burst advance (ADV) allows subsequent internally generated burst addresses. Read cycles initiated with ADSP (regardless ADSC) using external address clocked into on-chip address register when ADSP sampled Low, chip enables sampled active, output buffer enabled with read operation data accessed current address, registered address registers positive edge CLK, carried data-out registers driven output pins next positive edge CLK. ignored clock edge that samples ADSP asserted, sampled subsequent clock edges. Address incremented internally next access burst when sampled Low, both address strobes High. Burst operation selectable with input. With unconnected driven High, burst operations Pentium® count sequence. With driven device uses linear count sequence suitable PowerPCand many other applications. Write cycles performed disabling output buffers with asserting write command. global write enable writes bits regardless state individual BW[a:d] inputs. Alternately, when High, more bytes written asserting appropriate individual byte signal(s). ignored clock edge that samples ADSP Low, sampled subsequent clock edges. Output buffers disabled when sampled (regardless OE). Data clocked into data input register when sampled Low. Address incremented internally next burst address sampled Low. Read write cycles also initiated with ADSC instead ADSP. differences between cycles initiated with ADSC ADSP follow. ADSP must sampled HIGH when ADSC sampled initiate cycle with ADSC. signals sampled clock edge that samples ADSC (and ADSP High). Master chip enable blocks ADSP, ADSC. AS7C33128PFS32A AS7C33128PFS36A family operates from core 3.3V power supply. I/Os separate power supply that operate 2.5V 3.3V. These devices available 100-pin TQFP package.
*PowerPCis tradenark International Business Machines Corporation.
Capacitance
Parameter Input capacitance capacitance Symbol CI/O Signals Address control pins pins Test conditions VOUT Unit
Write enable truth table (per byte)
Key:
Don't Care, Low, High, True, False; Valid read; internal write signal.
2/1/01
Alliance Semiconductor
7C33128PFS32A 7C33128PFS36A
Signal descriptions
Signal A0-A16 DQ[a,b,c,d] CE1, ADSP ADSC Properties CLOCK SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC ASYNC STATIC default HIGH STATIC ASYNC Description Clock. inputs except synchronous this clock. Address. Sampled when chip enables active ADSC ADSP asserted. Data. Driven output when chip enabled active. Master chip enable. Sampled clock edges when ADSP ADSC active. When inactive, ADSP blocked. Refer Synchronous Truth Table more information. Synchronous chip enables. Active HIGH active Low, respectively. Sampled clock edges when ADSC active when ADSP active. Address strobe processor. Asserted load address enter standby mode. Address strobe controller. Asserted load address enter standby mode. Advance. Asserted continue burst read/write. Global write enable. Asserted write 32/36 bits. When High, BW[a:d] control write enable. Byte write enable. Asserted with HIGH enable effect BW[a:d] inputs. Write enables. Used control write individual bytes when HIGH Low. BW[a:d] active with HIGH cycle write cycle. BW[a:d] inactive cycle read cycle. Asynchronous output enable. pins driven when active chip read mode. Count mode. When driven High, count sequence follows Intel convention. When driven Low, count sequence follows linear convention. This signal internally pulled High.18 Flow-through mode.When low, enables single register flow-through mode. Connect unused pipelined operation. Sleep. Places device power mode; data retained. Connect unused.
BW[a,b,c,d]
Absolute maximum ratings
Parameter Power supply voltage relative Input voltage relative (input pins) Input voltage relative (I/O pins) Power dissipation output current Storage temperature (plastic) Temperature under bias Symbol VDD, VDDQ IOUT Tstg Tbias -0.5 -0.5 -0.5 +4.6 VDDQ +150 +135 Unit
Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions affect reliability.
2/1/01
Alliance Semiconductor
7C33128PFS32A 7C33128PFS36A
Synchronous truth table
ADSP ADSC
WEn1
Address accessed External External External External Next Next Current Current Next Next Current Current External Next Next Current Current
Operation Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read Begin read Cont. read Cont. read Suspend read Suspend read Cont. read Cont. read Suspend read Suspend read Begin write Cont. write Cont. write Suspend write Suspend write
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z2 Hi-Z Hi-Z2 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Key: Don't Care, Low, High. "Write enable truth table"on page more information. flow through mode. write operation following READ, must HIGH before input data time held HIGH throughout input hold time.
Recommended operating conditions
Parameter Supply voltage 3.3V supply voltage 2.5V supply voltage Address control pins pins Ambient operating temperature Symbol VDDQ VSSQ VDDQ VSSQ 3.135 3.135 2.35 -0.5* -0.5
Nominal
VDDQ
Unit
Input
voltages
-2.0V pulse width less than tRC. Input voltage ranges apply 3.3V operation. 2.5V operation, contact factory input specifications.
2/1/01
Alliance Semiconductor
7C33128PFS32A 7C33128PFS36A
TQFP thermal resistance
Description Thermal resistance (junction ambient)* Thermal resistance (junction case)*
This parameter sampled.
Conditions Test conditions follow standard test methods procedures measuring thermal impedance, EIA/ JESD51
Symbol
Typical
Units °C/W °C/W
electrical characteristics
-166 Parameter Input leakage current* Output leakage current Operating power supply current Symbol |ILI| |ILO| Standby power supply current ISB1 ISB2 Output voltage Test conditions Max, VIH, Max, VOUT VIL, VIH, VIL, fMax, IOUT Deselected, fMax, Deselected, 0.2V 0.2V 0.2V Deselected, fMax, 0.2V VDDQ 3.465V VDDQ 3.135V -150 -133 -100 Unit
internal pull-up input leakage Note: given with output loading. increases with faster cycles times greater output loading.
electrical characteristics 2.5V operation
-166 Parameter Output leakage current Output voltage Symbol |ILO| Test conditions VIH, Max, VOUT VDDQ 2.65V VDDQ 2.35V -150 -133 -100 Unit
2/1/01
Alliance Semiconductor
7C33128PFS32A 7C33128PFS36A
Timing characteristics over operating range
Parameter Clock frequency Cycle time (pipelined mode) Cycle time (flow-through mode) Clock access time (pipelined mode) Clock access time (flow-through mode) Output enable data valid Clock HIGH output Data output invalid from clock HIGH Output enable output Output enable HIGH output High Clock HIGH output High Output enable HIGH invalid output Clock HIGH pulse width Clock pulse width Address setup clock HIGH Data setup clock HIGH Write setup clock HIGH Chip select setup clock HIGH Address hold from clock HIGH Data hold from clock HIGH Write hold from clock HIGH Chip select hold from clock HIGH setup clock HIGH ADSP setup clock HIGH ADSC setup clock HIGH hold from clock HIGH ADSP hold fromclock HIGH ADSC hold from clock HIGH
*See "Notes" page
-166 Symbo fMax tCYC tCYCF tCDF tLZC tLZOE tHZOE tHZC tOHOE tCSS tCSH tADVS tADSPS tADSCS tADVH tADSPH tADSCH
-150
-133
-100 Unit
Notes
2,3,4 2,3,4 2,3,4 2,3,4
switching waveforms
Rising input Falling input Undefined/don't care
2/1/01
Alliance Semiconductor
7C33128PFS32A 7C33128PFS36A
Timing waveform read cycle
tADSPS tADSPH ADSP tADSCS tADSCH ADSC Address GWE, tCSS tCSH CE0, LOAD ADDRESS tCYC
tADVS tADVH tHZOE DOUT (pipelined mode) tLZOE DOUT (flow-through mode) Q(A1)
INSERTS WAIT STATES tHZC
Q(A1)
Q(A2)
Q(A3)
Q(A3)
tHZC
Note: when MODE HIGH/No Connect; when MODE LOW. BW[a:d] don't care.
2/1/01
Alliance Semiconductor
7C33128PFS32A 7C33128PFS36A
Timing waveform write cycle
tCYC tADSPS tADSPH ADSP
tADSCS tADSCH ADSC
Address
ADSC LOADS ADDRESS
BW[a:d]
tCSS tCSH CE0,
SUSPENDS BURST tADVS tADVH
Data
D(A1) D(A2) D(A3)
Note: when MODE HIGH/No Connect; when MODE LOW.
2/1/01
Alliance Semiconductor
7C33128PFS32A 7C33128PFS36A
Timing waveform read/write cycle
tCYC tADSPS tADSPH ADSP Address
CE0,
tADVS tADVH
tLZC DOUT (pipeline mode) tCDF DOUT (flow-through mode) Q(A1)
D(A2) tHZOE tLZOE Q(A3)
Q(A1)
Note: when MODE HIGH/No Connect; when MODE LOW.
2/1/01
Alliance Semiconductor
7C33128PFS32A 7C33128PFS36A
test conditions
Output load: Figure except tLZC, tLZOE, tHZOE, tHZC, Figure Input pulse level: Figure Input rise fall time (measured 0.3V 2.7V): Figure Input output timing reference levels: 1.5V. +3.0V DOUT 1.5V 3.3V I/O; DDQ/2 2.5V DOUT +3.3V 3.3V I/O; +2.5V 2.5V *including scope capacitance Thevenin equivalent:
Figure Input waveform
Figure Output load
Figure Output load(B)
Notes test conditions, Test Conditions, Figures This parameter measured with output load condition Figure This parameter sampled, 100% tested. tHZOE less than tLZOE; tHZC less than tLZC given temperature voltage. measured HIGH above measured below VIL. This synchronous device. addresses must meet specified setup hold times rising edges CLK. other synchronous inputs must meet setup hold times rising edges when chip enabled. Write refers GWE, BWE, BW[a:d]. Chip select refers CE0, CE1, CE2.
Package Dimensions
100-pin quad flat pack (TQFP)
TQFP 0.05 0.15 1.35 1.45 0.22 0.38 0.09 0.20 13.90 14.10 19.90 20.10 0.65 nominal 15.90 16.10 21.90 22.10 0.45 0.75 1.00 nominal
Dimensions millimeters
2/1/01
Alliance Semiconductor
AS7C33128PFS32A AS7C33128PFS36A
Ordering information
-166 AS7C33128PFS32A-166TQC AS7C33128PFS32A-166TQI AS7C33128PFS36A-166TQC AS7C33128PFS36A-166TQI -150 AS7C33128PFS32A-150TQC AS7C33128PFS32A-150TQI AS7C33128PFS36A-150TQC AS7C33128PFS36A-150TQI -133 AS7C33128PFS32A-133TQC AS7C33128PFS32A-133TQI AS7C33128PFS36A-133TQC AS7C33128PFS36A-133TQI -100 AS7C33128PFS32A-100TQC AS7C33128PFS32A-100TQI AS7C33128PFS36A-100TQC AS7C33128PFS36A-100TQI
Part numbering guide
AS7C 32/36 -XXX
1.Alliance Semiconductor SRAM prefix 2.Operating voltage: 33=3.3V 3.Organization: 128=128K 4.Pipeline-Flowthrough (each device works both modes) 5.Deselect: S=Single cycle deselect 6.Organization: 32=x32; 36=x36 7.Production version: A=first production version 8.Clock speed (MHz) 9.Package type: TQ=TQFP 10.Operating temperature: C=Commercial I=Industrial (-40°
2/1/01; V.0.9
Alliance Semiconductor
Copyright Alliance Semiconductor Corporation. rights reserved. three-point logo, name Intelliwatt trademarks registered trademarks Alliance. other brand product names trademarks their respective companies. Alliance reserves right make changes this document products time without notice. Alliance assumes responsibility errors that appear this document. data contained herein represents Alliance's best data and/or estimates time issuance. Alliance reserves right change correct this data time, without notice. product described herein under development, significant changes these specifications possible. information this product data sheet intended general descriptive information potential customers users, intended operate provide, guarantee warrantee user customer. Alliance does assume responsibility liability arising application product described herein, disclaims express implied warranties related sale and/or Alliance products including liability warranties related fitness particular purpose, merchantability, infringement intellectual property rights, except express agreed Alliance's Terms Conditions Sale (which available from Alliance). sales Alliance products made exclusively according Alliance's Terms Conditions Sale. purchase products from Alliance does convey license under patent rights, copyrights, mask works rights, trademarks, other intellectual property rights Alliance third parties. Alliance does authorize products critical components life-supporting systems where malfunction failure reasonably expected result significant injury user, inclusion Alliance products such life-supporting systems implies that manufacturer assumes risk such agrees indemnify Alliance against claims arising from such use.

3.3V 128K 32/36 pipeline burst synchronous SRAM Features Organiza

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