Order Number: 242689-035 Pentium® processor contain design defect
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Pentium® Processor Specification Update
Order Number: 242689-035
Pentium® processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata documented this Specification Update.
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CONTENTS
REVISION HISTORY. PREFACE .vii Specification Update 150-, 166-, 180-, 200-MHz Pentium® Processors GENERAL INFORMATION. ERRATA. DOCUMENTATION CHANGES SPECIFICATION CLARIFICATIONS SPECIFICATION CHANGES
PENTIUM® PROCESSOR SPECIFICATION UPDATE
REVISION HISTORY
Date Revision November 1995 December 1995 Version -001 -002 Description This document first Specification Update Intel Pentium® processor. Added Errata through 3AP. Included additional Sspecs. Added case Erratum Clarified Errata Added Errata through Updated status Erratum Added documentation 166-, 180-, 200-MHz processors. Clarified Errata Updated status Errata Added CPUID information determining cache size. Added S-specs errata column stepping. Added Errata through Added Specification Change Documentation Change Clarified Erratum corrected Errata Added cache stepping information. Added Erratum Updated General Information section with S-specs marking diagrams. Corrected Erratum Added Erratum Added Specification Change Errata 4AP, Specification Clarifications through Documentation Changes Updated status Errata Updated S-spec table with additional corrected S-spec information. Added Specification Change Errata 5AP, Specification Clarifications Documentation Change Updated Erratum Updated Errata 2AP. Added Specification Changes through Errata 6AP, Specification Clarifications Updated Specification Change Added Errata through Added Specification Clarifications Updated Errata Added Specification Clarifications through Added Documentation Changes through Updated S-spec table. Updated Errata 6AP. Added Errata 8AP, Specification Clarifications Documentation Changes through Updated Specification Change Updated S-spec table corrected cache stepping SY040. Updated marking diagrams components. Updated Specification Change Erratum Added Specification Change Errata 9AP. Added Errata Added Specification Clarification Added Documentation Change Updated S-Spec table.
January 1996 February 1996
-003 -004
March 1996
-005
April 1996 1996 June 1996
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July 1996
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September 1996 October 1996 November 1996
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December 1996
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January 1997 March 1997
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PENTIUM® PROCESSOR SPECIFICATION UPDATE
Date Revision April 1997
Version -018
Description Added Errata Added Specification Clarifications Added Documentation Changes Updated Erratum title description. Updated Specification Clarification Updated Documentation Change Added engineering sample markings identification information. Added Erratum Added Specification Clarification Added Erratum Added Documentation Change Added Boxed Pentium Processor Markings; Errata Specification Clarification Documentation Changes Updated Erratum Specification Change Specification Clarification S-Spec table. Updated Erratum Added Specification Clarification Corrected S-spec table. Updated Erratum Added Errata Updated S-spec table. Updated Erratum Added Erratum Updated Specification Clarification Added Documentation Changes Added Documentation Change Updated Errata Added Erratum Added Specification Clarification Added Documentation Change Updated identification information. Added markings. Updated S-spec table. Updated Specification Changes Corrected Erratum Added Errata Updated Specification Clarification Corrected Documentation Change Added Documentation Change Updated Errata Added Errata Added Specification Changes Added Documentation Changes Added Erratum Updated Specification Clarification Added Specification Clarifications Added Documentation Changes Added Errata Added Documentation Change Updated Erratum Added Erratum Updated Erratum Added Specification Change Updated Errata Added Errata through Added Specification Clarifications Added Errata through Updated Documentation Change Added Documentation Change Added Erratum Updated Specification Change Updated Specification Change Added Documentation Change Added Errata
June 1997 August 1997 October 1997
-019 -020 -021
November 1997 December 1997 January 1998
-022 -023 -024
February 1998 March 1998 April 1998
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1998
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August 1998 September 1998 October 1998
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November 1998 December 1998 January 1999
-033 -034 -035
PENTIUM® PROCESSOR SPECIFICATION UPDATE
PREFACE
This document update specifications contained Pentium® Family Developer's Manual, Volumes (Order Numbers 242690, 242691, 242692, respectively) Pentium® Processor with Cache datasheet (Order Number 243570-001). intended hardware system manufacturers software developers applications, operating systems, tools. contains Specification Changes, S-Specs, Errata, Specification Clarifications, Documentation Changes. complete listing characterized errata OverDrive® processor, please refer Pentium® Processor Specification Update.
Nomenclature
Specification Changes modifications current published specifications. These changes will incorporated next release specifications. S-Specs exceptions published specifications, apply only units assembled under that s-spec. Specification Clarifications describe specification greater detail further highlight specification's impact complex design situation. These clarifications will incorporated next release specifications. Documentation Changes include typos, errors, omissions from current published specifications. These changes will incorporated next release specifications. Errata design defects errors. Errata cause Pentium processor's behavior deviate from published specifications. Hardware software designed used with given stepping must assume that errata documented that stepping present devices.
Identification Information
Pentium processor identified following values: Family1 0110 150-, 166-, 180-, 200-MHz Model 0001
NOTES: Family corresponds bits [11:8] register after RESET, bits [11:8] register after CPUID instruction executed with register, generation field Device register accessible through Boundary Scan. Model corresponds bits [7:4] register after RESET, bits [7:4] register after CPUID instruction executed with register, model field Device register accessible through Boundary Scan.
Pentium processor's level (L2) cache size determined following values: 256-Kbyte Unified Cache1 512-Kbyte Unified Cache1 1-Mbyte Unified Cache1
NOTE: this model Pentium® processor, unified cache size corresponds value bits [3:0] register after CPUID instruction executed with register. Other Intel microprocessor models families move this information other positions otherwise reformat result returned this instruction; generic code should parse resulting token stream according definition CPUID instruction.
Specification Update 150-, 166-, 180-, 200-MHz Pentium® Processors
PENTIUM® PROCESSOR SPECIFICATION UPDATE
GENERAL INFORMATION
256K 512K Cache-size Processors Markings
B-Step Production Units Top:
SYYYY 256K
sA-Step Production Units Top:
SYYYY LLLK
intel
FFFFFFFF-XXXX INTEL
intel
PENTIUM
FFFFFFFF-XXXX INTEL
sB1-Step Production Units Top:
SLYYY LLLK ICOMP® =CCC
intel
FFFFFFFF-XXXX INTEL
PENTIUM
PENTIUM® PROCESSOR SPECIFICATION UPDATE
256K 512K Cache-size Processors Bottom Markings
sA-Step Production Units Bottom:
XXXXXXXXAA YYYYYYYYAA MALAY
SYYYY LLLK
sB1-Step Production Units Bottom:
XXXXXXXXAA MMMMM
SLYYY 256K
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Cache-size Processors Markings
sB1-Step Production Units Top:
SYYYY
FYWWFFFF-XXXX INTEL
PENTI
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Boxed Pentium® Processor Markings
Markings
sA-Step Production Units Top:
SYYYY LLLK
sB1-Step Production Units Top:
SLYYY LLLK ICOMP® =CCC
intel
intel
FFFFFFFF-XXXX INTEL
PENTIUM
PENTIUM
FFFFFFFF-XXXX INTEL
Bottom Markings
sA-Step Production Units Bottom: sB1-Step Production Units Bottom:
XXXXXX YYYYYY
XXXXXX YYYYYY
SYYYY LLLK
SYYYY LLLK
NOTES: Speed (MHz). SYYYY S-spec Number. LLLK Level Cache Size. FFFFFFFF (Test Traceability
XXXX Serialization Code. XXXXXXXXAA Alternative Identification Number. side: inner line indicates boundary heat spreader.
PENTIUM® PROCESSOR SPECIFICATION UPDATE Basic 150-, 166-, 180-, 200-MHz Pentium® Processor Identification Information
CPUID Size/ Cache Mfg. Stepping Stepping Stepping 256/ 256/ 256/ 256/ 256/ 256/ 256/ 256/ 256/ 256/ 256/ 256/ 512/ 256/ 256/ 512/ 512/ 256/ 256/ 256/ 256/ 512/ 512/ 256/ 256/ 256/ 256/ 512/ 1024/ 1024/ Speed (MHz) Core/Bus 150/60 150/60 150/60 150/60 180/60 200/66 200/66 200/66 180/60 200/66 180/60 200/66 166/66 180/60 200/66 166/66 200/66 180/60 200/66 180/60 200/66 166/66 200/66 180/60 200/66 200/66 200/66 166/66 200/66 200/66
Type
Family
Model
S-Spec SY002 SY011 SY014 SY010 SY012 SY013 SL245 SL247 SU103 SU104 SY031 SY032 SY034 SY039 SY040 SY047 SY048 SL22S SL22T SL22U SL22V SL22X SL22Z SL23L SL23M SL254 SL255 SL2FJ SL259 SL25A
3.3V
TCASE
Notes
PENTIUM® PROCESSOR SPECIFICATION UPDATE
NOTES: Cache Stepping refers silicon revision 256-Kbyte, 512-Kbyte, Mbyte on-chip cache. designation refers first production steppings, second production steppings, stepping logically equivalent stepping, different manufacturing process. pins supported these parts. pins functional tested these parts. These components have additional specification changes associated with them: VCCP Primary PMAX Thermal Design Power 39.4W MHz, 256K ICCP VCCP Current 11.9A pins supported these parts. Minimum GTL+ Input Hold Time VIHmin Minimum Non-GTL+ Input High Voltage [Only PICD[1:0] signals affected. Clocks
unaffected] This boxed Pentium® processor with unattached heatsink. This part also ships boxed processor with unattached heatsink. Please reference Pentium® Processor with Cache datasheet, Section 2.13, Specification," Table "Power Voltage Specification (Option 1)," Table "Power Voltage Specification (Option 2)," VCCP options.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Summary Table Changes
following table indicates Specification Changes, Errata, Specification Clarifications, Documentation Changes which apply 150-, 166-, 180-, 200-MHz Pentium processors. Intel intends some errata future stepping component, account other outstanding issues through documentation specification changes noted. This table uses following notations: CODES USED SUMMARY TABLE Doc: Fix: Fixed: NoFix: mark) (blank box): Shaded: Specification Change, Erratum, Specification Clarification, Documentation Change applies given stepping. Intel intends update appropriate documentation future revision. Intel investigating possibility fixing this erratum future stepping component(s). This erratum intended fixed future stepping component. There plans this erratum. This item fixed does apply given stepping. APIC related erratum. This item either modified from previous version document. Plans NoFix NoFix ERRATA Mixed cacheability lock variables problematic systems Data Operand Pointer incorrectly calculated after access which wraps 64-Kbyte boundary 16-bit code Differences exist debug exception reporting FLUSH# servicing delayed while waiting STARTUP_IPI systems Fast Strings MOVS transfer data Page table base change during task switch using Mode paging corrupt Code fetch matching disabled debug register cause debug exception Mode paging causes incorrect page tables Memory indirect near call corrupt single-bit correctable error cancel simultaneous valid data Page split access before write cause hang Active A20M# during dump Split access across 4-Kbyte page boundary cause hang
NoFix NoFix Fixed Fixed
NoFix NoFix Fixed Fixed Fixed Fixed Fixed
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Plans NoFix NoFix Fixed Fixed Fixed Fixed
ERRATA Checker BIST failure mode signaled BINIT# assertion causes FRCERR assertion mode Extra page fault occur IRET during task switch Some caching models cause shutdown Fast Strings feature re-enabled after INIT event THERMTRIP# feature present instruction, Branch Trace Message write incorrect data THERMTRIP# asserted catastrophic thermal condition LBER value updated correctly Bfor will contain incorrect FROM Task switch fault allow read access linear address frequencies with core clock ratio fail RDPMC cannot used conjunction with PWRGOOD forced during boundary scan resets BIST failure indicated when RUNBIST command used INVLPG invalidate targeted ITLB entry does flush entries with enabled restart fail after simultaneous SMBASE reset INIT# INIT_IPI error gives MCACOD.LL INVLPG does invalidate entire 4-Mbyte region BINIT# assertion during snoop cause double Machine Check Exception Machine Check Exception handler always execute successfully Double error read result BINIT# cannot return HALT SHUTDOWN 32-bit Accesses Modified data hang system Branch traps function BTMs also enabled Cache line exist different ways system HALT, SHUTDOWN, STPCLK special cycles issued
Fixed Fixed Fixed NoFix NoFix Fixed
Fixed Fixed Fixed Fixed Fixed NoFix Fixed NoFix Fixed Fixed
NoFix NoFix Fixed Fixed
NoFix Fixed
Fixed
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Plans Fixed
ERRATA cache incorrectly report BIST failure LOCK prefix does generate trap with some instructions FRCERR incorrectly asserted explicit writeback cycles inexact-result exception flag Snoop during segment load hang system Mbyte-aligned base address causes SHUTDOWN Machine Check Exception with coexisting large small pages WBINVD some modified addresses hangs system store reordered around transaction Spurious Error Reported With MCEs Enabled Extended TRDY# cause hang with DBSY# asserted Call gates cause incorrect handling stack size attribute LBER corrupted after some events during string instruction clears BTMs corrupted during simultaneous cache line replacement Spurious Machine Check Exception Data Parity Error Loss inclusion cause Machine Check Exception Controller automatically reset power-up Erroneous signaling user mode protection violation Invalid operation signaled FIST instruction some range operands EFLAGS incorrect after multiprocessor shootdown Possible system hang when paging disabled reenabled from uncached memory FLUSH# assertion disables Machine Check Exception reporting Delayed line invalidation issue during 2-way data ownership transfer Potential early deassertion LOCK# during Split-Lock Cycles A20M# inverted after returning from RESET
NoFix Fixed
NoFix Fixed Fixed
NoFix Fixed Fixed Fixed
NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Plans NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix Fixed
ERRATA EFLAGS discrepancy page fault after multiprocessor shootdown Near CALL creates unexpected address Memory type undefined nonmemory operations protocol conflict with optimized chipsets Data Operand Pointer zero after power Reset Premature execution load operation prior exception handler invocation Read Portion Instruction execute twice Intervening writeback occur during locked transaction MC2_STATUS Model Specific error code Machine Check Architecture error code reversed with debug register causes debug exception Data breakpoint exception displacement relative near call corrupt Misprediction program flow cause unexpected instruction execution RDMSR WRMSR invalid address cause fault SYSENTER/SYSEXIT instructions implicitly load "null segment selector" registers PRELOAD followed EXTEST does load boundary scan data jump with D-bit cleared cause system hang corrupted break return from handler Registers corrupted after break during string instruction HALT command corrupt state HALT command will bring processor AutoHALT state Power Mode Incorrect chunk ordering prevent execution Machine Check Exception handler after BINIT# Resume flag cleared after debug exception Misaligned locked access APIC space results hang Potential loss data coherency during data ownership transfer APIC access cacheable memory causes SHUTDOWN
Fixed Fixed NoFix NoFix NoFix NoFix NoFix NoFix
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Plans NoFix Fixed Fixed Fixed Fixed
ERRATA Possible hang catastrophic errors during determination INIT_IPI after STARTUP_IPI-STARTUP_IPI sequence cause execute Small window system hang after INIT# INIT_IPI Virtual Wire mode through local APIC cause Divide Zero error LINT0 glitch Write mask (programmed EXTINT) will deassert outstanding interrupt respond STARTUP_IPI after INIT# INIT_IPI Power Mode Serial interrupts lost APIC mixed mode DOCUMENTATION CHANGES number status word, Volume page 7-50 GTL+ edge rate range incorrect Power-on configuration register documented inconsistently GTL+ minimum overshoot specification Conditional move opcode incorrect entries 4-Kbyte pages ITLB value should Register names incorrect CPUID return value Corrections Volume Programmer's Reference Manual Remapping memory types B"From" "To" fields reversed Numeric underflow exception description clarification Page directory pointer table register present identification Flushing caches upon entering General protection fault description Invalid arithmetic operations masked responses them relative FIST/FISTP instruction Limit checking Flag usage correction MCI_ADDR reference section correction MC2_STATUS description correction FCOMI/FCOMIP/FUCOMI/FUCOMIP setting flags relative exceptions
NoFix NoFix NoFix Plans
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Plans Plans
DOCUMENTATION CHANGES Cache management instructions correction PUSH does with zeros DR7, reserved Additional states that automatically saved restored Cache description correction SMRAM State Save Contains Documentation Error EFLAGS Register mislabeled System Flags CS:EIP pushed onto stack prior code segment limit check BREQ# sampled incorrectly Corrections opcode maps initialization protocol algorithm correction Interrupt 13-General Protection Exception (#GP) Addition Lock instruction description RSVD flag definition correction SMRAM state save documentation correction SPECIFICATION CLARIFICATIONS Signal edge rate tolerant, APIC, JTAG signals OUTS instruction subsequent instructions Interrupt recognition determines priority References 2-Mbyte pages should include 4-Mbyte pages Modification reserved areas SMRAM saved state FRCERR asserted checker BIST failure Deassertion BREQn# during RESET# flush necessary after PDPE change LOCK# deasserted between locked sequences EXF4# assertion Preventing caching Mci_CTL registers cleared INIT# Stack during interrupts, exceptions, CALLs Performance-Monitoring counter issues Clock jitter measurement clarification
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Plans Plans
SPECIFICATION CLARIFICATIONS Exception handler error code clarification Clock frequencies ratios OverDrive® processors BERR# description clarification IERR# description clarification Propagation page table entry changes multiple processors APIC status cycles interpretation Multiple processors protocol restrictions handling while Critical sequence events during page fault exception POP[ESP] with 16-bit stack size Paging must enabled before enabling page global enable SMIACK transaction generated exiting from Software initialization requirements mode Switching protected mode while SPECIFICATION CHANGES Mixing steppings systems Change PICD[1:0] hold time valid delay Undershoot specification some GTL+ signals OverDrive® motherboard bulk capacitance specification MTRR precedences memory type overriding VCCS pins removed from specification Split lock across cache line boundary disable added Instruction streaming buffer disable added System timings changes Minimum storage specification change processors with cache buffer eviction data ordering
PENTIUM® PROCESSOR SPECIFICATION UPDATE
ERRATA
Mixed Cacheability Lock Variables Problematic Systems
PROBLEM: This errata only affects multiprocessor systems where lock variable address marked cacheable
processor uncacheable others. processors which have marked uncacheable stall indefinitely when accessing lock variable. stall only encountered processor lock variable cached, attempting execute cache lock. processor which that address cached cached only. Several other processors, meanwhile, issue back back accesses that same address bus.
IMPLICATION: systems where processors either cache locks consistent locks uncacheable
space will encounter this problem. however, lock variable's cacheability varies different processors, several processors attempting perform lock simultaneously, indefinite stall experienced processors which have marked uncacheable locking variable conditions above satisfied). Intel only encountered this problem focus testing with artificially generated external events. Intel currently identified commercial software which exhibits this problem.
WORKAROUND: Follow homogenous model memory type range registers (MTRRs), ensuring that
processors have same cacheability attributes each region memory; locks whose memory type cacheable processor, uncacheable others. Avoid page table aliasing, which produce nonhomogenous memory model.
STATUS: steppings affected Summary Table Changes beginning this section.
Data Operand Pointer Incorrectly Calculated After Access Which Wraps 64-Kbyte Boundary 16-Bit Code
PROBLEM: Data Operand Pointer effective address operand associated with last
noncontrol floating-point instruction executed machine. 80-bit floating-point access (load store) occurs 16-bit mode other than protected mode which case access will produce segment limit violation), memory access wraps 64-Kbyte boundary, floating-point environment subsequently saved, value contained Data Operand Pointer incorrect.
IMPLICATION: 32-bit operating system running 16-bit floating-point code encounter this erratum, under
following conditions: operating system using segment greater than Kbytes size. application running 16-bit mode other than protected mode. 80-bit floating-point load store which wraps 64-Kbyte boundary executed. operating system performs floating point environment store (FSAVE/FNSAVE/FSTENV/FNSTENV) after above memory access. operating system uses value contained Data Operand Pointer.
Wrapping 80-bit floating-point load around segment boundary this normal programming practice. Intel currently identified software which exhibits this behavior.
WORKAROUND: Data Operand Pointer used which 16-bit floating-point code, care must taken ensure that 80-bit floating-point accesses wrapped around 64-Kbyte boundary.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
STATUS: steppings affected Summary Table Changes beginning this section.
Differences Exist Debug Exception Reporting
PROBLEM: There exist some differences reporting code data breakpoint matches between that specified previous Intel processors' specifications behavior Pentium processor, described below:
CASE first case breakpoint MOVSS POPSS instruction, when instruction following causes debug register protection fault (DR7.gd already set, enabling fault). Pentium processor reports delayed data breakpoint matches from MOVSS POPSS instructions setting matching DR6.bi bits, along with debug register protection fault (DR6.bd). additional breakpoint faults matched during call debug fault handler, Pentium processor sets breakpoint match bits (DR6.bi) reflect breakpoints matched both MOVSS POPSS breakpoint debug fault handler call. Pentium processor only sets DR6.bd either situation, does DR6.bi bits. CASE second breakpoint reporting failure case, MOVSS POPSS instruction with data breakpoint followed store memory which crosses 4-Kbyte page boundary, breakpoint information MOVSS POPSS will lost. Previous processors retain this information across such page split. CASE they occur after MOVSS POPSS instruction, INTO, INT3 instructions zero DR6.Bi bits (bits through B3), clearing pending breakpoint information, unlike previous processors. CASE data breakpoint (System Management Interrupt) occur simultaneously, will serviced call handler, pending breakpoint will lost. CASE When instruction which accesses debug register executed, breakpoint encountered instruction, breakpoint reported twice.
IMPLICATION: When debugging when developing debuggers Pentium processor system, this behavior should noted. Normal usage MOVSS POPSS instructions (i.e., following them with ESP) will exhibit behavior cases 1-3. Debugging conjunction with will limited case workaround been identified this case). WORKAROUND: Following MOVSS POPSS instructions with instruction when using breakpoints will avoid first three cases this erratum. There known workarounds cases STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
FLUSH# Servicing Delayed While Waiting STARTUP_IPI Systems
PROBLEM: multiprocessor system, application processor waiting startup interprocessor
interrupt (STARTUP_IPI), then will service FLUSH# assertion until received STARTUP_IPI.
IMPLICATION: After initialization protocol, only processor becomes bootstrap processor (BSP).
others become slave application processors (APs). After losing arbitration, into wait loop waiting STARTUP_IPI. wake perform some tasks with STARTUP_IPI, then more back sleep with initialization interprocessor interrupt (INIT_IPI, which same affect asserting INIT#), which returns them wait loop. result possible loss cache coherency offline processor intended service FLUSH# assertion this point. FLUSH# will serviced soon processor awakened STARTUP_IPI, before other instructions executed. Intel encountered operating systems that affected this problem.
WORKAROUND: Operating system developers should take care execute WBINVD instruction before taken offline using INIT_IPI. STATUS: steppings affected Summary Table Changes beginning this section.
Fast Strings MOVS Transfer Data
PROBLEM: fast strings feature enabled (bit 1E0h MOVS instruction
incorrectly pre-decremented counter, thereby skipping cache line transfer. This will only occur paging enabled.
IMPLICATION: MOVS instruction executed with this feature enabled transfer requested data, leading stale data being left destination. WORKAROUND: steppings affected this erratum, fast strings feature must disabled BIOS, setting machine specific register (MSR) address 1E0h `1'. STATUS: steppings affected Summary Table Changes beginning this section.
Page Table Base Change During Task Switch Using Mode Paging Corrupt
PROBLEM: While using mode paging 36-bit address extension which uses 2-Mbyte pages), data
written during task switch, will corrupted, resulting unpredictable failure. CR3, which contains page table base, will written during task switch switch moving paging environment, entries must cleared.
IMPLICATION: operating system which uses hardware tasking model (via task switch segment, TSS) along with 36-bit extension mode paging, fail, most likely with invalid opcode exception. Intel identified operating systems which this combination features. WORKAROUND: When developing operating system which uses mode paging, hardware task switching, else only perform hardware task switches which change page table base register, CR3. STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Code Fetch Matching Disabled Debug Register Cause Debug Exception
PROBLEM: bits L0-3 G0-3 enable breakpoints local task global tasks, respectively. these bits set, breakpoint enabled, corresponding addresses debug registers DR0-DR3. least these breakpoints enabled, these registers disabled (i.e., disabled register (indicating breakpoint instruction execution), normally instruction fetch will cause instruction-breakpoint fault based match with address disabled register(s). However, address disabled register matches address code fetch which also results page fault, instruction-breakpoint fault will occur. IMPLICATION: While debugging software, extraneous instruction-breakpoint faults encountered breakpoint registers cleared when they disabled. Debug software which does implement code breakpoint handler will fail, this occurs. handler present, fault will serviced. Mixing data code exacerbate this problem allowing disabled data breakpoint registers break instruction fetch. WORKAROUND: debug handler should clear breakpoint registers which become disabled. STATUS: steppings affected Summary Table Changes beginning this section.
Mode Paging Causes Incorrect Page Tables
PROBLEM: mode paging 36-bit address extension which uses 2-Mbyte pages) use,
serviced, handler switches mode paging with different page tables, then upon returning from handler instruction, processor will wrong page tables address translation. Since paging not, general, supported SMM, this violation Pentium processor specification, been removed erratum, been included here continuity.
IMPLICATION: Using mode paging both normal operation System Management Mode (SMM) cause system hang. Intel currently identified software which affected this erratum. This violation Pentium processor specification; large size pages supported SMM. WORKAROUND: mode paging handler code. STATUS: steppings affected Summary Table Changes beginning this section.
Memory Indirect Near Call Corrupt
PROBLEM: Under some conditions, near indirect call (opcode cause corruption after partial completion instruction's execution. This occur access near indirect call:
Accesses memory which crosses page boundary. Results misaligned data breakpoint exception. first access page containing data used call. Results page fault which, upon walking page tables (see Erratum 13), found faulting condition.
IMPLICATION: most likely failure mechanism this erratum invalid opcode exception. WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Single-Bit Correctable Error Cancel Simultaneous Valid Data
PROBLEM: single-bit correctable error detected Pentium processor transaction between
data cache unit (DCU) cache, there second transaction pending which caches data from Pentium processor bus, Pentium processor will cancel both transactions instead just transaction which error occurred.
IMPLICATION: canceled transaction will never complete under these conditions. Single-bit errors which encounter this boundary condition will cause Pentium processor hang. However, since this erratum only affects error recovery, normal, hardware error-free execution will affected. WORKAROUND: None identified. STATUS: steppings affected Summary Table Changes beginning this section.
Page Split Access Before Write Cause Hang
PROBLEM: paging enabled, memory access occurs which crosses page boundary, future write
cause processor hang. write must occur specific time interval away from page split access; focus-testing, only test which encountered this hang mode paging instructions between split access write CR3. When using mode paging (2-Mbyte pages), probability encountering this erratum increased somewhat.
IMPLICATION: Using paging conjunction with writes invalidate page tables change paging environment) cause system hang. There small, timing dependent window opportunity encounter this erratum, which wider mode paging used. WORKAROUND: Some instructions inserted between memory access write prevent this erratum, such
CPUID, STD, CLD, CLI/STI.
Though following instructions between memory access write prevent erratum, they suitable situations workarounds this erratum their effect dependency system state: WRMSR, RDMSR, RDPMC, LDS, LFS, LGS, LSS, LES, CR0, reg, CR2, reg, CR4, reg, reg, reg, reg,
PENTIUM® PROCESSOR SPECIFICATION UPDATE
reg, reg, transfer, interrupt, software interrupt.
these which occur between memory access which crosses 4-Kbyte boundary write will prevent conditions necessary this erratum occur. long latency, nonstring instruction will also prevent erratum.
STATUS: steppings affected Summary Table Changes beginning this section.
Active A20M# During Dump
PROBLEM: A20M# signal (mask A20) active when handler saving state information
dump space prior executing handler code, state information will partially saved address with masked, partially with unmasked.
IMPLICATION: dump space uses addresses megabyte (A20 high), stored state will split among different address spaces system will recover state correctly after instruction. WORKAROUND: Either ensure that dump space does coincide with odd-megabyte addresses (under Mbyte acceptable), external logic prevent servicing until A20M# deasserted. STATUS: steppings affected Summary Table Changes beginning this section.
Split Access Across 4-Kbyte Page Boundary Cause Hang
PROBLEM: When load store access split across page boundary, page fault detected. page fault signaled during such access, Pentium processor will walk page table ensure that page being made accessible another agent (such another processor system, controller) before branching page fault handler. split access signals page fault, page which caused fault then found nonfaulting during page table walk, access will executed incorrectly, resulting hang. IMPLICATION: When multiple agents capable changing page table, load store which split across page boundary cause machine hang. WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
Checker BIST Failure Mode Signaled
PROBLEM: system running functional redundancy checking (FRC) mode, checker master-checker pair encounters hard failure while running built-in self test (BIST), checker will tri-state outputs without signaling IERR#. IMPLICATION: Assuming master passes BIST successfully, will continue execution unchecked, operating without functional redundancy. However, necessary pull-up FRCERR will cause FRCERR signaled. operation master depends implementation FRCERR. WORKAROUND: successful detection BIST failure checker pair, FRCERR signal
must used, instead IERR#.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
STATUS: steppings affected Summary Table Changes beginning this section.
BINIT# Assertion Causes FRCERR Assertion Mode
PROBLEM: pair Pentium processors running functional redundancy checking (FRC) mode, catastrophic error condition causes BINIT# asserted, checker master-checker pair will enter shutdown. next transaction from master will then result assertion FRCERR. IMPLICATION: initialization assertion BINIT# occurs result catastrophic error condition which precludes continuing reliable execution system. Under normal circumstances, masterchecker pair would remain synchronized execution BINIT# handler. However, this erratum, FRCERR will signaled. System behavior then depends implementation FRCERR. WORKAROUND: None identified. STATUS: steppings affected Summary Table Changes beginning this section.
Extra Page Fault Occur IRET During Task Switch
PROBLEM: During hardware task switch (using task switch segment, TSS) which jumps task with IRET which causes page fault, second page fault exception generated upon completion page miss handler routine, prompting Pentium processor execute page miss handler second time. IMPLICATION: Intel identified adverse implications this anomaly other than slight performance loss from executing page miss handler twice after task switch which causes page fault. WORKAROUND: None identified. STATUS: steppings affected Summary Table Changes beginning this section.
Some Caching Models Cause Shutdown
PROBLEM: condition exists Pentium processor such that upon returning from handler (via instruction), read executed soon data successfully loaded. This condition occurs whenever load read delayed because cache line which load accesses present cache. This occur
handler large into cache. WBINVD instruction executed upon servicing SMI. handler being memory mapped with (uncacheable) memory type.
When instruction executed under these conditions, first memory access after will cause multiple stack faults, Pentium processor will enter shutdown.
IMPLICATION: Under many operating conditions, returning from will result entering shutdown. WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Fast Strings Feature Re-enabled After INIT Event
PROBLEM: Fast Strings feature been disabled machine specific registers (MSRs) clearing appropriate `0'), after INIT initialization interprocessor interrupt (INIT_IPI), will `1'), feature will re-enabled. IMPLICATION: After each INIT INIT_IPI event, this feature will re-enabled, exposing system effects Erratum WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
THERMTRIP# Feature Present
PROBLEM: THERMTRIP# feature documented Pentium processor present. IMPLICATION: Pentium processor will shut down upon reaching catastrophic thermal condition defined Pentium® Processor Developer's Manual, Volume WORKAROUND: System manufacturers implement thermal management solution which does rely
upon THERMTRIP#.
STATUS: steppings affected Summary Table Changes beginning this section.
Instruction, Branch Trace Message Write Incorrect Data
PROBLEM: data cache load blocked internal conditions, speculatively awakened Pentium processor. this speculative wakeup occurs same time that instruction branch trace message (BTM) dispatched, load access crosses cache line boundary, buffer which contains data Bwill corrupted. IMPLICATION: Some instructions BTMs propagate corrupted data. WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
THERMTRIP# Asserted Catastrophic Thermal Condition
PROBLEM: catastrophic thermal condition reached specified Pentium® Processor
Developer's Manual, Volume processor will correctly shut down until hard reset performed. However, THERMTRIP# pin, which should asserted after processor shuts down, will remain unasserted.
IMPLICATION: processor shuts down catastrophic thermal condition, there will electrical indication reason shutdown, since THERMTRIP# will asserted. WORKAROUND: external temperature sensor should implemented system design requires notification
that catastrophic thermal condition caused system shut down.
STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
LBER Value Updated Correctly
PROBLEM: last branch record (LBR) last branch before exception record (LBER) used determine source destination information previous branches exceptions. contains source destination addresses last branch exception, LBER contains similar information last branch taken before last exception. This information typically used determine location branch which leads execution code which causes exception. However, after executing trap under some conditions, LBER updated after branch, updated incorrectly. IMPLICATION: LBER registers used only debugging purposes. When this erratum occurs, LBER will contain reliable address information. value LBER should used with caution when debugging branching code; values LBER same, value LBER value LBER same before after trap, then LBER value incorrect. WORKAROUND: None identified. STATUS: steppings affected Summary Table Changes beginning this section.
Bfor Will Contain Incorrect FROM
PROBLEM: system management interrupt (SMI) will produce branch trace message (BTM), BTMs enabled. However, FROM field B(used determine address instruction which being executed when serviced) will have been updated SMI, field will report same FROM previous BTM. IMPLICATION: Bwhich issued will contain correct FROM EIP, limiting usefulness BTMs debugging software conjunction with System Management Mode (SMM). WORKAROUND: None identified. STATUS: steppings affected Summary Table Changes beginning this section.
Task Switch Fault Allow Read Access Linear Address
PROBLEM: this erratum occur, following conditions must satisfied:
Task State Segment (TSS) must used handle task switches. task switch fault must occur while loading segment descriptors task switch. resulting task switch fault handler call must result task switch. task switch fault handler must executed successfully return task switch using return IRET instruction.
Upon coincidence these conditions, data segment registers which were loaded task switch will permit read access single byte linear address
IMPLICATION: Under these circumstances, target task privilege level allowed read byte linear address which normally permitted read. Intel currently identified software which could cause this behavior. WORKAROUND: When developing operating system which uses process task switches, task
switch fault should also generate task switch using TSS.
STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Frequencies With Core Clock Ratio Fail
PROBLEM: functional redundancy checking (FRC) system using core clock ratio, running frequencies 120/48 lower, phase-locked loops (PLL) master-checker pair function correctly, resulting assertion FRCERR with first request Pentium processor bus. first request does result assertion FRCERR, system will function normally. minimum core frequency specification Pentium® Processor Developer's Manual, Volume MHz. IMPLICATION: system should core frequencies lower than with core clock ratio. necessary system always begin executing correctly, power-cycling system after such behavior allow normal operation. WORKAROUND: system specified frequency, power-cycle system necessary
system under these conditions.
STATUS: steppings affected Summary Table Changes beginning this section.
RDPMC Cannot Used Conjunction With
PROBLEM: performance counter enable (PCE) (bit CR4) enabled (set `1'), instruction executed, processor will enter shutdown state, believing that reserved space been altered. IMPLICATION: operating system enable user code issue RDPMC (Read
Performance Monitor Counter) instruction. systems which support SMM, this should set, this instruction will available. However, performance monitoring capabilities Pentium processor still available through driver-based applications.
WORKAROUND: prevent shutdown from occurring, handler code clear this bit. However, this
will disable ability users issue RDPMC instruction, application which attempts issue this instruction after handler code been executed will cause general protection fault, unless operating system re-enabled setting bit.
STATUS: steppings affected Summary Table Changes beginning this section.
PWRGOOD Forced During Boundary Scan Resets
PROBLEM: According IEEE 1149.1-1990 (JTAG) Specification, rule 5.3.1(b), component input should initialize test access port (TAP) controller, other test logic within component. However, PWRGOOD Pentium processor forced will reset Controller. IMPLICATION: boundary scan testing forces PWRGOOD boundary scan errors will result. WORKAROUND: force PWRGOOD during boundary scan testing. BSDL file test vectors
edited ensure that this does occur, changing declaration PWRGOOD from `input' `internal' with safe value Note that while this will allow boundary scan tests generated correctly, will allow PWRGOOD tested.
STATUS: steppings affected Summary Table Changes beginning this section.
BIST Failure Indicated When RUNBIST Command Used
PROBLEM: test access port (TAP) RUNBIST command intended during boundary scan testing, should built-in self test (BIST), storing result BIST result register after completion. zero
PENTIUM® PROCESSOR SPECIFICATION UPDATE
result indicates BIST passed, nonzero result indicates BIST failure. Currently, this command executed from TAP, zero result will stored BIST result register regardless whether BIST passes fails.
IMPLICATION: Running RUNBIST command from will indicate failing condition. This command
functional steppings Pentium processor affected this erratum.
WORKAROUND: None identified. However, BIST still separately from boundary scan, allowing INIT# signal sampled active RESET# signal's active inactive transition. this case, passage failure indicated EAX. STATUS: steppings affected Summary Table Changes beginning this section.
INVLPG Invalidate Targeted ITLB Entry
PROBLEM: When INVLPG instruction used, entry translation look-aside buffer (TLB) which corresponds given address should invalidated, under most circumstances preserving validity rest TLB. However, variable memory type range registers (MTRRs) used region memory particular memory type, this occur. Specifically, variable MTRR specifies range which 4-Mbyte aligned (i.e., MTRR's mask register contains value with more bits range [21:12] nonzero), INVLPG instruction will invalidate proper entry data (DTLB), doing, lose information necessary invalidate entry instruction (ITLB). will, instead, invalidate entry ITLB, leaving stale translation ITLB. subsequent code fetch from addresses this entry will retrieve execute incorrect instructions. IMPLICATION: INVLPG entry cannot used system with MTRR range which 4-Mbyte
aligned.
WORKAROUND: BIOS operating system code should variable MTRR range which 4-Mbyte
aligned. such ranges should have bits [21:12] MTRR's mask register processor steppings affected this erratum.
STATUS: steppings affected Summary Table Changes beginning this section.
Does Flush Entries With Enabled
PROBLEM: When SMI# asserted, entries translation lookaside buffer (TLB) should flushed. However, entries with page global enable (PGE) will flushed from TLB. IMPLICATION: (System Management Mode) handler access address which will incorrectly translated stale entries TLB, resulting unexpected system behavior. WORKAROUND: write executed clear TLBs upon entry into SMM, then BIOS code
contain workaround this erratum.
STATUS: steppings affected Summary Table Changes beginning this section.
Restart Fail After Simultaneous
PROBLEM: instruction (IN, INS, INS, OUT, OUTS, OUTS) being executed, data this instruction becomes corrupted, Pentium processor will signal machine check exception (MCE). instruction directed device which powered down, processor also receive assertion SMI#. Since MCEs have higher priority, processor will call handler, SMI# assertion will remain pending. However, upon attempting execute first instruction handler,
PENTIUM® PROCESSOR SPECIFICATION UPDATE
SMI# will recognized processor will attempt execute handler. handler completed successfully, will attempt restart instruction, will have correct machine state, call handler.
IMPLICATION: simultaneous SMI# assertion occur instructions above. handler attempt restart such instruction, will have corrupted state handler call, leading failure restart SHUTDOWN processor. WORKAROUND: system implementation must support both MCEs, first thing handler
code (when restart performed) should check pending MCE. there pending, handler should immediately exit instruction allow machine check exception handler execute. there not, handler proceed with normal operation.
STATUS: steppings affected Summary Table Changes beginning this section.
SMBASE Reset INIT# INIT_IPI
PROBLEM: systems which support System Management Mode (SMM), default value SMBASE 30000h. This value changed, particularly systems, where processors' spaces overlap. However, when assertion INIT# initialization interprocessor interrupt (INIT_IPI) received Pentium processor, value SMBASE reset 30000h. IMPLICATION: assertion INIT# INIT_IPI will clear changes made SMBASE value. WORKAROUND: possible that BIOS code contain workaround this erratum, systems which
contain subsequent steppings Pentium processor silicon. workaround available stepping Pentium processor.
STATUS: steppings affected Summary Table Changes beginning this section.
Cache Error Gives MCACOD.LL
PROBLEM: error occurs access Pentium processor's cache, resulting Machine Check Exception (MCE) will logged with `01' field MCACOD. This value indicates cache error; value should `10'. IMPLICATION: cache access will improperly logged error. WORKAROUND: None identified. STATUS: steppings affected Summary Table Changes beginning this section.
INVLPG Does Invalidate Entire 4-Mbyte Region
PROBLEM: When using large paging modes (mode mode paging), entry created large page beginning address This page cover 4-Mbyte region. fixed memory type range registers (MTRRs) used conjunction with these paging modes, entries 4-Kbyte pages also created lower 1-Mbyte region memory. INVLPG instruction used invalidate these 4-Kbyte pages, large page which covers same region will invalidated; conversely, large page invalidated using INVLPG (with address from Mbytes), 4-Kbyte entries will invalidated. IMPLICATION: Intel currently identified software which affected this erratum. However, using INVLPG invalidate regions from Mbyte from Mbytes result stale data other part 4-Mbyte range expected invalidated when using 4-Mbyte pages 2-Mbyte
PENTIUM® PROCESSOR SPECIFICATION UPDATE
software uses 2-Mbyte pages). Future operating systems affected this erratum, only 4-Mbyte page invalidated using INVLPG. Since this page would most likely contain operating system kernel code, unlikely that such operating system would designed invalidate this page.
WORKAROUND: Operating systems should 4-Mbyte page address unless writes register performed clear entries this region set, this must cleared prior writing CR3, clear global pages). This will invalidate entire TLB. 4-Mbyte page used, INVLPG instructions used invalidate this region, INVLPG instructions must used repeatedly invalidate large page well 4-Kbyte ranges which should invalidated. STATUS: steppings affected Summary Table Changes beginning this section.
BINIT# Assertion During Snoop Cause Double Machine Check Exception
PROBLEM: cache locked modified cache line response external snoop, then assertion BINIT# between time ADS# asserted snoop time that implicit writeback data transferred cause double machine check exception (MCE). double encountered artificial internal parity errors generated BINIT# handler during cleanup routines. IMPLICATION: BINIT# cause processor shut down response double generated above conditions occur. IERR# will asserted, further operations possible until hard reset performed. WORKAROUND: BINIT# asserted upon detection catastrophic system condition. Leaving MCEs disabled
will result BINIT# causing enter shutdown well. avoid shutdown, BINIT# observation disabled. However, condition which would result generation BINIT# cause corrupt data propagated, unexpected system behavior occur. workaround which would enable BINIT# recognized this window without causing shutdown been identified.
STATUS: steppings affected Summary Table Changes beginning this section.
Machine Check Exception Handler Always Execute Successfully
PROBLEM: asynchronous machine check exception (MCE), such BINIT# event, which occurs during
access that splits 4-Kbyte page boundary leave some internal registers indeterminate state. Thus, handler code always successfully asynchronous occurred previously.
IMPLICATION: always result successful execution handler, hanging
CPU.
WORKAROUND: MCEs enabled, execution handler will occur. However, asynchronous MCEs usually occur upon detection catastrophic system condition. Leaving MCEs disabled will result condition which caused asynchronous instead causing enter shutdown. Therefore, leaving MCEs disabled improve overall system behavior. workaround which would guarantee successful handler execution under this condition been identified. STATUS: steppings affected Summary Table Changes beginning this section.
Double Error Read Result BINIT#
PROBLEM: this erratum occur, following conditions must met:
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Machine check exceptions (MCEs) must enabled. dataless transaction (such write invalidate) must occurring simultaneously with transaction which returns data normal read). read data must contain double-bit uncorrectable error.
these conditions met, Pentium processor will able determine which transaction erroneous, instead generating MCE, will generate BINIT#.
IMPLICATION: will reinitialized this case. However, since double-bit uncorrectable error occurred read, handler (which normally reached double-bit uncorrectable error read) would most likely cause same BINIT# event. WORKAROUND: Though ability drive BINIT# disabled Pentium processor, which would
prevent effects this erratum, overall system behavior would improve, since error which would normally cause BINIT# would instead cause machine shut down. other workaround been identified.
STATUS: steppings affected Summary Table Changes beginning this section.
Cannot Return HALT SHUTDOWN 32-Bit
PROBLEM: processor which previously operating 32-bit protected mode shut down executed instruction, then targeted System Management Interrupt (SMI), handler will executed different mode. Upon returning HALT SHUTDOWN state RSM, mode state will correctly updated back 32-bit protected mode, potentially crashing operating system. IMPLICATION: Systems which support hang software which executes instructions being run, processor expected able recover from SHUTDOWN state software recovery which uses SMM. WORKAROUND: HALT case, handler code clear Halt Auto Restart dump
space (offset 7F02h), then subtract from saved (offset 7FF0h). This will cause instruction re-executed upon completion RSM, which will allow 32-bit protected mode re-entered processor successfully enter HALT state. workaround currently been identified SHUTDOWN case; however, guaranteed that will properly serviced when this state.
STATUS: steppings affected Summary Table Changes beginning this section.
Accesses Modified Data Hang System
PROBLEM: Under heavy traffic system with multiple snooping agents (including processors controllers) which accessing multiple addresses that same data cache unit (DCU) cache, following sequence transactions cause system hang:
read-for-ownership cycle (a.k.a read invalidate line) issued address which Modified state both cache DCU. writes data that address back cache, that longer Modified state DCU, only cache. Invalidated state DCU. issues read same address cache, data returned Exclusive state (which incorrect). cache proceeds evict copy line Modified state. Meanwhile, modifies copy line Exclusive state, which then becomes Modified.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
external snoop from another processor controller occurs address, receives HITM# (hit Modified) response, DCU's data goes onto processor bus. this stage, internal state processor incorrect, incomplete cache eviction. attempts access line again, another external snoop occurs line, processor will hang, never completing operation.
IMPLICATION: Heavy traffic system with devices capable causing external snoops cause system hang. However, Intel observed conditions necessary cause traffic described above only 4-way systems, under heavy traffic stress-testing conditions where same-set data being rapidly transferred between main memory, cache, DCU. WORKAROUND: None identified. STATUS: steppings affected Summary Table Changes beginning this section.
Branch Traps Function BTMs Also Enabled
PROBLEM: branch traps branch trace messages (BTMs) enabled alone, both function expected. However, both enabled, only BTMs will function, branch traps will ignored. IMPLICATION: These debugging features cannot used together. WORKAROUND: branch trap functionality desired, BTMs must disabled. STATUS: steppings affected Summary Table Changes beginning this section.
Cache Line Exist Different Ways System
PROBLEM: heavy traffic system, possible cache line read into different "ways" cache, invalid line become spuriously validated. conditions necessary this behavior occur follows:
read-for-ownership (a.k.a. read invalidate line), normal read, second read-for-ownership must occur, that order, with other intervening transactions. These three transactions must pipelined together. They must accessing same cache. cache line which process being changed Shared state must snooped external agent (such another processor controller).
IMPLICATION: these conditions occur, unexpected behavior will result. most likely failure mechanism this erratum processor hang, possible that data corruption result. Intel observed this erratum only focus-testing environment with more processors system. Intel currently identified software which causes this behavior. WORKAROUND: Intel been unable reproduce this erratum with depth configured
BIOS. This recommended configuration affected steppings processor; production systems with this configuration known affected this erratum.
STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
HALT, SHUTDOWN, STPCLK Special Cycles Issued
PROBLEM: HALT, SHUTDOWN, STPCLK special cycles will issued Pentium
processor.
IMPLICATION: Systems which rely these special cycles will function correctly. Software that purposely
creates processor SHUTDOWN condition order create processor restart will SHUTDOWN without restart occurring.
WORKAROUND: known workaround exists systems which stepping Pentium
processor stepping Intel 450KX PCIset. Other systems contain workaround this erratum BIOS code.
STATUS: steppings affected Summary Table Changes beginning this section.
Cache Incorrectly Report BIST Failure
PROBLEM: BIST (Built-In Self Test) requested reset keeping INIT# asserted past rising edge RESET# (i.e., performing normal BIST request), possible that cache BIST will run. this occurs, BIST result reported register upon completion BIST will contain signature cache failure (bits and/or nonzero). IMPLICATION: BIST failure result from cache valid. This invalid failure result becomes more probable RESET# pulse lengthened. This erratum been observed Intel devices with both 256-Kbyte 512-Kbyte caches. This fixed steppings 256-Kbyte 512-Kbyte caches. WORKAROUND: Ignore result BIST masking bits register before
checking BIST result, BIST.
STATUS: steppings affected Summary Table Changes beginning this section.
LOCK Prefix Does Generate Trap With Some Instructions
PROBLEM: LOCK prefix used with CPUID near call indirect (FF/2 type CALL) instruction, exception should generated protected virtual 8086 mode, interrupt should generated real address mode. affected steppings Pentium processor, these exceptions occur; processor instead decode execute instruction LOCK prefix present. IMPLICATION: Illegal LOCK prefix always detected. cases where detected, will ignored (the LOCK# signal will asserted that instruction). WORKAROUND: LOCK prefix with CALL CPUID instructions. STATUS: steppings affected Summary Table Changes beginning this section.
FRCERR Incorrectly Asserted Explicit Writeback Cycles
PROBLEM: system configured (Functional Redundancy Checking) mode, explicit writeback operation (due capacity miss cache, example) cause FRCERR asserted, even though mismatch between master checker processors have occurred. IMPLICATION: affected steppings Pentium processor, mode reliable when used conjunction with explicit writebacks.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
WORKAROUND: system configured with memory write-through mode, explicit writebacks will occur (because writes through processor bus), thus avoiding this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
Inexact-Result Exception Flag
PROBLEM: When result floating-point operation exactly representable destination format (1/3 binary form, example), inexact-result (precision) exception occurs. When this occurs, (bit status word) normally processor. Under certain rare conditions, this when this rounding occurs. However, other actions taken processor (invoking software exception handler exception unmasked) affected. This erratum only occur floating-point operation which causes precision exception immediately followed following instructions: m32real m64real FSTP m32real FSTP m64real FSTP m80real FIST m16int FIST m32int FISTP m16int FISTP m32int FISTP m64int
Note that even this combination instructions encountered, there also dependency internal pipelining execution state both instructions processor.
IMPLICATION: Inexact-result exceptions commonly masked ignored applications, happens
frequently, produces rounded result acceptable most applications. status word always upon receiving inexact-result exception. Thus, these exceptions unmasked, floating-point error exception handler recognize that precision exception occurred. Note that this "sticky" bit, i.e., once inexact-result condition, remains until cleared software.
WORKAROUND: This condition avoided inserting instructions between floating-point
instructions.
STATUS: steppings affected Summary Table Changes beginning this section.
Snoop During Segment Load Hang System
PROBLEM: During execution instruction, processor must reload state which saved into (System Management Mode) dump space upon recognition SMI# event. while loading from address memory which contains saved contents segment registers (CS, GS), snoop occurs from external agent which matches address overlayed system memory region), then resulting postponement retry segment register load result processor hanging infinite loop microcode. IMPLICATION: processor will hang when exiting from SMM, address match occurs between external snoop memory address segment register being loaded from dump space. Note that there very small window opportunity this erratum occur.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
WORKAROUND: overlay system memory with dump space. overlaying memory this
desired, ensure that system does snoop system memory overlaid with SMRAM making this region uncacheable, example).
STATUS: steppings affected Summary Table Changes beginning this section.
Mbyte-Aligned Base Address Causes SHUTDOWN
PROBLEM: When servicing SMI# event, (code segment) selector formed shifting value (System Management Mode) base address field right bits using order bits selector. base address aligned megabyte boundary (i.e., with base address etc., Mbytes), these bits will resulting segment selector value 0000h, also known null selector. This results null this segment being segment register. selector containing null value subsequently used data selector while SMM, fault will result; since interrupt table exists default SMM, processor will then enter SHUTDOWN. Note that base address below Mbyte, this erratum will occur. IMPLICATION: base addresses which fall megabyte boundary (i.e., SMM_BASE 1048576
will result system failure upon data selector SMM. base addresses below Mbyte (most systems which support configured this way) will affected this erratum.
WORKAROUND: memory space must placed above Mbyte, Mbyte-aligned
base address when setting BIOS.
STATUS: steppings affected Summary Table Changes beginning this section.
Machine Check Exception with Coexisting Large Small Pages
PROBLEM: Pentium processor separate translation lookaside buffers (TLBs) caching 4-Kbyte 4-Mbyte page translations. When single linear address used access data, processor contains entry both 4-Kbyte 4-Mbyte TLBs that address, unrecoverable Machine Check Exception (MCE) generated MCEs enabled system. IMPLICATION: unrecoverable generated operating system environment which configures large pages after MCEs have been enabled (including cases where MCEs enabled, INIT# sequence executed, then large pages configured). WORKAROUND: This erratum avoided ensuring that after large page directory entries (PDEs)
created (e.g., operating system), entries flushed before executing code which enables MCEs. Also, code which dynamically creates large pages should ensure that large page PDEs mapped small (4-Kbyte) PDEs. BIOS which cause INIT# sequence must clear MC1_CTLMC4_CTL registers part initialization sequence.
STATUS: steppings affected Summary Table Changes beginning this section.
WBINVD Some Modified Addresses Hangs System
PROBLEM: system with cacheable memory address range 70000000h-7003FFFFh Modified address that range, WBINVD performed write back invalidate caches, processor hang. IMPLICATION: This region corresponds 256-Kbyte range beginning 1792 Mbytes. Systems with cacheable memory this region (i.e., with more than 1.792 Gbytes DRAM) hang while running software which performs WBINVD instructions. WBINVD privileged instruction only executable operating systems
PENTIUM® PROCESSOR SPECIFICATION UPDATE
driver software; some operating systems known execute this instruction, though infrequently (usually during bootup).
WORKAROUND: Using variable MTRRs, write-through (WT) memory region address
range 70000000h-7003FFFFh systems which support over 1.792 Gbytes DRAM (this should expanded 4-Mbyte region instead Kbytes, however, Erratum 29). This will prevent addresses this range from being Modified state, thus preventing this erratum. However, this also have performance impact operating system; BIOS should modify E820h function mark this range "reserved" memory descriptor list provided through this function. Operating systems which this function call experience some performance degradation when accessing memory this region (since type). Also note that memory type used override portion memory region, similar memory type currently documented; this will changed specification (see Specification Changes).
STATUS: steppings affected Summary Table Changes beginning this section.
Store Reordered Around Transaction
PROBLEM: Store operations uncacheable (UC) memory intended system serializing events processor bus, with respect transactions write-combining (WC) memory. This means that transactions before subsequent store should complete before store allowed execute, subsequent transactions should begin after store completes. However, last cache line chunk) data transaction retried processor bus, subsequent store reordered that store completes before retried transaction. also possible transactions reordered processor core opposed external bus) issued reverse order. Note that loads operate designed, will never reordered this way. IMPLICATION: device which uses memory dependent completion transactions before store executed, perhaps some designed-in effect store (such activating graphics accelerator sequence), this erratum occur data from last portion transaction would present, possibly causing failure designed-in effect. Note that linear frame buffer video implementation, effect this erratum would that some number pixels would updated screen order microsecond later than expected. WORKAROUND: system serialization store memory required, workarounds
used: Insert load before store instruction. transaction will reordered behind transactions this case. Insert XCHG reg, stack instruction before store instruction. This will also guarantee desired ordering.
STATUS: steppings affected Summary Table Changes beginning this section.
Spurious Error Reported With MCEs Enabled
PROBLEM: Pentium processor signal unrecoverable Machine Check Exception (MCE) consistency checking mechanism event that Instruction Fetch Unit (IFU) detects difference consistency absence code streaming buffers, victim cache instruction cache, i.e., loss inclusion. loss inclusion occur normal code execution. This condition requires processor detect internal restarting memory load operation coincident with internal signaling branch misprediction. with MCEs enabled, these internal events occur speculative execution path mispredicted code encountered multiple code cache hits same that from which original load executed, then signaled. With MCEs enabled, possible loss inclusion
PENTIUM® PROCESSOR SPECIFICATION UPDATE
detected signaled prematurely, such unrecoverable operating system shutdown resulting from this errata, essentially spurious.
IMPLICATION: conditions above MCEs enabled operating system, spurious
occur, causing operating system shutdown. MCEs disabled normal code execution with interruption will result. However MCEs disabled self- cross-modifying code being executed, then unpredictable application behavior possible, although current validation shown execution continue normally.
WORKAROUND: Enabling MCEs, Intel recommends, will provide system user with higher confidence level correct processor code execution, will allow possibility spurious above circumstances. Intel identified workaround prevent spurious MCEs, when they enabled. STATUS: steppings affected Summary Table Changes beginning this section.
Extended TRDY# Cause Hang With DBSY# Asserted
PROBLEM: Pentium processor asserts DBSY# during transfer data implicit writeback write request which receives HITM# (hit Modified) snoop response. responding agent asserts TRDY# more than clock beyond DBSY# deassertion (typically, TRDY# deasserted clock after DBSY# assertion observed) allow previously requested write data transfer, Pentium processor reassert DBSY# implicit writeback prematurely. Intel only observed this erratum focused testing environment, when memory aliasing used (i.e., system with processors mapping memory different types, when memory type changed dynamically programming Memory Type Range Registers (MTRRs) changing page-table entry's fly). IMPLICATION: This protocol violation result system hang systems with agents which assert TRDY# past typical window. WORKAROUND: Maintain consistent MTRR memory model between processors system, reprogram MTRRs change bits main memory fly. STATUS: steppings affected Summary Table Changes beginning this section.
Call Gates Cause Incorrect Handling Stack Size Attribute
PROBLEM: Transitioning processor privilege levels call gate descriptor result value with 16-bits cleared parameter copy portion call gate, CALL opcode restarted. parameters copied stack, this erratum will occur.
opcode restarted processor-initiated update page's Access bit, occurrence particular processor-initiated memory ordering event during opcode's execution. processor-initiated update Access occurs when call gate requires Task State Segment (TSS) whose page marked having been accessed, when page containing more privileged stack segment accessed call gate. processor-initiated memory ordering event occurs whenever address compare address signals A#[19:5]) previous store from different processor agent external matches address page containing kernel stack segment) being loaded call gate. Using incorrect value derived from during call gate results unexpected page fault (Trap 0Eh) during parameter copy, unless miscalculated linear address caller's stack resolves page that also present, accessible caller. page present accessible, possible that code could executed using stack containing incorrect data. this point, system behavior dependent upon what called routine does given incorrect stack data.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
IMPLICATION: application operating system) terminated with Page Fault Exception (Trap
0Eh) during call gate, miscalculated linear address caller's stack. event that miscalculated linear address caller's stack resolves page that also present accessible caller, system behavior becomes dependent upon called routine's behavior when given stack pointer.
WORKAROUND: software using call gates, there three possible complete workarounds this erratum,
which used alone combination: pass parameters using parameter passing feature call gate, 32-bit stack routine kernel being called, either never clear Access page containing ensure that Access when call gate performed, Align page containing TSS) linear address (i.e., etc.), either never clear Access bits page containing ensure that Access when call gate performed. systems using silicon, BIOS code contain workaround this erratum which precludes need above three workarounds.
STATUS: steppings affected Summary Table Changes beginning this section.
LBER Corrupted After Some Events
PROBLEM: last branch record (LBR) last branch before exception record (LBER) used determine source destination information previous branches exceptions. contains source destination addresses last branch exception, LBER contains similar information last branch taken before last exception. This information typically used determine location branch which leads execution code which causes exception. However, after catastrophic condition which results assertion BINIT# reinitialization buses, value LBER corrupted. Also, after either CALL which results fault software interrupt, LBER will updated same value, when LBER should have been updated. IMPLICATION: LBER registers used only debugging purposes. When this erratum occurs, LBER will contain reliable address information. value LBER should used with caution when debugging branching code; values LBER same, then LBER value incorrect. Also, value LBER should relied upon after BINIT# event. WORKAROUND: None identified. STATUS: steppings affected Summary Table Changes beginning this section.
During String Instruction Clears
PROBLEM: assertion SMI# occurs during string instruction, system will enter System
Management Mode (SMM). When this happens, cleared information this register lost. This register contains information system settings, such Page Global Enable (PGE) Performance Counter Enable (PCE) bits.
IMPLICATION: settings that stored register lost when system enters during
string instruction. This cause operating system application operate incorrectly halt unexpectedly.
WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
BTMs Corrupted During Simultaneous Cache Line Replacement
PROBLEM: When Branch Trace Messages (BTMs) enabled such message generated, Bmay corrupted when issued cache, line data brought into data cache simultaneously. Though line being stored cache stored correctly, corruption occurs data, information Bmay incorrect internal collision data line BTM. IMPLICATION: Although BTM's entirely reliable erratum, conditions this erratum occur have only been exhibited during focused simulation testing. Intel observed this erratum system level validation environment. WORKAROUND: None identified this time. STATUS: steppings affected Summary Table Changes beginning this section.
Spurious Machine Check Exception Data Parity Error
PROBLEM: Pentium processor signal unrecoverable Machine Check Exception (MCE) event that Instruction Fetch Unit (IFU) detects mismatch when verifying instruction parity. execution code which modifies current instruction sequence that already fetched into processor cause instruction given address appear differently depending when fetched time relative being modified. Thus, speculatively prefetched instruction have been modified such that differs from copy same instruction resident instruction cache. This discrepancy copy located speculative prefetch portion, different copy instruction cache) sensed IFU. When detects that instruction stream been modified, flushes pipeline attempts restart instruction stream. interim, recognizes disparate instructions described above, signals data parity error. data parity error signaled before instruction stream chance restart. This will cause operating system that enabled shutdown. incorrect code executed processor this situation (even disabled). Note that this erratum occurs under specific address dependencies timing events. IMPLICATION: Executing such sequence modifying code without proper synchronization always result predictable program behavior. processor's signaling data parity error then result unexpected system halt above conditions MCEs enabled. WORKAROUND: stepping processor, disabling Instruction Streaming Buffers setting
Model Specific Register (MSR) address "1", workaround this erratum. effect system performance setting this been found smaller than run-to-run measurement variations conventional benchmarks such SPECint* SYSmark* effect vary depending workload. prior steppings, possible BIOS code contain workaround this erratum.
STATUS: steppings affected Summary Table Changes beginning this section.
Loss Inclusion Cause Machine Check Exception
PROBLEM: Pentium processor signal unrecoverable Machine Check Exception (MCE) consistency checking mechanism event that Instruction Fetch Unit (IFU) detects differences consistency code instruction streaming buffers against code resident instruction cache, i.e., loss inclusion. When application code makes operating system call, processor transitions execution privilege levels. code call already resident level cache, then processor prefetch code while identifying cache line(s) eventual eviction make space code. Upon return from call, processor continues execution application code user level. processor, deep speculation branch prediction, attempt execute instructions from previously prefetched kernel
PENTIUM® PROCESSOR SPECIFICATION UPDATE
code starting attempting replace victim line with kernel code buffer internal IFU. detects that current application insufficiently privileged execute kernel code suppresses eviction previously selected victim line. Despite having detected this condition, does replace this victim line with kernel line. processor attempts restart execution current application code refetching original victim line longer finds instruction cache. detects this loss inclusion, signals this generating MCE. MCEs enabled, this event cause operating system shutdown. Note that this erratum occurs under specific address dependencies timing events.
IMPLICATION: occurrence conditions above lead signal loss inclusion generating MCE. MCEs enabled system, then operating system shutdown upon noticing resulting system failure. MCEs disabled, then unpredictable application behavior theoretically possible, although current validation shown execution continue normally. WORKAROUND: stepping processor, disabling Instruction Streaming Buffers setting Model Specific Register (MSR) address "1", workaround this erratum. effect system performance setting this been found smaller than run-to-run measurement variations conventional benchmarks such SPECint SYSmark effect vary depending workload. prior steppings, possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
Controller Automatically Reset Power-Up
PROBLEM: Pentium® Family Developer's Manual, Volume Specifications, Chapter "Pentium®
Processor Test Access Port," Section 10.2, page 10-3, under Test-Logic-Reset bullet, connection with controller reset, stated that: "The controller also enters this state immediately when TRST# pulled active, automatically upon power-up Pentium processor." stepping processor does automatically reset upon power-up.
IMPLICATION: controller also reset additional means, which documented workaround section below. controller reset these means, then possible stepping Pentium processor power-up indeterminate state preventing normal functionality. WORKAROUND: controller logic reset assertion TRST# (e.g., pull-down) assertion clocks (TCK). Systems which pull TRST# pull-down resistor affected this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
Erroneous Signaling User Mode Protection Violation
PROBLEM: Pentium processor attempts access page physical memory marked present (Present clear), page fault exception (#PF) generated. Before proceeding, there narrow internal timing window where processor verifies that other higher priority fault conditions present. During this time, possible another agent allocate page directory page table entry (PDE/PTE) corresponding same linear address original access, writing values into PDE/PTE with Access (A-bit) Dirty (D-bit) cleared. When original processor completes checking other fault conditions, re-examines recently modified PDE/PTE, finds that been cleared. Internal hardware correctly signals this scenario condition which processor should respond setting bit, erroneously reports generic paging protection violation. Instead attempting appropriate bit, this event reported Int14 with exception code 0x05, i.e., user mode protection violation. IMPLICATION: occurrence this scenario will result erroneous signaling user mode protection violation instead page fault result application termination depending operating system
PENTIUM® PROCESSOR SPECIFICATION UPDATE
behavior response user mode protection violation. Intel only observed this erratum date laboratory testing multi-processor systems.
WORKAROUND: Operating systems which allocate PTEs PDEs should Access (A-bit) Dirty (D-bit) work around this erratum. Alternately, operating system's Int14 handler determine protection violation condition truly exists, none found, return without further action. STATUS: steppings affected Summary Table Changes beginning this section.
Invalid Operation Signaled FIST Instruction Some Range Operands
PROBLEM: certain, large, negative, floating-point operands, only three four possible processor
rounding modes, instructions FIST[P] m16int FIST[P] m32int detect that operand large that will into target data size. consequence, expected Invalid Operation exception response this situation correctly provided, Invalid Operation flag Floating Point status word specified Intel Architecture Programmers Reference Manual, Volume Under failing conditions, noted below, precision exception (#PE) flag will also incorrectly set. erratum occurs only when following conditions met: FIST[P] instruction either 32-bit operation; 64-bit operations unaffected. Either nearest zero' `up' rounding modes being used. round `down' mode unaffected this erratum. sign floating-point operand negative. floating-point operand being converted significantly more negative than described integer size being targeted. ACTUAL EXPECTED RESPONSE
Actual Response
When required conditions encountered, processor provides following response: Return MAXNEG value (8000h FIST16 80000000h FIST32) memory. (Invalid Operation) Floating Point status word flag invalid operand. (precision error) Floating Point status word set. exception handler invoked. case FISTP instruction Operand will have been popped from floating point stack.
Expected Response
expected processor response when invalid operation exception masked Return MAXNEG value (8000h FIST16 80000000h FIST32) memory. (Invalid Operation) Floating Point status word flag overflow. (precision error) Floating Point status word set.
expected processor response when invalid operation exception unmasked return result memory. Keep original operand intact stack. (Invalid Operation) Floating Point status word flag overflow.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
(precision error) Floating Point status word set. Vector user numeric exception handler.
IMPLICATION: Erroneous operation results when operand large that will into target data
size. operands affected this erratum significantly outside factor range that correctly, converted integer value. figure below corresponding table identifies normal range integer numbers (between starting point operands affected this erratum. Discrete failing operands will present range between point maximum negative number that 1023 represented processor double precision format). Note below gives qualitative description nature discrete failing values. Software that does rely Invalid Operation exception flag being signaled either exception software polling impacted this erratum.
1023
1023
Range potentially affected numbers. number this range affected
Range valid Integer
16-bit Operation
-32,768.0
+32,767.0 +2,147,483,647.0
-98304.0 -6,442,450,944.0
32-bit Operation
-2,147,483,648.0
WORKAROUND: software workarounds will avoid occurrence this erratum:
Range checking performed prior execution FIST[P] instruction will prevent overflow condition from occurring, already implemented standard coding style. Software presence MAXNEG result integer indicate that range conversion have occurred. Note possible alternative FIST64 instruction store converted operand memory access lower bits required integer. Even though this mechanism will signal attempted range conversion with target, currently many compilers today. Note values affected this erratum those which contain exponent value within affected range, specific pattern specific offset within mantissa, least nonzero right above pattern. offset within mantissa function floating point exponent value. specific pattern 0x8000 FIST16 0x80000000 FIST32. This means that given exponent within range, mantissa value every possible mantissa values exhibits erratum FIST16, mantissa value every possible mantissa values exhibits erratum FIST32.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Examples affected values FIST16, binary notation (not exhaustive list) means pattern, means nonzero pattern)
sign exponent 100000000010100 100000000010101 100000000010110 mantissa
Examples affected values FIST32, binary notation (not exhaustive list) means pattern, means nonzero pattern)
sign exponent 100000000100011 100000000100100 100000000100101 mantissa
STATUS: steppings affected Summary Table Changes beginning this section.
EFLAGS Incorrect After Multiprocessor Shootdown
PROBLEM: When Pentium processor executes read-modify-write arithmetic instruction, with memory destination, possible page fault occur during execution store memory operand after read operation completed before write operation completes. this case EFLAGS value pushed onto stack page fault handler reflective status EFLAGS register after instruction would have completed execution rather than that before executed under certain circumstances. This class instruction will initially perform load operation that side effect ensuring that final store portion instruction will successfully complete. load ensures this verifying that page table information page containing data DTLB. This page entry could evicted from DTLB speculative loads from other instructions that same DTLB, before store executed. very small window time between change state page table shootdown becoming effective (i.e., processor being told remove translation from TLB), page table entry page permissions tightened (e.g., from Present Present, from Read/Write Read Only, etc.) operating system main memory another processor (with corresponding synchronization subsequent flush) store will generate DTLB miss call OS's page fault handler. EFLAGS register have already been updated arithmetic portion instruction before entry page fault handler. under these circumstances fault handler elects restart instruction, then re-execution generate incorrect result. Instructions affected this erratum memory destination forms ADC, SBB, (instructions that flag, carry, input instruction). should noted that locked version these instructions impacted this erratum. IMPLICATION: This scenario only occur multiprocessor system running under operating system that
implements `lazy' shootdown. Lazy shootdown occurs when processor makes changes page tables, memory, then signals other processors remove page entry from their without multiprocessor synchronization being performed. date, Intel observed this erratum laboratory testing commercially available software applications. multiprocessor system arithmetic flags EFLAGS register memory stack image, contain incorrect data read-modify-write arithmetic instruction encounters page fault. Page Fault handler software that uses resulting EFLAGS incorrect information. original instruction restarted
PENTIUM® PROCESSOR SPECIFICATION UPDATE
page fault handler, instruction produce incorrect results based prior modifications EFLAGS register.
WORKAROUND: Software locked form ADC, SBB, instructions avoid this erratum. Operating systems should ensure that processor currently accessing page that scheduled have page permissions tightened, e.g., moved from Present Present have page fault handler that handle incorrect state. Intel working with Multiprocessor Operating System vendors ensure that level workaround implemented required. STATUS: steppings affected Summary Table Changes beginning this section.
Possible System Hang When Paging Disabled Re-enabled from Uncached Memory
PROBLEM: paging disabled then later re-enabled while executing code from
page marked uncachable Page Table Entry (PCD=1) located memory mapped Write Back Write Through processor MTRRs, processor could internally enter state resulting system hang.
IMPLICATION: Operating systems that enable disable paging with above described memory configurations could hang. This erratum been seen commercially available operating systems applications. WORKAROUND: possible BIOS code contain workaround this erratum. STATUS: steppings affected Summary Table Changes beginning this section.
FLUSH# Assertion Disables Machine Check Exception Reporting
PROBLEM: Upon FLUSH# assertion, Machine Check Exception generation disabled. Once
FLUSH# asserted, processor disables MCA, clearing associated MCi_CTL control register "0"s. This operation invisible software being executed.
IMPLICATION: Errors that should reported reported from time that FLUSH#
signal asserted until time that MCi_CTL register written back "1"s. other errors will continue logged normal.
WORKAROUND: Platform specific code (e.g., BIOS system management software) potential
driving device assert FLUSH# pin. platform specific code asserts FLUSH# pin, this code should enhanced detect that Exceptions globally enabled (via register CR4.MCE). code should then write "0"s MCi_CTL registers clear spurious entries then write "1"s MCi_CTL registers order re-enable exception reporting. Hardware devices systems that require error reporting which could assert FLUSH# should assert FLUSH#.
STATUS: steppings affected Summary Table Changes beginning this section
Delayed Line Invalidation Issue During 2-Way Data Ownership Transfer
PROBLEM: 2-way systems, each processor attempt modify different portion same cache line, referenced line discussion below. When this erratum occurs (with following example given 2-way system with processors noted `P0' `P1'), each processor contains shared copy line
PENTIUM® PROCESSOR SPECIFICATION UPDATE
both their caches. Each processor must issue invalidation cycle before that processor definitively source results internal write portion line other processors. There exists narrow timing window when, wins external invalidation race gains ownership rights line sequence invalidation traffic, have completed pending invalidation own, currently valid shared copy line During this window, possible internal opportunistic write portion line (while awaiting ownership rights) occur with original shared copy line still resident P1's cache. Such internal modification permissible subject delaying broadcast such changes until line ownership actually been gained. However, processor must ensure that internal re-read line returns with data order actually written; this case, this should data written case this erratum, internal re-read uses data which written
IMPLICATION: Multiprocessor threaded application synchronization that implemented operating systemprovided synchronization constructs affected this erratum. Applications which rely upon usage locked semaphores rather than memory ordering also unaffected. Uniprocessor systems affected this erratum. Intel identified, date, commercially available application operating system software which affected this erratum. erratum does occur, delayed line invalidation that occurs naturally fact that processor will necessarily invalidation race allows narrow timing window exist where processor re-read line that just wrote internally, return with stale data that present from previous shared state rather than data written more recently another processor.
WORKAROUND: Deterministic barriers beyond which program variables will modified achieved
usage locked semaphore operations, this scheme been shown effectively work around this erratum.
STATUS: steppings affected Summary Table Changes beginning this section.
Potential Early Deassertion LOCK# During Split-Lock Cycles
PROBLEM: During split-lock cycle there four transactions; ADS# partial read), ADS# partial read), ADS# partial write), ADS# partial write). this erratum, LOCK# deassert clock after ADS# split-lock cycle instead after been sampled. following sequence events required this erratum occur:
lock cycle occurs (split nonsplit). Five more transactions (assertion ADS#) occur. split-lock cycle occurs BNR# toggles after ADS# (partial write) split-lock cycle. This turn delays assertion ADS# split-lock cycle. BNR# toggling this time could most likely happen when depth When these events occur, LOCK# will deasserted next clock after ADS# split-lock cycle.
IMPLICATION: This affect chipset logic which monitors behavior LOCK# deassertion. WORKAROUND: None identified. STATUS: steppings affected, Summary Table Changes beginning this section.
A20M# Inverted After Returning From Reset
PROBLEM: This erratum seen when software causes following events occur:
PENTIUM® PROCESSOR SPECIFICATION UPDATE
assertion A20M# real address mode. After entering 1-Mbyte address wrap-around mode caused assertion A20M#, there assertion SMI# intended cause Reset remove power processor. Once handler, software saves state save area nonvolatile memory from which restored some point future. Then software asserts RESET# removes power processor. After exiting Reset completion power-on, software asserts SMI# again. Once handler, then retrieves state save which saved event above copies into current state save map. Software then asserts A20M# executes instruction. After exiting handler, polarity A20M# inverted.
IMPLICATION: this erratum occurs, A20M# will behave with polarity opposite from what expected (i.e.,
1-Mbyte address wrap-around mode enabled when A20M# deasserted, does occur when A20M# asserted).
WORKAROUND: Software should save A20M# signal state nonvolatile memory before assertion
RESET# power down condition. After coming Reset power SMI# should asserted again. During restoration state save described event above, entire should restored, except byte offset 7F18h. This should retain value assigned when state save created event handler should then restore original value A20M# signal.
STATUS: steppings affected Summary Table Changes beginning this section.
EFLAGS Discrepancy Page Fault After Multiprocessor Shootdown
PROBLEM: This erratum occur when Pentium processor executes following read-modifywrite arithmetic instructions page fault occurs during store memory operand: ADD, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, ROL/ROR, SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, XADD. this case, EFLAGS value pushed onto stack page fault handler reflect status register after instruction would have completed execution rather than before following conditions required store generate page fault call operating system page fault handler:
store address entry must evicted from DTLB speculative loads from other instructions that same DTLB before store completed. DTLB eviction requires least three load operations that have linear address bits 15:12 equal each other address bits 31:16 different from each other close physical proximity arithmetic operation. page table entry store address must have permissions tightened during very small window time between DTLB eviction execution store. Examples page permission tightening include from Present Present from Read/Write Read Only, etc. Another processor, without corresponding synchronization flush, must cause permission change.
IMPLICATION: This scenario only occur multiprocessor platform running operating system that performs "lazy" shootdowns. memory image EFLAGS register page fault handler's stack prematurely contains final arithmetic flag values although instruction completed. Intel identified operating systems that inspect arithmetic portion EFLAGS register during page fault observed this erratum laboratory testing software applications. WORKAROUND: workaround needed upon normal restart instruction, since this erratum
transparent faulting code results correct instruction behavior. Operating systems ensure that processor currently accessing page that scheduled have page permissions tightened have page fault handler that ignores incorrect state.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
STATUS: steppings affected Summary Table Changes beginning this section.
Near CALL Creates Unexpected Address
PROBLEM: documented, CALL instruction saves procedure linking information procedure stack jumps called procedure specified with destination (target) operand. target operand specifies address first instruction called procedure. This operand immediate value, general purpose register, memory location. When accessing absolute address indirectly using stack pointer (ESP) base register, base value used value register before instruction executes. However, when accessing absolute address directly using base register, base value used value after return value pushed stack, value register before instruction executed. IMPLICATION: this erratum, processor transfer control unintended address. Results unpredictable, depending particular application, range from effect unexpected termination application exception. Intel observed this erratum only focused testing environment. Intel observed commercially available operating system, application, compiler that makes generates this instruction. WORKAROUND: other seven general purpose registers unavailable use, necessary
CALL register, first push onto stack, then perform indirect call using (e.g., CALL [ESP]). saved version should popped stack after call returns.
STATUS: steppings affected Summary Table Changes beginning this section.
Memory Type Undefined Nonmemory Operations
PROBLEM: Memory Type nonmemory operations such Special cycles driven uncacheable (UC) memory type. Although Memory Type Attribute nonmemory operations usually manifests itself this feature designed into implementation, memory type during nonmemory cycles undefined. IMPLICATION: agents could decode non-UC memory type nonmemory operations. WORKAROUND: agents must consider transaction type determine validity Memory Type
Attribute.
STATUS: steppings affected, Summary Table Changes beginning this section.
Protocol Conflict With Optimized Chipsets
PROBLEM: "dead" turnaround cycle with agent driving address, request command, request parity
signals must occur between processor driving these signals chipset driving them after asserting BPRI#. Pentium processor does follow this protocol. Thus, system uses chipset third party agent which optimizes arbitration latency (reducing clocks when observes active (low) ADS# signal inactive (high) LOCK# signal same clock that BPRI# asserted (driven low)), Pentium processor cause contention during unlocked exchange.
IMPLICATION: This violation reduced arbitration latency exchange protocol cause system-level
setup timing violation address, request command, request parity signals system bus. This result system hang assertion AERR# signal, causing spurious corrective action shutdown system, system hardware software dictate. possibility failure contention caused this erratum increased processor's internal active pull-up these signals clock after signals longer being driven processor.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
WORKAROUND: chipset third party agents used with Pentium processor optimize their arbitration latency described above, action required. agents that have implemented this optimization used, decreasing system frequency reduce possibility failure caused contention described above. STATUS: steppings affected Summary Table Changes beginning this section.
Data Operand Pointer Zero After Power Reset
PROBLEM: Data Operand Pointer, specified, should reset zero upon power Reset
processor. this erratum, Data Operand Pointer nonzero after power Reset.
IMPLICATION: Software which uses Data Operand Pointer count value being zero after power Reset without first executing FINIT/FNINIT instruction will incorrect value, resulting incorrect behavior software. WORKAROUND: Software should follow recommendation Section Intel Architecture Software
Developer's Manual, Volume System Programming Guide (Order Number 243192). This recommendation states that will used, software-initialization code should execute FINIT/FNINIT instruction following hardware reset. This will correctly clear Data Operand Pointer zero.
STATUS: steppings affected Summary Table Changes beginning this section.
Premature Execution Load Operation Prior Exception Handler Invocation
PROBLEM: This erratum occur with following situations:
instruction that performs memory load causes code segment limit violation waiting floating-point instruction With above circumstances, possible that load portion instruction will have prematurely executed before exception handler entered.
IMPLICATION: normal code execution where target load operation write back memory there
impact from load being prematurely executed, from restart subsequent re-execution that instruction exception handler. target load uncached memory that system side effect, restarting instruction cause unexpected system behavior.
WORKAROUND: Code that loads from memory that side effects effectively workaround this behavior
using simple integer based load instructions when accessing side effect memory ensuring that code written such that code segment limit violation cannot occur part reading side effect memory.
STATUS: steppings affected Summary Table Changes beginning this section.
Read Portion Instruction Execute Twice
PROBLEM: When Pentium processor executes read-modify-write arithmetic instruction, with memory destination, possible page fault occur during execution store memory operand after read operation completed before write operation completes. memory targeted instruction (uncached), memory will observe occurrence initial load before page fault handler again instruction restarted.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
IMPLICATION: memory targeted instruction side effects, then memory location will simply read twice with additional implications. however, load targets memory region that side effects, multiple occurrences initial load lead unpredictable system behavior. WORKAROUND: IHV's ISV's write device drivers custom hardware that have side effect style
design should simple loads simple stores transfer data from device.
STATUS: steppings affected Summary Table Changes beginning this section.
Intervening Writeback Occur During Locked Transaction
PROBLEM: During transaction which LOCK# signal asserted (i.e., locked transaction), there potential explicit writeback caused previous transaction complete while locked. explicit writeback will only issued processor which locked bus, lock signal will deasserted until locked transaction completes, atomicity lock compromised this erratum. Note that explicit writeback expected cycle, memory ordering violations will occur. This erratum however, violation lock protocol. IMPLICATION: chipset third-party agent (TPA) which tracks transactions such that locked
transactions only consist read-write read-read-write-write locked sequence, with transactions intervening, lose synchronization state intervening explicit writeback. Systems using chipsets TPAs which accept intervening transaction will affected.
WORKAROUND: tracking logic devices system should allow occurrence intervening transaction during locked transaction. STATUS: steppings affected Summary Table Changes beginning this section.
MC2_STATUS Model-Specific Error Code Machine Check Architecture Error Code Reversed
PROBLEM: Intel Architecture Software Developer's Manual, Volume System Programming Guide,
documents that MCi_STATUS MSR, bits 15:0 contain (machine-check architecture) error code field bits 31:16 contain model-specific error code field. However, MC2_STATUS MSR, these bits have been reversed. MC2_STATUS MSR, bits 15:0 contain model-specific error code field bits 31:16 contain error code field.
IMPLICATION: machine check error decoded incorrectly this erratum MC2_STATUS
taken into account.
WORKAROUND: When decoding MC2_STATUS MSR, reverse error fields STATUS: steppings affected Summary Table Changes beginning this section.
With Debug Register Causes Debug Exception
PROBLEM: When mode, instruction executed debug registers, general-protection exception (#GP) should generated, documented Pentium® Family Developer's Manual, Volume System Programming Guide, Section 10.2, "Debug Registers," Intel Architecture Software Developer's Manual, Volume System Programming Guide, Section 14.2, "Debug Registers." However, case when general detect enable flag (GD) set, observed behavior that debug exception (#DB) generated instead.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
IMPLICATION: With debug-register protection enabled (i.e., set),and attempting execute
debug registers mode, debug exception will generated instead expected general-protection fault.
WORKAROUND: general, operating systems when they mode.
generally used debuggers. debug exception handler should check that exception occur mode before continuing. exception occur mode, exception directed general-protection exception handler.
STATUS: steppings affected Summary Table Changes beginning this section.
Data Breakpoint Exception Displacement Relative Near Call Corrupt
PROBLEM: data breakpoint programmed memory location where stack push near call performed, processor will update stack appropriately, skip code destination call. Hence, program execution w
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