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Pentium® Processor Specification Update
Pentium® processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata documented this Specification Update.
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have order number referenced this document, other Intel literature, obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. *Third-party brands names property their respective owners.
COPYRIGHT INTEL CORPORATION 1995, 1996, 1997, 1998
CONTENTS
CONTENTS REVISION HISTORY PREFACE
Part Specification Update Pentium Processors Pentium Processors with MMXTechnology
GENERAL INFORMATION SPECIFICATION CHANGES S-SPECS ERRATA SPECIFICATION CLARIFICATIONS DOCUMENTATION CHANGES
Part Specification Update Pentium OverDrive Processors
GENERAL INFORMATION SPECIFICATION CHANGES ERRATA SPECIFICATION CLARIFICATIONS DOCUMENTATION CHANGES
Appendix Pentium Processor Related Technical Collateral
PUBLIC DOCUMENTATION.95
PENTIUM® PROCESSOR SPECIFICATION UPDATE
REVISION HISTORY
Date Revision February 1995 Version -001 Description This document consolidates information previously contained various versions stepping information, notably stepping Pentium® processor iCOMP® index (510\60, 567\66) C-stepping Pentium processor iCOMP index (610\75, 735\90, 815\100). Added Errata 22-25 Spec Clarification Part Added Spec Change Errata 24-27, 8DP-12DP, 11AP, Spec Clarification Change Part Part Added markings MHz; added Spec Changes 2TCP, 3TCP; revised Spec Changes 1TCP; added Errata revised Errata 2TCP. Part Added Errata added Spec Clarifications added Change Part Revised Spec Changes added Spec Change revised Errata added Errata 30-33; added Spec Clarifications 9-13; added Changes Part III: Section Pentium® OverDrive® Processor June 1995 -005 Part Added Spec Change added Erratum added Spec Clarification Part Added Pentium Processor with Voltage Reduction Technology; added MHz; added Spec Changes 19-23; revised Spec Changes 12-17; added S-Specs added Errata 13DP; revised Errata 9AP; added Spec Clarifications 14-17; revised Spec Clarification Part III: Added Spec Change added Erratum added Spec Clarifications 8-10. July 1995 -006 Part Added Erratum Part Added Spec Change revised Spec Changes added Erratum added Spec Clarification Part III: Added Spec Change added Errata August 1995 -007 Part Added Errata 30-32; added Spec Clarifications Part Revised Spec Change added S-Spec added Errata 37-41; revised Erratum added Spec Clarifications 19-26. Part III: Added Errata 25-29; added Spec Clarifications
March 1995
-002
April 1995
-003
1995
-004
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Date Revision September 1995
Version -008
Description Removed Spec Changes, Spec Clarifications Changes which were incorporated into 1995 Pentium® Processor Family Developer's Manual (Order Number 241563-004). Part Added Errata added Changes Part Added Errata 12AP; added Spec Clarification added Changes 1-6. Part III: Added Erratum added Changes
October 1995
-009
Part Added Spec Changes added Errata 35-37; added Spec Clarifications 4-7; added Changes Part Added Spec Changes added Errata 44-48; revised Erratum added Spec Clarifications 14-17; revised Spec Clarification added Changes 7-9; revised Change Part III: Added Pentium OverDrive processor; added Spec Changes 4-6; added Errata 31-33; revised Erratum added Spec Clarifications added Changes
November 1995
-010
Part Added Errata 38-40; added Spec Clarifications 8-10; added Change Part Added Pentium processor with Voltage Reduction Technology; added Spec Changes 14-15; added S-Spec added Errata 49-53, 13AP 14AP; revised Erratum added Spec Clarifications 18-21; added Change Part III: Added Errata 34-36; revised Erratum added Spec Clarifications 8-9; added Change
December 1995
-011
Part Added Errata 41-44; revised Errata added Spec Clarifications revised Spec Clarification added Change Part Added Spec Change added Errata 54-58; revised Errata added Spec Clarifications revised Spec Clarifications added Change Part III: Added Errata 37-40; revised Erratum added Spec Clarifications 10-12; revised Spec Clarification added Change
January 1996
-012
Part Added Errata revised Errata added Spec Clarification added Changes Part Added Pentium Processor 150-MHz 166-MHz, added Spec Changes 17-20; added Errata 59-64, 14DP, 15AP 16AP; revised Errata 11AP; added Spec Clarifications revised Spec Clarification added Changes Part III: Added Spec Change added Errata 41-45; revised Erratum added Spec Clarification added Changes
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Date Revision February 1996
Version -013 Part Added Erratum
Description Part Added S-Specs added Errata Part III: Added Erratum
March 1996
-014
Part Revised Erratum added Spec Clarification added Change Part Added S-Spec revised Erratum added Spec Clarifications 26-29; added Change Part III: Added 120/133-, 125-, 150- 166-MHz OverDrive processors; added Spec Change revised Erratum added Errata 47-55; added Spec Clarifications 14-16; added Changes
April 1996
-016*
Part Added Erratum revised Erratum added Spec Clarifications 15-17; revised Spec Clarification added Change Part Added Spec change added S-Spec revised S-Spec added Errata revised Errata added Spec Clarifications 30-35; revised Spec Clarification added Changes Part III: Added Errata revised Errata added Spec Clarifications 17-19; revised Spec Clarification added Changes
1996
-017
Part Added Spec Clarification Part Revised Spec Changes added Errata 15DP, 16DP 18AP; revised Erratum 17AP; added Spec Clarification Part III: Revised Spec Change added Erratum revised Erratum added Spec Clarification
June 1996
-018
Part Added Spec Change added Erratum added Spec Clarification Part Added Spec Change revised Spec Change added Erratum added Spec Clarifications revised Spec Clarifications Part III: Added Spec Change added Erratum added Spec Clarifications
July 1996
-019
Part Added Erratum revised Erratum revised Spec Clarification Part Added Spec Change added Erratum revised Erratum revised Spec Clarification Part III: Added Erratum revised Erratum revised Spec Clarification
Note: Revision -015 issued revision -016.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Date Revision August 1996
Version -020
Description Part Added Erratum added Spec Clarification Part Added Erratum added Spec Clarification Part III: Added Erratum added Spec Clarification
September 1996
-021
Part Added Spec Clarification revised Spec Clarification Part Added Spec Clarification revised Spec Clarification Part III: Added Spec Clarification revised Spec Clarification
October 1996
-022
Part Revised Spec Change Part Added Spec Change revised Spec Change Part III: Added Spec Change revised Spec Change
November 1996
-023
Part Revised Spec Change Part Added Spec Change revised Spec Change Part III: Added Spec Change revised Spec Change
January 1996
-024
Part Added Spec Clarifications Part Changed Spec Changes S-Specs 9-14; added S-Specs 15-21; added Errata 72-78 19AP; revised Errata added Spec Clarifications 41-49; added Change Part III: Revised Errata added Spec Clarifications
March 1997
-025
Removed Spec Changes, S-Specs, Errata, Spec Clarifications Changes which were incorporated 1997 edition Pentium® Processor Family Developer's Manual (Order Number 241428) Intel Architecture Software Developer's Manual, Volume (Order Number 243190) Volume (Order Number 243191) Part This section been replaced with Part from January's edition. section been removed been converted into Pentium® Processor Specification Update (Order Number 243326). Added Erratum added Change Part This section been replaced with Part from January's edition. Added Erratum
April 1997
-026
Part Added Spec Change added Changes Part Added Pentium OverDrive processor with Technology Stepping oxA3; added Spec Changes added Errata 63-68; added Spec Clarifications added Change
1997
-027
Part Added Spec Clarification added Change Part None.
viii
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Date Revision June 1997
Version -028
Description Part Added Spec Changes 4-14, Added S-Spec added Change Part None. Part Added Spec Changes added Changes Part Added Change Part Added Erratum 17DP; Added Spec Clarification Part Added Spec Clarification Part Added Erratum revised Erratum Added mobile Pentium Processor with technology stepping myA0. Part Added Erratum revised Erratum Part Added Pentium OverDrive processor with technology Stepping oxB1. Part Added Spec Change Part None. Part Added Erratum Spec Change Part Added Erratum Part Added Erratum Spec Clarification Part Added Erratum Spec Clarification Part Added Spec Clarification Added Changes Part Added Changes Part Added Spec Change Added Spec Clarification Part Added Spec Clarification Part Added Spec Change added Erratum added Spec Clarification added Change Part Added Errata added Spec Clarification added Change
August 1997
-029
September 1997 October 1997
-030 -031
November 1997 December 1997 January 1998 March 1998 April 1998
-032 -033 -034 -035 -036
June 1998 September 1998
-037 -038
November 1998 January 1999
-039 -041
Part Added stepping myB2. Part None. Part Added Spec Change Part None.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
PREFACE
This document update specifications contained Pentium® Processor Family Developer's Manual, (Order Number 241428) Intel Architecture Software Developer's Manual, Volume (Order Numbers 243190 243191). intended hardware system manufacturers software developers applications, operating systems, tools. contains Specification Changes, S-Specs, Errata, Specification Clarifications Documentation Changes, divided into following parts: Part Part Specification Update Pentium® Processors Pentium Processors with MMXTechnology Specification Update Pentium® OverDrive® Processors
Nomenclature
Specification Changes modifications current published specifications. These changes will incorporated next release specifications. S-Specs exceptions published specifications apply only units assembled under that s-spec. Errata design defects errors. Errata cause Pentium processor's behavior deviate from published specifications. Hardware software designed used with given stepping must assume that errata documented that stepping present devices. Specification Clarifications describe specification greater detail further highlight specification's impact complex design situation. These clarifications will incorporated next release specifications. Documentation Changes include typos, errors, omissions from current published specifications. These changes will incorporated next release specifications.
Identification Information
Pentium processor identified following register contents: 75/90/100/120/ 133/150/166/200/ Model (described Part Pentium® Processors with MMXTechnology Model (described Part Pentium Processors with Technology Model (described Part
Family
83-MHz Model (described Part
NOTES: Family corresponds bits [11:8] register after RESET, bits [11:8] register after CPUID instruction executed, generation field Device register accessible through Boundary Scan. Model corresponds bits [7:4] register after RESET, bits [7:4] register after CPUID instruction executed, model field Device register accessible through Boundary Scan.
Part
Specification Update 75/90/100/120/133/150/166/ 200/233/266/300 Pentium® Processors Pentium Processors with MMXTechnology
PENTIUM® PROCESSOR SPECIFICATION UPDATE
GENERAL INFORMATION
Markings
B-Step Engineering Samples:
A80502XX-YYY FFFFFFFF
B-Step Production Units:
A80502-SSS SZZZZ ICOMP INDEX=YYY
B-Step Engineering Samples:
pentium
pentiumFFFFFFFF-DDDD INTEL
QZZZZ DDDD 1993 CONFIDENTIAL
A80502-75 FFFFFFFF QZZZZ `92,
B-Step Production Units:
C-Step Engineering Samples:
cB1-Step Production Units:
pentium
pentium®
A80502-75 FFFFFFFF SKZZZ
1993 CONFIDENTIAL
A80502BB-SSS FFFFFFFQ QZZZZ DDDD
A80502-XXX SZZZZ ICOMP #=YYY FFFFFFFF-DDDD INTEL
C-Step Engineering Sample Units:
C-Step Production Units:
mA1-Step Engineering Sample Units:
A80502-XX FFFFFFFQ QZZZZ
A80502-75 FFFFFFFF SKZZZ
A80502-XX FFFFFFFF QZZZZ 2.9V
PENTIUM® PROCESSOR SPECIFICATION UPDATE
mA1-Step Engineering Sample SPGA Units:
mA1-Step Production Units:
mA1-Step Production SPGA Units:
pentium
pentium
TT80502-XX FFFFFFFF SKZZZ 2.9V `92,
`92,
A80502-XX FFFFFFFQ QZZZZ 2.9V DDDD
A80502-XX FFFFFFFF SKZZZ 2.9V `92,
mcB1-Step Engineering Sample Units:
mcB1-Step Production Units:
mcB1-Step Engineering Sample SPGA Units:
intel
intel
pentium®
PPXXX QZZZZ FFFFFFFF
PPXXX KZZZ FFFFFFFF
A80502-XXX FFFFFFFF QZZZZ INTEL
mcB1-Step Production SPGA Units:
cC0-Step Engineering Sample Units:
cC0-Step Engineering Sample PPGA Units:
pentium®
pentium
A80502-XXX FFFFFFFF SZZZZ 3.3V DDDD INTEL
A80502BB-XXX FFFFFFFQ QZZZZ DDDD `92,
iXXX
pentium
PENTIUM® PROCESSOR SPECIFICATION UPDATE
cC0-Step 200-MHz Engineering Sample PPGA Units:
cC0-Step Production Units:
166-MHz cC0-Step Production Units:
pentium®
pentium
iXXX
pentium®
A80502XXX SZZZZ ICOMP #=YYY FFFFFFFF-DDDD INTEL
A80502XXX SZZZZ ICOMP #=YYY FFFFFFFF-DDDD INTEL
cC0-Step Production PPGA Units:
mA4-Step Engineering Sample Units:
mA4-Step Engineering Sample SPGA Units:
pentium®
pentium
iXXX
mA4-Step Production Units:
TT80502-XXX FFFFFFFF QZZZZ 2.9V `92,
A80502-XXX FFFFFFFF QZZZZ 2.9V DDDD INTEL
mA4-Step Production SPGA Units:
mcC0-Step Engineering Sample SPGA Units
pentium®
pentium®
`92,
TT80502-XXX FFFFFFFF SKZZZ 2.9V
A80502-XXX FFFFFFFF SKZZZ 2.9V DDDD INTEL
A80502-XXX FFFFFFFF QZZZZ 3.1V INTELM
PENTIUM® PROCESSOR SPECIFICATION UPDATE
mcC0-Production SPGA Steppings:
mcC0-Step Engineering Sample Units:
mcC0-Step Production Units:
pentium®
PPXXX QZZZZ FFFFFFFF PPXXX YZZZ FFFFFFFF
A80502XXX SZZZZ ICOMP® #=YYY FFFFFFFF-DDDD INTEL
E0-Step Engineering Sample Units:
E0-Step Production Units:
xA3-Step Pentium Processor MMXTechnology Engineering Sample PPGA Units:
pentium
pentium®
pentium
MMXtech
A80502BB-XXX FFFFFFFQ QZZZZ DDDD `92,
A80502XXX SZZZZ ICOMP #=YYY FFFFFFFF-DDDD INTEL
xA3-Step Pentium® Processor MMXTechnology Production PPGA Units:
xA3-Step Pentium® Processor MMXTechnology Production SPGA Units:
mxA3-Step Pentium® Processor MMXTechnology Engineering Sample Units:
pentium®
pentium
pentium
TT80503XXX FFFFFFFF QZZZZ 2.45V `92,
tech
MMXtech
A80503XXX SZZZZ FFFFFFFF-DDDD INTEL
PENTIUM® PROCESSOR SPECIFICATION UPDATE
mxA3-Step Pentium Processor MMXTechnology Production Units:
mxA3-Step Pentium Processor MMXTechnology Engineering Sample PPGA Units:
mxA3-Step Pentium Processor MMXTechnology Production PPGA Units:
pentium
TT80503XXX FFFFFFFF SZZZZ 2.45V `92,
pentium
pentium
MMXtech
MMXtech
mxB1-Step Pentium Processor MMXTechnology Engineering Sample Units:
mxB1-Step Pentium Processor MMXTechnology Engineering Sample PPGA Units:
xB1-Step Pentium Processor MMXTechnology Engineering Sample SPGA Units:
pentium
TT80503XXX FFFFFFFF QZZZZ 2.45V `92,
pentium
MMXtech
pentium®
tech
A80503XXX QXXX FFFFFFFF-DDDD INTEL
mxB1-Step Pentium® Processor MMXTechnology Production Units:
mxB1-Step Pentium® Processor MMXTechnology Production PPGA Units:
xB1-Step Pentium® Processor MMXTechnology Production SPGA Units:
pentium
TT80503XXX FFFFFFFF QZZZZ 2.45V `92,
pentium
MMXtech
pentium®
tech
A80503XXX SZZZZ FFFFFFFF-DDDD INTEL
PENTIUM® PROCESSOR SPECIFICATION UPDATE
xB1-Step Pentium Processor MMXTechnology Engineering Sample PPGA Units:
xB1-Step Pentium Processor MMXTechnology Production PPGA Units:
myA0-Step Engineering Sample Units:
intel
pentium
pentium
MMXtech
MMXtech
TTXXX QZZZZ FFFFFFFF `92`95
myA0-Step Production Units:
intel
TTXXX SZZZZ FFFFFFFF `92`95
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Bottom Markings
C-Step Production Units: (before 7/95) cB1-Step Production Units: (after 7/95) mcB1-Step Engineering Sample SPGA Units:
XXXXXXXXXX XXXXXXXXXX INTEL A80502-SSS SZZZZ
XXXXXXXXXX XXXXXXXXXX A80502-SSS SXXXX
XXXXXXXXXX XXXXXXXXXX A80502-XXX QZZZZ
mcB1-Step Production SPGA Units:
cC0-Step Engineering Sample Units:
cC0-Step Production Units:
XXXXXXXXXX XXXXXXXXXX A80502-XXX SZZZZ
XXXXXXXXXX XXXXXXXXXX A80502-XXX QZZZZ
XXXXXXXXXX XXXXXXXXXX A80502XXX SZZZZ
mA4-Step Engineering Sample SPGA Units:
mA4-Step Production SPGA Units:
cC0-Step Engineering Sample PPGA Units:
XXXXXXXXXX XXXXXXXXXX A80502-XXX QZZZZ
XXXXXXXXXX XXXXXXXXXX A80502-XXX SKZZZ
pentium
FV80502-XXX QZZZZ ES/KLM XXXXX FFFFFFFF-DDDD
PENTIUM® PROCESSOR SPECIFICATION UPDATE
cC0-Step Engineering Sample PPGA Units:
mcC0-Step Production SPGA Units:
cC0-Step Production PPGA Units:
pentium
XXXXXXXXXX XXXXXX A80502XXX SZZZZ iHHH
pentium
FV80502XXX QZZZZ ES/KLM XXXXX FFFFFFFF-DDDD
FV80502XXX SZZZZ/KLM ICOMP® #=YYY XXXXX FFFFFFFF-DDDD
mcC0-Step Engineering Sample SPGA Units:
E0-Step Engineering Sample Units:
E0-Step Production Units:
XXXXXXXXXX XXXXXXXXXX A80502-XXX QZZZZ
XXXXXXXXXX XXXXXXXXXX A80502-XXX QZZZZ
XXXXXXXXXX XXXXXXXXXX A80502XXX SZZZZ
xA3-Step Pentium® Processor MMXTechnology Engineering Sample PPGA Units:
xA3-Step Pentium® Processor MMXTechnology Production PPGA Units:
xA3-Step Pentium® Processor MMXTechnology Production SPGA Units:
pentium
pentium
MMXtech FV80503XXX QBBB ES/2.8V XXXXX FFFFFFFF-[{SN}]
MMXtech FV80503XXX SZZZZ 2.8V XXXXX FFFFFFFF-[{SN}]
XXXXXXXXXX XXXXXXXXXX A80503XXX SZZZZ/2.8V
PENTIUM® PROCESSOR SPECIFICATION UPDATE
mxA3-Step Pentium Processor MMXTechnology Engineering Sample PPGA Units:
mxA3-Step Pentium Processor MMXTechnology Production PPGA Units:
mxB1-Step Pentium Processor MMXTechnology Engineering Sample PPGA Units:
pentium
pentium
pentium
MMXtech FV80503XXX QBBB ES/2.45V XXXXX FFFFFFFF-[{SN}]
MMXtech FV80503XXX SZZZZ 2.45V XXXXX FFFFFFFF-[{SN}]
MMXtech FV80503XXX QBBB ES/2.45V XXXXX FFFFFFFF-[{SN}]
mxB1-Step Pentium Processor MMXTechnology Production PPGA Units:
xB1-Step Pentium Processor MMXTechnology Engineering Sample SPGA Units:
xB1-Step Pentium Processor MMXTechnology Production SPGA Units:
pentium
MMXtech FV80503XXX QBBB 2.45V XXXXX FFFFFFFF-[{SN}]
XXXXXXXXXX XXXXXXXXXX A80503XXX QXXX/2.8V
XXXXXXXXXX XXXXXXXXXX A80503XXX SZZZZ/2.8V
xB1-Step Pentium® Processor MMXTechnology Engineering Sample PPGA Units:
xB1-Step Pentium® Processor MMXTechnology Production PPGA Units:
pentium
pentium
MMXtech FV80503XXX QBBB ES/2.8V XXXXX FFFFFFFF-[{SN}]
MMXtech FV80503XXX SZZZZ 2.8V XXXXX FFFFFFFF-[{SN}]
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Boxed Pentium® Processors with Unattached Heatsinks Markings
B-Step Boxed Production Units:
PCPU3VXXX SZZZZ ICOMP INDEX=YYY
C2-Step Boxed Production Units:
C2-Step Boxed Production Units:
pentiumpentium
pentium®
FFFFFFFF-DDDD INTEL
PCPU3VXXX SZZZZ ICOMP INDEX =YYY FFFFFFFF-DDDD INTEL
BP80502XXX SZZZZ ICOMP INDEX =YYY FFFFFFFF-DDDD INTEL
cC0, E0-Step Boxed Production Units:
cC0-Step Boxed Production PPGA Units:
xB1-Step Boxed Pentium Processor w/MMXTechnology Production PPGA Units:
pentium®
pentium
iXXX
pentium
MMXtech
BP80502-XXX SZZZZ ICOMP #=YYY FFFFFFFF-DDDD INTEL
xB1-Step Boxed Pentium® Processor MMXTechnology Production SPGA Units:
pentium®
tech
BP80503XXX SZZZZ FFFFFFFF-DDDD INTEL
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Boxed Pentium® Processors with Attached Heatsinks Markings
cB1, E0-Step Boxed Pentium® Processor Heatsink Base Marking: cB1, E0-Step Early Boxed Pentium® Processor Heatsink Base Marking: E0-Step Boxed Pentium Processor Heatsink Base Marking:
BP80502-XXX SZZZZ ICOMP INDEX=YYY FFFFFFFF INTEL '92'93
BP80502-XXX SZZZZ FFFFFFFF INTEL '92'93
BP80502-XXX SZZZZ ICOMP® =YYY FFFFFFFF INTEL '92'93
xB1-Step PPGA Boxed Pentium® Processor with MMXTechnology Heatsink Base Marking:
xB1-Step SPGA Boxed Pentium® Processor with MMXTechnology Heatsink Base Marking:
BP80503-XXX SZZZZ ICOMP® =YYY FFFFFFFF INTEL '92'93
PENTIUM(R) MMX(TM) TECH FFFFFFFF SZZZZ INTEL '92'95
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Boxed Pentium® Processors Bottom Markings
C2-Step Boxed Production Units: C2-Step Boxed Production Units: (before 7/95) cB1-Step Boxed Production Units: (after 7/95)
XXXXXXXXXX XXXXXXXXXX INTEL PCPU3VXXX SZZZZ
XXXXXXXXXX XXXXXXXXXX INTEL BP80502-XXX SZZZZ
XXXXXXXXXX XXXXXXXXXX BP80502-XXX SZZZZ
cB1-Step Boxed Production Units: (after 7/95)
E0-Step Boxed Production Units:
cC0-Step Boxed Production PPGA Units:
XXXXXXXXXX XXXXXXXXXX BP80502XXX SZZZZ
XXXXXXXXXX XXXXXXXXXX BP80502XXX SZZZZ
pentium
BP80502XXX SZZZZ/KLM ICOMP® #=YYY XXXXX FFFFFFFF-DDDD
E0-Step Boxed Production Units:
xA3-Step Boxed Pentium® Processor MMXTechnology Production PPGA Units:
xA3-Step Boxed Pentium® Processor MMXTechnology Production SPGA Units:
XXXXXXXXXX XXXXXXXXXX BP80502XXX SZZZZ
pentium
MMXtech BP80503XXX SZZZZ 2.8V XXXXX FFFFFFFF-[{SN}]
XXXXXXXXXX XXXXXXXXXX BP80503XXX SZZZZ 2.8V
PENTIUM® PROCESSOR SPECIFICATION UPDATE
xA3-Step xB1-Step Boxed Pentium® Processor MMXTechnology Production PPGA Units:
xA3-Step xB1-Step Boxed Pentium® Processor MMXTechnology Production SPGA Units:
pentium
MMXtech BP80503XXX SZZZZ 2.8V XXXXX FFFFFFFF-[{SN}]
XXXXXXXXXX XXXXXXXXXX BP80503XXX SZZZZ/2.8V
NOTES: Core Speed (MHz). speed (MHz). SZZZZ/SKZZZ Product S-Spec number. FFFFFFFF (Test Traceability packages with heat spreaders, inner line defines spreader edge. Mark logo information heat spreader. Laser Mark lines information above below heat spreader. bottomside information laser mark. Engineering Sample. QZZZZ Sample Specification number. DDDD Serialization code. iCOMP index iCOMP index. Intel making enhancement current plastic (PPGA) ceramic (CPGA) desktop mobile Pentium processors with addition iCOMP Index rating part processor package mark. PPGA Pentium processors, iCOMP index will marked bottom side (pin side) package CPGA will marked side package. part marking will iCOMP 75-MHz, 90-MHz, 100-MHz, 120-MHz, 133-MHz, 150-MHz, 166-MHz, 200-MHz). Older parts marked with iCOMP index (610 75-MHz 90-MHz, 100-MHz, 1000 120-MHz, 1110 133-MHz, 1176 150-MHz, 1308 166MHz parts). Package, SPGA Package, PPGA Package, Boxed Processor package. bottom markings cB1-step production units will replace existing bottom marking C-step parts effective 7/95. 133-MHz Pentium processors, other speeds mobile Pentium processors. voltage range standard voltage range. valid timings valid normal timings. tested tested tested
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Basic Pentium® Processor Pentium Processor with MMXTechnology Identification Information CPUID Manufacturing Speed (MHz) Type Family Model Stepping Stepping Core S-Spec Comments 75/50 75/50 90/60 90/60 90/60 100/66 100/66 100/66 75/50 90/60 90/60 90/60 90/60 100/66 100/66 90/60 90/60 90/60 100/66 75/50 75/50 90/60 90/60 90/60 90/60 90/60 90/60 90/60 100/66 Q0540 Q0541 Q0542 Q0613 Q0543 Q0563 Q0587 Q0614 Q0601 SX879 SX885 SX909 SX874 SX886 SX910 Q0628 Q0611 Q0612 Q0677 Q0606 SX951 SX923 SX922 SX921 SX942 SX943 SX944 SZ9515 SX960 Mobile VRE/MD Mobile Mobile VRE/MD
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Basic Pentium® Processor Pentium Processor with MMXTechnology Identification Information (Cont'd) CPUID Manufacturing Speed (MHz) Type Family Model Stepping Stepping Core S-Spec Comments 75/50 75/50 90/60 90/60 90/60 100/66 100/66 100/66 120/60 120/60 75/50 75/50 75/50 90/60 90/60 90/60 90/60 100/66 75/50 75/50 75/50 90/60 100/50 100/50 120/60 120/60 133/66 133/66 133/66 75/50 Q0704 Q0666 Q0653 Q0654 Q0655 Q0656 Q0657 Q0658 Q0707 Q0708 SX975 SX961 SZ9775 SX957 SX958 SX959 SZ9785 SX962 Q0725 Q0700 Q0749 Q0699 Q0698 Q0697 Q0711 Q0732 Q0733 Q0751 Q0775 SK079 Mobile VRE/MD VRE/MD1 STD1 Mobile VRE/MD Mobile VRE/MD VRE/MD VRE/MD VRE/MD Mobile
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Basic Pentium® Processor Pentium Processor with MMXTechnology Identification Information (Cont'd) CPUID Manufacturing Speed (MHz) Type Family Model Stepping Stepping Core S-Spec Comments mA14 mA14 mA14 mA14 mA14 mA14 mA14 mA14 cB14 cB14 cB14 cB14 cB14 cB14 cB14 cB14 cB14 75/50 75/50 75/50 75/50 90/60 90/60 90/60 100/50 100/50 100/50 100/50 120/60 120/60 120/60 133/66 75/50 75/50 90/60 90/60 75/50 75/50 90/60 90/60 120/60 133/66 133/66 133/66 120/60 133/66 133/66 133/66 133/66 SX969 SX998 SZ9945 SU0706 SX968 SZ9955 SU0316 SX970 SX963 SZ9965 SU0326 SK086 SX994 SU0336 SK098 Q0686 Q0689 Q0694 Q0695 SK089 SK091 SK090 SK092 Q0776 Q0772 Q0773 Q0774 SK110 SK106 S106J7 SK107 SU0386 VRE/MD VRE/MD VRE/MD VRE/MD VRT2, VRT2, SPGA VRT2, VRT2, SPGA VRT2, VRT2, SPGA VRT2, VRT2, SPGA STD/no Kit3 STD/no Kit3 VRE/MD, Kit3 STD/no Kit3 STD/no Kit3 STD/no Kit3 STD/no Kit3
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Basic Pentium® Processor Pentium Processor with MMXTechnology Identification Information (Cont'd) CPUID Manufacturing Speed (MHz) Type Family Model Stepping Stepping Core S-Spec Comments mcB14 mcB14 mcB14 mcB14 mcB14 mcB14 mcB14 100/66 120/60 120/60 100/66 120/60 120/60 120/60 133/66 133/66 150/60 150/60 150/60 166/66 166/66 166/66 166/66 166/66 166/66 200/66 200/66 200/66 120/60 120/60 120/60 133/66 133/66 133/66 133/66 133/66 Q0884 Q0779 Q0808 SY029 SK113 SK1187 SX999 Q0843 Q0844 Q0835 Q0878 SU1226 Q0836 SY055 Q0841 Q0886 Q0890 Q09498 Q0951F10 Q09518 SL25H6, SL22M6 SL25J5 SY062 SL22Q6 SL25L5 SY022 SY023 SU0736 VRT2, VRT2, 3.3V, SPGA VRT2, VRT2, VRT2, 3.3V, SPGA STD/No Kit3 STD, PPGA9 VRE/No Kit3 VRE/No Kit3 VRE, PPGA9 VRE, PPGA9 VRE, PPGA9 VRE, PPGA9 VRE, PPGA9 VRE, PPGA9 STD/ Kit3 STD/ Kit3
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Basic Pentium® Processor Pentium Processor with MMXTechnology Identification Information (Cont'd) CPUID Manufacturing Speed (MHz) Type Family Model Stepping Stepping Core S-Spec Comments mA44 mA44 mA44 mA44 mA44 mA44 mA44 mA44 mA44 mA44 mA44 mA44 mcC04 mcC04 mcC04 mcC04 mcC04 mcC04 150/60 150/60 166/66 166/66 166/66 166/66 166/66 200/66 200/66 200/66 200/66 75/50 75/50 90/60 90/60 100/66 100/66 75/50 75/50 90/60 90/60 100/66 100/66 100/66 120/60 120/60 133/66 133/66 150/60 SY015 SU0716 SL24R SY016 SY017 SU0726 SY0378 SY044 SY0458,15 SU1145,8, SL24Q8 Q0848 Q0851 Q0849 Q0852 Q0850 Q0853 SK119 SK122 SK120 SK123 SK121 SK124 Q0887 Q0879 Q0880 Q0881 Q0882 Q024 VRE, Kit3,13 VRE, Kit3 VRE, Kit3 VRE, PPGA9 VRE, PPGA9 VRE, PPGA9 VRE, PPGA9 VRE, PPGA9, Kit3, VRT2, VRT2, SPGA VRT2, VRT2, SPGA VRT2, VRT2, SPGA VRT2, VRT2, SPGA VRT2, VRT2, SPGA VRT2, VRT2, SPGA TCP/VRT2 TCP/VRT2 SPGA 3.1V TCP/VRT2 SPGA 3.1V TCP/VRT2
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Basic Pentium® Processor Pentium Processor with MMXTechnology Identification Information (Cont'd) CPUID Manufacturing Speed (MHz) Type Family Model Stepping Stepping Core S-Spec Comments mcC04 mcC04 mcC04 mcC04 mcC04 mcC04 mcC04 mcC04 mcC04 mcC04 mcC04 mcC04 mcC04 150/60 150/60 75/50 100/66 100/66 120/60 120/60 120/60 133/66 133/66 150/60 150/60 150/60 75/50 75/50 90/60 100/50 120/60 75/50 75/50 75/50 75/50 90/60 100/50 100/50 100/50 120/60 120/60 90/60 Q0906 Q040 SY056 SY020 SY046 SY021 SY027 SY030 SY019 SY028 SY061 SY043 SY058 Q0846 Q0837 Q0783 Q0784 Q0785 SY009 SY005 SU0975 SU0986 SY006 SY007 SU1105 SU0996 SY033 SU1006 SL2WW 3.1V SPGA/VRT2 TCP/VRT2 TCP/VRT2 SPGA 3.1V TCP/VRT2 SPGA 3.1V SPGA 3.3V TCP/VRT2 SPGA 3.1V TCP/VRT2 3.1V SPGA/VRT2 Mobile Mobile
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Basic Pentium® Processor Pentium Processor with MMXTechnology Identification Information (Cont'd) CPUID Manufacturing Speed (MHz) Type Family Model Stepping Stepping Core S-Spec Comments mxA3 mxA3 mxA3 mxA3 mxA3 mxA3 mxA3 mxA3 150/60 166/66 200/66 166/66 166/66 166/66 166/66 166/66 166/66 166/66 166/66 200/66 200/66 200/66 200/66 200/66 200/66 150/60 150/60 166/66 166/66 150/60 150/60 166/66 166/66 166/66 166/66 200/66 200/66 166/66 Q020 Q019 Q018 SL23T6, SL23R5 SL25M6 SY059 SL2HU SL239 SL26V SL26H SL26J15 SY060 SL26Q5 SL2746 SL23S5 SL25N6 Q016 Q061 Q017 Q062 SL22G SL246 SL22F SL23Z Q125 Q126 Q124 Q430 SL27H PPGA PPGA PPGA SPGA12 PPGA9,12 PPGA9,12 PPGA12 SPGA12 SPGA12 SPGA12,13 PPGA12,13 PPGA12,13 PPGA12 PPGA9,12,13 PPGA9,12,13 PPGA9,12 PPGA9,12 TCP11 PPGA TCP11 PPGA TCP11 PPGA11 TCP11 PPGA11 PPGA SPGA PPGA SPGA12 PPGA12
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Basic Pentium® Processor Pentium Processor with MMXTechnology Identification Information (Cont'd) CPUID Manufacturing Speed (MHz) Type Family Model Stepping Stepping Core S-Spec Comments mxB1 mxB1 mxB1 mxB1 mxB1 mxB1 mxB1 mxB1 mxB1 mxB1 mxB1 mxB1 mxB1 mxB1 mxB1 myA0 myA0 myA0 myA0 166/66 166/66 166/66 166/66 166/66 200/66 200/66 200/66 200/66 200/66 233/66 233/66 233/66 120/60 133/66 133/66 150/60 150/60 166/66 166/66 200/66 133/66 133/66 150/60 150/60 166/66 166/66 200/66 166/66 166/66 166/66 200/66 SL27K SL2HX5 SL23X
SPGA12 SPGA12 SPGA12 PPGA9, PPGA9, PPGA12
SL2FP5 SL23V SL27J SL2FQ
PPGA9, PPGA9, SPGA12 SPGA12 PPGA12 PPGA9, PPGA9,
SL23W SL2RY
SL2S96 SL27S SL2BM SL2936 Q230 Q130 Q129 Q116 Q128 Q115 Q127 Q586 SL27D SL27C SL26U SL27B SL26T SL27A SL2WK Q255 Q252 SL2N6 Q146
TCP11 PPGA TCP11 PPGA TCP11 PPGA PPGA11 TCP11 PPGA11 TCP11 PPGA11 TCP11 PPGA11 PPGA11 TCP16 TCP16 TCP16 TCP16
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Basic Pentium® Processor Pentium Processor with MMXTechnology Identification Information (Cont'd) CPUID Manufacturing Speed (MHz) Type Family Model Stepping Stepping Core S-Spec Comments myA0 myA0 myA0 myA0 myA0 myA0 myA0 myA0 myB2 myB2 myB2 myB2 myB2 myB2 233/66 200/66 233/66 266/66 266/66 266/66 266/66 266/66 266/66 266/66 266/66 266/66 300/60 300/66 Q147 SL28P SL28Q Q250 Q251 SL2N5 Q695 SL2ZH Q766 Q767 SL23M SL23P Q768 SL34N TCP16 TCP16 TCP16 TCP19 TCP19 TCP19 TCP16 TCP16 TCP19 TCP16 TCP19 TCP16 TCP19 TCP19
NOTES: definition STD, VRE, VRE/MD, refer Specification Change S-Spec this document. refers Engineering Samples. indicates that this part only used dual processor. Type indicates this part supports dual processing. Type corresponds bits [13:12] register after RESET, bits [13:12] register after CPUID instruction executed. This shown different values based operation device primary processor dual processor upgrade. Family corresponds bits [11:8] register after RESET, bits [11:8] register after CPUID instruction executed. Model corresponds bits [7:4] register after RESET, bits [7:4] register after CPUID instruction executed. Stepping corresponds bits [3:0] register after RESET, bits [3:0] register after CPUID instruction executed. absence package type comments column means processor SPGA default. TCASE 60°C. Intel's Voltage Reduction Technology: 3.3V, core accounting about power usage, reduced 2.9V, reduce power consumption heating. means that part meets specifications tested support 82498/82493 82497/82492 cache timings. STEPPING stepping logically equivalent C2-step, different manufacturing process. mcB1 step logically equivalent step (except does support APIC FRC). mcB1, mA1, mcC0-steps also Intel's (Voltage Reduction Technology, note above) available and/or SPGA package, primarily support mobile applications. mxA3 logically equivalent stepping (except does support APIC). mobile steppings distinguished additional prefix, "mobile". steppings Pentium® processor with MMXtechnology distinguished additional prefix.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
This boxed Pentium processor without attached heatsink. This boxed Pentium processor with attached heatsink. These parts support boundary scan. S106J previously marked (and same SK106J. APIC features supported these parts. These parts packaged Plastic Grid Array (PPGA) package. additional specifications this package, specification clarifications Some Q0951F units marked bottom side with spec number Q0951 with additional line immediately underneath spelling "Full Feature" properly identify unit. This mobile Pentium processor with technology with core operating voltage 2.285V 2.665V. This desktop Pentium processor with technology with core operating voltage 2.7V 2.9V. Freq means part only maximum specified frequency. Specifically, 200-MHz +0/-5 (195 MHz) 166-MHz +0/-5 (161 MHz). SU114 SL25H units marked bottom side with code "VSS". This incorrect. proper code should read "VSU", since units support APIC features. This spec number been discontinued replaced spec number SY045. This part also ships boxed processor with unattached heatsink. This mobile Pentium processor with technology with core operating voltage 1.665V 1.935V operating voltage 2.375V 2.625V. This mobile Pentium processor with technology with core operating voltage 2.10V 2.34V. Some SL23T parts incorrectly marked with "SSS" final line bottom side marking. marking should read "2.8V" this location. incorrect marking does affect specification operation those units. This mobile Pentium Processor with technology with core operating voltage 1.850V 2.150V operating voltage 2.375V 2.625V.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Summary Table Changes
following table indicates Specification Changes, S-Specs, Errata, Specification Clarifications Documentation Changes, which apply listed Pentium processor Pentium processor with MMXtechnology steppings. Intel intends some errata future stepping component, account other outstanding issues through documentation specification changes noted. This table uses following notations: CODES USED SUMMARY TABLE Doc: Fix: Fixed: NoFix: mark) (Blank Box): TCP: Shaded: Erratum, Specification Change Clarification that applies this stepping. Document change update that will implemented. This erratum intended fixed future stepping component. This erratum been previously fixed. There plans this erratum. This erratum fixed listed stepping specification change does apply listed stepping. Dual processing related errata. APIC related errata. Applies listed stepping mobile Pentium processor package only. This item either modified from previous version document.
SPECIFICATION CHANGES
mcB1 mcC0 mxA3 mxB1 myA0 myB2 Plans
limit violation causes fault, interrupt active power dissipation (typical) change Redundant timing spec: frequencies Stop clock power valid delay valid delay data Maximum Stop-Grant/AutoHALT Power fraction 233-MHz speciifications Active power 133-MHz current power specifications fraction Maximum thermal design power
PENTIUM® PROCESSOR SPECIFICATION UPDATE
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SPECIFICATION CHANGES (Cont'd)
PCHK# state output current mode Absolute maximum rating VCC3 120/60 VCC, power, specifications 166- 266-MHz CC2, power specifications Mobile 200/66 0.35 micron VCC2, ICC, TCASE power specifications voltage 0.25 micron process technology (for only) VCC2, ICC, TCASE power specifications Mobile Pentium processor with technology 0.25 micron process specifications
S-SPECS
mcB1 mcC0 mxA3 mxB1 myA0 myB2 Plans
Fixed t6a, t6b, valid delay BE7# BE0#, ADS#, LOCK# Fixed Minimum required voltage separation between Vcc2 Fixed TRST# Fixed reduced Fixed Boundary scan timing changes Fixed SPGA Vcc2 supply voltage change Fixed specifications Pentium Processor with Voltage Reduction Technology Fixed Reduced Fixed Mixing steppings dual processing mode
Fixed MD/VR/VRE specifications Fixed 120-MHz 133-MHz parts (Q0707, Q0708, Q0711, Q0732, Q0733, Q0751, Q0775, SK086, SX994, SK098, SU033) support dual processing
PENTIUM® PROCESSOR SPECIFICATION UPDATE
mcB1 mcC0 mxA3 mxB1 myA0 myB2 Plans
S-SPECS (Cont'd)
Fixed 120-MHz 133-MHz parts (Q0707, Q0708, Q0711, Q0733, Q0751, Q0775, SK086, SK098) support Fixed 120-MHz 133-MHz parts (Q0707, Q0708, Q0711, Q0733, Q0751, Q0775, SK086, SK098) startup specification Fixed 120-MHz 133-MHz parts (Q0707, Q0708, Q0711, Q0733, Q0751, Q0775, SK086, SK098) current leakage PICD1 Fixed Mobile stop clock power Fixed IIH, input leakage current NoFix valid delay (Replaced Spec Change) Fixed valid delay ADS# Fixed valid delay HITM# NoFix valid delay data (Replaced Spec Change) Fixed Desktop stop clock power NoFix valid delay data
ERRATA
mcB1 mcC0 mxA3 mxB1 myA0 myB2 Plans
Fixed Branch trace messages during lock cycles Fixed Breakpoint single-step missed instruction following Fixed restart does function during single stepping data breakpoint exceptions Fixed INIT with restart during single-stepping Fixed SMI# FLUSH# during shutdown Fixed shutdown after IERR# Fixed FLUSH# with breakpoint pending causes false values Fixed Processor core serialize idle Fixed SMIACT# premature assertion during replacement writeback cycle
PENTIUM® PROCESSOR SPECIFICATION UPDATE
mcB1 mcC0 mxA3 mxB1 myA0 myB2 Plans
ERRATA (Cont'd)
Superceded Specification Change
STPCLK# deassertion recognized CLKs after BRDY# returned Fixed Future Pentium OverDrive® processor FERR# contention two-socket systems Fixed Code cache lines invalidated snooped during AutoHALT Stop-Grant states Fixed STPCLK# assertion during execution HALT instruction hangs system
NoFix INIT during HALT within cause large amount activity Fixed RUNBIST restrictions when through boundary scan circuitry Fixed mode miscompare uninitialized internal register STPCLK# restrictions during EWBE# Fixed Multiple allocations into branch target buffer Fixed 100-MHz MOVS speed path Fixed Overflow undetected some numbers FIST Fixed operands result unexpected FIST operation Fixed Snoop with table-walk violation invalidate snooped line Fixed Slight precision loss floatingpoint divides specific operand pairs Fixed FLUSH#, INIT machine check dropped floating-point exception
Superceded Specification Change
Fixed Floating-point operations clear alignment check Fixed CMPXCHG8B across page boundary cause invalid opcode exception NoFix Single-step debug exception breaks HALT
PENTIUM® PROCESSOR SPECIFICATION UPDATE
mcB1 mcC0 mxA3 mxB1 myA0 myB2 Plans
ERRATA (Cont'd)
Fixed Branch trace message corruption Fixed lock-step failure during APIC write
Fixed BE4# BE0# sampled incorrectly Fixed Incorrect PCHK# output during boundary scan mode
Fixed altered after specific operations followed Sreg, Fixed WRMSR into illegal does generate Fault Fixed Inconsistent data cache state from concurrent snoop memory write Fixed BE3# BE0# driven during boundary scan RESET high
Fixed Incorrect after RESET NoFix Second assertion FLUSH# ignored NoFix Segment limit violation operand corrupt state NoFix exception inside with pending hangs system Fixed Current Stop Clock state exceeds specification
Fixed STPCLK# buffer samples incorrectly during boundary scan testing Fixed Incorrect decode certain instructions
NoFix Data breakpoint deviations NoFix Event monitor counting discrepancies NoFix VERR type instructions causing page fault task switch with corrupt CS:EIP NoFix BUSCHK# interrupt wrong priority Fixed CPUTYP buffers sample incorrectly during boundary scan testing
PENTIUM® PROCESSOR SPECIFICATION UPDATE
mcB1 mcC0 mxA3 mxB1 myA0 myB2 Plans
ERRATA (Cont'd)
NoFix Matched disabled data breakpoint lost STPCLK# assertion NoFix STPCLK# ignored when INIT pending Fixed STPCLK# pullup engaged RESET
NoFix fault causing page fault cause instruction execute twice NoFix Machine check exception pending, then HLT, cause skipped incorrect instruction, hang NoFix FBSTP stores operand incorrectly address wrap error both occur NoFix interrupt routine illegal privilege level cause spurious pushes stack NoFix Corrupted flag cause skipped incorrect instruction, hang NoFix Benign exceptions erroneously cause double fault NoFix Double fault counter increment correctly Fixed Some input pins float high when core powers after (mobile CPU)
NoFix Short form pair NoFix Turning paging result prefetch random location NoFix STPCLK#, FLUSH# SMI# after NoFix string instruction interruptable STPCLK# NoFix Single step reported first instruction after FLUSH# NoFix Double fault generate illegal cycle NoFix TRST# asynchronous
PENTIUM® PROCESSOR SPECIFICATION UPDATE
mcB1 mcC0 mxA3 mxB1 myA0 myB2 Plans
ERRATA (Cont'd)
NoFix STPCLK# causes non-normal behavior NoFix Code cache dump cause wrong IERR# NoFix Asserting TRST# issuing JTAG instructions does exit Hi-Z state NoFix ADS# delayed after HLDA deassertion NoFix Stack underflow IRET gives #GP, NoFix Performance monitoring pins PM[1:0] count events incorrectly Fixed BIST disabled
NoFix Branch trace messages cause system hang Fixed Enabling RDPMC also using cause shutdown Fixed Event monitor counting discrepancies (fix) NoFix Event monitor counting discrepancies (Nofix) Fixed INVD leave valid entries cache snoop interaction NoFix update blocked after specific sequence events with misaligned descriptor NoFix Erroneous debug exception POPF/IRET instructions with fault NoFix Content upon Return from Fixed Invalid operand with locked CMPXCHG8B instruction Fixed Event monitor counting discrepancy
NoFix FBSTP instruction incorrectly sets Accessed Dirty bits Page Table entry Fixed Problem with external snooping while cycles pending
PENTIUM® PROCESSOR SPECIFICATION UPDATE
mcB1 mcC0 mxA3 mxB1 myA0 myB2 Plans
ERRATA (Cont'd)
Fixed STPCLK# assertion StopGrant cycle Fixed External snooping with AHOLD asserted cause processor hang Fixed Address parity check supported dual processing mode Fixed Inconsistent cache state result from interprocessor pipelined READ into WRITE Fixed Processors hang during Zero pipelined cycles Fixed lock-up problem specific dual processing mode sequence Fixed Incorrect assertion PHITM# without PHIT# Fixed Double issuance read cycles Fixed Line invalidation occur read prefetch cycles Fixed EADS# floating ADS# cause extra invalidates Fixed HOLD BOFF# during APIC cycle cause dual processor arbitration problem Fixed System hang after hold during local APIC second INTA cycle Fixed External snoop incorrectly invalidated NoFix STPCLK# re-assertion recognition constraint with NoFix Second assertion FLUSH# during flush acknowledge cycle cause hang NoFix Asserting FLUSH# cause processor deadlock system with fraction Fixed Remote read message shows valid status after checksum error Fixed Chance clearing unread error error register Fixed Writes error register clears register
10DP 11DP 12DP
13DP 14DP 15DP 16DP
17DP
PENTIUM® PROCESSOR SPECIFICATION UPDATE
mcB1 mcC0 mxA3 mxB1 myA0 myB2 Plans
ERRATA (Cont'd)
Fixed Three interrupts same priority causes lost local interrupt Fixed APIC synchronization lost checksum error remote read message Fixed HOLD during READ from local APIC register cause incorrect PCHK# Fixed HOLD during outstanding interprocessor pipelined APIC cycle hangs processor Fixed PICCLK reflection cause APIC checksum error Fixed Spurious interrupt APIC through local mode Fixed Potential lost interrupts while using APIC through Local mode Fixed Back back assertions HOLD BOFF# cause lost APIC write cycle Fixed System hangs when BOFF# asserted during second internal INTA cycle Fixed APIC pipeline cycle during cache linefill causes restarted cycle lose attribute NoFix INIT APIC threewire lost Fixed IERR# lock-step mode during APIC write Fixed Inadvertent BRDY# during external INTA cycle with BOFF# Fixed APIC read cycle complete upon assertion BOFF# HOLD NoFix PICCLK must toggle least twenty cycles before RESET Fixed APIC changed Fixed reset correctly floating FRCMC# Fixed BRDY# does have buffer selection capability
10AP 11AP
12AP
13AP
14AP 15AP 16AP 17AP
18AP 19AP 1TCP 2TCP
PENTIUM® PROCESSOR SPECIFICATION UPDATE
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SPECIFICATION CLARIFICATIONS
Pentium processor's response startup init IPIs APIC timer clarification
Fixed PICCLK reflection cause APIC checksum errors dropped IPIs Fixed Boundary scan RUNBIST register requires initialization prior Only SMI# latched during APIC 8-bit access LOCK prefix excludes APIC memory space SMI# activation cause nested handling Code breakpoints meaningless prefixes guaranteed recognized Resume flag should software Data breakpoints delayed iteration When cache disabled, inquire cycles blocked Serializing operation required when modifies another CPU's code correct translations, should flushed after When APIC enabled, block should used regular memory Extra code break occur instruction coincides maybe updated noncacheable cycles FYL2XP1 does generate exceptions range Enabling inside BF[1:0] must change values while RESET active
PENTIUM® PROCESSOR SPECIFICATION UPDATE
mcB1 mcC0 mxA3 mxB1 myA0 myB2 Plans
SPECIFICATION CLARIFICATIONS (Cont'd)
Active A20M# during POP[ESP] with 16-bit stack size #190 (TCP package) connection Line fill order optimization revision Test parity check mechanism clarification
DOCUMENTATION CHANGES
mcB1 mcC0 mxA3 mxB1 myA0 myB2 Plans
cannot nested task switch, Volume page 13-12 Incorrect pinout Interrupt sampling window, Volume page 23-39 FSETPM like NOP, like FNOP Errors three tables special descriptor types iCOMP® index rating correction Default setting BF1-0 Pentium processor with MMXtechnology exceptions cause branch trace messages fraction size reduction Absolute maximum rating VCC3 Invalid arithmetic operations masked responses them relative FIST/FISTP instruction Incorrect sequence registers stored PUSHA/PUSHAD One-byte opcode correction Boundary scan chain order revision
PENTIUM® PROCESSOR SPECIFICATION UPDATE
SPECIFICATION CHANGES
Specification Changes listed this section apply Pentium® Processor Family Developer's Manual, (Order Number 241428), Intel Architecture Software Developer's Manual, Volume Basic Architecture (Order Number 243190); Volume Instruction Reference Manual (Order Number 243191), Pentium® Processor iCOMP® index 610\75 MHz, 735\90 MHz, 815\100 MHz, 1000\120 MHz, 1110\133 datasheet, (Order Number 241997), Pentium® Processor with MMXTechnology datasheet (Order Number 243185). Specification Changes incorporated into future versions appropriate document(s).
Limit Violation Causes Fault, Interrupt
last sentence Section Pentium® Processor Family Developer's Manual, Volume says about exception handling Real Mode: interrupt occurs entry interrupt table beyond limit stored IDTR register, double-fault exception generated." fact, Pentium processor, there difference between Real Protected Mode when limit violation occurs. generates interrupt General Protection Fault both modes.
Active Power Dissipation (typical) Change
These specifications Pentium processors active power dissipation (typical) apply ONLY mcC0 stepping (mobile specific) parts. previous, preliminary range giving typical power (3.8 Core 2.9V been reduced range (3.4 Parts with Core 3.1V specified have typical power range (3.8 Parameter Active Power (typical) Dissipation Previous Value (Watts) 2.9V Current Value (Watts) 3.1V 2.9V
Redundant Timing Specification: t42d Frequencies (50, MHz)
t42d minimum hold time required when BRDYC# used configuration signal when RESET driven synchronously with CLK. This timing specification redundant because subset hold time BRDYC# with respect CLK. Therefore, t42d will removed from future documentation.
Stop Clock Power
This specification condition maximum stop clock power dissipation mobile Pentium processor with technology. This will replace both original specification Mobile Pentium® Processor with MMXTechnology datasheet well S-Spec mobile stop clock power. Parameter Maximum Stop Clock Power Dissipation Previous Power Power
NOTES: Maximum stop clock power dissipation measured 50°C. maximum temperature 95°C, parts will typically draw 90mW.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Valid Delay
These specifications maximum valid delay Pentium processor with technology. This will replace both original specifications Pentium® Processor with MMXTechnology datasheet well Spec mobile valid delay A31. Symbol Parameter Frequency (mobile only) Previous Valid Delay Valid Delay
Valid Delay Data
These specifications maximum valid delay mobile Pentium processor with technology. This will replace both original specifications Mobile Pentium® Processor with MMXTechnology datasheet well Spec mobile valid delay D63. Symbol Parameter Frequency Previous Valid Delay Valid Delay
Maximum Stop-Grant/AutoHALT Power
These specifications maximum Stop-Grant Power/AutoHALT dissipation mobile Pentium processor with technology. These will replace original specifications Mobile Pentium® Processor with MMXTechnology datasheet. When Stop-Grant/AutoHALT Power Down mode, B-step mobile Pentium processor with technology power-savings feature which allows Power Down additional internal circuitry compared A-step. This enables even lower power dissipation while Stop-Grant/AutoHALT Power Down mode when this feature enabled. order enable this feature, TR12 must (the default disabled). Parameter Maximum Stop-Grant/AutoHALT Power Maximum Stop-Grant/AutoHALT Power Maximum Stop-Grant/AutoHALT Power Core/Bus Frequency 133/66 150/60 166/66 Previous Power 1.60 1.75 Power 0.86W 0.93W
NOTES: This corresponds default state which TR12.21 cleared. This corresponds state with TR12.21 set.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
This specification mobile Pentium processor with technology. This will replace original specification Mobile Pentium® Processor with MMXTechnology datasheet. Symbol Parameter Previous 0.8V 0.6V
Fraction
Frequency Selections Bus/Core Ratio Bus/Core Frequency (MHz) 66/200 66/166 66/133 66/233 Bus/Core Frequency (MHz) 33/100 33/83 33/66 33/116
NOTES: This default core ratio Pentium processor with MMXtechnology. pins left floating, processor will configured core frequency ratio.
233-MHz Specifications
Specifications (Measured Vcc2 =2.9V Vcc3 =3.6V)
Symbol ICC2 ICC3
Parameter Power Supply Current Power Supply Current
6500
Unit
Notes
NOTES: This value should used power supply design. determined using worst case instruction maximum Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from Stop Clock full Active modes.
Active Power
Power Dissipation Requirements Thermal Design (Measured Vcc2 =2.8V Vcc3 =3.3V Parameter Typical
17.0
Unit Watts
Notes
Active Power
NOTES: This typical power dissipation system. This value expected average value that will measured system using typical device 2.8V running typical applications. This
PENTIUM® PROCESSOR SPECIFICATION UPDATE
value highly dependent upon specific system configuration. Typical power specifications tested. Systems must designed thermally dissipate maximum active power dissipation. determined using worst case instruction with 2.8V also takes into account thermal time constants package. Active Power (typ) average power measured system using typical device running typical applications under normal operating conditions nominal room temperature. Active Power (max) maximum power dissipation under normal operating conditions nominal Vcc2, worst-case temperature, while executing worst case power instruction mix. Active power (max) equivalent Thermal Design Power (max).
133-MHz Current Power Specifications
These power specifications unannounced MHz-mobile Pentium processor with technology. These specifications will part Mobile Pentium® Processor with MMXTechnology datasheet. Specifications Symbol ICC2 ICC3 Parameter Power Supply Current Power Supply Current Unit Notes
NOTES: This value should used power supply design. determined using worst case instruction maximum Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from Stop Clock full Active modes. Power Dissipation Requirements Thermal Design Parameter Thermal Design Power Active Power Stop-Grant/AutoHALT Power Stop Clock Power Typical 0.02 0.86 0.05 Unit Watts Watts Watts Watts Notes
NOTES: This typical power dissipation system. This value expected average value that will measured system using typical device 2.45V Vcc3 3.3V running typical applications. This value highly dependent upon specific system configuration. Typical power specifications tested. Systems must designed thermally dissipate maximum active power dissipation. determined using worst-case instruction with 2.45V Vcc3 3.3V. nominal this measurement takes into account thermal time constant package. Stop-Grant/AutoHALT Power Down Power Dissipation determined asserting STPCLK# executing HALT instruction. achieve these, TR12.21 must set. Stop Clock Power Dissipation determined 50°C asserting STPCLK# then removing external input. maximum temperature 95°C, parts will typically draw
Active Power average power measured system using typical device running typical applications under normal operating conditions nominal room temperature.
(typ) refer Mobile Design Considerations application note.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Fraction
Fraction supported 133/66 mobile Pentium processor with technology. This will added Table Mobile Pentium® Processor with MMXTechnology datasheet. Mobile Frequency Selections Bus/Core Ratio Bus/Core Frequency (MHz) 66/133 Bus/Core Frequency (MHz) 33/66
NOTES: This default core ratio Pentium processor with MMXtechnology. pins left floating, processor will configured core frequency ratio.
Maximum Thermal Design Power
This power specification (B-Step) mobile Pentium processor with technology. Power Dissipation Requirements Thermal Design Parameter Thermal Design Power Thermal Design Power Typical
Unit Watts Watts
Notes A-Step B-Step
NOTES: This typical power dissipation system. This value expected average value that will measured system using typical device 2.45V Vcc3 3.3V running typical applications. This value highly dependent upon specific system configuration. Typical power specifications tested. Systems must designed thermally dissipate maximum active power dissipation. determined using worst-case instruction with 2.45V Vcc3 3.3V. nominal this measurement takes into account thermal time constant package. typical Thermal Design Power refer Mobile Design Considerations application note.
PCHK# State Output Current Mode
Pentium® Processor with MMXTechnology datasheet, Note page should modified. Specifically, PCHK# system should changed from note should read: dual processing systems, load from second processor observed PCHK# signal. Based silicon characterization data, VOL3 PCHK# will remain less than even with load. PCHK# VOL3 will increase approximately with load (worst case system with system load)."
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Absolute Maximum Rating VCC3
1997 Pentium® Processor Family Developer's Manual, Section 7.2, Table 7-1, states maximum VCC3 4.6V. This applies Pentium processor 75/90/100/120/133/150/166/200 only. maximum VCC3 Pentium processor with technology 4.0V.
120/60 VCC, ICC, Power, Specifications
These VCC, ICC, power dissipation, specifications 120/60 mobile Pentium processor with technology. other specifications identical 150/60 mobile Pentium processor with technology. Specifications Symbol VCC2 VCC3 Parameter Core Supply Voltage Supply Voltage Nominal 2.22 3.30 Specifications Symbol ICC2 ICC3 Parameter Power Supply Current Power Supply Current 2600 Unit ±0.120 ±0.165 Unit Volts Volts
Power Dissipation Requirements Thermal Design Parameter Thermal Design Power Active Power Stop-Grant/AutoHALT Power 0.67 Typical 5.70 Unit Watts Watts Watts
NOTES: Active power (typ) average power measured system using typical device running typical applications under normal operating conditions nominal room temperature. achieve this, TR12.21 must set. 3.3V Specifications Symbol VIL3* *TTL Level Specifications Symbol t10b Parameter D/C#, SCYC Valid Delay A3-A31 Valid Delay HITM# Valid Delay Unit Parameter Input Voltage Unit Volts
PENTIUM® PROCESSOR SPECIFICATION UPDATE
166- 266-MHz VCC2, ICC2 Power Specifications
These VCC2, power dissipation specifications 166- 266-MHz mobile Pentium processor with technology with 0.25 micron process. other specifications identical mobile Pentium processor with technology with 0.25 micron process.
Specifications Symbol VCC2 Parameter Core Supply Voltage 1.85 2.15 Tolerance ±0.150 Unit Notes
Specifications Symbol ICC2 ICC3 Parameter Power Supply Current Power Supply Current 2.35 4.00 0.38 Unit Notes
NOTES: This value should used power supply design. determined using worst case instruction maximum TCASE 0°C. Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes which occur during transition from Stop Clock full Active modes.
Power Dissipation Requirements Thermal Design Parameter Thermal Design Power Stop-Grant/AutoHALT Power Down power dissipation Stop Clock Power Typical 4.10 7.60 0.42 0.70 0.06 Unit Watts Watts Watts Watts Watts Notes
NOTES: Stop-Grant/AutoHALT Power Down power dissipation determined asserting STPCLK# executing HALT instruction. When this mode, processor feature which allows power down additional circuitry enable lower power dissipation. This power without snooping VCC2 with TR12 set. order enable this feature, TR12 must (the default disabled). Stop-Grant/AutoHALT Power Down power dissipation without TR12 higher. maximum rating changed future specification update.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Bus/Core (Speed) Ratio Pins Mobile Pentium Processor with MMXTechnology with 0.25 micron Process Bus/Core Ratio Reserved Reserved Reserved Bus/Core Frequency 66/166 66/200 66/133 66/233 66/266
NOTES: mobile Pentium® processor with MMXtechnology with 0.25 micron process uses BF0, pins determine bus-to-core frequency ratio. Each processor must externally configured with BF2-0 pins operate specific fraction mode. Operation specification supported. example, processor only supports fraction 2/5, 1/2, modes.
Mobile 200/66 0.35 micron VCC, ICC, TCASE Power Specifications
These VCC, power dissipation specifications mobile Pentium processor with technology. other specifications identical mobile Pentium processor with technology. Frequency Selection Bus/Core Ratio TCASE Specifications Package/Version PPGA TCASE 85°C Supply VCC2 VCC3 Voltage 2.285V 3.135V Specifications Symbol ICC3 ICC2 Parameter Power Supply Current Power Supply Current 0.56 Unit Notes Voltage 2.665V 3.465V Voltage Tolerance 2.45 +0.215/-0.165 3.3V Bus/Core Frequency (MHz) 66/200
NOTES: This value should used power supply design. determined using worst case instruction maximum TCASE 0°C. Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from Stop Clock full Active modes.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Power Dissipation Requirements Thermal Design Parameter Thermal Design Power Active Power StopGrant AutoHALT Power Down Power Dissipation Stop Clock Power Dissipation Typical 0.02 11.70 1.20 0.05 Unit Watts Watts Watts Watts Notes 200MHz
NOTES: This typical power dissipation system. This value expected average value that will measured system using typical device 2.45V running typical applications. This value highly dependent upon specific system configuration. Systems must designed thermally dissipate maximum thermal design power unless system uses thermal feedback limit maximum power. maximum thermal design power determined using worst case instruction with VCC2 2.45V also takes into account thermal time constants package. Stop-Grant/AutoHALT Power Down Power Dissipation determined asserting STPCLK# executing HALT instruction. Stop Clock Power Dissipation determined asserting STPCLK# then removing external input. This specified CASE 50°C. Active Power average power measured system using typical device running typical applications under normal operating conditions nominal room temperature. (typ), refer Mobile Design Considerations application note. Thermal design power referenced nominal supply voltage normal values shown (VCC2=2.45, VCC3=3.3V). System designers choose operate anywhere within allowable VCC2 range (2.285V 2.665V) long adequate decoupling used maintain voltage tolerance within this range. Common power supply voltages include: VCC2 2.45V+0.215V/-0.165V VCC3 3.3V ±5%. actual value will higher VCC2 nominal voltage increased above target value 2.45V. Likewise, actual value will decrease VCC2 lowered below target value 2.45V. example, VCC2 2.5V will increase TDP(typ)
Voltage 0.25 micron Process Technology (for only) VCC, ICC, TCASE Power Specifications
These VCC, power dissipation specifications voltage Pentium processor with technology 0.25 micron process technology. Frequency Selection Bus/Core Ratio TCASE Specification Package/Version TCASE 95°C Supply VCC2 VCC3 Voltage 1.665V 2.375V Voltage 1.935V 2.625V Voltage Tolerance 1.8V ±7.5% 2.5V Bus/Core Frequency (MHz) 66/266
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Specifications Symbol ICC2 ICC3 Parameter Power Supply Current Power Supply Current Units Notes
NOTES: This value should used power supply design. determined using worst case instruction maximum TCASE 0°C. Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from Stop Clock full Active modes. Power Dissipation Requirements Thermal Design Parameter Thermal Design Power Active Power Stop-Grant AutoHALT Power Down Power Dissipation Stop Clock Power Dissipation Typical 0.55 0.60 Units Watts Watts Watts Watts Notes (6,7)
NOTES: This typical power dissipation system. This value expected average value that will measured system using typical device 1.8V running typical applications. This value highly dependent upon specific system configuration. Systems must designed thermally dissipate maximum thermal design power unless system uses thermal feedback limit maximum power. maximum thermal design power determined using worst case instruction with 1.8V also takes into account thermal time constants package. Stop-Grant/AutoHALT Power Down Power Dissipation determined asserting STPCLK# executing HALT instruction. Stop Clock Power Dissipation determined asserting STPCLK# then removing external input. This specified CASE 50°C. Active Power average power measured system using typical device running typical applications under normal operating conditions nominal room temperature. (typ) refer Mobile Design Considerations application note. Thermal design power referenced nominal supply voltage normal values shown (VCC2 1.8V, VCC3 2.5V). System designers choose operate anywhere within allowable VCC2 range (1.75V 2.04V) long adequate decoupling used maintain voltage tolerance within this range. Common power supply voltages include VCC2 1.8V ±7.5% VCC3 2.5V ±5%. Actual value will higher VCC2 nominal voltage increased above target value 1.8V. Likewise, value will decrease VCC2 lowered below target value 1.8V.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Mobile Pentium® Processor with MMXTechnology 0.25 micron Process Specifications
Following specifications mobile Pentium processor with technology 0.25 micron process. other specifications remain same published Mobile Pentium® Processor with MMXTechnology 0.25 micron Process datasheet (Order Number 243468). Fraction Bus/Core Ratio Bus/Core Frequency (MHz) 66/300
NOTES: Each processor must externally configured with BF0-2 pins operate specified fraction mode. Operation this specification supported.
Absolute Maximum Ratings Symbol Parameter Storage Temperature Case Temperature Under Bias VCC3 VCC2 VIN3 2.5V Supply Voltage with respect 2.0V Supply Voltage with respect 2.5V Only Buffer Input Voltage -0.5 -0.5 -0.5 VCC3 +0.5 exceed VCC3 Unit
Following specifications: TCASE Specifications Package/ Version TCASE 95oC Supply VCC2 VCC3 1.850V 2.375V 2.150V 2.625V Voltage Tolerance 2.0V ±7.5% 2.5V
Specifications (See Table TCASE assumptions.) Symbol VIL3 VIH3 VOL3 VOH3 ICC3 ICC2 Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Power Supply Current Power Supply Current VCC3 -0.4 VCC3 -0.2 0.38 4.50 -0.3 VCC3 -0.7 VCC3+0.3 Unit Level Level Level Level Notes
PENTIUM® PROCESSOR SPECIFICATION UPDATE
NOTES: Parameter measured Parameter measured Parameter measured 100% tested. Guaranteed design. This value should used power supply design. determined using worst case instruction maximum TCASE 0oC. Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from Stop Clock full Active modes.
Following power dissipation requirements: Power Dissipation Requirements Thermal Design Parameter Thermal Design Power Active Power Stop-Grant/AutoHALT Power Down Power Dissipation Stop Clock Power Dissipation
Typical
0.75 0.06
Unit Watts Watts Watts Watts
Notes @300
NOTES: This typical power dissipation system. This value expected average value that will measured system using typical device 2.0V running typical applications. This value highly dependent upon specific system configuration. Systems must designed thermally dissipate maximum thermal design power unless system uses thermal feedback limit maximum power Pentium® processor with MMXtechnology 0.25µ process. maximum thermal design power determined using worst case instruction with 2.0V also takes into account thermal time constants package. Stop-Grant/AutoHALT Power Down power dissipation determined asserting STPCLK# executing HALT instruction. This power without snooping 2.0V with TR12 set. Stop-Grant/AutoHALT Power Down dissipation without TR12 higher. rating changed later revision this document. Stop Clock power dissipation determined asserting STPCLK# then removing external input. This specified CASE 50oC.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
S-SPECS
Refer Appendix 1997 Pentium® Processor Family Developer's Manual (Order Number 241428) Valid Delay Data
These Specs minimum valid delay mobile Pentium processor with technology. Symbol Parameter Frequency Normal Valid Delay S-Spec Valid Delay
PENTIUM® PROCESSOR SPECIFICATION UPDATE
ERRATA
Refer Appendix 1997 Pentium® Processor Family Developer's Manual (Order Number 241428) REVISED ERRATUM: STPCLK#, FLUSH# SMI# After
PROBLEM: specification says that external interrupts enabled next instruction after STI. However, external interrupts enabled before next instruction executed following STPCLK#, FLUSH# SMI# asserted serviced before instruction boundary this next instruction. IMPLICATION: External interrupts which assumed blocked until after instruction following recognized before this instruction executes. WORKAROUND: None identified this time. STATUS: steppings affected, Summary Table Changes beginning this section.
Refer Appendix 1997 Pentium® Processor Family Developer's Manual (Order Number 241428) Erroneous Debug Exception POPF/IRET Instructions with Fault
PROBLEM: erroneous debug exception occur execution POPF IRET instruction virtual 8086 mode, there data breakpoint address pointed SS:ESP, POPF IRET triggers general protection fault. This occurs virtual 8086 mode when IOPL causing POPF IRET trap fault without accessing stack. data breakpoint stack should triggered, fact incorrectly triggered soon fault handler entered. IMPLICATION: This results invalid debug exception where saved state (CS:EIP stack, case task-switch interrupt points first instruction Fault handler. This confuse debug monitor which expects find pointer instruction accessing stack. Note this erratum only occurs during debugging does affect normal execution. WORKAROUND: debug monitor could revised detect this erratum, only perform IRET
when this erratum detected cause entry into debugger.
STATUS: steppings affected Summary Table Changes beginning this section.
Content upon Return from
PROBLEM: Control registers should maintain values across breakpoints interrupts. contains page fault linear address. used protected mode control operations such virtual8086 support, enabling breakpoints, page size extension machine check exceptions. modified SMM, original contents prior entering restored when exiting SMM.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
IMPLICATION: either modified during execution handler, modified values will remain after resume from handler. values unexpected. WORKAROUND: handler needs modify CR4, handler should store values
upon entering handler restore values prior instruction.
STATUS: steppings affected, Summary Table Changes beginning this section.
Invalid Operand with Locked CMPXCHG8B Instruction
PROBLEM: CMPXCHG8B instruction compares byte value with byte value memory (the destination operand). only valid destination operands this instruction memory operands. destination operand register processor should generate invalid opcode exception, execution CMPXCHG8B instruction should halted processor should execute invalid opcode exception handler. This erratum occurs LOCK prefix used with CMPXCHG8B instruction with (invalid) register destination operand. this case, processor start execution invalid opcode exception handler because locked. This results system hang. IMPLICATION: (invalid) register destination operand used with CMPXCHG8B instruction LOCK prefix, system hang. memory data corrupted user perform system reset return normal operation. Note that specific invalid code sequence necessary this erratum occur normally generated course programming such sequence known Intel generated commercially available software. This erratum only applies Pentium processors, Pentium processors with technology, Pentium OverDrive® processors Pentium OverDrive processors with technology. Pentium processors, Pentium processors i486and earlier processors affected. WORKAROUND: There workarounds this erratum protected mode operating systems. Both workarounds generate page fault when invalid opcode exception occurs. both cases, page fault will serviced before invalid opcode exception thus prevent lock condition from occurring. implementation details will differ depending operating system. following: first part this workaround sets first entries (0-6) Interrupt Descriptor Table (IDT) non-writeable page. When invalid opcode exception (exception occurs locked CMPXCHG8B instruction with invalid register destination (and only then), processor will generate page fault does have write access page containing entry IDT. second part this workaround modifies page fault handler recognize correctly dispatch invalid opcode exceptions that routed through page fault handler. Part Page Access: Mark page containing first seven entries (0-6) read only setting page table entry zero. Also CR0.WP (bit when invalid opcode exception occurs locked CMPXCHG8B instruction, processor will check write access lock prefix trigger page fault since does have write access page containing entry IDT. This page fault prevents lock condition gives complete control process invalid operand exception appropriate. Note that exception invalid opcode exception, with this scheme complete control program executing invalid CMPXCHG8B instruction. Optional: updates entries 7-255 occur during course normal operation, page faults should avoided writes these entries. These page faults avoided aligning across page boundary such that first seven entries (0-6) first read only page remaining entries read/writeable page.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Page Fault Handler Modifications: Modify page fault handler calculate which exception caused page fault using fault address CR2. error code stack indicates exception occurred from ring address corresponds invalid opcode exception, then error code stack jump invalid opcode exception handler. Otherwise continue with normal page fault handler. This workaround parts. First, Interrupt Descriptor Table (IDT) aligned such that invalid opcode exception will cause page fault (due page being present). Second, page fault handler modified recognize correctly dispatch invalid opcode exception certain other exceptions that routed through page fault handler. Part Alignment: Align Interrupt Descriptor Table (IDT) such that spans page boundary placing first entry starting bytes from first page. This places first seven entries (0-6) first page, remaining entries second page. page containing first seven entries must have mapping page tables. This will cause exceptions generate page present fault. page fault prevents lock condition gives complete control process these exceptions appropriate. Note that exception invalid opcode exception, with this scheme complete control program executing invalid CMPXCHG8B instruction. Part Page Fault Handler Modifications: Recognize accesses first page testing fault address CR2. Page present faults other addresses processed normally. page present faults first page IDT, must recognize dispatch exception which caused page present fault. Before proceeding, test fault address determine address range corresponding exceptions 0-6. Calculate which exception caused page present fault from fault address CR2. Depending operating system, certain privilege level checks adjustments interrupt stack required before jumping normal exception handler Step below. operating system vendor, please contact your local Intel representative more information. Jump normal handler appropriate exception. Both workarounds should only implemented Intel processors that return Family=5 CPUID instruction.
Event Monitor Counting Discrepancy
PROBLEM: Pentium processor contains registers which count occurrence specific events
used measure monitor various parameters that contribute performance processor. There condition where counter does operate specified: "Stall write state line" (event 011011) event counts number clocks processor stalled memory write state line, while write buffers empty, EWBE# negated. order event 011011 accurately count stalled clocks cycles, must ignore other stall cases, such TLB-miss. However, data resides Kbyte physical address space, some stalls TLB-miss were also counted.
IMPLICATION: event monitor counters report inaccurate count event 011011.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
WORKAROUND: Avoid mapping Kbytes address space, physical page `0xFFFFF. STATUS: steppings affected Summary Table Changes beginning this section.
FBSTP Instruction Incorrectly Sets Accessed Dirty Bits Page Table Entry
PROBLEM: This erratum occurs only program does following:
Paging enabled. program uses 16-bit addressing inside USE32 segment (requiring addressing override prefix) order wrap addresses offsets above back bottom segment. 10-byte operand written memory FBSTP instruction must actually straddle boundary. bytes either above below 64K, wrap works normally. result that Accessed Dirty bits Page Table entry sometimes incorrectly FBSTP instruction case 16-bit address wraparound (Prefix 67H) within 32-bit code segment. FBSTP does wraparound, attributes next sequential Page Table entry also page accessed written
IMPLICATION: incorrectly Accessed cause non-used page kept memory. incorrectly Dirty cause unnecessary disk write-back cycles. WORKAROUND: None.
16DP. Refer Appendix Pentium® Processor Family Developer's Manual (Order Number 241428) 17DP. Asserting FLUSH# Cause Processor Deadlock System with Fraction
PROBLEM: Dual Processing (DP) system, when FLUSH# asserted system, ownership
first transferred from primary secondary processor. With ownership bus, secondary processor starts flush cache. Upon completion flush, secondary processor then returns ownership primary processor. Next, secondary processor will into waiting loop until primary processor finishes flushing cache generates flush acknowledge special cycle. Finally, upon sampling flush acknowledge special cycle from primary processor, secondary processor exits waiting loop both processors return normal mode. However, FLUSH# function correctly internal cycle alignment issue mode when operating with fraction. this erratum, secondary processor fails wait primary processor release bus, initiates request before primary processor finishes flushing cache. this case, primary processor does have access therefore cannot finish flushing cache cannot generate flush acknowledgment special cycle; same time, secondary processor cannot resume operation until primary processor issues flush acknowledgement special cycle.
IMPLICATION: system which operates fraction, usage FLUSH# cause primary
secondary processors dead-lock situation.
WORKAROUND: While using processors fractions mode, FLUSH#.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
19AP. Refer Appendix Pentium® Processor Family Developer's Manual (Order Number 241428) 1TCP 2TCP. Refer Appendix Pentium® Processor Family Developer's Manual (Order Number 241428)
PENTIUM® PROCESSOR SPECIFICATION UPDATE
SPECIFICATION CLARIFICATIONS
Pentium® Processor's Response Startup Init IPIs
Pentium processor when used dual processor upgrade component, will require STARTUP wake this part after following situations: After assertion RESET. After assertion INIT. (The assertion INIT could come from toggling INIT though APIC IPI.) either case, dual processor upgrade component will jump RESET Vector, will instead into halt state. INIT then sent halted upgrade component, will latched kept pending until STARTUP received. From time STARTUP received will respond further INIT IPIs will ignore STARTUP IPIs. will respond future STARTUP IPIs until RESET assertion INIT assertion (INIT INIT IPI) happens again. Pentium processor when used primary processor, will never respond STARTUP time. will ignore STARTUP with effects. shutdown processors operating system should only INIT IPI, STARTUP IPIs should never used once processors running. following pseudo-code shows generic algorithm waking Pentium processors, including 82489DX based systems, dual processor systems multi-processor systems. algorithm will work with future processors too. sends INIT DELAYs (10mSec) (APIC VERSION 82489DX) sends STARTUP DELAYs (200uSec) sends STARTUP DELAYs (200uSec) verifies synchronization with executing additional information please refer Intel Multiprocessor Specification, Version (Order Number 242016).
APIC Timer Clarification
APIC Timer functions correctly, there timer "tick" that different pulse width than other timer "ticks". countdown performs correctly regardless divisor that programmed, each these ticks same pulse width, last tick held just single timer clock regardless divisor programmed. This results slightly inaccurate timer. This last tick pulse width shown diagram. lower diagram shows accuracy timer will corrected future stepping. This phenomenon occurs when timer used single shot generator well.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
NOTE clock which loaded from occurs clock after loaded.
Clock TimeBase Clock
Start
Interrupt Occurs Here
Interrupt Occurs Here
Clock TimeBase Clock
Start
Interrupt Occurs Here
Interrupt Occurs Here
PICCLK Reflection Cause APIC Checksum Errors Dropped IPIs
Many APIC errors that listed erratum concern checksum errors APIC bus. This specification clarification address elimination checksum errors APIC bus. Doing would reduce error rate would eliminate possibility dropping Interprocessor Interrupts (IPI) multiple data errors same APIC message. Getting single checksum error does typically pose problem, because error will cause APIC message will resent, there high error rate then there possibility that retries APIC messages take bandwidth APIC some rescheduled accidentally dropped. system that performs this manner fundamental design problem that needs corrected. Most checksum errors observed result PICCLK crossing threshold cleanly, this tracked down possible issues: PICCLK marginally meeting rise/fall time specification, reflections causing PICCLK re-cross threshold. Both problems fairly easily solved, robust system design will typically show zero checksum errors hour period during stress testing.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
current specification rise/fall time PICCLK signal shown timing tables t60f frequencies. This rise/fall time must guarantee correct operation device. This rise/fall time should verified receivers PICCLK signal. daisy chain type route used with large series termination resistor rise/fall time devices near driver most critical should checked. high time specifications also need verified meet specification. There also good chance that system using daisy chain route topologies that there will reflections seen receivers located close driver. would recommended balanced star type route clock signals like PICCLK ensure there reflections that re-cross trip thresholds inputs CPU. correct balanced route based both length traces relative input capacitance loading presented each device. also important verify selection correct series terminating resistors dampen reflections this line. values series resistances should chosen using following guidelines: Single Receiver: Driver receiver opposite ends trace. R_driver R_terminator Multiple Receivers: Trace branch receiver, branches equal equivalent capacitive loads. Branch close possible Driver. single termination resistor branches): Place terminator close driver possible. R_driver R_terminator multiple termination resistors branches): Place terminators each branch, close branch point possible. R_driver R_terminator Even though PICCLK lower frequency clock this clock still critical should routed with care reflections each node should eliminated. More detailed clock routing techniques available AP479 PentiumProcessor Clock Design application note (Order Number 241574).
Boundary Scan RUNBIST Register Requires Initialization Prior
been found that Reset cell Boundary Scan register correctly initialized prior use. There failing result reported from running RUNBIST Command through Boundary Scan circuitry. IEEE 1149.1-1990 specification states, "Where test data register (other than Boundary Scan register) must initialized prior execution self-test this must occur start self-test without requirement shift data into component." execute RUNBIST instruction: Select "Sample/Preload" instruction (XXXXXXXXX0001) load RESET BSCAN cell (cell #52) with `0'. Shift "Runbist" instruction move wait "run-test-idle" state clocks. Examine pass/fail status advancing "shift-dr" state read runbist register.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Only SMI# Latched During
Section 20.1.4.2 Volume Pentium® Processor Family Developer's Manual correctly states that only SMI# latched while (end second paragraph). However, Section 5.1.50 Volume manual SMI# definition incorrectly implies plural that more than SMI# request held pending during SMM. Thus following changes will implemented next revision Manual: Section 20.1.4.2 Volume next last sentence second paragraph, will have underlined phrase added: "The first SMI# interrupt request that occurs while processor (i.e. after SMIACT# been asserted) latched, serviced when processor exits with instruction. Section 5.1.50 Volume second paragraph Signal Description, that refers SMI# requests held pending during SMM, will replaced with entire second paragraph Section 20.1.4.2 Volume
APIC 8-Bit Access
following should added Pentium® Processor Family Developer's Manual, Volume Section 19.3.1.4. APIC supports sized, aligned, read write cycles registers. Therefore, APIC registers should accessed using 32-bit loads stores. 32-bit APIC register accessed with write cycle result unpredictable. This implies that modify field, entire 32-bit register should read, field modified, entire bits written back.
LOCK Prefix Excludes APIC Memory Space
Pentium® Processor Family Developer's Manual, Volume page 25-216, LOCK prefix described. line should added description follows: LOCK prefix effect instructions that address APIC memory space. Therefore, LOCK# asserted.
SMI# Activation Cause Nested Handling
Pentium® Processor Family Developer's Manual, Volume Section 20.1.4.4, following note should added just before last paragraph. During interrupt handling interrupts disabled. interrupts serviced completed with IRET time. When processor enters from interrupt handler, processor saves SMRAM State Save (e.g. contents status registers) does save attribute keep interrupts disabled. Potentially could latched (while upon exit) serviced upon exit even though previous handler still completed. more NMI's could nested first handler. interrupt handler should take this into consideration.
Code Breakpoints Meaningless Prefixes Guaranteed Recognized
following should added Pentium® Processor Family Developer's Manual, Volume Section 17.3.1.1 (Instruction-Breakpoint Fault). Code breakpoints meaningless instruction prefixes prefix which logical meaning that instruction, e.g. segment override prefix instruction that does access memory) guaranteed recognized.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Code breakpoints should instruction opcode, meaningless prefix. Pentium® Processor Family Developer's Manual, Volume Sections (Instruction Format) 25.2 (Instruction Format), after "For each instruction prefix used from each group. effect redundant prefixes (more than prefix from group) undefined vary from processor processor." following should added: Some prefixes when attached specific instructions have logical meaning (e.g. segment override prefix instruction that does access memory). effect attaching meaningless prefixes instructions undefined vary from processor processor.
Resume Flag Should Software
lead-in sentences first bullet Section 14.3.3 Pentium® Processor Family Developer's Manual, Volume should replaced with following: (Resume Flag) EFLAGS register should used during debugging avoid servicing instruction breakpoint fault multiple times. works follows: debug handler (interrupt should EFLAGS image stack whenever servicing instruction breakpoint fault (rather than data breakpoint trap), breakpoint being left place. this done, will return execute instruction, fault breakpoint again interrupt
following should added fifth sixth bullets: fault type breakpoint coincides with another fault (the instruction accesses present page, violates general protection rule, etc.) spurious repetition breakpoint will occur after second fault handled, even though debug handler sets optional debugging convenience, avoid this occasional confusion, interrupt handlers that could interact during debugging this modified having them also EFLAGS image their stack. CPU, branching fault handlers under some circumstances, will EFLAGS image stack hardware action. Exactly when does this implementation specific should relied upon software. problem caused setting this again already set.
Data Breakpoints Delayed Iteration
Pentium® Processor Family Developer's Manual, Volume last paragraph sentence Section 17.3.1.2 states, "Repeated OUTS instructions generate memory breakpoint debug exception trap after iteration which memory address breakpoint location accessed." sentence should read, "Repeated OUTS instructions generate memory breakpoint debug exception trap after iteration which memory address breakpoint location accessed. Repeated instructions generate memory breakpoint debug exception trap iteration later".
When Cache Disabled, Inquire Cycles Blocked
last line Table 18-2 Pentium® Processor Family Developer's Manual, Volume presently reads "Invalidation inhibited". This part description cache behavior when "disabled" setting bits This line will clarified read "Inquire cycles (triggered EADS# active) resulting invalidation APCHK# assertions inhibited."
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Serializing Operation Required When Modifies Another CPU's Code
subsection, 19.2.1, will added Pentium® Processor Family Developer's Manual, Volume titled Processor Modifying Another Processor's Code, will referenced current subsection 18.2.3 self modifying code. particular problem memory access ordering occurs multiprocessing system processor (CPU1) modifies code another (CPU2). This obviously requires semaphore check CPU2 before executing area being modified, assure that CPU1 finished with changes before CPU2 begins executing changed code. addition, necessary CPU2 execute serializing operation after semaphore allows access before modified code executed. This needed because external snoops into CPU2 caused code modification CPU1 will invalidate matching lines CPU2's code cache, prefetch buffers execution pipeline. Note that this different from situation described Section 18.2.3 self-modifying code. When modifies code, prefetch buffers pipeline well code cache checked invalidated necessary.
Correct Translations, Should Flushed After
Memory mapping tables changed setting page size extension (bit However flushed after CR4.PSE set, provide erroneous Kbyte page translation rather than Mbyte page translation, other around. Therefore correct translations, should flushed writing after CR4.PSE set.
This will added Pentium® Processor Family Developer's Manual, Volume Sections 10.1.3
11.3.5.
When APIC Enabled, Block Should Used Regular Memory
When local APIC enabled, uses Kbyte memory mapped address block starting 0FEE00000H control status registers. Obviously can't block 0FEE00000H regular memory data, because reads writes would always APIC registers instead. obviously, code placed this location memory usually fetched correctly, because unit normally distinguishes code fetches from APIC reads puts code fetches external bus. Nonetheless, this block should used code either, because case when code fetch backed off, unit directs recovered code fetch cycle APIC, resulting interrupt unpredictable execution. following NOTE will added last text Section 19.3.1.4 Pentium® Processor Family Developer's Manual, Volume "When APIC enabled, page regular memory that overlays block assigned APIC should used, either code data."
Extra Code Break Occur Instruction Coincides
code breakpoint instruction, usual breakpoint will taken before instruction executed. instruction also used part restart protocol, restart enabled, executing instruction triggers SMI, from handler will return start instruction, code breakpoint will taken again before instruction executed second time.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Similarly, code breakpoint instruction, breakpoint will taken before processor enters state. occurs during this state, handler chooses instruction (the usual choice, transparent), code breakpoint will taken again before state re-entered. this case, other problems occur, because internal flag remains incorrectly. These problems documented Erratum case This information will added Section 17.3.1.1, "Instruction-Breakpoint Faults," Pentium® Processor Family Developer's Manual, Volume
Updated Non-cacheable Cycles
following will added Pentium® Processor Family Developer's Manual, Volume page 18-7: Memory reads update bits Pentium processor with technology even cycle non-cacheable. replacement mechanism implementation specific vary between processors.
FYL2XP1 Does Generate Exceptions Range
FYL2XP1 instruction intended used only taking numbers very close one, provide improved accuracy. values outside FYL2XP1 instruction's valid range, FYL2X instruction should used instead. present documentation what happens when outside FYL2XP1 instruction's valid range inconsistent. FYL2XP1, range behavior will replaced operand outside acceptable range, result undefined, software should rely exception being generated. Under some circumstances exceptions generated when range, this behavior implementation specific guaranteed." information pages 7-15 25-161 Pentium® Processor Family Developer's Manual, Volume will clarified.
Enabling Inside
Page 20-11 Pentium® Processor Family Developer's Manual Volume states "Although requests blocked when enters SMM, they enabled through software invoking dummy interrupt vectoring Interrupt Service Routine." This will changed "Although requests blocked when enters SMM, they enabled first enabling interrupts through INTR setting flag, then triggering INTR. Also, Pentium processor, exceptions that invoke trap fault handler will enable inside SMM. This behavior exceptions enabling within part Intel Architecture, implementation specific".
BF[1:0] Must Change Values While RESET Active
Table page 2-49 Pentium® Processor Family Developer's Manual states that BF[1:0] must change values while RESET active. Page 5-18 Pentium® Processor Family Developer's Manual also states that BF[1:0] must meet setup time falling edge RESET. Since RESET active least 1ms, setup time spec subset specification Table will removed. t43a (BF[1:0] setup time falling edge RESET) will also removed from Tables 7-8, 7-10, 7-12 page 2-49. following will also added "When Sampled/Driven" section page 5-18: Additionally, BF[1:0] must change values while RESET active.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
following will added first paragraph page 5-17 note page 7-27: order override internal defaults guarantee that BF[1:0] inputs remain stable while RESET active, these pins should strapped directly through pullup/pulldown resistor ground. Driving these pins with active logic recommended unless stability during RESET guaranteed. pages 5-80, sentence starting with "During power RESET must asserted while VCC." will modified follows: During power RESET should asserted prior ramped simultaneously with core voltage supply processor.
Active A20M# During
Section 14.3.3. 1997 Pentium® Processor Family Developer's Manual describes considerations when using A20M# input when SMRAM relocated above Megabyte. system designer must ensure that A20M# de-asserted entry into SMM. A20M# must driven inactive before first cycle state save, must returned original level after last cycle state restore. This done blocking assertion A20M# whenever SMIACT# active. following will added Section 14.3.3: addition blocking assertion A20M# whenever SMIACT# active, system must also guarantee that A20M# de-asserted least clock prior assertion SMIACT#. processor start state save soon SMIACT# asserted. Processors faster than have enough time recognize de-assertion A20M# before starting state save. result, this cause processor start first cycles state save with A20M# asserted. avoid this, system designer either following: When relocating SMRAM above Megabyte, ensure that SMRAM does coincide with megabyte addresses. (Note that systems which A20M# relocate SMRAM above Megabyte affected.) external logic prevent assertion processor until A20M# de-asserted (and guarantee that A20M# remains de-asserted while SMM). Note that A20M# input must also meet setup hold times order recognized specific clock.
POP[ESP] with 16-bit Stack Size
Pentium® Family Developer's Manual, Volume Programmer's Reference Manual Intel Architecture Software Developer's Manual, Volume Instruction Reference section regarding "POP-Pop Value from Stack", following note incomplete: register used base register addressing destination operand memory, instruction computes effective address operand after increments register. should read follows: register used base register addressing destination operand memory, instruction computes effective address operand after increments register. case 16-bit stack where wraps result instruction, resulting location memory write processor family specific."
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Section 15.12.1. Pentium® Family Developer's Manual, Volume Operating System Writer's Guide Section 17.23.1. Intel Architecture Software Developer's Manual, Volume System Programming Guide, section: POP-to-memory instruction, which uses stack pointer (ESP) base register. POP-to-memory instruction that meets following conditions:
stack segment size 16-bit, 32-bit addressing form with byte specifying base register, initial stack pointer FFFCh(32-bit operand) FFFEh (16-bit operand) will wrap around
result operation, result memory write processor family specific. example, Pentium Pentium processors, result memory write SS:0h plus scaled index displacement. Pentium Intel486 processors, result memory write either stack fault (real mode protected mode with stack segment size Kbytes), write SS:10000h plus scaled index displacement (protected mode stack segment size exceeds Kbytes).
#190 (TCP Package) Connection
Design Consideration mobile Pentium processor with technology 0.25 micron process only: (VCC2) #190 (VCC2) mobile Pentium processor with technology 0.25 micron process connected either VCC2 VCC3. When connected VCC2, there minor increase leakage current #190. avoid incremental leakage current, recommended connect these pins CC3. addition, future power offerings mobile Pentium processors with technology, #190 should tied VCC3 allow maximum margin spec.
Line Fill Order Optimization Revision
Section 3.5.3 Intel Architecture Optimization Manual following passage incomplete: "For Pentium processors with technology, Pentium Pentium processors, data available order that arrives from memory. array data being read serially, preferable access sequential order that each data item will used arrives from memory. Pentium processors, first 8-byte section available immediately, rest cache line available until entire line read from memory." Instead, should read follows: "For Pentium processors with technology, Pentium Pentium processors, data available order that arrives from memory. these processors, array data being read serially, preferable access sequential order that each data item will used arrives from memory. Pentium processors, first 8-byte section available immediately after arrives from memory, rest cache line available until entire line read from memory. array data being read serially, often preferable pre-fetch portions array mapping other cache lines. first 8-byte section other cache line will available immediately after arrives from memory. This technique used effectively hide latency associated with accessing last three 8-byte sections cache line."
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Test Parity Check Mechanism Clarification
Pentium® Processor Family Developer's Manual, Section 16.2.1.4 Test Parity Check, sentence, "For microcode, parity forced read setting PRR.MC incorrect. correct wording should follows: "For microcode, parity forced read transition PRR.MC from parity will forced setting PRR.MC already
PENTIUM® PROCESSOR SPECIFICATION UPDATE
DOCUMENTATION CHANGES
Documentation Changes listed this section apply Pentium® Processor Family Developer's Manual, Volumes Documentation Changes will incorporated into future version appropriate Pentium processor documentation.
Cannot Nested Task Switch, Volume Page 13-12
Pentium® Processor Family Developer's Manual, Volume Section 13.6, sentence "When interrupt, exception, jump, call causes task switch. incorrectly includes jump list actions that cause nested task switch. word "jump" will removed from sentence. Table 13-2 correctly shows effects task switches jumps Task switches CALL's interrupts, flag Link field TSS.
Incorrect Pinout Drawing
pinout drawing page Pentium Processor with Voltage Reduction Technology datasheet inadvertently rotated. correct orientation shown below.
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Interrupt Sampling Window, Volume Page 23-39
Pentium® Processor Family Developer's Manual, Volume Section 23.3.7 first sentence second paragraph "The Pentium processor. asserts FERR# pin." Should replaced with following: Pentium processor Intel486 processor implement "No-Wait" Floating-Point instructions (See Section 6.3.7) DOS-Compatibility mode (CR0.NE following manner: event pending unmasked numeric exception, "No-Wait" class instructions asserts FERR# pin.
FSETPM Like NOP, Like FNOP
Pentium® Processor Family Developer's Manual, Volume page 23-37 Section 23.3.4 Instructions, 80287 instruction FSETPM described being equivalent FNOP when executed Intel387 math coprocessor Intel486 Pentium processors. fact, FSETPM treated these processors, correctly explained (along with difference between FNOP NOP) next page Section 23.3.6. "FNOP" will changed "NOP" FSETPM description.
Errors Three Tables Special Descriptor Types
Pentium® Processor Family Developer's Manual, Volume page 25-199 page 25-222, descriptions instructions respectively, tables given special segment gate descriptor types names, with indication which ones valid with given instruction. same pairs descriptor types interchanged these tables. Descriptor type 16-bit interrupt gate, trap gate, type 16-bit trap gate, interrupt gate. Similarly, descriptor type 32-bit interrupt gate, 32-bit trap gate. Table 12-1 gives completely correct listing special descriptor types, same chapter, Table 12-3 (page 12-22) incorrectly indicates that 16-bit gates valid instruction (this table does have correct types interrupt trap gates that shows).
iCOMP® Index Rating Correction
Pentium processor with technology iCOMP index Rating 182. table page Pentium® Processor Family Developer's Manual lists iCOMP Index Rating Pentium processor with technology incorrect 183.
Default Setting BF1-0 Pentium® Processor with MMXTechnology
Pentium® Processor Family Developer's Manual, Section 5.1.10 page 5-18, sentence" BF[1:0] left unconnected Pentium processor with technology, bus-to-core ratio defaults 2/5." should BF[1:0] left unconnected Pentium processor with technology, bus-to-core ratio defaults 1/2".
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Exceptions Cause Branch Trace Messages
Pentium® Processor Family Developer's Manual, Section 13.1.0 page 13-2, sentence "Masked floating point exceptions other exceptions that invoke trap fault handler" should changed "certain Floating point exceptions (both masked un-masked) other exceptions that invoke trap fault handler".
Fraction
Section Mobile Pentium® Processor with MMXTechnology datasheet, Table "Bus Frequency Selections," incorrectly states Fraction. Table amended follows: Mobile Frequency Selections Bus/Core Ratio Bus/Core Frequency (MHz) Bus/Core Frequency (MHz)
NOTES: This ratio currently supported mobile Pentium processor products.
Size Reduction
B-Step size been reduced following dimensions:
Length 12.238 Width 10.579
PICD0-1 External Capacitance Requirement
1997 Pentium® Processor Family Developer's Manual, Section 7.4.3, Table 7-13, Note states, "This assumes external pullup resistor lumped capacitive load. pullup resistor must between ohms ohms, capacitance must between product must between PICD0-1 0.55 This should replaced with following: "This assumes external pullup resistor lumped capacitive load. pullup resistor must between ohms ohms, capacitance must between product must between PICD0-1 0.55
PENTIUM® PROCESSOR SPECIFICATION UPDATE
Invalid Arithmetic Operations Masked Responses Them Relative FIST/FISTP Instruction
Pentium® Family Developer's Manual, Volume Programmer's Reference Manual, Table 7-20 Intel Architecture Software Developer's Manual, Volume Table 7-20 show "Invalid Arithmetic Operations Masked Responses Them." table entry corresponding FIST/FISTP condition missing, shown below: Condition FIST/FISTP instruction when input operand MAXINT destination operand size. Masked Response Return MAXNEG destination operand.
Incorrect Sequence Registers Stored PUSHA/PUSHAD
Intel Architecture Software Developer's Manual, Volume section PUSHA/PUSHAD-Push General Purpose Registers, sentence, "The registers stored stack following order: EAX, ECX, EDX, EBX, EBP, (original value), EBP, current operand-size attribute 32). incorrectly states sequence registers stored stack. sentence should state, "The registers stored stack following order: EAX, ECX, EDX, EBX, (original value), EBP, current operand-size attribute 32).".
One-Byte Opcode Correction
Intel Architecture Software Developer's Manual, Volume there corrections that need made Opcode Map: Appendix Opcode Map, Table A-1, Column only indicated. should indicate both CWDE. Appendix Opcode Map, Table A-1, Column operand defined "aP". should defined "Ap". Operand "Ap" selects pointer, 32-/48-bits size without specifying byte.
Boundary Scan Chain Order Revision
Pentium® Processor Family Developer's Manual, Section 11.3.2, order Pentium processor with technology Boundary Scan Register (left right, bottom): Reserved, Reserved, Reserved, STPCLK#, Reserved, PICD0, PICD1, Disapsba* reversed. correct order follows (left right, bottom): Disapsba*, PCD1, PICD0, Reserved, Reserved, STPCLK#, Reserved, Reserved
Part
Specification Update Pentium® OverDrive® Processors
PENTIUM® PROCESSOR SPECIFICATION UPDATE
GENERAL INFORMATION
This section covers various Pentium OverDrive processors. 83-MHz Pentium OverDrive processors Pentium processor technology upgrades Intel486 processor-based systems. more information 83-MHz Pentium OverDrive processors, please refer Intel Pentium® OverDrive® Processor datasheet (Order Number 290544). 120/133-MHz Pentium OverDrive processor Pentium processor technology upgrade 60/66-MHz Pentium processor-based systems. 125-, 150- 166-MHz Pentium OverDrive processors Pentium processor technology upgrades 75-, 100-MHz Pentium processor-based systems. more information Pentium OverDrive processors Pentium processor based systems, please refer Pentium® OverDrive® Processors Pentium Processor-Based Systems datasheet, (Order Number 290579). 125/150/166/180- 200-MHz Pentium OverDrive processors with technology upgrades 75-, 100-MHz Pentium processor-based systems. addition normal increased performance from running faster than original Pentium processor system, these OverDrive processors enable endusers experience benefits technology.
Markings
Pentium OverDrive processor identified number base heat sink, under integrated fan. remove fan, squeeze retaining clips upper left corner chip lift figure below shows laser mark found heatsink base processor. marking also used indicate speed part located upper right package.
Speed Marking
Speed Marking
PODP CCCCC FFFFFFFF DDDD SZZZZ VW.W INTEL '92'94
PODP CCCCC FFFFFFFF DDDD SZZZZ VW.W INTEL '92'93
83-MHz Pentium® OverDrive® Processors Intel486Processor-based Sy
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