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Intel Processor Identification CPUID Instruction
Order Number: 241618-018
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel's Intel Architecture processors (e.g., Pentium® processor, Pentium® processor with MMXtechnology, Pentium® processor, Pentium® processor, Pentium® Xeonprocessor, Pentium® processor, Pentium® Xeonprocessor, Pentium® processor, Intel® Celeronprocessor, Intel® Xeonprocessor) contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained from: Intel Corporation P.O. 7641 Prospect 60056-7641 call 1-800-879-4683 visit Intel's website http://www.intel.com/ Copyright Intel Corporation 1993-2001. Third-party brands names property their respective owners.
AP-485 CONTENTS
PAGE INTRODUCTION. Update Support DETECTING CPUID INSTRUCTION OUTPUT CPUID INSTRUCTION Vendor String. Processor Signature Feature Flags SYSENTER/SYSEXIT Features Cache Size, Format Information Pentium® Processor, Model Output Example PROCESSOR SERIAL NUMBER. Presence Processor Serial Number Forming 96-bit Processor Serial Number BRAND BRAND STRING. USAGE GUIDELINES. PROPER IDENTIFICATION SEQUENCE USAGE PROGRAM EXAMPLES
ALTERNATE METHOD DETECTING FEATURES DENORMALS ZERO. OPERATING FREQUENCY.
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REVISION HISTORY Revision
-001 -002 -003 Original Issue. Modified Table Intel486and Pentium® Processor Signatures. Updated accommodate processor versions. Program examples modified ease use, section added discussing BIOS recognition OverDrive® processors feature flag information updated. Updated with Pentium OverDrive processors information. Modified Tables1, Inserted Tables Inserted Sections 3.4. 3.5. Added Figures Added Footnotes Modified Figure Added Assembly code example Section Modified Tables Added bullets Section 5.0. Modified cpuid3b.ASM cpuid3b.C programs determine processor features MMXtechnology. Modified Figure 6.0.
Revision History
Date
05/93 10/93 09/94
-004
12/95
-005
11/96
-006
Modified Table Added reserved future member family 3/97 processors entry. Modified table header reflect Pentium processor family. Modified Table Added definition. Added Section 3.5. Added Section Table Corrected references family reflect correct usage. Modified cpuid3a.asm, cpuid3b.asm cpuid3.c example code sections check feature check for, identify, Pentium processor. Added additional disclaimer related designers errata. Modified Table Added Pentium processor, model entry. Modified existing Pentium processor entry read "Pentium processor, model Modified Table Added additional feature bits, FXSR. Modified Table Added entries 45h. Removed note assume value feature flag indicates that given feature present. future feature flags, value indicate that specific feature present" section 4.0. Modified cpuid3b.asm cpuid3.c example code section check for, identify, Pentium processor, model Modified existing Pentium processor code print Pentium processor, model Added note identify Intel Celeronprocessor, model section 3.2. Modified Table Added Intel Celeron processor Pentium® OverDrive® processor with MMXtechnology entry. Modified Table Added additional feature bit, PSE-36. Modified cpuid3b.asm cpuid3.c example code check for, identify, Intel Celeron processor. Added note identify Pentium Xeonprocessor section 3.2. Modified Table Added Pentium Xeon processor entry. Modified cpuid3b.asm cpuid3.c example code check for, identify, Pentium Xeon processor. Changes Modified Table Added Intel Celeron processor, model entry. Modified cpuid3b.asm cpuid3.c example code check for, identify, Intel Celeron processor, model 12/98 1/98
4/98
-009
6/98
-010 -011
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REVISION HISTORY Revision
-012
Revision History
Modified Figure reserved information Intel386 processors. Modified Figure Added Processor serial number information returned when CPUID instruction executed with EAX=3. Modified Table Added Processor serial number parameter. Modified Table Added Pentium processor Pentium Xeon processor. Added Section "Processor serial number". Modified cpuid3a.asm, cpuid3b.asm cpuid3.c example code check identify Pentium processor Pentium Xeon processor. Modified Figure Added Brand information returned when CPUID instruction executed with EAX=1. Added section "Brand ID". Added Table that shows defined Brand values. Modified cpuid3a.asm, cpuid3b.asm cpuid3.c example code check identify Pentium processor, model Pentium Xeon processor, model Modified Table Added Intel Celeron processor, model Modified Table Added Pentium Xeon processor, model Modified Table Added 8-way associative 8way associative cache descriptor entries. Revised Figure include Extended Family Extended Model when CPUID executed with EAX=1. Added section which describes Brand String. Added section Alternate Method Detecting Features sample code Example Added Pentium processor signature Table Added feature flags (SSE2, Table Added cache descriptors Table Removed Pentium cache descriptor example. Modified Figure include additional features reported Pentium processors. Modified Table include additional Cache descriptors defined Intel® NetBurstMicro-Architecture. Added Section program Example which describes detect processor supports feature. Added Section program Example which describes method calculating actual operating frequency processor. Changed second cache descriptor Table 68h. Added cache descriptor Table Added Pentium processor, model processor signature Intel Xeon processor, processor signature Table Modified Table include extended family extended model fields. Modified Table include information returned extended CPUID functions.
Date
12/98
-013
10/99
-014 -015
03/00 05/00
-016
11/00
-017
02/01
-018
06/01
AP-485
INTRODUCTION
Intel Architecture evolves with addition generations models processors (8086, 8088, Intel286, Intel386TM, Intel486TM, Pentium® processors, Pentium® OverDrive® processors, Pentium® processors with MMXtechnology, Pentium® OverDrive processors with MMXtechnology, Pentium® processors, Pentium® processors, Pentium® Xeonprocessors, Pentium® Overdrive® processors, Intel® Celeronprocessors, Pentium® processors, Pentium® Xeonprocessors, Pentium® processors Intel® Xeonprocessors), essential that Intel provide increasingly sophisticated means with which software identify features available each processor. This identification mechanism evolved conjunction with Intel Architecture follows:
Originally, Intel published code sequences that could detect minor implementation architectural differences identify processor generations. Later, with advent Intel386 processor, Intel implemented processor signature identification that provided processor family, model, stepping numbers software, only upon reset. Intel Architecture evolved, Intel extended processor signature identification into CPUID instruction. CPUID instruction only provides processor signature, also provides information about features supported implemented Intel processor.
evolution processor identification necessary because, Intel Architecture proliferates, computing market must able tune processor functionality across processor generations models that have differing sets features. Anticipating that this trend will continue with future processor generations, Intel Architecture implementation CPUID instruction extensible. This application note explains CPUID instruction software applications, BIOS implementations, various processor tools. taking advantage CPUID instruction, software developers create software applications tools that execute compatibly across widest range Intel processor generations models, past, present, future.
8086 Flags Register
Update Support
Flags Register
obtain Intel processor signature feature bits information from developer's manual, programmer's reference manual appropriate documentation processor. addition, receive updated versions programming examples included this application note; contact your Intel representative more information, visit Intel's website http://developer.intel.com/.
Intel386Processor lags Register
Intel486Processor lags Register
DETECTING CPUID INSTRUCTION
Intel486 family subsequent Intel processors provide straightforward method determining whether processor's internal architecture able execute CPUID instruction. This method uses flag EFLAGS register. software change value this flag, CPUID instruction executable1 (see Figure
Pentium subsequent IA32 Processor lags Register Notes: Intel Reserv CPUID Presence
Figure Flag Register Evolution
Only some Intel486and succeeding processors. Intel386processor's Eflag register cannot changed software, Intel386 processor cannot execute CPUID instruction. Execution CPUID processor that does support this instruction will result invalid opcode exception.
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POPF, POPFD, PUSHF, PUSHFD instructions used access Flags Eflags register. program examples this application note show PUSHFD instruction read POPFD instruction change value flag.
OUTPUT CPUID INSTRUCTION
CPUID instruction supports sets functions. first returns basic processor information. second returns extended processor information. Figure summarizes basic processor information output CPUID instruction. output from CPUID instruction fully dependent upon contents register. This means, placing different values register then executing CPUID, CPUID instruction will perform specific function dependent upon whatever value resident register (see Table order determine highest acceptable value register input CPUID functions that return basic processor information, program should register parameter value then execute CPUID instruction follows
CPUID EAX,
After execution CPUID instruction, return value will present register. Always parameter value that equal greater than zero less than equal this highest "returned" value. order determine highest acceptable value register input CPUID functions that return extended processor information, program should register parameter value "80000000h" then execute CPUID instruction follows
CPUID EAX, 80000000H
After execution CPUID instruction, return value will present register. Always parameter value that equal greater than 80000000h less than equal this highest "returned" value. current future IA-32 processors, register will clear when CPUID executed with input parameter greater then highest value either functions, when extended functions supported. other values returned processor response CPUID instruction with value higher than appropriate that processor model specific should relied upon.
Vendor String
addition returning highest value register, Intel Vendor-ID string simultaneously verified well. register contains input value CPUID instruction also returns vendor identification string EBX, EDX, registers (see Figure These registers contain ASCII string:
GenuineIntel
While imitator Intel Architecture provide CPUID instruction, imitator legitimately claim that part genuine Intel part. presence "GenuineIntel" string assurance that CPUID instruction processor signature implemented described this document. "GenuineIntel" string returned after execution CPUID instruction, rely upon information described this document interpret information returned CPUID instruction.
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Output CPUID Highest Value Vendor Highest Integer Value (75) (6E)) (65) (47) (49) (65) (6E) (69) (6C) (65) (74) (6E) ASCII String (with Hexadecimal)
Output CPUID Processor Signature
Reserved (gray) Extended Family Extended Model Processor Type Family Code Model Number Stepping
Misc. Info Feature Flags
APIC Reserved chunks Brand Array (reserved future features) Array (Refer Table
Output CPUID Configuration Parameters Cache Descriptors (Refer Section 3.5)
Output CPUID Lower 64-bits 96-bit processor serial number Reserved Reserved Bits 31-00 processor serial number Bits 63-32 processor serial number
Figure CPUID Instruction Outputs
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Table Information Returned CPUID Instruction Initial Value
Information Provided about Processor
Basic CPUID Information Maximum Input Value Basic CPUID Information "Genu" "ntel" "ineI" 32-bit Processor Signature (Extended Family, Extended Model, Type, Family, Model Stepping also bits 95-64 96-bit processor serial number when feature flag set. Bits 7-0: Brand Index Bits 15-8: CLFLUSH line size. (Value returned cache line size) Valid only CLFSH feature flag set. Bits 23-16: Reserved Bits 31-24: Processor local APIC physical Valid Pentium subsequent processors Reserved Feature Flags (see Table Cache Descriptors Reserved Reserved Bits 31-0 96-bit processor serial number. (Available only Pentium processors when feature flag set; otherwise, value this register reserved.) Bits 31-0 96-bit processor serial number. (Available only Pentium processors when feature flag set; otherwise, value this register reserved.) Extended Function CPUID Information
EAX, EBX, ECX,
80000000H 80000001H
Maximum Input Value Extended Function CPUID Information EBX, ECX, Reserved Extended Processor Signature Extended Feature Bits (Currently Reserved.) EBX, ECX, Reserved Processor Brand String EBX, ECX, Processor Brand String Continued EAX, EBX, ECX, EAX, EBX, ECX, Processor Brand String Continued Processor Brand String Continued
80000002H 80000003H 80000004H
Processor Signature
Beginning with Intel486 processor family, register contains processor identification signature after reset (see Figure processor identification signature 32-bit value. processor signature composed from different fields. fields gray represent reserved bits, should masked when utilizing processor signature. remaining fields form processor identification signature.
Extended Family
Extended Model
Type
Family Code
Model Number
Stepping
Figure Register after RESET
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Processors that implement CPUID instruction also return 32-bit processor identification signature after reset; however, CPUID instruction gives flexibility checking processor signature time. Figure shows format 32-bit processor signature Intel486, subsequent Intel processors. Note that processor signature value after reset equivalent processor signature output value register Figure Table shows values returned register currently defined these processors. extended family, positions through used conjunction with family code, specified positions through indicate whether processor belongs Intel386, Intel486, Pentium, Pentium Pentium family processors. family processors include processors based Pentium® processor architecture have extended family equal family code equal Pentium family processors include processors based Intel® NetBurstMicro-Architecture have extended family equal family code equal 0Fh. extended model, positions through conjunction with model number, specified bits though used identify model processor within processor's family. stepping bits through indicates revision number that model. processor type, specified positions Table indicates whether processor original processor, OverDrive processor, dual processor (capable being used dual processor system). Table shows processor type values returned bits register.
Table Processor Type (Bit Positions Value
Description
Original processor
OverDrive processor Pentium processor, model Pentium Xeon processor, Dual processor model Intel Celeron processor, model share same extended family, family code, extended model model number. Intel reserved use.) differentiate between processors, software should check cache descriptor values through executing CPUID instruction with cache returned, processor identified Intel Celeron processor, model cache size reported, processor Pentium Xeon processor otherwise Pentium processor, model Pentium Xeon processor with 512K cache.
Pentium processor, model Pentium Xeon processor, model share same extended family, family code, extended model model number. differentiate between processors, software should check cache descriptor values through executing CPUID instruction with cache size reported, processor Pentium Xeon processor otherwise Pentium processor Pentium Xeon processor with 512K cache. processor brand Pentium processor, model Pentium Xeon processor, model Intel Celeron processor, model determined using Brand values returned CPUID instruction when executed with equal Table shows processor brands defined Brand Older versions Intel486 Intel486 IntelDX2 processors support CPUID instruction,2 they only return processor signature reset. Refer Table determine which processors support CPUID instruction. Figure shows format processor signature Intel386 processors, which different from other processors. Table shows values currently defined these Intel386 processors.
Intel486 SL-enhanced Write-Back enhanced processors capable executing CPUID instruction. Table
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RESET
Type Family Major Stepping Minor Stepping Intel Reserved. define.
000813
Figure Processor Signature Format Intel386Processors Table Intel386Processor Signatures Type
0000 0010 0010 0010 0100 0000
Family
0011 0011 0011 0011 0011 0011
Major Stepping
0000 0000 0000 0000 0000 0001 0100
Minor Stepping
xxxx xxxx xxxx xxxx xxxx xxxx
Description
Intel386DX processor Intel386 processor Intel386 processor Intel386 processor Intel386 processor RapidCAD® coprocessor
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Table Intel486TM, Subsequent Processor Signatures Extended Extended Family Model
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Type
Family Code
0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0101 0101 0101 0101 0101 0101 0101
Model Stepping Number
000x 0010 0011 0011 0011 0100 0101 0111 1000 1000 0001 0010 0001 0010 0011 0100 0100 xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Description
Intel486DX processors Intel486 processors Intel487processors IntelDX2processors IntelDX2 OverDrive® processors Intel486 processor IntelSX2processors Write-Back Enhanced IntelDX2 processors IntelDX4processors IntelDX4 OverDrive processors Pentium® processors (60, Pentium processors (75, 100, 120, 133, 150, 166, 200) Pentium OverDrive processor Pentium processor (60, Pentium OverDrive processor Pentium processor (75, 100, 120, 133) Pentium OverDrive processors Intel486 processor-based systems Pentium processor with MMXtechnology (166, 200) Pentium OverDrive processor with MMXtechnology Pentium processor (75, 100, 120, 133) Pentium processor Pentium processor, model Pentium processor, model Pentium Xeon processor, model Intel Celeron processor, model Intel Celeron processor, model Pentium processor, model Pentium Xeon processor, model Pentium processor, model Pentium Xeon processor, model Intel Celeron processor, model Pentium Xeon processor, model Pentium processor, model Intel Pentium OverDrive processor Intel Pentium processor Intel Xeon processor
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx xxxx xxxx xxxx xxxx
00000000 00000000 00000000
0000 0000 0000
0110 0110 0110
0001 0011 0101(5)
xxxx xxxx
xxxx
00000000 00000000 00000000
0000 0000 0000
0110 0110 0110
0110 0111(6) 1000(7)
xxxx xxxx xxxx
00000000 00000000 00000000 00000000
0000 0000 0000 0000
0110 0110 0110 1111
1010 1011 0011 000x
xxxx xxxx
xxxx xxxx
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NOTES:
This processor does implement CPUID instruction. Refer Intel486documentation, Pentium® Processor Specification Update (Order Number 242480), Pentium® Processor Specification Update (Order Number 242689), Pentium® Processor Specification Update (Order Number 243337), Pentium® Xeon Processor Specification Update (Order Number 243776), Intel Celeron Processor Specification Update (Order Number 243748), Pentium Processor Specification Update (Order Number 244453), Pentium® XeonProcessor Specification Update (Order Number 244460), Pentium® Processor Specification Update (Order Number 249199) Intel® XeonProcessor Specification Update (Order Number 249678) latest list stepping numbers. Stepping implements CPUID instruction. definition type field OverDrive® processor 01h. erratum Pentium OverDrive processor will always return type. differentiate between Pentium processor, model Pentium Xeon processor Intel Celeron processor, model software should check cache descriptor values through executing CPUID instruction with cache returned, processor identified Intel Celeron processor, model cache size reported, processor Pentium Xeon processor otherwise Pentium processor, model Pentium Xeon processor with 512K cache size. differentiate between Pentium processor, model Pentium Xeon processor, model software should check cache descriptor values through executing CPUID instruction with cache size reported, processor Pentium Xeon processor otherwise Pentium processor Pentium Xeon processor with 512K cache size. differentiate between Pentium processor, model Pentium Xeon processor, model software should check Brand values through executing CPUID instruction with
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Feature Flags
When register contains value CPUID instruction addition loading processor signature register) loads register with feature flags. feature flags (when Flag indicate what features processor supports. Table lists currently defined feature flag values. future processors, refer programmer's reference manual, user's manual, appropriate documentation latest feature flag values.
feature flags your applications determine which processor features supported. using CPUID feature flags determine processor features, your software detect avoid incompatibilities introduced addition removal processor features. Table Feature Flag Values Reported Register
Name
Description when Flag
Floating-point unit onChip Virtual Mode Extension Debugging Extension
Comments
processor contains that supports Intel387 floating-point instruction set. processor supports extensions virtual-8086 mode. processor supports breakpoints, including CR4.DE enabling debug extensions optional trapping access registers. processor supports 4-Mbyte pages. RDTSC instruction supported including CR4.TSD access/privilege control.
APIC
Page Size Extension Time Stamp Counter
Model Specific Registers Model Specific Registers implemented with RDMSR, WRMSR instructions Physical Address Extension Machine Check Exception CMPXCHG8 Instruction Supported On-chip APIC Hardware Supported Reserved Fast System Call Physical addresses greater than bits supported. Machine Check Exception, Exception CR4.MCE enable supported compare exchange bytes instruction supported. processor contains software-accessible Local APIC. count their value. Indicates whether processor supports Fast System Call instructions, SYSENTER SYSEXIT. NOTE: Refer Section further information regarding SYSENTER/ SYSEXIT feature feature bit. Processor supports Memory Type Range Registers specifically MTRR_CAP register. global page directory entries (PDEs) page table entries (PTEs) supported, indicating entries that common different processes need flushed. CR4.PGE controls this feature. Machine Check Architecture supported, specifically MCG_CAP register. processor supports CMOVcc, feature flag (bit also set, supports FCMOVCC FCOMI instructions.
MTRR
Memory Type Range Registers Page Global Enable
CMOV
Machine Check Architecture Conditional Move Instruction Supported
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Table Feature Flag Values Reported Register
Name
Description when Flag
Page Attribute Table
Comments
Indicates whether processor supports Page Attribute Table. This feature augments Memory Type Range Registers (MTRRs), allowing operating system specify attributes memory granularity through linear address. Indicates whether processor supports 4-Mbyte pages that capable addressing physical memory beyond 4GB. This feature indicates that upper four bits physical address 4-Mbyte page encoded bits 13-16 page directory entry. processor supports 96-bit processor serial number feature, feature enabled. Indicates that processor supports CLFLUSH instruction. count their value. Indicates that processor ability write history branch from addresses into memory buffer. processor implements internal MSRs that allow processor temperature monitored processor performance modulated predefined duty cycles under software control. processor supports technology instruction extensions Intel Architecture. Indicates whether processor supports FXSAVE FXRSTOR instructions fast save restore floating point context. Presence this also indicates that CR4.OSFXSR available operating system indicate that uses fast save/restore instructions. processor supports Streaming SIMD Extensions Intel Architecture. Indicates processor supports Streaming SIMD Extensions Instructions. processor supports management conflicting memory types performing snoop cache structure transactions issued bus. count their value. processor implements Thermal Monitor automatic thermal control circuit (TCC). count their value.
PSE-36
36-bit Page Size Extension
CLFSH
Processor serial number present enabled CLFLUSH Instruction supported Reserved Debug Store Thermal Monitor Software Controlled Clock Facilities supported Intel Architecture technology supported Fast floating point save restore
ACPI
FXSR
SSE2
Streaming SIMD Extensions supported Streaming SIMD Extensions Self-Snoop
Reserved Thermal Monitor supported Reserved
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SYSENTER/SYSEXIT Features
SYSENTER Present (SEP) CPUID indicates presence this facility. operating system that detects presence must also qualify processor family model ensure that SYSENTER/SYSEXIT instructions actually present:
(CPUID set) ((Processor Signature 0x0FFF3FFF) 0x00000633) Fast System Call supported ELSE Fast System Call supported
Pentium processor (Model returns CPUID feature bit, should used software.
Cache Size, Format Information
When register contains value CPUID instruction loads EAX, EBX, registers with descriptors that indicate processors cache characteristics. lower bits register (AL) contain value that identifies number times CPUID executed obtain complete image processor's caching systems. example, Pentium processor returns value lower bits register indicate that CPUID instruction need only executed once (with obtain complete image processor configuration. remainder register, EBX, registers contain cache descriptors. Table shows that when given register zero, that register contains valid 8-bit descriptors. decode descriptors, move sequentially from most significant byte register down through least significant byte register. Assuming then that register contains valid cache descriptors bits through bits through bits through bits through Software must compare value contained each descriptor fields with values found Table determine cache features processor.
Table Descriptor Formats Register
Descriptor Type
Reserved
Description
Reserved future use.
descriptors Descriptors point parameter table identify cache characteristics. descriptor null value.
Table lists current cache descriptor values their respective characteristics. This list will extended future necessary. Between models steppings processors cache information change field locations, therefore important that software assume fixed locations when parsing cache descriptors.
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Table Descriptor Decode Values Value
Null Instruction TLB, pages, 4-way associative, entries Instruction TLB, pages, fully associative, entries Data TLB, pages, 4-way associative, entries Data TLB, pages, 4-way associative, entries Instruction cache, 4-way associative, byte line size Instruction cache 16K, 4-way associative, byte line size Data cache, 2-way associative, byte line size Data cache, 16K, 4-way associative, byte line size cache family), cache (Pentium processor) Unified cache, byte cache line,4-way associative, 128K Unified cache, byte cache line, 4-way associative, 256K Unified cache, byte cache line, 4-way associative, 512K Unified cache, byte cache line, 4-way associative, Unified cache, byte cache line, 4-way associative, Instruction TLB, pages, fully associative, entries Instruction TLB, pages, fully associative, entries Instruction TLB, pages, fully associative, entries Data TLB, pages, fully associative, entries Data TLB, pages, fully associative, entries Data TLB, pages, fully associative, entries Data cache, sectored, byte cache line, associative, Data cache, sectored, byte cache line, associative, Data cache, sectored, byte cache line, associative, Instruction Trace cache, associative, uOps Instruction Trace cache, associative, uOps Instruction Trace cache, associative, uOps Unified cache, sectored, byte cache line, associative, 128K Unified cache, sectored, byte cache line, associative, 256K Unified cache, sectored, byte cache line, associative, 512K Unified cache, sectored, byte cache line, associative, Unified cache, byte cache line, associative, 256K Unified cache, byte cache line, associative, 512K Unified cache, byte cache line, associative, Unified cache, byte cache line, associative,
Cache Description
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Pentium® Processor, Model Output Example
Pentium processor, model returns values shown Table Since value AL=1, valid interpret remainder registers. Table also shows (bit registers which indicates that each register contains valid 8-bit descriptor. register values Table show that this Pentium processor following cache characteristics:
(66h) data cache that 8K-Bytes, associative, sectored, byte line size. (5Bh) data that maps pages, fully associative, entries. (50h) instruction that maps pages, fully associative, entries. (7Ah) unified cache that 256K-Bytes, associative, sectored, byte line size. (70h) instruction trace cache that store 12K-uOps, associative. (40h) cache.
Table Pentium® Processor, model with 256K Cache, CPUID (EAX=2) Example Return Values
PROCESSOR SERIAL NUMBER
processor serial number extends concept processor identification. Processor serial number 96-bit number accessible through CPUID instruction. Processor serial number used applications identify processor, extension, system. processor serial number creates software accessible identity individual processor. processor serial number, combined with other qualifiers, could applied user identification. Applications include membership authentication, data backup/restore protection, removable storage data protection, managed access files, confirm document exchange between appropriate users. Processor serial number another tool asset management, product tracking, remote systems load configuration, boot-up configuration. case system service, processor serial number could used differentiate users during help desk access, track error reporting. Processor serial number provides identifier processor, should assumed unique itself. There potential modes which erroneous processor serial numbers reported. example, event processor operated outside recommended operating specifications, (e.g. voltage, frequency, etc.) processor serial number correctly read from processor. Improper BIOS software operations could yield inaccurate processor serial number. These events could lead possible erroneous duplicate processor serial numbers being reported. System manufacturers strengthen robustness feature including redundancy features, other fault tolerant methods. Processor serial number used qualifier another independent number could used create electrically accessible number that likely distinct. Processor serial number building block useful purpose enabling trusted, connected
Presence Processor Serial Number
determine processor serial number feature supported, program should register parameter value then execute CPUID instruction follows:
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CPUID EAX,
After execution CPUID instruction, register contains Feature Flags. Feature Flags, (EDX register, equals "1", processor serial number feature supported, enabled. Feature Flags equals "0", processor serial number feature either supported, disabled.
Forming 96-bit Processor Serial Number
96-bit processor serial number concatenation three 32-bit entities. access most significant 32-bits processor serial number program should register parameter value then execute CPUID instruction follows:
CPUID EAX,
After execution CPUID instruction, register contains Processor Signature. Processor Signature comprises most significant 32-bits processor serial number. value should saved prior gathering remaining 64-bits processor serial number. access remaining 64-bits processor serial number program should register parameter value then execute CPUID instruction follows:
CPUID EAX,
After execution CPUID instruction, register contains middle 32-bits, register contains least significant 32-bits processor serial number. Software then concatenate saved Processor Signature, EDX, before returning complete 96-bit processor serial number. Processor serial number should displayed groups nibbles (Ex. XXXX-XXXX-XXXX-XXXXXXXX-XXXX where represents digit). Alpha characters should displayed capital letters.
BRAND
Beginning with Pentium processors, model Pentium Xeon processors, model Intel Celeron processor, model concept processor identification further extended with addition Brand Brand 8-bit number accessible through CPUID instruction. Brand used applications assist identifying processor. Processors that implement Brand feature return Brand bits through register when CPUID instruction executed with EAX=1 (see Table Processors that support feature return value bits through differentiate previous models Pentium processor, Pentium Xeon processor, Intel Celeron processor, Pentium processor Pentium Xeon processor, application software relied cache descriptors. cases results were ambiguous, example software could accurately differentiate Pentium processor from Pentium Xeon processor with 512K cache. Brand eliminates this ambiguity providing software accessible value unique each processor brand. Table shows values defined each processor.
Table Brand CPUID (EAX=1) Return Values (bits through Value Description
other values Unsupported Intel® Celeronprocessor Intel® Pentium® processor Intel® Pentium® Xeonprocessor Intel® Pentium® processor Intel® Pentium® processor Intel® Xeonprocessor Reserved
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BRAND STRING
Brand string extension CPUID instruction implemented some Intel IA-32 processors, including Pentium processor. Using brand string feature, future IA-32 architecture based processors will return their ASCII brand identification string maximum operating frequency extended CPUID instruction. Note that frequency returned maximum operating frequency that processor been qualified current operating frequency processor. When CPUID executed with values listed Table processor will return ASCII brand string general-purpose registers detailed Table brand/frequency string defined characters long, bytes will contain characters 48th byte defined NULL (0). processor return less than ASCII characters long string null terminated processor returns valid data when CPUID executed with 80000002h, 80000003h 80000004h. cpuid3a.asm program shows software forms brand string (see Example determine brand string supported processor, software must follow step below:
Execute CPUID instruction with EAX=80000000h ((returned value EAX) 80000000h) then processor supports extended CPUID functions contains largest extended function supported. processor brand string feature supported 80000000h
input value
80000000h 80000001h 80000002h 80000003h 80000004h
Table Processor Brand String Feature Function Return value
Largest Extended Function Supported Extended Processor Signature Extended Feature Bits Processor Brand String Processor Brand String Processor Brand String EAX=80000004, Reserved Reserved EAX, EBX, ECX, contain ASCII brand string EAX, EBX, ECX, contain ASCII brand string EAX, EBX, ECX, contain ASCII brand string
USAGE GUIDELINES
This document presents Intel-recommended feature-detection methods. Software should identify features exploiting programming tricks, undocumented features, otherwise deviating from guidelines presented this application note. following guidelines intended help programmers maintain widest range compatibility their software.
depend absence invalid opcode trap CPUID opcode detect CPUID instruction. depend absence invalid opcode trap PUSHFD opcode detect 32-bit processor. Test flag, described Section 2.0. shown Section assume that given family model specific feature. example, assume family value (Pentium processor) means there floating-point unit on-chip. feature flags this determination. assume processors with higher family model numbers have features processor with lower family model number. example, processor with family value family processor) necessarily have features processor with family value
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assume that features OverDrive processors same those version processor. Internal caches instruction execution might vary. undocumented features processor identify steppings features. example, Intel386 processor Astep instructions that were withdrawn with B-step. Some software attempted execute these instructions depended invalid-opcode exception signal that running A-step part. software failed work correctly when Intel486 processor used same opcodes different instructions. software should have used stepping information processor signature. Test feature flags individually make assumptions about undefined bits. example, would mistake test comparing feature register binary with compare instruction. assume clock given family model runs specific frequency, write processor speeddependent code, such timing loops. instance, OverDrive Processor could operate higher internal frequency still report same family and/or model. Instead, combination system's timers measure elapsed time (Time Stamp Counter) measure processor core clocks allow direct calibration processor core. Section Example details. Processor model-specific registers differ among processors, including various models Pentium processor. these registers unless identified installed processor. This particularly important systems upgradeable with OverDrive processor. Only Model Specific registers that defined BIOS writers guide that processor. rely result CPUID algorithm when executed virtual 8086 mode. assume ordering model and/or stepping numbers. They assigned arbitrarily. assume processor serial number unique number without further qualifiers. Display processor serial number groups nibbles (Ex. XXXX-XXXX-XXXX-XXXX-XXXX-XXXX where represents digit). Display alpha characters capital letters. zero lower bits processor serial number indicate processor serial number invalid, supported, disabled this processor.
PROPER IDENTIFICATION SEQUENCE
Determine CPUID instruction supported modifying flag EFLAGS register. flag cannot modified, processor cannot identified using CPUID instruction. Execute CPUID instruction with equal 80000000h. CPUID function 80000000h used determine Brand String supported. CPUID function 80000000h returns value greater than 80000000h Brand String feature supported software should CPUID functions 80000002h through 80000004h identify processor. Brand String feature supported, execute CPUID with equal CPUID function returns processor signature register, Brand register bits through register bits through contain non-zero value, Brand supported. Software should scan list Brand (see Table identify processor. Brand feature supported, software should processor signature (see Figure conjunction with cache descriptors (see Table identify processor.
identify processor using CPUID instructions, software should follow following steps.
cpuid3a.asm program example demonstrates correct CPUID instruction (see Example also shows identify earlier processor generations that implement Brand String, Brand processor signature CPUID instruction (see Figure This program example contains following procedures:
get_cpu_type identifies processor type. Figure illustrates flow this procedure. get_fpu_type determines type floating-point unit (FPU) math coprocessor (MCP).
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This procedure been tested with 8086, 80286, Intel386, Intel486, Pentium processor, Pentium processor with technology, OverDrive processor with technology, Pentium processors, Pentium processors, Pentium Xeon processors, Pentium Overdrive processors, Intel Celeron processors, Pentium processors, Pentium Xeon processors Pentium processors. This program example written assembly language suitable inclusion run-time library, system calls operating systems.
8086 processor?
_type=0
80286 processor?
_type=2
80386 processor?
_type=3
u_type>=4
CPUID instruct supp orted
cpuid_flag indicates CPUID instruction presen Execute CPUID with input vendor string values EAX.
Does vend "GenuineIntel"
highest inpu valu least execut CPUID with btain del, steppin amily, features. Save u_type, stepp ing, feature_flags.
end_get u_type
Figure Flow Processor get_cpu_type Procedure
USAGE PROGRAM EXAMPLES
cpuid3b.asm cpuid3.c program examples demonstrate applications that call get_cpu_type get_fpu_type procedures interpret returned information. This code shown Example Example results, which displayed monitor, identify installed processor features. cpuid3b.asm example written assembly language demonstrates application that displays returned information environment. cpuid3.c example written language (see Example Example Figure presents overview relationship between three program examples.
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cpuid3b.ASM cpuid3.C
Main
cpuid3a.ASM
get_cpu_type*
Call cpu_type Call fpu_type
get_fpu_type
Processor features check
000964
Figure Flow Processor Identification Extraction Procedure
ALTERNATE METHOD DETECTING FEATURES
Some feature flags indicate support instruction extensions (i.e. MMX, SSE2). preferred mechanism determining support instruction extensions through CPUID instruction, testing feature flags. However alternate method determining processor support instruction extensions install exception handler execute instructions. instruction executes without generating exception, then processor supports that instruction extensions. exception raised, exception handler executed, then those instruction extensions supported processor. Before installing exception handler, software should execute CPUID instruction with CPUID instruction returns Intel vendor-ID string "GenuineIntel", then software knows that test Intel instruction extensions. long CPUID instruction returns Intel vendor-ID, this method used support future Intel processors. This method does require software check family model. features.cpp program written using language (see Example demonstrates exceptions determine support SSE2, SSE, instruction extensions. performs following steps:
Check that vendor-ID "GenuineIntel" Install exception handler SSE2 test Attempt execute SSE2 instruction (paddq xmm1, xmm2) Install exception handler test Attempt execute instruction (orps xmm1, xmm2) Install exception handler test Attempt execute instruction (emms) Print supported instruction extensions.
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DENORMALS ZERO
With introduction SSE2 extensions, some Intel Architecture processors have ability convert SSE2 source operand denormal numbers zero. This feature referred Denormals-Are-Zero (DAZ). mode compatible with IEEE Standard 754. mode provided improve processor performance applications such streaming media processing, where rounding denormal operand zero does appreciably affect quality processed data. Some processor steppings support SSE2 support mode. determine processor supports mode, software must perform following steps.
Execute CPUID instruction with input value EAX=0 ensure vendor-ID string returned "GenuineIntel". Execute CPUID instruction with EAX=1. This will load register with feature flags.
Ensure that FXSR feature flag (EDX set. This indicates processor supports FXSAVE FXRSTOR instructions. Ensure that feature flag (EDX feature flag (EDX set. This indicates that processor supports least SSE/SSE2 instruction sets MXCSR control register. Zero 16-byte aligned, 512-byte area memory. This necessary since some implementations FXSAVE modify reserved areas within image. Execute FXSAVE into cleared area. Bytes 28-31 FXSAVE image defined contain MXCSR_MASK. this value then processor's MXCSR_MASK 0xFFBF, otherwise MXCSR_MASK value this dword. MXCSR_MASK set, then supported.
After completing this algorithm, supported, software enable mode setting MXCSR register save area executing FXRSTOR instruction. Alternately software enable mode setting MXCSR executing LDMXCSR instruction. Refer chapter titled "Programming with Streaming SIMD Extensions (SSE)" Intel Architecture Software Developer's Manual volume Basic Architecture. assembly language program dazdtect.asm (see Example demonstrates this detection algorithm.
OPERATING FREQUENCY
With introduction Time Stamp Counter, possible software operating real mode protected mode with ring privilege calculate actual operating frequency processor. calculate operating frequency, software needs reference period. reference period periodic interrupt, another timer that based time, based system clock. Software needs read Time Stamp Counter (TSC) beginning ending reference period. Software read executing RDTSC instruction, setting register executing RDMSR instruction. Both instructions copy current 64-bit into EDX:EAX register pair. determine operating frequency processor, software performs following steps. assembly language program frequenc.asm (see Example demonstrates frequency detection algorithm.
Execute CPUID instruction with input value EAX=0 ensure vendor-ID string returned "GenuineIntel". Execute CPUID instruction with EAX=1 load register with feature flags.
Ensure that feature flag (EDX set. This indicates processor supports Time Stamp Counter RDTSC instruction. Read beginning reference period Read reference period. Compute delta from beginning ending reference period.
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Compute actual frequency dividing delta reference period.
Actual frequency (Ending value Beginning value) reference period
Note: measured accuracy dependent accuracy reference period. longer reference period produces more accurate result. addition, repeating calculation multiple times also improve accuracy.
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Example Processor Identification Extraction Procedure Filename: cpuid3a.asm Copyright(c) 1993 2001 Intel Corp. This program been developed Intel Corporation. Intel various intellectual property rights which assert under certain circumstances, such another manufacturer's processor mis-identifies itself being "GenuineIntel" when CPUID instruction executed. Intel specifically disclaims warranties, express implied, liability, including consequential other indirect damages, this program, including liability infringement proprietary rights, including warranties merchantability fitness particular purpose. Intel does assume responsibility errors which appear this program responsibility update This code contains procedures: _get_cpu_type: Identifies processor type _cpu_type: 0=8086/8088 processor 2=Intel processor 3=Intel386(TM) family processor 4=Intel486(TM) family processor 5=Pentium(R) family processor 6=P6 family processors F=Pentium family processors _get_fpu_type: Identifies type _fpu_type: 0=FPU present 1=FPU present 2=287 present (only _cpu_type=3) 3=387 present (only _cpu_type=3) This program been tested with Microsoft Developer Studio. This code correctly detects current Intel 8086/8088, 80286, 80386, 80486, Pentium(R) processor, Pentium(R) processor, Pentium(R) processor, Pentium Xeon(TM) processor, Pentium Overdrive(R), Intel Celeron processor, Pentium processor, Pentium Xeon processor, Pentium processors Intel(R) Xeon(TM) processors. NOTE: When using this code with program cpuid3.c, 32-bit segments recommended.
assemble this code with TASM, JUMPS directive. jumps Uncomment this line TASM
TITLE cpuid3a comment this line 32-bit segments DOSSEG uncomment following lines 32-bit segments .386
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.model flat
comment this line 32-bit segments .model small
CPU_ID MACRO 0a2h ENDM .data public public public public public public public public public public public public public public public public _cpu_type _fpu_type _v86_flag _cpuid_flag _intel_CPU _vendor_id _cpu_signature _features_ecx _features_edx _features_ebx _cache_eax _cache_ebx _cache_ecx _cache_edx _sep_flag _brand_string
Hardcoded CPUID instruction
_cpu_type _fpu_type _v86_flag _cpuid_flag _intel_CPU _sep_flag _vendor_id intel_id _cpu_signature _features_ecx _features_edx _features_ebx _cache_eax _cache_ebx _cache_ecx _cache_edx fp_status _brand_string .code .8086
"GenuineIntel"
comment this line 32-bit segments
uncomment this line 32-bit segments .386
public _get_cpu_type _get_cpu_type proc
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This procedure determines type processor system sets _cpu_type variable with appropriate value. CPUID instruction available, used determine more specific details about processor. registers used this procedure, none preserved. avoid faults, must set. Intel 8086 processor check Bits 12-15 FLAGS register always 8086 processor.
32-bit segments comment following lines down next comment line that says "STOP" check_8086: pushf push original FLAGS original FLAGS save original FLAGS 0fffh clear bits 12-15 FLAGS push save FLAGS value stack popf replace current FLAGS value pushf FLAGS store FLAGS 0f000h bits 12-15 set, then 0f000h processor 8086/8088 _cpu_type, turn 8086/8088 flag check_80286 check 80286 push double check with push value pushed different means it's really 8086 end_cpu_type jump processor 8086/8088 _cpu_type, indicate unknown processor end_cpu_type Intel processor check Bits 12-15 FLAGS register always clear Intel processor real-address mode.
.286 check_80286: smsw push popf pushf
_v86_flag, 0f000h
save machine status word isolate save indicate bits 12-15 save FLAGS value stack replace current FLAGS value FLAGS store FLAGS bits 12-15 clear processor=80286, turn 80286 flag jump processor 80286
0f000h _cpu_type, end_cpu_type
Intel386 processor check bit, #18, introduced EFLAGS register Intel486 processor generate alignment faults. This cannot Intel386 processor.
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.386 "STOP" check_80386: pushfd push popfd pushfd push popfd
safe instructions push original EFLAGS original EFLAGS save original EFLAGS flip EFLAGS save EFLAGS value stack replace current EFLAGS value EFLAGS store EFLAGS can't toggle bit, processor=80386 turn 80386 processor flag jump 80386 processor restore EFLAGS first
ecx, eax, 40000h
eax, _cpu_type, end_cpu_type
Intel486 processor check Checking ability set/clear flag (Bit EFLAGS which indicates presence processor with CPUID instruction.
.486 check_80486: push popfd pushfd
_cpu_type, eax, eax, 200000h
eax, end_cpu_type
turn 80486 processor flag original EFLAGS flip EFLAGS save EFLAGS value stack replace current EFLAGS value EFLAGS store EFLAGS can't toggle bit, processor=80486
Execute CPUID instruction determine vendor, family, model, stepping features. purpose this code, only initial CPUID information saved. push push push CPU_ID _cpuid_flag, eax, flag indicating CPUID inst. save registers
CPUID instruction save vendor
dword _vendor_id, dword _vendor_id[+4], dword _vendor_id[+8], dword intel_id, end_cpuid_type dword intel_id[+4], end_cpuid_type dword intel_id[+8], end_cpuid_type _intel_CPU, eax,
equal, Intel processor indicate Intel processor make sure valid input CPUID
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CPU_ID end_cpuid_type eax, _cpu_signature, _features_ebx, _features_edx, _features_ecx, eax, eax, _cpu_type, isolate family _cpu_type with family not, jump family/model/stepping/features
Execute CPUID instruction determine cache descriptor information. eax, CPU_ID end_cpuid_type eax, CPU_ID end_cpuid_type check value cache descriptors supported?
read cache descriptor iteration enough obtain cache information? This code supports iteration only. store cache information NOTE: future processors, CPUID instruction need more than once complete cache information check brand string supported
_cache_eax, _cache_ebx, _cache_ecx, _cache_edx,
eax, 80000000h CPU_ID eax, 80000000h end_cpuid_type CPU_ID CPU_ID CPU_ID
take jump supported
offset _brand_string eax, 80000002h dword [di], dword [di+4], dword [di+8], dword [di+12], eax, 80000003h dword [di], dword [di+4], dword [di+8], dword [di+12], eax, 80000004h dword [di], dword [di+4], dword [di+8], dword [di+12], save bytes save bytes first bytes brand string save bytes
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end_cpuid_type: restore registers comment this line 32-bit segments .8086 end_cpu_type: _get_cpu_type endp public _get_fpu_type _get_fpu_type proc This procedure determines type system sets _fpu_type variable with appropriate value. registers used this procedure, none preserved. Coprocessor check algorithm determine whether floating-point status control words present. not, coprocessor exists. status control words saved, correct coprocessor then determined depending processor type. Intel386 processor work with either Intel287 Intel387 NDP. infinity coprocessor must checked determine correct coprocessor type. fninit fnstsw reset status word initialize temp word non-zero save status word check status word correct status written present
fp_status, 5a5ah fp_status fp_status _fpu_type, end_fpu_type
check_control_word: fnstcw fp_status fp_status 103fh _fpu_type, end_fpu_type _fpu_type,
save control word check control word selected parts examine control word correct incorrect control word,
80287/80387 check Intel386 processor
check_infinity: fld1 fldz fdiv fchs fcompp fstsw
_cpu_type, end_fpu_type must default control from FNINIT form infinity 8087/Intel287 +inf -inf form negative infinity Intel387 says +inf -inf they same look status from FCOMPP
fp_status
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sahf end_fpu_type: _get_fpu_type fp_status _fpu_type, end_fpu_type _fpu_type,
store Intel287 type infinities matched jump 8087 Intel287 present store Intel387 type
endp
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Example Processor Identification Procedure Assembly Language Filename: cpuid3b.asm Copyright(c) 1993 2001 Intel Corp. This program been developed Intel Corporation. Intel various intellectual property rights which assert under certain circumstances, such another manufacturer's processor mis-identifies itself being "GenuineIntel" when CPUID instruction executed. Intel specifically disclaims warranties, express implied, liability, including consequential other indirect damages, this program, including liability infringement proprietary rights, including warranties merchantability fitness particular purpose. Intel does assume responsibility errors which appear this program responsibility update This program contains three parts: Part Identifies processor type variable _cpu_type: Part Part Identifies type variable _fpu_type: Prints appropriate message. This part specific environment uses system calls print messages.
This program been tested with Microsoft Developer Studio. this code assembled with options specified linked with cpuid3a module, correctly identifies current Intel 8086/8088, 80286, 80386, 80486, Pentium(R), Pentium(R) Pro, Pentium(R) processors, Pentium(R) Xeon processors, Pentium Overdrive processors, Intel Celeron(TM) processors, Pentium processors, Pentium Xeon processors, Pentium(R) processors Intel(R) Xeon(TM) processors when executed real-address mode.
NOTE: This code written using 16-bit Segments assemble this code with TASM, JUMPS directive. jumps Uncomment this line TASM TITLE DOSSEG .model small .stack OP_O ENDM .data extrn extrn extrn extrn _cpu_type: _fpu_type: _cpuid_flag: _intel_CPU: byte byte byte byte
cpuid3b
100h MACRO
hardcoded operand override
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extrn extrn extrn extrn extrn extrn extrn extrn extrn extrn .code .8086 start: call call call @data _get_cpu_type _get_fpu_type print 4c00h segment register segment register align stack avoid fault determine processor type _vendor_id: _cpu_signature: _features_ecx: _features_edx: _features_ebx: _cache_eax: _cache_ebx: _cache_ecx: _cache_edx: _brand_string: byte dword dword dword dword dword dword dword dword byte
purpose this code identify processor coprocessor that currently system. program first determines processor type. Then determines whether coprocessor exists system. coprocessor integrated coprocessor exists, program identifies coprocessor type. program then prints processor floating point processors present type.
extrn _get_cpu_type: proc
extrn _get_fpu_type: proc
FPU_FLAG VME_FLAG DE_FLAG PSE_FLAG TSC_FLAG MSR_FLAG PAE_FLAG MCE_FLAG CX8_FLAG APIC_FLAG SEP_FLAG MTRR_FLAG PGE_FLAG MCA_FLAG CMOV_FLAG PAT_FLAG PSE36_FLAG PSNUM_FLAG
0001h 0002h 0004h 0008h 0010h 0020h 0040h 0080h 0100h 0200h 0800h 1000h 2000h 4000h 8000h 10000h 20000h 40000h
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CLFLUSH_FLAG DTS_FLAG ACPI_FLAG MMX_FLAG FXSR_FLAG SSE_FLAG SSE2_FLAG SS_FLAG TM_FLAG .data id_msg cp_error cp_8086 cp_286 cp_386 cp_486 cp_486sx fp_8087 fp_287 fp_387 intel486_msg intel486dx_msg intel486sx_msg inteldx2_msg intelsx2_msg inteldx4_msg inteldx2wb_msg pentium_msg pentiumpro_msg 80000h 200000h 400000h 800000h 1000000h 2000000h 4000000h 8000000h 20000000h
"This system unknown processor$" 8086/8088 processor$" 80286 processor$" 80386 processor$" 80486DX, 80486DX2 processor 80487SX math coprocessor$" 80486SX processor$" 8087 math coprocessor$" 80287 math coprocessor$" 80387 math coprocessor$" Genuine Intel486(TM) processor$" Genuine Intel486(TM) processor$" Genuine Intel486(TM) processor$" Genuine IntelDX2(TM) processor$" Genuine IntelSX2(TM) processor$" Genuine IntelDX4(TM) processor$" Genuine Write-Back Enhanced" IntelDX2(TM) processor$" Genuine Intel(R) Pentium(R) processor$" Genuine Intel Pentium(R) processor$" Genuine Intel(R) Pentium(R) processor, model Genuine Intel(R) Pentium(R) processor, model Intel(R) Pentium(R) Genuine Intel(R) Pentium(R) Xeon(TM) processor$" Genuine Intel(R) Celeron(TM) processor, model Genuine Intel(R) Celeron(TM) processor, model Genuine Intel(R) Celeron(TM) processor$" Genuine Intel(R) Pentium(R) processor, model Intel Pentium(R) Xeon(TM) Genuine Intel(R) Pentium(R) Xeon(TM) processor, model Genuine Intel(R) Pentium(R) Xeon(TM) processor$" Genuine Intel(R) Pentium(R) processor$" Genuine Intel(R) Pentium(R) processor$" Genuine Intel(R) Xeon(TM) processor$" unknown Genuine Intel(R) processor$"
pentiumiimodel3_msg pentiumiixeon_m5_msg Xeon(TM) processor$" pentiumiixeon_msg celeron_msg celeronmodel6_msg celeron_brand pentiumiii_msg processor, model pentiumiiixeon_msg pentiumiiixeon_brand pentiumiii_brand pentium4_brand xeon_brand unknown_msg brand_entry struct brand_value brand_string brand_entry ends brand_table
brand_entry brand_entry brand_entry brand_entry
<01h, offset celeron_brand> <02h, offset pentiumiii_brand> <03h, offset pentiumiiixeon_brand> <04h, offset pentiumiii_brand>
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brand_entry brand_entry brand_table_size <08h, offset pentium4_brand> <0Eh, offset xeon_brand>
offset brand_table) (sizeof brand_entry)
following entries must stay intact array intel_486_0 offset intel486dx_msg intel_486_1 offset intel486dx_msg intel_486_2 offset intel486sx_msg intel_486_3 offset inteldx2_msg intel_486_4 offset intel486_msg intel_486_5 offset intelsx2_msg intel_486_6 offset intel486_msg intel_486_7 offset inteldx2wb_msg intel_486_8 offset inteldx4_msg intel_486_9 offset intel486_msg intel_486_a offset intel486_msg intel_486_b offset intel486_msg intel_486_c offset intel486_msg intel_486_d offset intel486_msg intel_486_e offset intel486_msg intel_486_f offset intel486_msg array family_msg model_msg stepping_msg ext_fam_msg ext_mod_msg cr_lf turbo_msg dp_msg fpu_msg vme_msg de_msg pse_msg tsc_msg msr_msg pae_msg mce_msg cx8_msg apic_msg sep_msg no_sep_msg mtrr_msg pge_msg
13,10,"Processor Family: 13,10,"Model: 13,10,"Stepping: 13,10," Extended Family: 13,10," Extended Model: 13,10,"$" 13,10,"The processor OverDrive(R)" processor$" 13,10,"The processor upgrade" processor dual processor system$" 13,10,"The processor contains on-chip" FPU$" 13,10,"The processor supports Virtual" Mode Extensions$" 13,10,"The processor supports Debugging" Extensions$" 13,10,"The processor supports Page Size" Extensions$" 13,10,"The processor supports Time Stamp" Counter$" 13,10,"The processor supports Model" Specific Registers$" 13,10,"The processor supports Physical" Address Extensions$" 13,10,"The processor supports Machine" Check Exceptions$" 13,10,"The processor supports the" CMPXCHG8B instruction$" 13,10,"The processor contains on-chip" APIC$" 13,10,"The processor supports Fast System" Call$" 13,10,"The processor does support Fast" System Call$" 13,10,"The processor supports Memory Type" Range Registers$" 13,10,"The processor supports Page Global"
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Enable$" 13,10,"The processor supports Machine" Check Architecture$" 13,10,"The processor supports Conditional" Move Instruction$" 13,10,"The processor supports Page Attribute" Table$" 13,10,"The processor supports 36-bit Page" Size Extension$" 13,10,"The processor supports the" processor serial number$" 13,10,"The processor supports the" CLFLUSH instruction$" 13,10,"The processor supports the" Debug Trace Store feature$" 13,10,"The processor supports the" ACPI registers space$" 13,10,"The processor supports Intel Architecture" MMX(TM) Technology$" 13,10,"The processor supports Fast floating point" save restore$" 13,10, "The processor supports Streaming" SIMD extensions$" 13,10,"The processor supports Streaming" SIMD extensions instructions$" 13,10, "The processor supports Self-Snoop$" 13,10,"The processor supports the" Thermal Monitor$" least 80486 processor." 13,10,"It does contain Genuine" "Intel part result," "the",13,10,"CPUID" detection information cannot determined this time.$"
mca_msg cmov_msg pat_msg pse36_msg psnum_msg clflush_msg dts_msg acpi_msg mmx_msg fxsr_msg sse_msg sse2_msg ss_msg tm_msg
not_intel
ASC_MSG LOCAL ascii_done: ENDM .code .8086 print proc
MACRO ascii_done ascii_done byte msg[20], offset
local label 0-9?
This procedure prints appropriate cpuid string numeric processor presence status. CPUID instruction used, this procedure prints CPUID info. registers used this procedure, none preserved. offset id_msg print initial message
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print_86: print_286: print_287: print_386: print_486: print_486sx:
_cpuid_flag, print_cpuid_data processor supports CPUID instruction print detailed CPUID info
_cpu_type, print_286 offset cp_8086 _fpu_type, end_print offset fp_8087 end_print
_cpu_type, print_386 offset cp_286 _fpu_type, end_print
offset fp_287 end_print
_cpu_type, print_486 offset cp_386 _fpu_type, end_print _fpu_type, print_287 offset fp_387 end_print
_cpu_type, print_unknown offset cp_486sx _fpu_type, print_486sx offset cp_486
Intel processors will have CPUID instruction
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print_unknown: end_print
offset cp_error print_486sx
print_cpuid_data: .486 _intel_CPU, not_GenuineIntel skip_spaces: loop offset _brand_string byte [di], print_brand_id
check genuine Intel processor brand string supported?
brand string length
byte [di], print_brand_string skip_spaces
skip leading space chars
print_brand_string: print_brand_id byte [di], print_brand_id print_brand_char: [di] loop print_brand_id: print_486_type: byte [di], print_family print_brand_char print_family
Nothing print
print upto chars
_cpu_type, print_486_type print_pentiumiiimodel8_type eax, dword _cpu_signature eax, print_pentiumiiimodel8_type
_cpu_type, print 80486 processor print_pentium_type eax, dword _cpu_signature eax, eax, isolate model intel_486_0[eax*2] print_common
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print_pentium_type: _cpu_type, print_pentiumpro_type offset pentium_msg print_common print_pentiumpro_type: _cpu_type,
print Pentium processor
model print Pentium processor
print_unknown_type eax, dword _cpu_signature eax, eax, isolate model eax, print_pentiumiimodel3_type eax, print_unknown_type incorrect model number offset pentiumpro_msg print_common
print_pentiumiimodel3_type: eax,
model print Pentium processor, model
print_pentiumiimodel5_type offset pentiumiimodel3_msg print_common
print_pentiumiimodel5_type: eax,
model either Pentium processor, model Pentium Xeon processor Intel Celeron processor, model
celeron_xeon_detect eax, model check cache descriptors determine Pentium Pentium Xeon
print_celeronmodel6_type celeron_xeon_detect: Pentium processor, model Pentium Xeon processor, Intel Celeron processor, Pentium processor Pentium Xeon processor. eax, dword _cache_eax eax,
celeron_detect_eax: print_celeron_type print_pentiumiixeon_type loop eax, celeron_detect_eax eax, dword _cache_ebx
celeron_detect_ebx: print_celeron_type
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loop print_pentiumiixeon_type eax, celeron_detect_ebx eax, dword _cache_ecx
celeron_detect_ecx: print_celeron_type print_pentiumiixeon_type loop eax, celeron_detect_ecx eax, dword _cache_edx
celeron_detect_edx: print_celeron_type print_pentiumiixeon_type loop eax, celeron_detect_edx
offset pentiumiixeon_m5_msg eax, dword _cpu_signature eax, eax, isolate model eax, print_common offset pentiumiii_msg print_common
print_celeron_type: offset celeron_msg print_common print_pentiumiixeon_type: offset pentiumiixeon_msg word _cpu_signature eax, isolate model eax, print_common offset pentiumiiixeon_msg print_common print_celeronmodel6_type: eax,
model print Intel Celeron processor, model
print_pentiumiiimodel8_type offset celeronmodel6_msg print_common
print_pentiumiiimodel8_type:
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next_brand: loop brand_found: eax, print_unknown_type eax, dword _features_ebx brand_id supported? print_unknown_type offset brand_table brand_table_size Setup pointer brand_id table maximum entry count Pentium processor, model Pentium Xeon processor, model
byte [di] brand_found sizeof brand_entry next_brand print_unknown_type
this brand reported processor
Point next Brand Defined Check next brand table exhausted
word [di+1] print_common
Load with offset brand string
print_unknown_type: offset unknown_msg print_common: print family, model, stepping print_family: _cpu_type ASC_MSG family_msg push
neither, print unknown
print family
eax, dword _cpu_signature Check Extended Family print_model offset ext_fam_msg eax, Copy extended family into 0f0fh Convert upper nibble ascii Convert lower nibble ascii print upper nibble family print lower nibble family
print_model: eax, dword _cpu_signature ASC_MSG model_msg print model
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eax, dword _cpu_signature 0f0h Check Extended Model 0f0h print_stepping offset ext_mod_msg eax, Convert extended model ascii print lower nibble family
print_stepping: eax, dword _cpu_signature ASC_MSG stepping_msg print stepping print_upgrade: test check_dp: test print_features: check_VME: check_DE: check_PSE:
eax, dword _cpu_signature 1000h check turbo upgrade check_dp offset turbo_msg print_features
2000h print_features offset dp_msg
check dual processor
eax, dword _features_edx eax, FPU_FLAG check check_VME offset fpu_msg
eax, dword _features_edx eax, VME_FLAG check check_DE offset vme_msg
eax, dword _features_edx eax, DE_FLAG check check_PSE offset de_msg
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check_TSC: check_MSR: check_PAE: check_MCE: check_CX8: check_APIC: check_SEP:
eax, dword _features_edx eax, PSE_FLAG check check_TSC offset pse_msg
eax, dword _features_edx eax, TSC_FLAG check check_MSR offset tsc_msg
eax, dword _features_edx eax, MSR_FLAG check check_PAE offset msr_msg
eax, dword _features_edx eax, PAE_FLAG check check_MCE offset pae_msg
eax, dword _features_edx eax, MCE_FLAG check check_CX8 offset mce_msg
eax, dword _features_edx eax, CX8_FLAG check CMPXCHG8B check_APIC offset cx8_msg
eax, dword _features_edx eax, APIC_FLAG check APIC check_SEP offset apic_msg
eax, dword _features_edx eax, SEP_FLAG Check Fast System Call check_MTRR _cpu_type, Determine Fast System
AP-485
print_sep: print_no_sep: check_MTRR: check_PGE: check_MCA: check_CMOV: check_PAT: check_PSE36: print_sep Calls supported.
eax, dword _cpu_signature print_no_sep
offset sep_msg check_MTRR
offset no_sep_msg
eax, dword _features_edx eax, MTRR_FLAG check MTRR check_PGE offset mtrr_msg
eax, dword _features_edx eax, PGE_FLAG check check_MCA offset pge_msg
eax, dword _features_edx eax, MCA_FLAG check check_CMOV offset mca_msg
eax, dword _features_edx eax, CMOV_FLAG check CMOV check_PAT offset cmov_msg
eax, dword _features_edx eax, PAT_FLAG check_PSE36 offset pat_msg
eax, dword _features_edx eax, PSE36_FLAG check_PSNUM
AP-485
check_PSNUM: check_CLFLUSH: check_DTS: check_ACPI: check_MMX: check_FXSR: check_SSE: check_SSE2:
offset pse36_msg
eax, dword _features_edx eax, PSNUM_FLAG check processor serial number check_CLFLUSH offset psnum_msg
eax, dword _features_edx eax, CLFLUSH_FLAG check Cache Line Flush check_DTS offset clflush_msg
eax, dword _features_edx eax, DTS_FLAG check Debug Trace Store check_ACPI offset dts_msg
eax, dword _features_edx eax, ACPI_FLAG check processor serial number check_MMX offset acpi_msg
eax, dword _features_edx eax, MMX_FLAG check technology check_FXSR offset mmx_msg
eax, dword _features_edx eax, FXSR_FLAG check FXSR check_SSE offset fxsr_msg
eax, dword _features_edx eax, SSE_FLAG check Streaming SIMD check_SSE2 Extensions offset sse_msg
AP-485
check_SS: check_TM: eax, dword _features_edx eax, SSE2_FLAG check Streaming SIMD check_SS Extensions offset sse2_msg
eax, dword _features_edx eax, SS_FLAG check Self Snoop check_dx, offset ss_msg
eax, dword _features_edx eax, TM_FLAG check Thermal Monitor end_print offset tm_msg end_print
not_GenuineIntel: offset not_intel end_print: print endp start
offset cr_lf
AP-485
Example Processor Identification Procedure Language FILENAME: CPUID3.C Copyright(c) 1994 2001 Intel Corp. This program been developed Intel Corporation. Intel various intellectual property rights which assert under certain circumstances, such another manufacturer's processor mis-identifies itself being "GenuineIntel" when CPUID instruction executed. Intel specifically disclaims warranties, express implied, liability, including consequential other indirect damages, this program, including liability infringement proprietary rights, including warranties merchantability fitness particular purpose. Intel does assume responsibility errors which appear this program responsibility update This program contains three parts: Part Identifies type variable _cpu_type: Part Identifies type variable _fpu_type: Part Prints appropriate message. This program been tested with Microsoft Developer Studio. this code compiled with options specified linked with cpuid3a module, correctly identifies current Intel 8086/8088, 80286, 80386, 80486, Pentium(R), Pentium(R) Pro, Pentium(R) Pentium(R) Xeon, Pentium(R) OverDrive(R), Intel(R) Celeron, Pentium(R) processors, Pentium(R) Xeon(TM) processors, Pentium(R) processors Intel(R) Xeon(TM) processors #define FPU_FLAG #define VME_FLAG #define DE_FLAG #define PSE_FLAG #define TSC_FLAG #define MSR_FLAG #define PAE_FLAG #define MCE_FLAG #define CX8_FLAG #define APIC_FLAG #define SEP_FLAG #define MTRR_FLAG #define PGE_FLAG #define MCA_FLAG #define CMOV_FLAG #define PAT_FLAG #define PSE36_FLAG #define PSNUM_FLAG #define CLFLUSH_FLAG #define DTS_FLAG #define ACPI_FLAG #define MMX_FLAG #define FXSR_FLAG #define SSE_FLAG
0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 0x0800 0x1000 0x2000 0x4000 0x8000 0x10000 0x20000 0x40000 0x80000 0x200000 0x400000 0x800000 0x1000000 0x2000000
AP-485
#define SSE2_FLAG #define SS_FLAG #define TM_FLAG 0x4000000 0x8000000 0x20000000
extern char cpu_type; extern char fpu_type; extern char cpuid_flag; extern char intel_CPU; extern char vendor_id[12]; extern long cpu_signature; extern long features_ecx; extern long features_edx; extern long features_ebx; extern long cache_eax; extern long cache_ebx; extern long cache_ecx; extern long cache_edx; extern char brand_string[48]; extern brand_id; long cache_temp; long celeron_flag; long pentiumxeon_flag; struct brand_entry long brand_value; char *brand_string; #define brand_table_size struct brand_entry brand_table[brand_table_size] 0x01, Genuine Intel(R) Celeron(TM) processor", 0x02, Genuine Intel(R) Pentium(R) processor", 0x03, Genuine Intel(R) Pentium(R) Xeon(TM) processor", 0x04, Genuine Intel(R) Pentium(R) processor", 0x08, Genuine Intel(R) Pentium(R) processor", 0x0E, Genuine Intel(R) Xeon(TM) processor"
main() get_cpu_type(); get_fpu_type(); print(); return(0); print()
brand_index
printf("This system a"); (cpuid_flag switch (cpu_type) case printf("n 8086/8088 processor"); (fpu_type) printf(" 8087 math coprocessor"); break; case printf("n 80286 processor");
AP-485
(fpu_type) printf(" 80287 math coprocessor"); break; case printf("n 80386 processor"); (fpu_type printf(" 80287 math coprocessor"); else (fpu_type) printf(" 80387 math coprocessor"); break; case (fpu_type) printf("n 80486DX, 80486DX2 processor 80487SX math coprocessor"); else printf("n 80486SX processor"); break; default: printf("n unknown processor"); else using cpuid instruction (intel_CPU) (brand_string[0]) brand_index while ((brand_string[brand_index] (brand_index 48)) brand_index++; (brand_index printf(" %s", &brand_string[brand_index]); else (cpu_type switch ((cpu_signature>>4) 0xf) case case printf(" Genuine Intel486(TM) processor"); break; case printf(" Genuine Intel486(TM) processor"); break; case printf(" Genuine IntelDX2(TM) processor"); break; case printf(" Genuine Intel486(TM) processor"); break; case printf(" Genuine IntelSX2(TM) processor"); break; case printf(" Genuine Write-Back Enhanced IntelDX2(TM) processor"); break; case printf(" Genuine IntelDX4(TM) processor"); break; default: printf(" Genuine Intel486(TM) processor"); else (cpu_type printf(" Genuine Intel Pentium(R) processor"); else ((cpu_type (((cpu_signature 0xf)
AP-485
printf(" Genuine Intel Pentium(R) processor"); else ((cpu_type (((cpu_signature 0xf) printf(" Genuine Intel Pentium(R) processor, model 3"); else (((cpu_type (((cpu_signature 0xf) ((cpu_type (((cpu_signature 0xf) 7))) celeron_flag pentiumxeon_flag cache_temp cache_eax 0xFF000000; (cache_temp 0x40000000) celeron_flag ((cache_temp 0x44000000) (cache_temp 0x45000000)) pentiumxeon_flag cache_temp cache_eax 0xFF0000; (cache_temp 0x400000) celeron_flag ((cache_temp 0x440000) (cache_temp 0x450000)) pentiumxeon_flag cache_temp cache_eax 0xFF00; (cache_temp 0x4000) celeron_flag ((cache_temp 0x4400) (cache_temp 0x4500)) pentiumxeon_flag cache_temp cache_ebx 0xFF000000; (cache_temp 0x40000000) celeron_flag ((cache_temp 0x44000000) (cache_temp <=0x45000000)) pentiumxeon_flag cache_temp cache_ebx 0xFF0000; (cache_temp 0x400000) celeron_flag ((cache_temp 0x440000) (cache_temp 0x450000)) pentiumxeon_flag cache_temp cache_ebx 0xFF00; (cache_temp 0x4000) celeron_flag ((cache_temp 0x4400) (cache_temp 0x4500)) pentiumxeon_flag cache_temp cache_ebx 0xFF; (cache_temp 0x40) celeron_flag ((cache_temp 0x44) (cache_temp 0x45)) pentiumxeon_flag cache_temp cache_ecx 0xFF000000; (cache_temp 0x40000000) celeron_flag ((cache_temp 0x44000000) (cache_temp 0x45000000)) pentiumxeon_flag cache_temp cache_ecx 0xFF0000; (cache_temp 0x400000) celeron_flag ((cache_temp 0x440000) (cache_temp 0x450000)) pentiumxeon_flag
AP-485
cache_temp cache_ecx 0xFF00; (cache_temp 0x4000) celeron_flag ((cache_temp 0x4400) (cache_temp 0x4500)) pentiumxeon_flag cache_temp cache_ecx 0xFF; (cache_temp 0x40) celeron_flag ((cache_temp 0x44) (cache_temp 0x45)) pentiumxeon_flag cache_temp cache_edx 0xFF000000; (cache_temp 0x40000000) celeron_flag ((cache_temp 0x44000000) (cache_temp 0x45000000)) pentiumxeon_flag cache_temp cache_edx 0xFF0000; (cache_temp 0x400000) celeron_flag ((cache_temp 0x440000) (cache_temp 0x450000)) pentiumxeon_flag cache_temp cache_edx 0xFF00; (cache_temp 0x4000) celeron_flag ((cache_temp 0x4400) (cache_temp 0x4500)) pentiumxeon_flag cache_temp cache_edx 0xFF; (cache_temp 0x40) celeron_flag ((cache_temp 0x44) (cache_temp 0x45)) pentiumxeon_flag (celeron_flag printf(" Genuine Intel Celeron(TM) processor, model 5"); else (pentiumxeon_flag (((cpu_signature 0x0f) printf(" Genuine Intel Pentium(R) Xeon(TM) processor"); else printf(" Genuine Intel Pentium(R) Xeon(TM) processor,"); printf(" model 7"); else (((cpu_signature 0x0f) printf(" Genuine Intel Pentium(R) processor, model printf("or Intel Pentium(R) Xeon processor"); else printf(" Genuine Intel Pentium(R) processor, model 7"); printf(" Intel Pentium(R) Xeon(TM) processor,"); printf(" model 7");
AP-485
else ((cpu_type (((cpu_signature 0xf) printf(" Genuine Intel Celeron(TM) processor, model 6"); else ((features_ebx 0xff) while ((brand_index brand_table_size) ((features_ebx 0xff) brand_index++; (brand_index brand_table_size) printf("%s", else printf("n unknown Genuine Intel processor"); else printf("n unknown Genuine Intel processor"); printf("\nProcessor Family: %X", cpu_type); (cpu_type 0xf) printf("\n Extended Family: %x",(cpu_signature>>20)&0xff); printf("\nModel: %X", (cpu_signature>>4)&0xf); (((cpu_signature>>4) 0xf) 0xf) printf("\n Extended Model: %x",(cpu_signature>>16)&0xf); printf("\nStepping: %X\n", cpu_signature&0xf); (cpu_signature 0x1000) printf("\nThe processor OverDrive(R) processor"); else (cpu_signature 0x2000) printf("\nThe processor upgrade processor dual processor system"); (features_edx FPU_FLAG) printf("\nThe processor contains on-chip FPU"); (features_edx VME_FLAG) printf("\nThe processor supports Virtual Mode Extensions"); (features_edx DE_FLAG) printf("\nThe processor supports Debugging Extensions"); (features_edx PSE_FLAG) printf("\nThe processor supports Page Size Extensions"); (features_edx TSC_FLAG) printf("\nThe processor supports Time Stamp Counter"); (features_edx MSR_FLAG) printf("\nThe processor supports Model Specific Registers"); (features_edx PAE_FLAG) printf("\nThe processor supports Physical Address Extension"); (features_edx MCE_FLAG) printf("\nThe processor supports Machine Check Exceptions"); (features_edx CX8_FLAG) printf("\nThe processor supports CMPXCHG8B instruction"); (features_edx APIC_FLAG) printf("\nThe processor contains on-chip APIC"); (features_edx SEP_FLAG) ((cpu_type ((cpu_signature 0xff) 0x33)) printf("\nThe processor does support Fast System Call"); else printf("\nThe processor supports Fast System Call"); (features_edx MTRR_FLAG) printf("\nThe processor supports Memory Type Range Registers"); (features_edx PGE_FLAG) printf("\nThe processor supports Page Global Enable"); (features_edx MCA_FLAG) printf("\nThe processor supports Machine Check Architecture"); (features_edx CMOV_FLAG) printf("\nThe processor supports Conditional Move Instruction"); (features_edx PAT_FLAG)
AP-485
printf("\nThe processor supports Page Attribute Table"); (features_edx PSE36_FLAG) printf("\nThe processor supports 36-bit Page Size Extension"); (features_edx PSNUM_FLAG) printf("\nThe processor supports processor serial number"); (features_edx CLFLUSH_FLAG) printf("\nThe processor supports CLFLUSH instruction"); (features_edx DTS_FLAG) printf("\nThe processor supports Debug Trace Store feature"); (features_edx ACPI_FLAG) printf("\nThe processor supports ACPI registers space"); (features_edx MMX_FLAG) printf("\nThe processor supports Intel Architecture MMX(TM) technology"); (features_edx FXSR_FLAG) printf("\nThe processor supports Fast floating point save restore"); (features_edx SSE_FLAG) printf("\nThe processor supports Streaming SIMD extensions Intel Architecture"); (features_edx SSE2_FLAG) printf("\nThe processor supports Streaming SIMD extensions instructions"); (features_edx SS_FLAG) printf("\nThe processor supports Self-Snoop"); (features_edx TM_FLAG) printf("\nThe processor supports Thermal Monitor"); else printf("t least 80486 processor. printf("\nIt does contain Genuine Intel part result, printf("\nCPUID detection information cannot determined this time."); printf("\n"); return(0);
AP-485
Example Instruction Extension Detection Using Exception Handlers FILENAME: FEATURES.CPP Copyright(c) 2000 2001 Intel Corp. This program been developed Intel Corporation. Intel various intellectual property rights which assert under certain circumstances, such another manufacturer's processor mis-identifies itself being "GenuineIntel" when CPUID instruction executed. Intel specifically disclaims warranties, express implied, liability, including consequential other indirect damages, this program, including liability infringement proprietary rights, including warranties merchantability fitness particular purpose. Intel does assume responsibility errors which appear this program responsibility update #include "stdio.h" #include "string.h" #include "excpt.h" follow code sample demonstrate using exception handlers identify available IA-32 features, sample code Identifies IA-32 features such support Streaming SIMD Extensions (SSE2), support Streaming SIMD Extensions (SSE), support (TM) instructions. This technique used safely determined IA-32 features provide forward compatibility optimally future IA-32 processors. Please note that technique trapping invalid opcodes suitable identifying processor family model. main(int argc, char* argv[]) char sSupportSSE2[80]="Don't know"; char sSupportSSE[80]="Don't know"; char sSupportMMX[80]="Don't know"; identify whether SSE2, SSE, instructions supported compatible processor fashion that will compatible future IA-32 processors, following tests performed sequence: (This sample code will assume cpuid instruction supported target processor.) Test whether target processor Genuine Intel processor, Test executing SSE2 instruction would cause exception, exception occurs, SSE2 supported; exception occurs, Test executing instruction would cause exception, exception occurs, supported; exception occurs, Test executing instruction would cause exception, exception occurs, instruction supported, exception occurs, instruction supported this processor. clarity, following stub function "IsGenuineIntelProcessor()" shown this example, function "IsGenuineIntelProcessor()" adapted from sample code implementation assembly procedure "_get_cpu_type". purpose this stub function examine whether Vendor string, which returned when executing cpuid instruction with indicates processor genuine Intel processor. (IsGenuineIntelProcessor()) First, execute SSE2 instruction whether exception occurs
AP-485
_try _asm paddq xmm1, xmm2 strcpy(&sSupportSSE2[0], "Yes"); _except( EXCEPTION_EXECUTE_HANDLER SSE2 exception handler exception occurred when executing SSE2 instruction strcpy(&sSupportSSE2[0], "No"); Second, execute instruction whether exception occurs _try _asm orps xmm1, xmm2 strcpy(&sSupportSSE[0], "Yes"); _except( EXCEPTION_EXECUTE_HANDLER exception handler exception occurred when executing instruction strcpy(&sSupportSSE[0], "No"); Third, execute instruction whether exception occurs _try _asm emms technology strcpy(&sSupportMMX[0], "Yes"); _except( EXCEPTION_EXECUTE_HANDLER exception handler exception occurred when executing instruction strcpy(&sSupportMMX[0], "No"); printf("This Processor supports following instruction extensions: \n"); printf("SSE2 instruction: \t\t%s \n", &sSupportSSE2[0]); printf("SSE instruction: \t\t%s \n", &sSupportSSE[0]); printf("MMX instruction: \t\t%s \n", &sSupportMMX[0]); return exception executing instruction this instruction available this instruction available exception executing instruction this instruction available SSE2 exception executing SSE2 instruction
AP-485
Example Detecting Denormals-Are-Zero Support Filename: DAZDTECT.ASM Copyright(c) 2001 Intel Corp. This program been developed Intel Corporation. Intel various intellectual property rights which assert under certain circumstances, such another manufacturer's processor mis-identifies itself being "GenuineIntel" when CPUID instruction executed. Intel specifically disclaims warranties, express implied, liability, including consequential other indirect damages, this program, including liability infringement proprietary rights, including warranties merchantability fitness particular purpose. Intel does assume responsibility errors which appear this program responsibility update This example assumes system booted DOS. This program runs Real mode. This program performs following steps determine processor supports SSE/SSE2 mode. Step Execute CPUID instruction with input value EAX=0 ensure vendor-ID string returned "GenuineIntel". Step Execute CPUID instruction with EAX=1. This will load register with feature flags. Step Ensure that FXSR feature flag (EDX set. This indicates processor supports FXSAVE FXRSTOR instructions. Step Ensure that feature flag (EDX feature flag (EDX set. This indicates that processor supports least SSE/SSE2 instruction sets MXCSR control register. Step Zero 16-byte aligned, 512-byte area memory. This necessary since some implementations FXSAVE modify reserved areas within image. Step Execute FXSAVE into cleared area. Step Bytes 28-31 FXSAVE image defined contain MXCSR_MASK. this value then processor's MXCSR_MASK 0xFFBF, otherwise MXCSR_MASK value this dword. Step MXCSR_MASK set, then supported. .DOSSEG .MODEL small, .STACK
AP-485
Data segment .DATA buffer not_intel noSSEorSSE2 no_FXSAVE daz_mask_clear no_daz supports_daz 512+16 "This Genuine Intel processor.", 0Dh, 0Ah, "Neither SSE2 extensions supported.", 0Dh, 0Ah, "FXSAVE supported.", 0Dh, 0Ah, "DAZ MXCSR_MASK zero (clear).", 0Dh, 0Ah, "DAZ mode supported.", 0Dh, 0Ah, "DAZ mode supported.", 0Dh, 0Ah,
Code segment .CODE .686p .XMM dazdtect PROC NEAR .startup Allow assembler create code that initializes stack data segment registers
Step ;Verify Genuine Intel processor checking CPUID generated vendor cpuid Step feature flags Verify FXSAVE either SSE2 supported cpuid eax, edx, noFxsave edx, sse_or_sse2_supported edx, no_sse_sse2 Feature Flags FXSAVE support jump FXSAVE supported Feature Flags support jump supported Feature Flags SSE2 support jump SSE2 supported eax,
ebx, 'uneG' notIntelprocessor edx, 'Ieni' notIntelprocessor ecx, 'letn' notIntelprocessor
Compare first letters Vendor Jump Genuine Intel processor Compare next letters Vendor Jump Genuine Intel processor Compare last letters Vendor Jump Genuine Intel processor
sse_or_sse2_supported:
AP-485
FXSAVE requires 16-byte aligned buffer offset into buffer Step Clear buffer that will used FXSAVE data push Step fxsave Step eax, DWORD [bx][28t] MXCSR_MASK eax, Check valid mask check_mxcsr_mask eax, 0FFBFh Force default MXCSR_MASK [bx] 512/2 stosw Fill FXSAVE buffer with zeroes OFFSET buffer 0FFF0h offset buffer into aligned 16-byte boundary
check_mxcsr_mask: contains MXCSR_MASK from FXSAVE buffer default mask Step supported: eax, supported OFFSET daz_mask_clear notSupported MXCSR_MASK support Jump supported
OFFSET supports_daz print
Indicate supported.
notIntelProcessor: OFFSET not_intel print no_sse_sse2: noFxsave: notSupported:
Assume Intel processor
OFFSET noSSEorSSE2 Setup error message assuming SSE/SSE2 notSupported
OFFSET no_FXSAVE
Execute print string function
AP-485
print: exit: .exit dazdtect ENDP Allow assembler generate code that returns control Execute print string function OFFSET no_daz
AP-485
Example Frequency Calculation Filename: FREQUENC.ASM Copyright(c) 2001 Intel Corp. This program been developed Intel Corporation. Intel various intellectual property rights which assert under certain circumstances, such another manufacturer's processor mis-identifies itself being "GenuineIntel" when CPUID instruction executed. Intel specifically disclaims warranties, express implied, liability, including consequential other indirect damages, this program, including liability infringement proprietary rights, including warranties merchantability fitness particular purpose. Intel does assume responsibility errors which appear this program responsibility update This example assumes system booted DOS. This program runs Real mode. This program assembled using MASM 6.14.8444 tested system with Pentium(r) processor, system with Pentium(r) processor, system with Pentium(r) processor, stepping, system with Pentium(r) processor, stepping. This program performs following steps determine actual processor frequency. Step Execute CPUID instruction with input value EAX=0 ensure vendor-ID string returned "GenuineIntel". Step Execute CPUID instruction with EAX=1 load register with feature flags. Step Ensure that feature flag (EDX set. This indicates processor supports Time Stamp Counter RDTSC instruction. Step Read beginning reference period Step Read reference period. Step Compute delta from beginning ending reference period. Step Compute actual frequency dividing delta reference period. .DOSSEG .MODEL small, pascal .STACK ;4096 wordToDec PROTO NEAR PASCAL decAddr:WORD, hexData:WORD Macro printst This macro used print string passed input parameter word value immediately after string.
AP-485
string delared data segment routine during assembly time. word converted ascii printed after string. Input: stringData string printed. wordData word converted ascii printed Destroys: None Output: None Assumes: Stack available ;-printst MACRO stringdata, hexWord local stringlabel, decData .data stringlabel decData stringdata 0dh, 0ah,
.code pushf pusha Convert word ascii store string invoke wordToDec, offset decData, hexWord popa popf ENDM offset stringlabel Setup string printed Execute print function
SEG_BIOS_DATA_AREA OFFSET_TICK_COUNT INTERVAL_IN_TICKS
Data segment .DATA
Code segment .CODE .686p cpufreq PROC NEAR local tscLoDword:DWORD, tscHiDword:DWORD, mhz:WORD,\ Nearest66Mhz:WORD,\
AP-485
Nearest50Mhz:WORD,\ delta66Mhz:WORD
.startup
Allow assembler create code that initializes stack data segment registers
Step ;Verify Genuine Intel processor checking CPUID generated vendor cpuid Step feature flags Verify supported cpuid push eax, edx, exit SEG_BIOS_DATA_AREA OFFSET_TICK_COUNT ebx, DWORD es:[si] Flags support jump supported eax,
ebx, 'uneG' exit edx, 'Ieni' exit ecx, 'letn' exit
Check VendorID GenuineIntel Jump Genuine Intel processor
BIOS tick count updateds 18.2 times second.
wait_for_new_tick: ebx, DWORD es:[si] wait_for_new_tick Step **Timed interval starts** Read time stamp rdtsc tscLoDword, tscHiDword, ebx, INTERVAL_IN_TICKS
Wait tick count change
Read save immediately after tick
time delay value ticks.
wait_for_elapsed_ticks: ebx, DWORD es:[si] wait_for_elapsed_ticks Step **Time interval ends**
Have delay?
Read time stamp immediatly after tick delay reached. rdtsc
AP-485
Step Step 54945 18.2) 1,000,000 This adjusts MHz. 54945*INTERVAL_IN_TICKS adjusts number ticks interval ebx, 54945*INTERVAL_IN_TICKS eax, tscLoDword edx, tscHiDword Calculate delta from beginning interval
contains measured speed mhz, Find nearest full/half multiple 66/133 100t 200t contains nearest full/half multiple 66/100 delta66: contains delta between actual nearest 66/133 multiple Delta66Mhz, Find nearest full/half multiple contains nearest full/half multiple delta50: contains delta between actual nearest 50/100 multiple
Nearest66Mhz, delta66
abs(ax)
Nearest50Mhz, delta50
abs(ax)
Nearest50Mhz Delta66Mhz
AP-485
useNearest50Mhz Nearest66Mhz
Correction (should reported MHZ) correct666 correct666: useNearest50MHz: contains nearest full/half multiple 66/100/133 printst "Reported printst "Measured exit: .exit cpufreq ENDP Procedure wordToDec This routine will convert word value into byte decimal ascii string. Input: decAddr address byte location converted string (near address assumes segment) hexData word value converted ascii Destroys: Output: byte converted string Assumes: Stack available ;-wordToDec PROC NEAR PUBLIC uses decAddr:WORD, hexData:WORD pusha push stosb stosb returns control
print decimal value
decAddr @data hexData 10000t
ES:DI 5-byte converted string
1000t
AP-485
stosb stosb stosb popa wordToDec
100t
ENDP
AP-485
UNITED STATES, Intel Corporation 2200 Mission College Blvd., P.O. 58119, Santa Clara, 95052-8119 Tel: 765-8080 JAPAN, Intel Japan K.K. Tokodai, Tsukuba-shi, Ibaraki-ken 300-26 Tel: 81-29847-8522 FRANCE, Intel Corporation S.A.R.L. Quai Grenelle, 75015 Paris Tel: 1-45717171 UNITED KINGDOM, Intel Corporation (U.K.) Ltd. Pipers Way, Swindon, Wiltshire, England Tel: 1-793-641440 GERMANY, Intel GmbH Dornacher Strasse 85622 Feldkirchen/ Muenchen Tel: 89/99143-0 HONG KONG, Intel Semiconductor Ltd. 32/F Pacific Place, Queensway, Central Tel: +852 2844-4555 CANADA, Intel Semiconductor Canada, Ltd. Attwell Drive, Suite Rexdale, Ontario Tel: +416 675-2438
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