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Intel Processor Identification and the CPUID Instruction

Order Number: 241618-018

AP-485 APPLICATION NOTE
Intel Processor Identification and the CPUID Instruction
June 2001
Order Number: 241618-018
AP-485 CONTENTS
PAGE 1 INTRODUCTION................................................................................... 6 1.1 Update Support .................................................................................. 6 DETECTING THE CPUID INSTRUCTION ............................................................... 6 OUTPUT OF THE CPUID INSTRUCTION ............................................................... 7 3.1 Vendor ID String................................................................................. 7 3.2 Processor Signature .............................................................................. 9 3.3 Feature Flags .................................................................................. 14 3.4 SYSENTER / SYSEXIT - SEP Features Bit ............................................................ 16 3.5 Cache Size, Format and TLB Information ............................................................. 16 3.6 Pentium® 4 Processor, Model 0 Output Example ....................................................... 18 PROCESSOR SERIAL NUMBER..................................................................... 18 4.1 Presence of Processor Serial Number ................................................................ 18 4.2 Forming the 96-bit Processor Serial Number ........................................................... 19 BRAND ID ...................................................................................... 19 BRAND STRING.................................................................................. 20 USAGE GUIDELINES.............................................................................. 20 PROPER IDENTIFICATION SEQUENCE ............................................................... 21 USAGE PROGRAM EXAMPLES ..................................................................... 22
10 ALTERNATE METHOD OF DETECTING FEATURES ..................................................... 23 11 DENORMALS ARE ZERO.......................................................................... 24 12 OPERATING FREQUENCY......................................................................... 24
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REVISION HISTORY Revision
-001 -002 -003 Original Issue. Modified Table 2, Intel486 and Pentium® Processor Signatures. Updated to accommodate new processor versions. Program examples modified for ease of use, section added discussing BIOS recognition for OverDrive® processors and feature flag information updated. Updated with Pentium Pro and OverDrive processors information. Modified Tables1, 3 and 5. Inserted Tables 6, 7 and 8. Inserted Sections 3.4. and 3.5. Added Figures 1 and 3. Added Footnotes 1 and 2. Modified Figure 2. Added Assembly code example in Section 4. Modified Tables 3, 5 and 7. Added two bullets in Section 5.0. Modified cpuid3b.ASM and cpuid3b.C programs to determine if processor features MMX technology. Modified Figure 6.0.
Revision History
Modified Table 3. Added reserved for future member of P6 family 3 / 97 of processors entry. Modified table header to reflect Pentium II processor family. Modified Table 5. Added SEP bit definition. Added Section 3.5. Added Section 3.7 and Table 9. Corrected references of P6 family to reflect correct usage. Modified cpuid3a.asm, cpuid3b.asm and cpuid3.c example code sections to check for SEP feature bit and to check for, and identify, the Pentium II processor. Added additional disclaimer related to designers and errata. Modified Table 2. Added Pentium II processor, model 5 entry. Modified existing Pentium II processor entry to read "Pentium II processor, model 3". Modified Table 5. Added additional feature bits, PAT and FXSR. Modified Table 7. Added entries 44h and 45h. Removed the note "Do not assume a value of 1 in a feature flag indicates that a given feature is present. For future feature flags, a value of 1 may indicate that the specific feature is not present" in section 4.0. Modified cpuid3b.asm and cpuid3.c example code section to check for, and identify, the Pentium II processor, model 5. Modified existing Pentium II processor code to print Pentium II processor, model 3. Added note to identify Intel Celeron processor, model 5 in section 3.2. Modified Table 2. Added Intel Celeron processor & Pentium® OverDrive® processor with MMX technology entry. Modified Table 5. Added additional feature bit, PSE-36. Modified cpuid3b.asm and cpuid3.c example code to check for, and identify, the Intel Celeron processor. Added note to identify Pentium II Xeon processor in section 3.2. Modified Table 2. Added Pentium II Xeon processor entry. Modified cpuid3b.asm and cpuid3.c example code to check for, and identify, the Pentium II Xeon processor. No Changes Modified Table 2. Added Intel Celeron processor, model 6 entry. Modified cpuid3b.asm and cpuid3.c example code to check for, and identify, the Intel Celeron processor, model 6. 12 / 98 1 / 98
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REVISION HISTORY Revision
Revision History
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1 INTRODUCTION
As the Intel Architecture evolves with the addition of new generations and models of processors (8086, 8088, Intel286, Intel386TM, Intel486TM, Pentium® processors, Pentium® OverDrive® processors, Pentium® processors with MMX technology, Pentium® OverDrive processors with MMX technology, Pentium® Pro processors, Pentium® II processors, Pentium® II Xeon processors, Pentium® II Overdrive® processors, Intel® Celeron processors, Pentium® III processors, Pentium® III Xeon processors, Pentium® 4 processors and Intel® Xeon processors), it is essential that Intel provide an increasingly sophisticated means with which software can identify the features available on each processor. This identification mechanism has evolved in conjunction with the Intel Architecture as follows:
1. 2. 3. Originally, Intel published code sequences that could detect minor implementation or architectural differences to identify processor generations. Later, with the advent of the Intel386 processor, Intel implemented processor signature identification that provided the processor family, model, and stepping numbers to software, but only upon reset. As the Intel Architecture evolved, Intel extended the processor signature identification into the CPUID instruction. The CPUID instruction not only provides the processor signature, but also provides information about the features supported by and implemented on the Intel processor.
The evolution of processor identification was necessary because, as the Intel Architecture proliferates, the computing market must be able to tune processor functionality across processor generations and models that have differing sets of features. Anticipating that this trend will continue with future processor generations, the Intel Architecture implementation of the CPUID instruction is extensible. This application note explains how to use the CPUID instruction in software applications, BIOS implementations, and various processor tools. By taking advantage of the CPUID instruction, software developers can create software applications and tools that can execute compatibly across the widest range of Intel processor generations and models, past, present, and future.
8086 Flags Register
Update Support
286 Flags Register
Intel386 Processor Ef lags Register
Intel486 Processor Ef lags Register
DETECTING THE CPUID INSTRUCTION
Pentium ® and subsequent IA32 Processor Ef lags Register Notes: 1) R - Intel Reserv ed 2) ID - CPUID Presence bit
Figure 1. Flag Register Evolution
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The POPF, POPFD, PUSHF, and PUSHFD instructions are used to access the Flags in Eflags register. The program examples at the end of this application note show how you use the PUSHFD instruction to read and the POPFD instruction to change the value of the ID flag.
OUTPUT OF THE CPUID INSTRUCTION
The CPUID instruction supports two sets of functions. The first set returns basic processor information. The second set returns extended processor information. Figure 2 summarizes the basic processor information output by the CPUID instruction. The output from the CPUID instruction is fully dependent upon the contents of the EAX register. This means, by placing different values in the EAX register and then executing CPUID, the CPUID instruction will perform a specific function dependent upon whatever value is resident in the EAX register (see Table 1). In order to determine the highest acceptable value for the EAX register input and CPUID functions that return the basic processor information, the program should set the EAX register parameter value to "0" and then execute the CPUID instruction as follows
MOV CPUID EAX, 00H
After the execution of the CPUID instruction, a return value will be present in the EAX register. Always use an EAX parameter value that is equal to or greater than zero and less than or equal to this highest EAX "returned" value. In order to determine the highest acceptable value for the EAX register input and CPUID functions that return the extended processor information, the program should set the EAX register parameter value to "80000000h" and then execute the CPUID instruction as follows
MOV CPUID EAX, 80000000H
After the execution of the CPUID instruction, a return value will be present in the EAX register. Always use an EAX parameter value that is equal to or greater than 80000000h and less than or equal to this highest EAX "returned" value. On current and future IA-32 processors, bit 31 in the EAX register will be clear when CPUID is executed with an input parameter greater then highest value for either set of functions, and when the extended functions are not supported. All other bit values returned by the processor in response to a CPUID instruction with EAX set to a value higher than appropriate for that processor are model specific and should not be relied upon.
Vendor ID String
In addition to returning the highest value in the EAX register, the Intel Vendor-ID string can be simultaneously verified as well. If the EAX register contains an input value of 0, the CPUID instruction also returns the vendor identification string in the EBX, EDX, and ECX registers (see Figure 2). These registers contain the ASCII string:
GenuineIntel
While any imitator of the Intel Architecture can provide the CPUID instruction, no imitator can legitimately claim that its part is a genuine Intel part. So the presence of the "GenuineIntel" string is an assurance that the CPUID instruction and the processor signature are implemented as described in this document. If the "GenuineIntel" string is not returned after execution of the CPUID instruction, do not rely upon the information described in this document to interpret the information returned by the CPUID instruction.
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Reserved (gray) Extended Family Extended Model Processor Type Family Code Model Number Stepping ID
Misc. Info Feature Flags
31 23 15 7 0 APIC ID Reserved chunks Brand ID EBX ECX Bit Array (reserved for future features) EDX Bit Array (Refer to Table 5)
Figure 2. CPUID Instruction Outputs
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Table 1. Information Returned by the CPUID Instruction Initial EAX Value
0H EAX EBX ECX EDX EAX
Information Provided about the Processor
ECX EDX 2H 3H EAX EBX ECX
EAX, EBX, ECX, EDX
80000000H 80000001H
EAX Maximum Input Value for Extended Function CPUID Information EBX, ECX, EDX Reserved EAX Extended Processor Signature and Extended Feature Bits (Currently Reserved.) EBX, ECX, EDX Reserved EAX Processor Brand String EBX, ECX, EDX Processor Brand String Continued EAX, EBX, ECX, EDX EAX, EBX, ECX, EDX Processor Brand String Continued Processor Brand String Continued
80000002H 80000003H 80000004H
Processor Signature
Beginning with the Intel486 processor family, the EDX register contains the processor identification signature after reset (see Figure 3). The processor identification signature is a 32-bit value. The processor signature is composed from 8 different bit fields. The fields in gray represent reserved bits, and should be masked out when utilizing the processor signature. The remaining 6 fields form the processor identification signature.
Extended Family
Extended Model
Family Code
Model Number
Stepping ID
Figure 3. EDX Register after RESET
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Table 2. Processor Type (Bit Positions 13 and 12) Value
Description
Original OEM processor
2 All Intel486 SL-enhanced and Write-Back enhanced processors are capable of executing the CPUID instruction. See Table 4.
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31 RESET EDX 15 11 7 3 0
Type Family Major Stepping Minor Stepping Intel Reserved. Do not define.
Figure 4. Processor Signature Format on Intel386 Processors Table 3. Intel386 Processor Signatures Type
Family
Major Stepping
0000 0000 0000 0000 0000 and 0001 0100
Minor Stepping
xxxx xxxx xxxx xxxx xxxx xxxx
Description
Intel386 DX processor Intel386 SX processor Intel386 CX processor Intel386 EX processor Intel386 SL processor RapidCAD® coprocessor
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Table 4. Intel486TM, and Subsequent Processor Signatures Extended Extended Family Model
00 00 00 00 00 00 00 00 00 0x 00 00 01 (4) 01 (4) 01 00 01
Family Code
Model Stepping Number ID
000x 0010 0011 0011 0011 0100 0101 0111 1000 1000 0001 0010 0001 0010 0011 0100 0100 xxxx (1) xxxx xxxx xxxx xxxx xxxx xxxx
Description
Intel486 DX processors Intel486 SX processors Intel487 processors IntelDX2 processors IntelDX2 OverDrive® processors Intel486 SL processor IntelSX2 processors Write-Back Enhanced IntelDX2 processors IntelDX4 processors IntelDX4 OverDrive processors Pentium® processors (60, 66) Pentium processors (75, 90, 100, 120, 133, 150, 166, 200) Pentium OverDrive processor for Pentium processor (60, 66) Pentium OverDrive processor for Pentium processor (75, 90, 100, 120, 133) Pentium OverDrive processors for Intel486 processor-based systems Pentium processor with MMX technology (166, 200) Pentium OverDrive processor with MMX technology for Pentium processor (75, 90, 100, 120, 133) Pentium Pro processor Pentium II processor, model 3 Pentium II processor, model 5, Pentium II Xeon processor, model 5, and Intel Celeron processor, model 5 Intel Celeron processor, model 6 Pentium III processor, model 7, and Pentium III Xeon processor, model 7 Pentium III processor, model 8, Pentium III Xeon processor, model 8, and Intel Celeron processor, model 8 Pentium III Xeon processor, model A Pentium III processor, model B Intel Pentium II OverDrive processor Intel Pentium 4 processor or Intel Xeon processor
xxxx (1)
xxxx (3)
xxxx (2)
xxxx (2) xxxx (2) xxxx (2) xxxx (2) xxxx (2)
xxxx (2) xxxx
xxxx (2)
xxxx (2) xxxx (2) xxxx (2)
1010 1011 0011 000x
xxxx (2) xxxx
xxxx (2) xxxx (2)
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NOTES:
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Feature Flags
Use the feature flags in your applications to determine which processor features are supported. By using the CPUID feature flags to determine processor features, your software can detect and avoid incompatibilities introduced by the addition or removal of processor features. Table 5. Feature Flag Values Reported in the EDX Register Bit
FPU VME DE
Floating-point unit onChip Virtual Mode Extension Debugging Extension
Comments
The processor contains an FPU that supports the Intel387 floating-point instruction set. The processor supports extensions to virtual-8086 mode. The processor supports I / O breakpoints, including the CR4.DE bit for enabling debug extensions and optional trapping of access to the DR4 and DR5 registers. The processor supports 4-Mbyte pages. The RDTSC instruction is supported including the CR4.TSD bit for access / privilege control.
PSE TSC MSR PAE MCE CX8 APIC
Page Size Extension Time Stamp Counter
MTRR PGE
Memory Type Range Registers Page Global Enable
MCA CMOV
Machine Check Architecture Conditional Move Instruction Supported
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Table 5. Feature Flag Values Reported in the EDX Register Bit
Page Attribute Table
Comments
Indicates whether the processor supports the Page Attribute Table. This feature augments the Memory Type Range Registers (MTRRs), allowing an operating system to specify attributes of memory on 4K granularity through a linear address. Indicates whether the processor supports 4-Mbyte pages that are capable of addressing physical memory beyond 4GB. This feature indicates that the upper four bits of the physical address of the 4-Mbyte page is encoded by bits 13-16 of the page directory entry. The processor supports the 96-bit processor serial number feature, and the feature is enabled. Indicates that the processor supports the CLFLUSH instruction. Do not count on their value. Indicates that the processor has the ability to write a history of the branch to and from addresses into a memory buffer. The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control. The processor supports the MMX technology instruction set extensions to Intel Architecture. Indicates whether the processor supports the FXSAVE and FXRSTOR instructions for fast save and restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it uses the fast save / restore instructions. The processor supports the Streaming SIMD Extensions to the Intel Architecture. Indicates the processor supports the Streaming SIMD Extensions - 2 Instructions. The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus. Do not count on their value. The processor implements the Thermal Monitor automatic thermal control circuit (TCC). Do not count on their value.
PSE-36
36-bit Page Size Extension
PSN CLFSH
Processor serial number is present and enabled CLFLUSH Instruction supported Reserved Debug Store Thermal Monitor and Software Controlled Clock Facilities supported Intel Architecture MMX technology supported Fast floating point save and restore
DS ACPI
MMX FXSR
SSE SSE2 SS
Streaming SIMD Extensions supported Streaming SIMD Extensions 2 Self-Snoop
Reserved Thermal Monitor supported Reserved
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SYSENTER / SYSEXIT - SEP Features Bit
The SYSENTER Present (SEP) bit 11 of CPUID indicates the presence of this facility. An operating system that detects the presence of the SEP bit must also qualify the processor family and model to ensure that the SYSENTER / SYSEXIT instructions are actually present:
Cache Size, Format and TLB Information
Table 6. Descriptor Formats Register bit 31
Descriptor Type
Reserved
Description
Reserved for future use.
8 bit descriptors Descriptors point to a parameter table to identify cache characteristics. The descriptor is null if it has a 0 value.
Table 7 lists the current cache and TLB descriptor values and their respective characteristics. This list will be extended in the future as necessary. Between models and steppings of processors the cache and TLB information may change bit field locations, therefore it is important that software not assume fixed locations when parsing the cache and TLB descriptors.
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Table 7. Descriptor Decode Values Value
00h 01h 02h 03h 04h 06h 08h 0Ah 0Ch 40h 41h 42h 43h 44h 45h 50h 51h 52h 5Bh 5Ch 5Dh 66h 67h 68h 70h 71h 72h 79h 7Ah 7Bh 7Ch 82h 83h 84h 85h Null Instruction TLB, 4K pages, 4-way set associative, 32 entries Instruction TLB, 4M pages, fully associative, 2 entries Data TLB, 4K pages, 4-way set associative, 64 entries Data TLB, 4M pages, 4-way set associative, 8 entries Instruction cache, 8K, 4-way set associative, 32 byte line size Instruction cache 16K, 4-way set associative, 32 byte line size Data cache, 8K, 2-way set associative, 32 byte line size Data cache, 16K, 4-way set associative, 32 byte line size No L2 cache (P6 family), or No L3 cache (Pentium 4 processor) Unified cache, 32 byte cache line, 4-way set associative, 128K Unified cache, 32 byte cache line, 4-way set associative, 256K Unified cache, 32 byte cache line, 4-way set associative, 512K Unified cache, 32 byte cache line, 4-way set associative, 1M Unified cache, 32 byte cache line, 4-way set associative, 2M Instruction TLB, 4K, 2M or 4M pages, fully associative, 64 entries Instruction TLB, 4K, 2M or 4M pages, fully associative, 128 entries Instruction TLB, 4K, 2M or 4M pages, fully associative, 256 entries Data TLB, 4K or 4M pages, fully associative, 64 entries Data TLB, 4K or 4M pages, fully associative, 128 entries Data TLB, 4K or 4M pages, fully associative, 256 entries Data cache, sectored, 64 byte cache line, 4 way set associative, 8K Data cache, sectored, 64 byte cache line, 4 way set associative, 16K Data cache, sectored, 64 byte cache line, 4 way set associative, 32K Instruction Trace cache, 8 way set associative, 12K uOps Instruction Trace cache, 8 way set associative, 16K uOps Instruction Trace cache, 8 way set associative, 32K uOps Unified cache, sectored, 64 byte cache line, 8 way set associative, 128K Unified cache, sectored, 64 byte cache line, 8 way set associative, 256K Unified cache, sectored, 64 byte cache line, 8 way set associative, 512K Unified cache, sectored, 64 byte cache line, 8 way set associative, 1M Unified cache, 32 byte cache line, 8 way set associative, 256K Unified cache, 32 byte cache line, 8 way set associative, 512K Unified cache, 32 byte cache line, 8 way set associative, 1M Unified cache, 32 byte cache line, 8 way set associative, 2M
Cache or TLB Description
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3.6 Pentium® 4 Processor, Model 0 Output Example
(66h) A data cache that is 8K-Bytes, 4 way set associative, and has a sectored, 64 byte line size. (5Bh) A data TLB that maps 4K or 4M pages, is fully associative, and has 64 entries. (50h) An instruction TLB that maps 4K, 2M or 4M pages, is fully associative, and has 64 entries. (7Ah) A unified cache that is 256K-Bytes, 8 way set associative, and has a sectored, 64 byte line size. (70h) An instruction trace cache that can store up to 12K-uOps, and is 8 way set associative. (40h) No L3 cache.
31 EAX EBX ECX EDX 66h 00h 00h 00h 23 5Bh 00h 00h 7Ah 15 50h 00h 00h 70h 7 01h 00h 00h 40h 0
PROCESSOR SERIAL NUMBER
The processor serial number extends the concept of processor identification. Processor serial number is a 96-bit number accessible through the CPUID instruction. Processor serial number can be used by applications to identify a processor, and by extension, its system. The processor serial number creates a software accessible identity for an individual processor. The processor serial number, combined with other qualifiers, could be applied to user identification. Applications include membership authentication, data backup / restore protection, removable storage data protection, managed access to files, or to confirm document exchange between appropriate users. Processor serial number is another tool for use in asset management, product tracking, remote systems load and configuration, or to aid in boot-up configuration. In the case of system service, processor serial number could be used to differentiate users during help desk access, or track error reporting. Processor serial number provides an identifier for the processor, but should not be assumed to be unique in itself. There are potential modes in which erroneous processor serial numbers may be reported. For example, in the event a processor is operated outside its recommended operating specifications, (e.g. voltage, frequency, etc.) the processor serial number may not be correctly read from the processor. Improper BIOS or software operations could yield an inaccurate processor serial number. These events could lead to possible erroneous or duplicate processor serial numbers being reported. System manufacturers can strengthen the robustness of the feature by including redundancy features, or other fault tolerant methods. Processor serial number used as a qualifier for another independent number could be used to create an electrically accessible number that is likely to be distinct. Processor serial number is one building block useful for the purpose of enabling the trusted, connected PC.
Presence of Processor Serial Number
To determine if the processor serial number feature is supported, the program should set the EAX register parameter value to "1" and then execute the CPUID instruction as follows:
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MOV CPUID EAX, 01H
After execution of the CPUID instruction, the ECX and EDX register contains the Feature Flags. If the PSN Feature Flags, (EDX register, bit 18) equals "1", the processor serial number feature is supported, and enabled. If the PSN Feature Flags equals "0", the processor serial number feature is either not supported, or disabled.
Forming the 96-bit Processor Serial Number
The 96-bit processor serial number is the concatenation of three 32-bit entities. To access the most significant 32-bits of the processor serial number the program should set the EAX register parameter value to "1" and then execute the CPUID instruction as follows:
MOV CPUID EAX, 01H
After execution of the CPUID instruction, the EAX register contains the Processor Signature. The Processor Signature comprises the most significant 32-bits of the processor serial number. The value in EAX should be saved prior to gathering the remaining 64-bits of the processor serial number. To access the remaining 64-bits of the processor serial number the program should set the EAX register parameter value to "3" and then execute the CPUID instruction as follows:
MOV CPUID EAX, 03H
After execution of the CPUID instruction, the EDX register contains the middle 32-bits, and the ECX register contains the least significant 32-bits of the processor serial number. Software may then concatenate the saved Processor Signature, EDX, and ECX before returning the complete 96-bit processor serial number. Processor serial number should be displayed as 6 groups of 4 hex nibbles (Ex. XXXX-XXXX-XXXX-XXXXXXXX-XXXX where X represents a hex digit). Alpha hex characters should be displayed as capital letters.
BRAND ID
00h 01h 02h 03h 04h 08h 0Eh All other values Unsupported Intel® Celeron processor Intel® Pentium® III processor Intel® Pentium® III Xeon processor Intel® Pentium® III processor Intel® Pentium® 4 processor Intel® Xeon processor Reserved
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6 BRAND STRING
EAX input value
80000000h 80000001h 80000002h 80000003h 80000004h
Table 10. Processor Brand String Feature Function Return value
USAGE GUIDELINES
This document presents Intel-recommended feature-detection methods. Software should not try to identify features by exploiting programming tricks, undocumented features, or otherwise deviating from the guidelines presented in this application note. The following guidelines are intended to help programmers maintain the widest range of compatibility for their software.
Do not depend on the absence of an invalid opcode trap on the CPUID opcode to detect the CPUID instruction. Do not depend on the absence of an invalid opcode trap on the PUSHFD opcode to detect a 32-bit processor. Test the ID flag, as described in Section 2.0. and shown in Section 8. Do not assume that a given family or model has any specific feature. For example, do not assume the family value 5 (Pentium processor) means there is a floating-point unit on-chip. Use the feature flags for this determination. Do not assume processors with higher family or model numbers have all the features of a processor with a lower family or model number. For example, a processor with a family value of 6 (P6 family processor) may not necessarily have all the features of a processor with a family value of 5.
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PROPER IDENTIFICATION SEQUENCE
Determine if the CPUID instruction is supported by modifying the ID flag in the EFLAGS register. If the ID flag cannot be modified, the processor cannot be identified using the CPUID instruction. Execute the CPUID instruction with EAX equal to 80000000h. CPUID function 80000000h is used to determine if Brand String is supported. If the CPUID function 80000000h returns a value in EAX greater than 80000000h the Brand String feature is supported and software should use CPUID functions 80000002h through 80000004h to identify the processor. If the Brand String feature is not supported, execute CPUID with EAX equal to 1. CPUID function 1 returns the processor signature in the EAX register, and the Brand ID in the EBX register bits 0 through 7. If the EBX register bits 0 through 7 contain a non-zero value, the Brand ID is supported. Software should scan the list of Brand Ids (see Table 9) to identify the processor. If the Brand ID feature is not supported, software should use the processor signature (see Figure 2) in conjunction with the cache descriptors (see Table 7) to identify the processor.
To identify the processor using the CPUID instructions, software should follow the following steps.
The cpuid3a.asm program example demonstrates the correct use of the CPUID instruction (see Example 1). It also shows how to identify earlier processor generations that do not implement the Brand String, Brand ID, processor signature or CPUID instruction (see Figure 5). This program example contains the following two procedures:
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This procedure has been tested with 8086, 80286, Intel386, Intel486, Pentium processor, Pentium processor with MMX technology, OverDrive processor with MMX technology, Pentium Pro processors, Pentium II processors, Pentium II Xeon processors, Pentium II Overdrive processors, Intel Celeron processors, Pentium III processors, Pentium III Xeon processors and Pentium 4 processors. This program example is written in assembly language and is suitable for inclusion in a run-time library, or as system calls in operating systems.
USAGE PROGRAM EXAMPLES
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cpuid3b.ASM or cpuid3.C
cpuid3a.ASM
Processor features check
Print
Figure 6. Flow of Processor Identification Extraction Procedure
10 ALTERNATE METHOD OF DETECTING FEATURES
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11 DENORMALS ARE ZERO
With the introduction of the SSE2 extensions, some Intel Architecture processors have the ability to convert SSE and SSE2 source operand denormal numbers to zero. This feature is referred to as Denormals-Are-Zero (DAZ). The DAZ mode is not compatible with IEEE Standard 754. The DAZ mode is provided to improve processor performance for applications such as streaming media processing, where rounding a denormal operand to zero does not appreciably affect the quality of the processed data. Some processor steppings support SSE2 but do not support the DAZ mode. To determine if a processor supports the DAZ mode, software must perform the following steps.
12 OPERATING FREQUENCY
With the introduction of the Time Stamp Counter, it is possible for software operating in real mode or protected mode with ring 0 privilege to calculate the actual operating frequency of the processor. To calculate the operating frequency, the software needs a reference period. The reference period can be a periodic interrupt, or another timer that is based on time, and not based on a system clock. Software needs to read the Time Stamp Counter (TSC) at the beginning and ending of the reference period. Software can read the TSC by executing the RDTSC instruction, or by setting the ECX register to 10h and executing the RDMSR instruction. Both instructions copy the current 64-bit TSC into the EDX:EAX register pair. To determine the operating frequency of the processor, software performs the following steps. The assembly language program frequenc.asm (see Example 6) demonstrates the frequency detection algorithm.
Ensure that the TSC feature flag (EDX bit 4) is set. This indicates the processor supports the Time Stamp Counter and RDTSC instruction. Read the TSC at the beginning of the reference period Read the TSC at the end of the reference period. Compute the TSC delta from the beginning and ending of the reference period.
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7. Compute the actual frequency by dividing the TSC delta by the reference period.
Note: The measured accuracy is dependent on the accuracy of the reference period. A longer reference period produces a more accurate result. In addition, repeating the calculation multiple times may also improve accuracy.
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To assemble this code with TASM, add the JUMPS directive. jumps Uncomment this line for TASM
TITLE cpuid3a comment this line for 32-bit segments DOSSEG uncomment the following 2 lines for 32-bit segments .386
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comment this line for 32-bit segments .model small
Hardcoded CPUID instruction
"------" "GenuineIntel" 0 0 0 0 0 0 0 0 0 48 dup (0)
comment this line for 32-bit segments
uncomment this line for 32-bit segments .386
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Intel386 processor check The AC bit, bit #18, is a new bit introduced in the EFLAGS register on the Intel486 processor to generate alignment faults. This bit cannot be set on the Intel386 processor.
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eax ecx, eax eax, 40000h eax
Intel486 processor check Checking for ability to set / clear ID flag (Bit 21) in EFLAGS which indicates the presence of a processor with the CPUID instruction.
set up for CPUID instruction get and save vendor ID
if not equal, not an Intel processor indicate an Intel processor make sure 1 is valid input for CPUID
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mov mov mov mov
take jump if not supported
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save FP control word check FP control word selected parts to examine was control word correct incorrect control word, no FPU
80287 / 80387 check for the Intel386 processor
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store Intel287 NDP for FPU type see if infinities matched jump if 8087 or Intel287 is present store Intel387 NDP for FPU type
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This program has been tested with the Microsoft Developer Studio. If this code is assembled with no options specified and linked with the cpuid3a module, it correctly identifies the current Intel 8086 / 8088, 80286, 80386, 80486, Pentium(R), Pentium(R) Pro, Pentium(R) II processors, Pentium(R) II Xeon processors, Pentium II Overdrive processors, Intel Celeron(TM) processors, Pentium III processors, Pentium III Xeon processors, Pentium(R) 4 processors and Intel(R) Xeon(TM) processors when executed in the real-address mode.
cpuid3b
100h MACRO db 66h
hardcoded operand override
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The purpose of this code is to identify the processor and coprocessor that is currently in the system. The program first determines the processor type. Then it determines whether a coprocessor exists in the system. If a coprocessor or integrated coprocessor exists, the program identifies the coprocessor type. The program then prints the processor and floating point processors present and type.
equ 0001h equ 0002h equ 0004h equ 0008h equ 0010h equ 0020h equ 0040h equ 0080h equ 0100h equ 0200h equ 0800h equ 1000h equ 2000h equ 4000h equ 8000h equ 10000h equ 20000h equ 40000h
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Intel processors will have CPUID instruction
ah, 9h 21h
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max brand string length
skip leading space chars
Nothing to print
print upto the max chars
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if 5, print Pentium processor
if 6 & model 1, print Pentium Pro processor
if 6 & model 3, print Pentium II processor, model 3
if 6 & model 5, either Pentium II processor, model 5, Pentium II Xeon processor or Intel Celeron processor, model 5
je cmp
AP-485
if 6 & model 6, print Intel Celeron processor, model 6
AP-485
Is this the brand reported by the processor
Point to next Brand Defined Check next brand if the table is not exhausted
Load DX with the offset of the brand string
if neither, print unknown
print family msg
AP-485
mov and cmp jne mov mov int shr and add mov mov int
check for dual processor
AP-485
0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 0x0800 0x1000 0x2000 0x4000 0x8000 0x10000 0x20000 0x40000 0x80000 0x200000 0x400000 0x800000 0x1000000 0x2000000
AP-485