AK2548 channel Transceiver FEATURE transceiver Jitter Tolerance:

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AK2548 channel Transceiver FEATURE transceiver Jitter Tolerance:

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[AK2548]
AK2548 channel Transceiver
FEATURE transceiver Jitter Tolerance: Compliant with ITU-T G.823, I.431 Transmitter Pulse Shape: Compliant with ITU-T G.703 Loss Signal Detection: Compliant with ITU-T G.775 Return loss: Compliant with Selectable Signal Polarity Local/Remote Loopback Parallel/Serial Microprocessor Interface Single 3.3V±5% Operation Power Consumption Pin-to-pin compatible with AK2546(7 channel transceiver) except serial interface Small Plastic Package 144pin LQFP BLOCK DIAGRAM
MCLK CLKSEL RESET TEST1-4 (WR) AD7-AD0 AS(ALE) DS(RD) SCLK LOS1
CLKGEN CONTROL
TRANSCEIVER
RTIP1 RRING1 TTIP1
Remote Loopback
RECOVER
Local Loopback
RCLK1 RPOS RNEG1 TCLK1 TPOS TNEG1
SHAPER
TRING1
RTIP2-7 RRING2-7 TTIP2-7 TRING2-7
TRANSCEIVER
LOS2-7 RCLK2-7 RPOS2-7 RNEG2-7 TCLK2-7 TPOS2-7 TNEG2-7
Channel Transceiver Block Diagram
C0028-E-00
1999/9
[AK2548]
GENERAL DESCRIPTION AK2548 channel transceiver SDH/SONET MUX, MUX, etc. includes seven independent transmitters, clock data recovery, detector, control circuit LQFP-144 package which saves space, power consumption board design time. Internally generated transmit pulse provides appropriate pulse shape.
ASSIGNMENTS
C0028-E-00
R/W(WR) AS(ALE)/SCLK DS(RD)/SDI PVDD MCLK PVSS RAVSS2 RAVDD2 RESET RRING7 RTIP7 RRING6 RTIP6 TEST4 RRING5 RTIP5 TEST3 BVSS BGREF BVDD TEST2 RRING4 RTIP4 RRING3 RTIP3 CLKSEL RRING2 RTIP2 TEST1 RRING1 RTIP1 RAVSS1
TCLK7 TPOS7 TNEG7 RCLK7 RPOS7 RNEG7 TCLK6 TPOS6 TNEG6 RCLK6 RPOS6 RNEG6 IOVDD2 IOVSS2 TAVDD2 TAVSS2 TCLK5 TPOS5 TNEG5 RCLK5 RPOS5 RNEG5 DAVSS2 DVSS2 DVDD2 LOS7 LOS6 LOS5 AD7/SDO
AVSS8 TTIP7 TVSS7 TVDD7 TRING7 AVSS7 TTIP6 TVSS6 TVDD6 TRING6 AVSS6 TTIP5 TVSS5 TVDD5 TRING5 AVSS5 TTIP4 TVSS4 TVDD4 TRING4 AVSS4 TTIP3 TVSS3 TVDD3 TRING3 AVSS3 TTIP2 TVSS2 TVDD2 TRING2 AVSS2 TTIP1 TVSS1 TVDD1 TRING1 AVSS1
(TOP VIEW)
TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 RNEG1 TCLK2 TPOS2 TNEG2 RCLK2 RPOS2 RNEG2 IOVDD1 IOVSS1 TAVDD1 TAVSS1 TCLK3 TPOS3 TNEG3 RCLK3 RPOS3 RNEG3 DAVSS1 DVSS1 DVDD1 TCLK4 TPOS4 TNEG4 RCLK4 RPOS4 RNEG4 LOS1 LOS2 LOS3 LOS4 RAVDD1
1999/9
[AK2548]
CONDITION
Name TCLK7 TPOS7 TNEG7 RCLK7 RPOS7 RNEG7 TCLK6 TPOS6 TNEG6 RCLK6 RPOS6 RNEG6 IOVDD2 IOVSS2 TAVDD2 TAVSS2 TCLK5 TPOS5 TNEG5 RCLK5 RPOS5 RNEG5 DAVSS2 DVSS2 DVDD2 LOS7 LOS6 LOS5 AD7/SDO
Type CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power Power CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Load
Load
Comments
15pF 15pF 15pF
15pF 15pF 15pF
15pF 15pF 15pF
15pF 15pF 15pF 50pF 50pF 50pF 50pF 50pF 50pF 50pF 50pF
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[AK2548]
Name R/W(WR) AS(ALE)/SCLK DS(RD)/SDI PVDD MCLK PVSS RAVSS2 RAVDD2 RESET RRING7 RTIP7 RRING6 RTIP6 TEST4 RRING5 RTIP5 TEST3 BVSS BGREF BVDD TEST2 RRING4 RTIP4 RRING3 RTIP3 CLKSEL RRING2 RTIP2 TEST1 RRING1 RTIP1 RAVSS1
Type CMOS CMOS CMOS CMOS Open drain Power CMOS Power Power Power CMOS Analog Analog CMOS Analog Analog CMOS Analog Analog CMOS Power Analog Power CMOS Analog Analog CMOS Analog Analog CMOS Analog Analog CMOS Analog Analog Power
Load
Load
Comments
PMOS open drain
Note
Note accuracy Note
Note
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[AK2548]
Name RAVDD1 LOS4 LOS3 LOS2 LOS1 RNEG4 RPOS4 RCLK4 TNEG4 TPOS4 TCLK4 DVDD1 DVSS1 DAVSS1 RNEG3 RPOS3 RCLK3 TNEG3 TPOS3 TCLK3 TAVSS1 TAVDD1 IOVSS1 IOVDD1 RNEG2 RPOS2 RCLK2 TNEG2 TPOS2 TCLK2 RNEG1 RPOS1 RCLK1 TNEG1 TPOS1 TCLK1
Type Power CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power Power CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Load 15pF 15pF 15pF 15pF 15pF 15pF 15pF
Load
Comments
15pF 15pF 15pF
15pF 15pF 15pF
15pF 15pF 15pF
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[AK2548]
Name AVSS1 TRING1 TVDD1 TVSS1 TTIP1 AVSS2 TRING1 TVDD2 TVSS2 TTIP2 AVSS3 TRING3 TVDD3 TVSS3 TTIP3 AVSS4 TRING4 TVDD4 TVSS4 TTIP4 AVSS5 TRING5 TVDD5 TVSS5 TTIP5 AVSS6 TRING6 TVDD6 TVSS6 TTIP6 AVSS7 TRING7 TVDD7 TVSS7 TTIP7 AVSS8
Type Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power
Load
Load
Comments driver output
driver output driver output
driver output driver output
driver output driver output
driver output driver output
driver output driver output
driver output driver output
driver output
Note 1)Should connected externally.
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[AK2548]
FUNCTION
Name TTIP1-7 TRING1-7 TPOS1-7 TNEG1-7 TCLK1-7 RTIP1-7 RRING1-7 RPOS1-7 RNEG1-7 RCLK1-7 LOS1-7 Transmit Tip/Ring Output Bipolar output over transmit transformer Transmit Positive/Negative Data Input Input falling edge TCLK Transmit Clock Input Receive Tip/Ring Input Bipolar Input over receive transformer Receive Positive/Negative Data Output Output falling edge RCLK Receive Clock Output recovered from receive data input Loss signal output Output "high" when detect loss signal LOSx output masked MLOSx register. TVDD1-7 TVSS1-7 AVSS1-8 Common Block MCLK AS(ALE) 2.048/32.768MHz External Reference Clock Input Address Select(Address Latch Enable) Input Interrupt Output(PMOS open drain, should tied through resistor), Active High, output goes "high" when alarm reported LOSx, LOTCx LOMC registers. This masked MLOSx, MLOTCx MLOMC registers. DS(RD) (WR) Data Strobe(Read Enable) Input Read/Write(Write Enable) Input Chip Select Input Type Select Input BTS="H" Motorola Mode BTS="L" Intel Mode SCLK AD0-AD7 Serial Clock Input Serial Data Input Serial Data Output Address/Data Input/Output Used read/write internal registers. Positive Power Supply Transmit Driver Negative Power Supply Transmit Driver Analog ground Function Comment
Transceiver
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[AK2548]
Name CLKSEL
MCLK Select Input CLKSEL="H":2.048MHz CLKSEL="L":34.768MHz
Function
Comment
Common Block
Parallel/Serial Port Select P/S="H": Serial Port selected P/S="L": Parallel Port selected
RESET
Reset Input Active "Low" input pulse over 200ns initializes internal circuit forces RPOSx/RNEGx output "low" LOSx output "high".
TEST1,2,3,4 TAVDD1,2 TAVSS1,2 RAVDD1,2 RAVSS1,2 DVDD1,2 DVSS1,2 DAVSS1,2 IOVDD1,2 IOVSS1,2 BVDD BVSS PVDD PVSS BGREF
Factory Use. Should connected externally. Positive Power Supply analog circuitry transmitters Negative Power Supply analog circuitry transmitters Positive Power Supply analog circuitry receivers Negative Power Supply analog circuitry receivers Positive Power Supply Digital Negative Power Supply Digital Ground Digital Positive Power Supply Negative Power Supply Positive Power Supply Reference Circuit Negative Power Supply Reference Circuit Positive Power Supply Negative Power Supply Bandgap Reference Output. 12k±1% exeternal register should connected across this VSS.
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ASAHI KASEI ABSOLUTE MAXIMUM RATINGS
[AK2548]
Parameter Supply Input Voltage
Symbol VIN1 VIN2
-0.3 -0.3
VDD+0.3 VDD+0.3
Units
Condition
Apply except RTIPx, RRINGx Apply RTIPx, RRINGx
Input Current Storage Temperature
Tstg
Note) voltages with respect ground. negative voltage pins=0V. apply positive voltage pins.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Ambient Operating Temperature
Symbol
3.135
3.465
Units
Condition 3.3V±5%
Note) voltages with respect ground. negative voltage pins=0V. apply positive voltage pins.
ELECTORICAL CHARACTERISTICS
CHARACTERISTICS
Parameter Power Consumption(/ch) Digital High-Level Output Voltage Digital Low-Level Output Voltage Digital High-Level Input Voltage Digital Low-Level Input Voltage Input Leak Current Output Current Note1: 0.7VDD 0.3VDD 0.9VDD Symbol Units Condition Note1 IOH=-40µA IOL=500µA
typ: mark, Room temp., 3.3V max: 100% mark, Temp./VDD range
include other load(ex. External pull register) except lines.
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[AK2548]
RECEIVER
Receiver characteristics guaranteed conditions shown below. VDD=3.3V±5%, VSS, MCLK frequency: 2.048MHz±100ppm, 32.768MHz±100ppm. Bipolar input input level: 2.37V0p±10%@75system, 3V0p±10%@120system) Parameter Input Impedance Sensitivity Loss Signal Threshold Allowable Consecutive Zeros before tolerance Generated Jitter pulse density immunity Jitter Tolerance 1/16 Symbol 0.28 0.35 0.55 Units bits Mark Note3 nspp Note4 Note1 Note2 Condition
ITU-T G.823
Note1: Relative value reference level. Compare 1.024MHz with mark pattern. Note2: Level line side transformer. Loss signal logical between analog loss signal monitors input level digital loss signal check recovered data stream. Note3: PN15 Mark pattern input. Noise frequency 1MHz. Note4: PN15 pattern input.
Jitter Tolerance(G.823)
Jitter Amplitude(UIpp)
36.9
20Hz 2.4kHz 18kHz 100kHz
Jitter Frequency
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[AK2548]
TRANSMITTER
Transmitter characteristics guaranteed conditions shown below. MCLK frequency:2.048MHz±100ppm, 32.768MHz±100ppm Parameter Output Pulse Shape Output Pulse Amplitude Pulse Amplitude space Output Pulse Imbalance amplitudes widths Output Jitter Return Loss 51kHz-102kHz 102kHz-2.048MHz 2.048MHz-3.072MHz 20Hz-100kHz 2.14 -0.237 -0.3 2.37 2.60 0.237 0.05 UIpp Note Symbol Units Condition
G.703
Note
Note1: Turns Ratio, external resistors recommended value. (P27)
Pulse Mask Template (G.703)
(244
100%
(244
Nominal pulse
(244 244) Note corresponds nominal peak value.
Mask pulse 2048 kbit/s interface
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(244
1999/9
[AK2548]
CHARACTERISTICS(Clock/Data)
Parameter Clock Frequency Clock Pulse Width Clock Pulse Width Duty Cycle Setup/Hold Time MCLK TCLK RCLK RCLK TCLK RCLK RPOS RNEG Setup/Hold Time TCLK TPOS TNEG Rise Time RCLK RPOS RNEG Fall Time TCLK TPOS TNEG Note1) Duty Cycle:(tpwho/( Note2) Drive 15pF Load Capacitance Refer Fig.3 Note2 Refer Fig.3 Note2 tsu2 Refer Fig.2 tsu1 Refer Fig.1 Symbol tpwhi tpwli tpwho tpwlo Note1 Refer Fig.1 Units Condition
2.047795 2.048000 2.048204 32.76472 32.76800 32.77127
±100ppm Refer Fig.2
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[AK2548]
tpwho
tpwlo tsur
RCLK
RPOS/RNEG
Figure Receiver Timing
tpwhi tpwli
TCLK
tsut
TPOS/TNEG
Figure Transmitter Timing
Figure Rise Fall Times (RCLK,RPOS,RNEG,TCLK,TPOS,TNEG)
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[AK2548]
CHARACTERISTICS(Parallel Port)
Parameter Read/Write Cycle Motorola Mode Address Setup Time Address Hold Time Delay Time Delay Time Read Data Delay Time Read Data Hold Time Setup Time Hold Time Setup Time Hold Time Write Data Setup Time Write Data Hold Time Pulse Width Pulse Width Address Invalid Delay Time Symbol tcyc Units Condition
Intel Mode
Address Setup Time Address Hold Time Delay Time Delay Time Delay Time Read Data Delay Time Read Data Hold Time Setup Time Hold Time Write Data Setup Time Write Data Hold Time Pulse Width Pulse Width Pulse Width Address Invalid Delay Time
Notes) 50pF AD0-AD7. timing specified 50%VDD.
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[AK2548]
Motorola Mode(READ)
Data
AD7-0
Address
Motorola Mode(WRITE)
Data
AD7-0
Address
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[AK2548]
Intel Mode(READ)
AD7-0 Data
Address
Intel Mode(WRITE)
AD7-0 Data
Address
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[AK2548]
CHARACTERISTICS(Serial Port)
Parameter Setup Time Hold Time SCLK Time SCLK High Time SCLK Rise Time SCLK Fall Time Setup Time Hold Time Inactive Time SCLK Valid High Symbol tp10 tp11 Units Condition
Notes) 50pF. timing specified 50%VDD.
Serial Port Input Timing
SCLK
Serial Port Output Timing
tp10
SCLK
tp11
High-Z
High-Z
SCLK
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[AK2548]
REGISTER DESCRIPTION
REGISTER
*A7-A4="0" Address
Bit7 <AD7> Bit6 <AD6> Bit5 <AD5>
Function
Bit4 <AD4> Bit3 <AD3> Bit2 <AD2> Bit1 <AD1> Bit0 <AD0>
Status Register (READ ONLY)
LOS7 LOTC7
LOS6 LOTC6
LOS5 LOTC5
LOS4 LOTC4
LOS3 LOTC3
LOS2 LOTC2
LOS1 LOTC1
LOMC
Mask Control Register (WRITE/READ)
MLOS7 MLOTC7
MLOS6 MLOTC6
MLOS5 MLOTC5
MLOS4 MLOTC4
MLOS3 MLOTC3
MLOS2 MLOTC2
MLOS1 MLOTC1
RDEN MLOMC
Channel Control Register (WRITE/READ)
Reserved
TAOS1
RLOOP1 RLOOP2 RLOOP3 RLOOP4 RLOOP5 RLOOP6 RLOOP7
LLOOP1 LLOOP2 LLOOP3 LLOOP4 LLOOP5 LLOOP6 LLOOP7
POLN1 POLN2 POLN3 POLN4 POLN5 POLN6 POLN7
MSK1 MSK2 MSK3 MSK4 MSK5 MSK6 MSK7
Reserved
TAOS2
Reserved
TAOS3
Reserved
TAOS4
Reserved
TAOS5
Reserved
TAOS6
Reserved
TAOS7
*Other address reserved.
Initial value "<>" show name. Address A0-A3 should input AD0-AD3 pins.
C0028-E-00
1999/9
[AK2548]
STATUS REGISTER
Symbol LOSx (x=1 LOTCx (x=1 LOMC Description Loss signal alarm channel Read only register. When loss signal loss MCLK detected, LOSx goes High. Loss TCLK alarm channel Read only register. When loss TCLKx detected, LOTCx goes High. Loss MCLK alarm. Read only register. When loss MCLK detected, LOMC LOSx High.
MASK CONTROL REGISTER
Symbol MLOSx (x=1 Description Mask loss signal alarm channel MLOSx active-high prevent LOSx from setting output "high" possible read LOSx register regardless status MLOSx. Initial value "high". Mask loss TCLK alarm channel MLOTCx active-high prevent LOTCx from setting output "high" possible read LOTCx register regardless status MLOTCx. Initial value "high". Mask loss MCLK alarm. MLOMC active-high prevent LOMC from setting output "high" possible read LOMC register regardless status MLOMC. Initial value "high". Note) Please refer "Loss MCLK theory operation". (P25)
MLOTCx (x=1
MLOMC
CHANNEL CONTROL REGISTER
Symbol RLOOPx/ LLOOPx POLNx Description Loopback mode channel activated through setting these register shown below Table TIPx/RINGx output polarity controlled this register shown below Table Initial value "high". active-high corresponding transceiver power down mode. TTIPx TRINGx "low". LOSx goes "high" power down mode. Initial value "high". MSKx active-high prevent LOSx LOTCx from setting output "high". Initial value "high". RDEN active-high prevent RCLK, RPOS, RNEG output from forcing "low" "high" detection Loss signal. Initial value "low". TAOS active-high output one's signal from TTIPx TRINGx. one's signal synchronized with TCLK. When TCLK lost, signal synchronized with MCLK. Application selected this register Table Initial value low.
MSKx RDEN
TAOSx
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[AK2548]
Table Loopback mode Select
RLOOPx LLOOPx Normal Local Loop back Remote Loop back Inhibited Function (Initial value)
Table TIPx/RINGx Polarity Control
POLNx POSx/NEGx TIPx/RINGx space mark mark space
Table Equalizer Control
Application E1-Coax(75) E1-Twisted Pair(120) (Initial value)
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[AK2548]
OUTPUT CONTROL
don't care LOS: LOSx output LOSx register
Reset, Loss MCLK, Power down
RESET MCLK TAOS Loopback Local loss loss clocked clocked Remote POLN RDEN TCLK Receive Signal TTIP TRING RCLK RPOS RNEG
Normal Operation(RESET=1, MCLK:clocked, PD=0)
TAOS Loopback Local Remote Clocked POLN RDEN TCLK Receive signal TTIP TRING TPOS TNEG Clocked loss TPOS TNEG Loss RCLK RTIP RRING Loss Clocked loss loss TPOS TNEG Loss loss RCLK RCLK RTIP RRING RTIP RRING Clocked TPOS TNEG Clocked loss TPOS TNEG Loss 0RCLK RTIP RRING Loss clocked loss loss TPOS TNEG loss loss RCLK RCLK RTIP RRING RTIP RRING RCLK RTIP RRING RCLK RCLK RPOS RNEG RTIP RRING
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[AK2548]
Normal Operation(RESET=1, MCLK:clocked, PD=0)
TAOS Loopback Local Remote clocked POLN RDEN TCLK Receive signal TTIP TRING Mark RCLK RCLK RPOS RNEG RTIP RRING clocked loss loss Mark Mark RCLK RTIP RRING loss clocked loss loss Mark Mark RCLK RTIP RRING loss loss Mark RCLK RTIP RRING clocked Mark RCLK RTIP RRING clocked loss loss Mark Mark RCLK RTIP RRING loss clocked loss loss Mark Mark RCLK RTIP RRING loss loss Mark RCLK RTIP RRING
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[AK2548]
Remote Loopback(RESET=1, MCLK:clocked, PD=0)
TAOS Loopback Local Remote POLN RDEN TCLK Receive signal TTIP TRING RTIP RRING loss RTIP RRING loss RTIP RRING RTIP RRING loss RTIIP RRING loss RTIP RRING RCLK RTIP RRING RCLK RCLK RTIP RRING RTIP RRING RCLK RCLK RPOS RNEG RTIP RRING
Remote Loopback(RESET=1, MCLK:clocked, PD=0)
TAOS Loopback Local Remote POLN RDEN TCLK Receive signal TTIP TRING Mark RCLK RCLK RPOS RNEG RTIP RRING loss loss Mark Mark RCLK RTIP RRING Mark RCLK RTIP RRING loss loss Mark Mark RCLK RTIP RRING
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[AK2548]
Local Loopback(RESET=1, MCLK:clocked, PD=0)
TAOS Loopback Local Remote clocked POLN RDEN TCLK Receive signal TTIP TRING TPOS TNEG clocked loss TPOS TNEG loss loss clocked loss TPOS TNEG clocked loss TPOS TNEG loss loss loss TCLK (Note) TCLK (Note) TCLK (Note) TCLK (Note) RCLK RPOS RNEG TPOS TNEG TPOS TNEG TPOS TNEG TPOS TNEG
Note) phase satisfy receive output timing.
Local Loopback(RESET=1, MCLK:clocked, PD=0)
TAOS Loopback Local Remote clocked POLN RDEN TCLK Receive signal TTIP TRING Mark TCLK (Note) clocked loss Mark TCLK (Note) loss loss clocked loss Mark Mark Mark TCLK (Note) clocked loss Mark TCLK (Note) loss loss loss Mark Mark RCLK RPOS RNEG TPOS TNEG TPOS TNEG TPOS TNEG TPOS TNEG
Note) phase satisfy receive output timing.
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[AK2548]
THEORY OPERATION
Loss signal Loss signal channel reported setting LOSx register "high". receiver will indicate loss signal upon receiving consecutive zeros detecting input level being below threshold(ALOS). LOSx returns "low" when received signal returns 12.5% ones density include consecutive zeros.
When Loss Signal detected channel LOSx register "high" LOSx becomes "high". When LOSx "high", interrupt will issued MLOSx "low". LOSx becomes high regardless MLOSx status. MLOSx active-high masks LOSx interrupt. LOSx register represents current status received signal regardless status MLOSx status.
Loss TCLK Loss TCLKx reported setting LOTCx "high". When LOTCx "high", output becomes "high" MLOTCx "low". Even TCLK return normal quickly, LOTCx remain "high" 126us. MLOTCx active-high masks LOTCx interrupt. LOTCx represents current status TCLKx read regardless status MLOTCx status. When Loss TCLKx detected, TTIPx/TRINGx will forced "0". Loss MCLK Loss MCLK reported setting LOMC "high". When LOMC goes "high", output becomes "high" MLOMC "low". Even MCLK return normal quickly, LOMC remain "high" 126us. MLOMC active-high masks LOMC interrupt. LOMC represents current status MCLK read regardless MLOMC status. When loss MCLK detected, LOSx register LOSx goes "high" same time. Therefore MLOSx register must "high" prevent loss MCLK from setting output. output output goes "high" when alarm reported LOSx, LOTCx LOMC registers. This masked MLOSx, MLOTCx MLOMC registers.
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[AK2548]
Local Loopback Local Loopback mode, TPOSx,TNEGx,TCLKx signals looped back RPOSx, RNEGx, RCLKx output. RTIPx,RRINGx inputs ignored loss signal detection active. transmitter channel outputs TTIPx,TRINGx normally. Remote Loopback Remote Loopback mode, RTIPx/RRINGx signals looped back TTIPx/TRINGx output. receiver channel output RPOSx,RNEGx,RCLKx normally detect loss signal. TPOSx,TNEGx,TCLKx inputs ignored. When TAOSx "high", mark signal output TTIPx/TRINGx. Interface
Interface control/status register selected pin. interface selected. Parallel Interface type(Intel/Motorola) selected pin. When "high", Motorola mode selected. When "low", Intel mode selected. Serial Interface timing serial interface shown below. SCLK High-Z When "low", parallel When "high", serial interface selected.
R/W=1: read R/W=0: write
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ASAHI KASEI RECOMMENDED EXTERNAL CIRCUIT
[AK2548]
Transmit Circuit
AK2548 TTIPx TRINGx
Trans Rate R1.R2
8.2±1% 470pF
1:2.2 9.1±1% 470pF
Received Circuit
AK2548 RTIPx
RRINGx
R1,R2 R3,R4
protection resistance against surge. used surge current limiting. (ITU-T K.41)
Recommended Transformer Specification Turns Primary Leakage Ratio Inductance Inductance (Typ) (Min) (Max)
1:2.2 720uH 720uH 1.2mH 0.3uH 0.3uH 0.3uH
Interwinding Capacitance (Max) 30pF 30pF 30pF
(Max)
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[AK2548]
Reference current circuit
determine input reference current, connect 12k±1% resistor. AK2548 BGREF
R1=12k±1%
Power Supply
attenuate power supply noise, connect capacitors between respectively. value capacitance AK2548 need depend condition power supply line. Please decide value capacitance after your evaluation.
AK2548
name RAVDD1-RAVSS1, RAVDD2-RAVSS2, BVDD-BVSS, TAVDD1-TAVSS1, TAVDD2-TAVSS2 TVDD1-TVSS1, TVDD2-TVSS2, TVDD3-TVSS3, TVDD4-TVSS4, TVDD5-TVSS5, IOVSS1, PVDD-PVSS TVDD6-TVSS6, TVDD7-TVSS7, IOVDD1IOVDD2-IOVSS2, DVDD1-DVSS1, DVDD2-DVSS2,
0.01uF
C0028-E-00
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[AK2548]
PACKAGE
144pin LQFP
OUTPUT DIMENSIONS
22.0 20.0
AK2548 XXXXXXX JAPAN
20.0
0.07
1.70 1.40
0.50 0.20
0.10
0.17±
0.04
22.0
0~10°
0.10
0.10
0.50±0.1
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IMPORTANT NOTICE These products their specifications subject change without notice.
[AK2548]
Before considering
application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
C0028-E-00
1999/9

AK2548 channel Transceiver FEATURE transceiver Jitter Tolerance:

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