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Embedded AMD-K6Processors BIOS Design Guide
Publication 23913 Rev: Issue Date: November 2000
Amendment/0
2000 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, logo, combinations thereof, AMD-K6, 3DNow!, E86, PowerNow!, Super7 trademarks, FusionE86 service mark Advanced Micro Devices, Inc. trademark Pentium registered trademark Intel Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
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Embedded AMD-K6Processors BIOS Design Guide
Contents
Revision History Introduction Audience Processor Models Steppings AMD-K6TME Embedded Processor AMD-K6TM-2 Processor. AMD-K6TM-2E Embedded Processor. AMD-K6TM-2E+ Embedded Processor. AMD-K6TM-III Processor. AMD-K6TM-IIIE+ Embedded Processor
BIOS Consideration Checklist CPUID Speed Detection Model-Specific Registers (MSRs) Cache Testing Issues
States after RESET INIT. Register States after RESET INIT Processor State after INIT. Built-In Self-Test (BIST) CPUID Identification Algorithms System Management Mode (SMM) State-Save Differences Trap Dword Differences Model-Specific Registers Overview Standard Model-Specific Registers (All Models) Model Model 8/[7:0] Registers. Extended Feature Enable Register (EFER) Write Handling Control Register (WHCR) SYSCALL/SYSRET Target Address Register (STAR) Contents
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Model 8/[F:8] Registers Extended Feature Enable Register (EFER) Write Handling Control Register (WHCR) UC/WC Cacheability Control Register (UWCCR) Processor State Observability Register (PSOR) Page Flush/Invalidate Register (PFIR) Model Registers Extended Feature Enable Register (EFER) Level-2 Cache Array Access Register (L2AAR) Model Registers. Processor State Observability Register (PSOR) (Low-Power Versions) Level-2 Cache Array Access Register (L2AAR) Enhanced Power Management Register (EPMR) (Low-Power Versions) 16-Byte Block (Low-Power Versions Only)
Embedded Processor Recognition. CPUID Instruction Overview Testing CPUID Instruction Using CPUID Functions. Identifying Processor's Vendor Testing Extended Functions Determining Processor Signature Identifying Supported Features Determining Instruction Support. Detection Algorithm Determining Instruction Support Processor Signature (Extended Function). Displaying Processor's Name Displaying Cache Information Determining PowerNow!Technology Information Sample Code
AMD-K6Processor Instructions. Additional Considerations Contents
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Software Timing Dependencies Relative Memory Controller Setup Pipelining Support Read-Only Memory Appendix CPUID Standard Functions Extended Functions Cache Associativity Field Definitions
Appendix Values Returned CPUID Instruction Index.
Contents
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Contents
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Embedded AMD-K6Processors BIOS Design Guide
List Figures
Figure CPUID Instruction Flow Chart Figure Extended Feature Enable Register (EFER) (Models 8/[7:0]) Figure Write Handling Control Register (WHCR) (Models 8/[7:0]) Figure SYSCALL/SYSRET Target Address Register (STAR) (Models Figure Extended Feature Enable Register (EFER) (Model 8/[F:8]) Figure Write Handling Control Register (WHCR) (Models 8/[F:8], Figure UC/WC Cacheability Control Register (UWCCR) (Models 8/[F:8], Figure Processor State Observability Register (PSOR) (Models 8/[F:8], Standard-Power Figure Page Flush/Invalidate Register (PFIR) (Models 8/[F:8], Figure Extended Feature Enable Register (EFER) (Models Figure Cache Organization (AMD-K6TM-III Processor) Figure Cache Sector Line Organization Figure Data Location (AMD-K6TM-III Processor)-EDX Figure Data-EAX Figure Information (AMD-K6TM-III Processor)-EAX Figure Byte. Figure Processor State Observability Register (PSOR) (Model Low-Power Versions) Figure Cache Organization. Figure Cache Sector Line Organization (same Figure
List Figures
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Figure Data Location (AMD-K6TM-2E+ Processor)-EDX Figure Data Location (AMD-K6TM-IIIE+ Processor)-EDX Figure Data-EAX (same Figure Figure Information (AMD-K6TM-2E+ Processor)-EAX Figure Information (AMD-K6TM-IIIE+ Processor)-EAX Figure Byte (same Figure Figure Enhanced Power Management Register (EPMR) (Low-Power Model Figure 16-Byte Block (Low-Power Model Figure Divisor Voltage Control (BVC) Field (Low-Power Model Figure Contents Register Returned Function Figure Contents Register Returned Extended Function 8000_0001h
viii
List Figures
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List Tables
Table Table Table Table Features AMD-K6Processor Family AMD-K6TME Processor (Model AMD-K6Processor (Model 8/[7:0]) State after RESET AMD-K6Processor (Model 8/[F:8]) AMD-K6TM-2E Processor (Model 8/[F:8]) State after RESET AMD-K6TM-2E+ (Model AMD-K6TM-III (Model AMD-K6TM-IIIE+ Processors (Model State after RESET Recommended Boot Strings AMD-K6Processors AMD-K6Processor Trap Dword Configuration Offset FFA4h Summary Register Differences within AMD-K6Family. Summary Model Differences within AMD-K6Family. Model-Specific Registers Supported Models 8/[7:0]
Table Table Table Table Table
Table Extended Feature Enable Register (EFER) Definition (Models 8/[7:0]) Table SYSCALL/SYSRET Target Address Register (STAR) Definition (Models Table Model-Specific Registers Supported Model 8/[F:8] Table Extended Feature Enable Register (EFER) Definition (Model 8/[F:8]) Table Write Ordering Performance Settings EFER Register Table WC/UC Memory Type UWCCR Register Table Valid Masks Range Sizes UWCCR Register. Table Processor-to-Bus Clock Ratios (Models 8/[F:8] List Tables
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Table Processor-to-Bus Clock Ratios (Model Standard-Power Table Model-Specific Registers Supported Model Table Extended Feature Enable Register (EFER) Definition (Models Table versus Data Selector Table Model-Specific Registers Supported Model Table Processor-to-Bus Clock Ratios (Low-Power Model Table versus Data Selector (same Table Table Enhanced Power Management Register (EPMR) Definition (Low-Power Model Table 16-Byte Block Definition (Low-Power Model Table Divisor Voltage Control (BVC) Definition (Low-Power Model Table CPUID Functions AMD-K6Processors. Table Processor Signatures AMD-K6Processors Table Standard Extended Feature Bits Table Standard Feature Flag Descriptions. Table Extended Feature Flag Descriptions Table Format Returned Function 8000_0005h. Table Format Returned Function 8000_0005h. Table Format Returned Function 8000_0005h Table Format Returned Function 8000_0006h. Table Format Returned Function 8000_0007h Table Associativity Values Cache Table CPUID Values Returned AMD-K6Processors
List Tables
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Revision History
Date November 2000 Description Initial public release.
Revision History
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Revision History
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Embedded AMD-K6Processors BIOS Design Guide
Application Note Embedded AMD-K6Processors BIOS Design Guide
Introduction
This document highlights BIOS modifications required fully support AMD-K6processors used AMD's embedded customers. information this application note pertains following processors AMD-K6 family:
AMD-K6E embedded processor AMD-K6-2 processor AMD-K6-2E embedded processor AMD-K6-2E+ embedded processor AMD-K6-III processor AMD-K6-IIIE+ embedded processor
There more than implement functionality detailed this document, information provided demonstration purposes. referenced AMD-K6 processor documents found website http://www.amd.com/.
Audience
assumed that reader solid understanding processors, architecture, programming requirements. Introduction
Preliminary Information Embedded AMD-K6Processors BIOS Design Guide
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Processor Models Steppings
Four models within AMD-K6 family processors-models D-are discussed this document. most models, feature function detection determined reading standard extended feature bits executing CPUID instruction. However, certain models, necessary check stepping-by executing CPUID instruction-to determine specific function support. Table shows features each model stepping AMD-K6 processor family. Table Features AMD-K6Processor Family
3DNow! PowerNow!Model/ Process Number 3DNow!Technology Stepping microns) MSRs1 Instructions Extensions
8/[7:0] 8/[F:8] D/[7:4] 9/[3:0] D/[3:0] 0.25 0.25 0.25 0.18 0.25 0.18 113,4 113,4 Yes5 Yes5 Kbytes Kbytes
Processor
AMD-K6E AMD-K6-2 AMD-K6-2 AMD-K6-2E AMD-K6-2E+ AMD-K6-III AMD-K6-IIIE+
Notes:
Cache
Refer "Model-Specific Registers Overview" page more information. Model 8/[F:8] defines bits fields Write Handling Control Register (WHCR) Extended Feature Enable Register (EFER) differently from models 8/[7:0]. This model implements same MSRs Model 8/[F:8]. With exception (L2D) EFER register, bits fields within these MSRs defined identically. Low-power versions implement additional register support PowerNow!technology. PowerNow! technology supported low-power versions these processors only.
descriptions remainder this section provide more detailed information AMD-K6 processor family members, models steppings that comprise each member. Table page Table page summarize differences between models steppings AMD-K6 family processors.
Processor Models Steppings
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AMD-K6TME Embedded Processor
Model Model first processor manufactured 0.25-micron process.
Model supports model-specific registers (MSRs).
AMD-K6TM-2 Processor
Some important features supported AMD-K6-2 processor include 3DNow!instruction 100-MHz processor bus. Model 8/[7:0] Model 8/[7:0] eight possible model/steppings-models Model manufactured 0.25-micron process original version AMD-K6-2 available desktop product.
Model 8/[7:0] implements same MSRs Model bits fields within these MSRs defined identically. Model 8/[7:0] also implements SYSCALL/SYSRET Target Address Register (STAR) total seven MSRs.
Model 8/[F:8]
Model 8/[F:8] eight possible model/steppings-models 8/8, 8/9, 8/A, 8/B, 8/C, 8/D, 8/E, 8/F. Model 8/[F:8] manufactured 0.25-micron process.
Model 8/[F:8] implements same MSRs models 8/[7:0], bits fields within these MSRs-WHCR EFER-are defined identically. Also, Model 8/[F:8] supports STAR three additional MSRs, total MSRs.
Processor Models Steppings
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AMD-K6TM-2E Embedded Processor
instruction 100-MHz processor bus. Model 8/[F:8] Model 8/[F:8] eight possible model/steppings-models 8/8, 8/9, 8/A, 8/B, 8/C, 8/D, 8/E, 8/F. Model 8/[F:8] manufactured 0.25-micron process.
Model 8/[F:8] implements same MSRs models 8/[7:0], bits fields within these MSRs-WHCR EFER-are defined identically. Also, Model 8/[F:8] supports STAR three additional MSRs, total MSRs.
AMD-K6TM-2E+ Embedded Processor
addition supporting 3DNow! instruction 100MHz processor bus, AMD-K6-2E+ processor contains 128Kbyte backside cache. also supports 3DNow! instructions extensions. Low-power versions processor support PowerNow!technology. Model D/[7:4] Model D/[7:4] four possible model/steppings-models D/4, D/5, D/6, D/7. Model D/[7:4] manufactured 0.18micron process.
Model D/[7:4] implements same MSRs Model 8/[F:8]. With exception (L2D) EFER register, bits fields within these MSRs defined identically standard-power versions. PSOR register defined differently low-power versions. Model D/[7:4] supports additional MSR, Level-2 Cache Array Access Register (L2AAR), total eleven MSRs. Low-power versions Model D/[7:4] support additional MSR, Enhanced Power Management Register (EPMR), total twelve MSRs.
Processor Models Steppings
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AMD-K6TM-III Processor
addition supporting 3DNow! instruction 100MHz processor bus, AMD-K6-III processor contains 256Kbyte backside cache. Model 9/[3:0] Model 9/[3:0] four possible model/steppings-models 9/0, 9/1, 9/2, 9/3. Model 9/[3:0] manufactured 0.25micron process.
Model 9/[3:0] implements same MSRs Model 8/[F:8]. With exception (L2D) EFER register, bits fields within these MSRs defined identically. Model 9/[3:0] supports additional total eleven MSRs.
AMD-K6TM-IIIE+ Embedded Processor
addition supporting 3DNow! instruction 100MHz processor bus, AMD-K6-IIIE+ processor contains 256Kbyte backside cache. also supports 3DNow! instruction extensions. Low-power versions processor support PowerNow! technology. Model D/[3:0] Model D/[3:0] four possible model/steppings-models D/0, D/1, D/2, D/3. Model D/[3:0] manufactured 0.18micron process.
Model D/[3:0] implements same MSRs Model 8/[F:8]. With exception (L2D) EFER register, bits fields within these MSRs defined identically standard-power versions. PSOR register defined differently low-power versions. Model D/[7:4] supports additional MSR, Level-2 Cache Array Access Register (L2AAR), total eleven MSRs. Low-power versions Model D/[7:4] support additional MSR, Enhanced Power Management Register (EPMR), total twelve MSRs.
Processor Models Steppings
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BIOS Consideration Checklist
CPUID
CPUID instruction properly identify processor. information CPUID instruction, "CPUID Instruction Overview" page Determine processor model, stepping, features using functions 0000_0001h 8000_0001h CPUID instruction. Display processor name (BIOS boot strings) described "CPUID Identification Algorithms" page
Speed Detection
speed detection algorithms that rely repetitive instruction sequences. Time Stamp Counter (TSC) `clock' timed operation compare result real-time clock (RTC) determine operating frequency. Speed Determination Program available website Display recommended BIOS boot string shown Table page
Model-Specific Registers (MSRs)
Only access MSRs implemented processor. Enable write allocation programming Write Handling Control Register (WHCR). "Write Handling Control Register (WHCR)" page page Implementation Write Allocate K86Processors Application Note, order# 21326 more information. Note: WHCR register defined models 8/[7:0] implemented differently models 8/[F:8],
AMD-K6-2E, AMD-K6-2E+, AMD-K6-III, AMD-K6-IIIE+ processors, utilize information provided Processor State Observability Register (PSOR) display correct processor frequency.
BIOS Consideration Checklist
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Cache Testing
AMD-K6 family processors does contain MSRs allow testing cache. However, AMD-K6-2E+, AMD-K6-III, AMD-K6-IIIE+ processors contain that allows testing their caches. This called L2AAR, described "Level-2 Cache Array Access Register (L2AAR)" page
Issues
System Management Mode (SMM) functionality processor same Pentium® processor. Implement processor state-save area similar manner Pentium processors except Base possibly Pentium processor-reserved areas. "System Management Mode (SMM)" page more information.
BIOS Consideration Checklist
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States after RESET INIT
Register States after RESET INIT
After processor completed initialization following recognition asserted RESET INIT signal, states architecture registers MSRs compatible with those Pentium processors. Differences listed Table through Table Table AMD-K6TME Processor (Model AMD-K6Processor (Model 8/[7:0]) State after RESET
RESET State 0000_05MSh1 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h EFER STAR2 WHCR
Notes:
Register
represents Model represents Stepping. Processor Model does support STAR register.
Table
AMD-K6Processor (Model 8/[F:8]) AMD-K6TM-2E Processor (Model 8/[F:8]) State after RESET
RESET State 0000_05MSh1 0000_0000_0000_0002h 0000_0000_0000_0000h 0000_0000_0000_01SBh1,2 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h EFER PFIR PSOR STAR UWCCR WHCR
Register
Notes:
represents Model represents Stepping. represents PSOR[3:0], where PSOR[3] equals PSOR[2:0] equal value BF[2:0] signals sampled during falling transition RESET.
States after RESET INIT
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Table
AMD-K6TM-2E+ (Model AMD-K6TM-III (Model AMD-K6TM-IIIE+ Processors (Model State after RESET
RESET State 0000_05MSh1 0000_0000_0000_0002h 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_00SBh1,3 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h EFER2 L2AAR PFIR PSOR STAR UWCCR WHCR EPMR4
Register
Notes:
represents Model represents Stepping. Because EFER[4] equals after RESET, cache enabled default after RESET. represents PSOR[3:0], where PSOR[3] equals PSOR[2:0] equal value BF[2:0] signals sampled during falling transition RESET. Supported low-power versions only Model processors.
Processor State after INIT
assertion INIT causes processor empty pipelines, initialize most internal state, branch address FFFF_FFF0h-the same instruction execution starting point used after RESET. Unlike RESET, processor preserves contents caches, floating-point state, base, MSRs, bits register. edge-sensitive interrupts FLUSH# SMI# sampled preserved during INIT process handled accordingly after initialization complete. However, processor resets pending interrupt upon sampling INIT asserted. INIT used accelerator 80286 code that requires reset exit from protected mode back real mode.
States after RESET INIT
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Built-In Self-Test (BIST)
unconditionally following falling transition RESET. results test contained general-purpose register EAX. contains 0000_0000h, then BIST successful. contents non-zero, BIST failed. internal resources tested during BIST include following:
instruction data caches unified cache (models only) Instruction data translation lookaside buffers (TLBs)
States after RESET INIT
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CPUID Identification Algorithms
CPUID instruction provides information about processor (vendor, type, name, etc.) capabilities (features). After detecting processor capabilities, software accurately tuned system maximum formance benefi more ailed "Embedded Processor Recognition" page determine processor enabled with PowerNow! technology, CPUID function 8000_0007, described page recommended boot strings processor names) displayed AMD-K6 processors shown Table Table
Model
Recommended Boot Strings AMD-K6Processors
Recommended Boot String Display1
Model steppings Models Model D/[7:4]2 Model 9/[3:0] Model D/[3:0]2
Notes:
AMD-K6(tm)/XXX AMD-K6(tm)-2/XXX AMD-K6(tm)-2+/XXX AMD-K6(tm)-III/XXX AMD-K6(tm)-III+/XXX
value determined calculating core frequency processor. Time Stamp Counter (TSC) `clock' timed operation compare result real-time clock (RTC) determine operating frequency. "Functions 8000_0002h, 8000_0003h, 8000_0004h Processor Name String" page more information about these steppings.
example, BIOS boot string Model stepping 450MHz AMD-K6-III processor would look like this:
AMD-K6(tm)-III/450
Figure page shows flow chart CPUID instruction. this chart implement CPUID algorithm.
CPUID Identification Algorithms
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Check CPUID instruction support
Execute CPUID Extended Function EAX=8000_0001h
CPUID instruction supported
CPUID instruction-Use other means detect type
Utilize Vendor String Extended Function Feature bits determine 3DNow!, 3DNow! Extensions, MMXExtensions support
Execute CPUID Standard Function EAX=0 Store Vendor String
Utilize Processor Signature determine support
processor present-Check other brands
Execute CPUID Extended Functions EAX=8000_0002h, 8000_0003h, 8000_0004h display processor name string Execute CPUID Extended Functions EAX=8000_0005h EAX=8000_0006h (Model Model gather processor cache information
Execute CPUID Standard Function EAX=1
Store returned Standard Function Feature bits Processor Signature; Determine and, optionally, SSE* support Execute CPUID Extended Function EAX=8000_0000h determine number extended functions supported
Extended Functions Supported
Execute CPUID Extended Function EAX=8000_0007h (Model gather PowerNow! technology information processor
8000_0001h Streaming SIMD Extensions
Tune software optimize features present
Done
Figure CPUID Instruction Flow Chart
CPUID Identification Algorithms
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System Management Mode (SMM)
This section documents System Management Mode (SMM) differences between specified models AMD-K6 processor Pentium processor. more information implementation processors, appropriate AMD-K6 AMD-K6E processor data sheet.
State-Save Differences
implemented AMD-K6 processor differs from implemented Pentium® processor way. Interrupt Descriptor Table (IDT) base location AMD-K6 processors located offset FF90h. Pentium processor base located offset FF94h.
Trap Dword Differences
trap dword located offset FFA4h. AMD-K6 processor fields shown Table This state-save area, which reserved Pentium processors, contains information regarding instruction that have been trapped SMI# assertion. Table AMD-K6Processor Trap Dword Configuration Offset FFA4h
Bits 15-4 Reserved String Operation String Operation Valid Instruction Input Output
Bits 31-16 Port Address
System Management Mode (SMM)
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Model-Specific Registers Overview
Each models AMD-K6 processor family support different model-specific registers (MSRs). These differences summarized register Table differences summarized model Table page where indicates support register field. content selects addressed RDMSR WRMSR instruction. Table
Register
Summary Register Differences within AMD-K6Family
Mnemonic Value Models Description
Machine-Check Address Register Machine-Check Type Register Test Register Time Stamp Counter
MCAR MCTR TR12
8/[7:0]
page page page page page page page page page supported page supported page supported page page supported page
Extended Feature Enable Register
EFER
C000_0080h
8/[F:8]
Write Handling Control Register
WHCR
C000_0082h
8/[7:0] 8/[F:8], 8/[7:0] 8/[F:8], 8/[7:0]
SYSCALL/SYSRET Target Address Register
STAR
C000_0081h
UC/WC Cacheability Control Register
UWCCR
C000_0085h
Processor State Observability Register
PSOR
C000_0087h
8/[F:8],
Page Flush/Invalidate Register
PFIR
C000_0088h
8/[7:0] 8/[F:8],
Model-Specific Registers Overview
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Table
Register
Summary Register Differences within AMD-K6Family (continued)
Mnemonic Value Models Description
Level-2 Cache Array Access Register L2AAR C000_0089h Enhanced Power Management Register
Notes:
supported page page supported page
EPMR
C000_0086h
Standard-power versions only. Low-power versions only.
Table
Summary Model Differences within AMD-K6Family
EFER2 WHCR3 4092 PSOR STAR UWCCR PFIR L2AAR EPMR
Standard EWBEC Model Stepping MSRs1
Notes:
There four MSRs that every model stepping AMD-K6 family processors support identically-MCAR, MCTR, TR12, TSC. L2D, EWBEC, bits/fields supported EFER indicated models/steppings. models/steppings support System Call Extension (SCE) EFER, even corresponding SYSCALL SYSRET instructions STAR register supported. Indicates whether WAELIM field supports Mbytes 4092 Mbytes memory. location WAE15M WAELIM field within WHCR register differs between models/steppings that support Mbytes memory those that support 4092 Mbytes memory. Supported standard-power versions only. Supported low-power versions only.
Model-Specific Registers Overview
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Standard Model-Specific Registers (All Models)
This section describes four standard MSRs that every model stepping AMD-K6 family processors support identically. appropriate AMD-K6 AMD-K6E processor data sheet more detail these standard registers. Machine-Check Address Register (MCAR) Machine-Check Type Register (MCTR) processor does support generation machine check exception, does provide 64-bit Machine Check Address Register (MCAR) 64-bit Machine Check Type Register (MCTR) software compatibility. Because processor does support machine check exceptions, contents MCAR MCTR only affected WRMSR instruction RESET being sampled asserted (where bits each register reset processor also provides Machine Check Exception (MCE) Control Register (CR4, read-write bit. However, state this effect operation processor. Test Register (TR12) processor provides 64-bit Test Register (TR12), only Cache Inhibit (CI) (bit TR12) supported. other bits TR12 have effect processor's operation. Note: Trap Restart function (bit TR12) always enabled AMD-K6 processors. Time Stamp Counter (TSC) With each processor clock cycle, processor increments 64-bit time stamp counter (TSC) MSR. counter written read using WRMSR RDMSR instructions when register contains value current privilege level (CPL) counter also read using RDTSC instruction, required privilege level this instruction determined Time Stamp Disable (TSD) CR4. With either these instructions, registers hold upper lower dwords 64-bit value written read from TSC, follows: EDX-Upper bits EAX-Lower bits loaded with arbitrary value. This feature compatible with Pentium processor.
Model-Specific Registers Overview
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Model Model 8/[7:0] Registers
AMD-K6E processor Model AMD-K6-2 processor Model 8/[7:0] provide model-specific registers listed Table contents selects addressed RDMSR WRMSR instruction. Table Model-Specific Registers Supported Models 8/[7:0]
Mnemonic Value Description Comments
Register Name
Machine-Check Address Register Machine-Check Type Register Test Register Time Stamp Counter Extended Feature Enable Register Write Handling Control Register
MCAR MCTR TR12 EFER WHCR
C000_0080h C000_0082h C000_0081h
page page page page page page page
Identical models Identical models Identical models Identical models
SYSCALL/SYSRET Target Address Register STAR
supported Model
Model Model 8/[7:0] Registers
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Extended Feature Enable Register (EFER)
Extended Feature Enable Register (EFER) contains control bits that enable extended features AMD-K6 processor. Figure shows format EFER register, Table defines function each EFER register. EFER register C000_0080h.
Reserved Symbol Description System Call Extension
Figure Extended Feature Enable Register (EFER) (Models 8/[7:0])
Table Extended Feature Enable Register (EFER) Definition (Models 8/[7:0])
63-1
Notes:
Description
Function
Reserved System Call Extension (SCE)1
Writing reserved causes general protection fault occur. reserved bits always read must enable usage SYSCALL SYSRET instructions.
AMD-K6E processor Model provides EFER register, this does affect processor operation because SYSCALL SYSRET instructions STAR register supported this models.
Model Model 8/[7:0] Registers
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Write Handling Control Register (WHCR)
Write Handling Control Register (WHCR) (see Figure page that contains three fields Write Cacheability Detection Enable (WCDE) bit, Write Allocate Enable Limit (WAELIM) field, Write Allocate Enable 15-to-16-Mbyte (WAE15M) bit. WHCR register C000_0082h. AMD-K6 processors contain split level-1 (L1) 64-Kbyte writeback cache organized separate 32-Kbyte instruction cache 32-Kbyte data cache with two-way associativity. cache line size bytes lines read from memory using efficient pipelined burst read cycle. Further performance gains achieved implementation write allocation scheme. Write Allocation write allocate, enabled, occurs when processor pending memory write cycle cacheable line line does currently reside cache. more information, Implementation Write Allocate K86Processors Application Note, order# 21326, "Cache Organization" chapter appropriate AMD-K6 AMD-K6E processor data sheet. This section describes programmable mechanisms used processor determine when perform write allocate. When either these mechanisms indicates that pending write cacheable area memory, write allocate performed. cacheability/writeability, BIOS must writeback invalidate internal cache using WBINVD instruction. addition, write allocate should enabled only after performing memory sizing typing algorithms.
Model Model 8/[7:0] Registers
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WAELIM
Reserved Symbol WCDE WAELIM WAE15M Description Bits Always program Write Allocate Enable Limit Write Allocate Enable 15-to-16-Mbyte
Note: Hardware RESET initializes this zeros.
Figure Write Handling Control Register (WHCR) (Models 8/[7:0]) Write Cacheability Detection Enable Write Allocate Enable Limit Field proper functionality, always program WHCR "Pipelining Support" page more information WCDE bit. WAELIM field bits wide. This field, multiplied Mbytes, defines upper memory limit. pending write cycle that misses cache that addresses memory below this limit causes processor perform write allocate (assuming address within range where write allocates disallowed). Write allocate disabled memory accesses above this limit unless processor determines pending write cycle cacheable means other write allocate mechanisms "Write Cacheable Page" "Write Sector" (for more information, "Cache Organization" chapter appropriate AMD-K6 AMD-K6E processor data sheet. maximum value this limit ((27-1) Mbytes) Mbytes. When bits this field memory above this limit write allocate mechanism disabled (even bits WAELIM field write allocates still occur "Write Cacheable Page" "Write Sector" mechanisms). Once BIOS determines amount installed system, this number should also used program WAELIM field. example, system with Mbytes would program WAELIM field with value 0001000b.
Model Model 8/[7:0] Registers
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This value (8), when multiplied Mbytes, yields Mbytes write allocate limit. Write Allocate Enable 15-to-16-Mbyte Field. WAE15M used enable write allocations memory write cycles that address Mbyte memory between Mbytes Mbytes. This must allow write allocates this memory area. This sub-mechanism WAELIM provides memory hole prevent write allocates. This memory hole provided account small number uncommon memory-mapped adapters that this particular memory address space. system contains these peripherals, should (even WAE15M write allocates still occur between Mbytes Mbytes "Write Cacheable Page" "Write Sector" mechanisms). WAE15M ignored value WAELIM field less than Mbytes. definition, write allocations performed memory area between Kbytes Mbyte unless processor determines pending write cycle cacheable means "Write Cacheable Page" "Write Sector." safe perform write allocations between Kbytes Mbyte (000A_0000h 000F_FFFFh) because considered noncacheable region memory.
Model Model 8/[7:0] Registers
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SYSCALL/SYSRET Target Address Register (STAR)
Models implement STAR register. This register contains target address used SYSCALL instruction 16-bit code stack segment selector bases used SYSCALL SYSRET instructions. Figure shows format STAR register, Table defines function each field STAR register. STAR register C000_0081h. more information about SYSCALL/SYSRET, SYSCALL SYSRET Instruction Specification Application Note, order# 21086.
SYSRET Selector Selector Base
SYSCALL Selector Selector Base
Target Address
Figure SYSCALL/SYSRET Target Address Register (STAR) (Models Table SYSCALL/SYSRET Target Address Register (STAR) Definition (Models
63-48 Description Function
SYSRET Selector Base
During SYSRET instruction, this field copied into register contents this field, plus 1000b, copied into register. During SYSCALL instruction, this field copied into register contents this field, plus 1000b, copied into register. During SYSCALL instruction, this address copied into points starting address.
47-32
SYSCALL Selector Base Target Address
31-0
Model Model 8/[7:0] Registers
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Model 8/[F:8] Registers
AMD-K6-2 processor Model 8/[F:8] AMD-K6-2E processor Model 8/[F:8] provides MSRs listed Table contents select addressed RDMSR WRMSR instruction. Table Model-Specific Registers Supported Model 8/[F:8]
Register Name Mnemonic Value Description Comments
Machine-Check Address Register Machine-Check Type Register Test Register Time Stamp Counter Extended Feature Enable Register Write Handling Control Register UC/WC Cacheability Control Register Processor State Observability Register Page Flush/Invalidate Register
MCAR MCTR TR12 EFER WHCR UWCCR PSOR PFIR
C000_0080h C000_0082h C000_0081h C000_0085h C000_0087h C000_0088h
page page page page page page page page page page
Identical models Identical models Identical models Identical models Newly defined Model 8/[F:8] Newly defined Model 8/[F:8] Identical Model 8/[7:0] Model 8/[F:8] Model 8/[F:8] Model 8/[F:8]
SYSCALL/SYSRET Target Address Register STAR
Model 8/[F:8] Registers
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Extended Feature Enable Register (EFER)
Extended Feature Enable Register (EFER) contains control bits that enable extended features processor. Figure shows format EFER register, Table defines function each EFER register. EFER register C000_0080h. Note: EFER register defined models 8/[7:0] defined differently Model 8/[F:8]. complete description newly defined register included this section Model 8/[F:8].
EWBEC
Reserved Symbol EWBEC Description EWBE Control Data Prefetch Enable System Call Extension
Figure Extended Feature Enable Register (EFER) (Model 8/[F:8]) Table Extended Feature Enable Register (EFER) Definition (Model 8/[F:8])
63-4 Description Function
Reserved
Writing reserved causes general protection fault occur. reserved bits always read This 2-bit field controls behavior processor with respect ordering write cycles EWBE# signal. EFER[3] EFER[2] Global EWBE# Disable (GEWBED) Speculative EWBE Disable (SEWBED), respectively. must enable data prefetching (this default setting following reset). enabled, cache misses initiated memory read within 32-byte cache line conditionally followed cache-line fetches other line 64-byte sector. must enable usage SYSCALL SYSRET instructions.
EWBE# Control (EWBEC)
Data Prefetch Enable (DPE)
System Call Extension (SCE)
External Write Buffer Empty Control Field
Model 8/[F:8] contains 8-byte write merge buffer that allows processor conditionally combine data from multiple noncacheable write cycles into this merge buffer. merge Model 8/[F:8] Registers
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buffer operates conjunction with Memory Type Range Registers (MTRRs). Refer "UC/WC Cacheability Control Register (UWCCR)" page description MTRRs. Merging multiple write cycles into single write cycle reduces processor utilization processor stalls, thereby increasing overall system performance. Out-of-Order Write Cycles. sence merge creates potential perform out-of-order write cycles relative processor's cache. general, ordering write cycles that driven externally system those that processor's cache controlled EWBE# signal. EWBE# sampled negated, processor delays commitment write cycles cache lines modified state exclusive state processor's cache. Therefore, system logic enforce strong ordering negating EWBE# until external write cycle complete, thereby ensuring that subsequent write cycle that hits cache does complete ahead external write cycle. However, addition write merge buffer introduces potential out-of-order write cycles occur between writes merge buffer writes processor's cache. Because these writes occur entirely within processor sent processor bus, system logic able enforce strong ordering with EWBE# signal. EWBE# control (EWBEC) bits provide mechanism enforcing three different levels write ordering presence write merge buffer: Best Performance. EFER[3] defined Global EWBE# Disable (GEWBED). When GEWBED equals processor does attempt enforce write ordering internally externally (the EWBE# signal ignored). This maximum performance setting. Close-to-Best Performance. EFER[2] defined Speculative EWBE# Disable (SEWBED). SEWBED only fect processor when GEWBED equals GEWBED equals SEWBED equals processor enforces strong ordering internal write cycles with exception write cycles addressed range memory defined uncacheable (UC) write-combining (WC) MTRRs. addition, processor Model 8/[F:8] Registers
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samples EWBE# signal. EWBE# sampled negated, processor delays commitment write cycles processor cache lines modified state exclusive state until EWBE# sampled asserted. This setting provides performance comparable slightly less than, performance obtained when GEWBED equals because some degree write ordering maintained. Slowest Performance. GEWBED equals SEWBED equals processor enforces strong ordering internal external write cycles. this setting, processor assumes, speculates, that strong order must maintained between writes merge buffer writes that processor's cache. Once merge buffer written processor's bus, EWBE# signal sampled. EWBE# sampled negated, processor delays commitment write cycles processor cache lines modified state exclusive state until EWBE# sampled asserted. This setting default after RESET provides lowest performance three settings because full write ordering maintained. Write Ordering Performance. Table summarizes three settings EWBEC field, along with effect write ordering performance. Table Write Ordering Performance Settings EFER Register
EFER[3] (GEWBED) (Default) EFER[2] (SEWBED) (Default) Write Ordering Performance
None except UC/WC
Best Close-to-Best Slowest
Enforcing complete write ordering uniprocessor system usually necessary. order achieve highest level performance while still maintaining support EWBE# signal, recommends that BIOS EFER[3:2] (close-to-best performance). Many uniprocessor systems support EWBE# signal, which case recommends that BIOS EFER[3:2] (best performance).
Model 8/[F:8] Registers
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Write Handling Control Register (WHCR)
Write Handling Control Register (WHCR) (see Figure page that contains fields-the Write Allocate Enable Limit (WAELIM) field Write Allocate Enable 15-to-16-Mbyte (WAE15M) bit. WHCR register C000_0082h. Note: WHCR register defined models 8/[7:0] defined differently models 8/[F:8], complete description newly defined register included this section models 8/[F:8], AMD-K6 processors contain split level-1 (L1) 64-Kbyte writeback cache organized separate 32-Kbyte instruction cache 32-Kbyte data cache with two-way associativity. cache line size bytes, lines read from memory using efficient pipelined burst read cycle. Further performance gains achieved implementation write allocation scheme. Write Allocation write allocate, enabled, occurs when processor pending memory write cycle cacheable line line does currently reside cache. more information write allocate, Implementation Write Allocate K86Processors Application Note, order# 21326 "Cache Organization" chapter appropriate AMD-K6 AMD-K6E processor data sheet. This section describes programmable mechanisms used processor determine when perform write allocate. When either these mechanisms indicates that pending write cacheable area memory, write allocate performed. cacheability, BIOS must write back invalidate internal cache using WBINVD instruction. addition, write allocate should enabled only after performing memory sizing typing algorithms.
Model 8/[F:8] Registers
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WAELIM
Reserved Symbol WAELIM WAE15M Description Bits Write Allocate Enable Limit 31-22 Write Allocate Enable 15-to-16-Mbyte
Note: Hardware RESET initializes this zeros.
Figure Write Handling Control Register (WHCR) (Models 8/[F:8], Write Allocate Enable Limit Field WAELIM field bits wide. This field, multiplied Mbytes, defines upper memory limit. pending write cycle that misses cache that addresses memory below this limit causes processor perform write allocate (assuming address within range where write allocates disallowed). Write allocate disabled memory accesses above this limit unless processor determines pending write cycle cacheable means other write allocate mechanisms "Write Cacheable Page" "Write Sector" (for more information, "Cache Organization" chapter appropriate AMD-K6 AMD-K6E processor data sheet. maximum value this limit ((210 Mbytes) 4092 Mbytes. When bits this field memory above this limit write allocate mechanism disabled (even bits WAELIM field write allocates still occur "Write Cacheable Page" "Write Sector" mechanisms). Once BIOS determines amount installed system, this number should also used program WAELIM field. example, system with Mbytes 00_0000_1000b. This value (8), when multiplied Mbytes, yields Mbytes write allocate limit.
Model 8/[F:8] Registers
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Write Allocate Enable 15-to-16-Mbyte Field
WAE15M used enable write allocations memory write cycles that address Mbyte memory between Mbytes Mbytes. This must allow write allocates this memory area. This sub-mechanism WAELIM provides memory hole prevent write allocates. This memory hole provided account small number uncommon memory-mapped adapters that this particular memory address space. system contains these peripherals, should (even WAE15M write allocates still occur between Mbytes Mbytes "Write Cacheable Page" "Write Sector" mechanisms). WAE15M ignored value WAELIM field less than Mbytes. definition, write allocations performed memory area between Kbytes Mbyte unless processor determines pending write cycle cacheable means "Write Cacheable Page" "Write Sector." safe perform write allocations between Kbytes Mbyte (000A_0000h 000F_FFFFh) because considered noncacheable region memory. Additionally, memory region defined write-combinable uncacheable MTRR, write allocates performed that region.
Model 8/[F:8] Registers
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UC/WC Cacheability Control Register (UWCCR)
Models 8/[F:8], provide variable-range Memory Type Range Registers (MTRRs)-MTRR0 MTRR1-that each specify range memory. Each range defined following memory types: Uncacheable (UC) Memory-Memory read cycles sourced directly from specified memory address, processor does allocate cache line. Memory write cycles targeted specified memory address, write allocation does occur. Write-Combining (WC) Memory-Memory read cycles sourced directly from specified memory address, processor does allocate cache line. processor conditionally combines data from multiple noncacheable write cycles that addressed within this range into merge buffer. Merging multiple write cycles into single write cycle reduces processor utilization processor stalls, thereby increasing overall system performance. This memory type applicable linear video frame buffers. Note: MTRRs defined this document softwarecompatible MTRRs defined Pentium Pentium processors.
programmer accesses MTRRs addressing 64-bit known UC/WC Cacheability Control Register (UWCCR). address UWCCR C000_0085h. Following reset, bits UWCCR register MTRR0 (lower bits UWCCR register) defines size memory type range MTRR1 (upper bits) defines size memory type range (see Figure page 31). Prior programming write-combining uncacheable areas memory UWCCR, software must disable processor's cache, then flush cache. This achieved setting executing WBINVD instruction. Following programming UWCCR, processor's cache must enabled setting
Model 8/[F:8] Registers
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Symbol
Description Uncacheable Memory Type Write-Combining Memory Type
Bits
Symbol
Description Uncacheable Memory Type Write-Combining Memory Type
Bits
Physical Base Address
Physical Address Mask
Physical Base Address
Physical Address Mask
MTRR1
MTRR0
Figure UC/WC Cacheability Control Register (UWCCR) (Models 8/[F:8], Physical Base Address (n=0, This address most-significant bits physical base address memory range. least-significant bits base address needed because base address definition always aligned 128-Kbyte boundary. This value most-significant bits physical address mask that used define size memory range. This mask logically ANDed with both physical base address field UWCCR register physical address generated processor. results operations equal, then generated physical address considered within range. That
Mask Physical Base Address Mask Physical Address Generated
Physical Address Mask (n=0,
then, physical address generated processor range. (n=0, When this memory range defined writecombinable (refer Table 15). Write-combinable memory uncacheable. When this memory range defined uncacheable (refer Table 15). Table WC/UC Memory Type UWCCR Register
Memory Type effect cacheability write-combining Write-combining memory range (uncacheable) Uncacheable memory range
(n=0,
Model 8/[F:8] Registers
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Memory-Range Restrictions
following rules regarding address alignment size each range must adhered when programming physical base address physical address mask fields UWCCR register:
minimum size each range Kbytes. physical base address must aligned 128-Kbyte boundary. physical base address must range-size aligned. example, size range Mbyte, then physical base address must aligned 1-Mbyte boundary. bits physical address mask must contiguous. Likewise, bits physical address mask must contiguous. example: 111_1111_1100_0000b valid physical address mask. 111_1111_1101_0000b invalid.
Table lists valid physical address masks resulting range sizes that programmed UWCCR register. Table Valid Masks Range Sizes UWCCR Register
Masks Size
111_1111_1111_1111b 111_1111_1111_1110b 111_1111_1111_1100b 111_1111_1111_1000b 111_1111_1111_0000b 111_1111_1110_0000b 111_1111_1100_0000b 111_1111_1000_0000b 111_1111_0000_0000b 111_1110_0000_0000b 111_1100_0000_0000b 111_1000_0000_0000b 111_0000_0000_0000b 110_0000_0000_0000b 100_0000_0000_0000b 000_0000_0000_0000b
Kbytes Kbytes Kbytes Mbyte Mbytes Mbytes Mbytes Mbytes Mbytes Mbytes Mbytes Mbytes Mbytes Gbyte Gbytes Gbytes
Model 8/[F:8] Registers
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Examples
Suppose that range memory from Mbytes Mbytes uncacheable, 8-Mbyte range memory Gbyte writ e-com binable Range ined uncacheable range, range defined writecombining range.
Extracting most-significant bits 32-bit physical base address that corresponds Mbytes (0100_0000h) yields physical base address field 000_0000_1000_0000b. Because uncacheable range size Mbytes, physical mask value field 111_1111_1000_0000b, according Table page UWCCR register (WC0) UWCCR register (UC0). Extracting most-significant bits 32-bit physical base address that corresponds Gbyte (4000_0000h) yields physical base address field 010_0000_0000_0000b. Because write-combining range size Mbytes, physical mask value field 111_1111_1100_0000b, according Table UWCCR register (WC1) UWCCR register (UC1).
Model 8/[F:8] Registers
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Processor State Observability Register (PSOR)
Models 8/[F:8], standard-power versions Model provide Processor State Observability Register (PSOR) defined Figure PSOR register C000_0087h. Note: page definitions PSOR fields lowpower Model processors.
STEP
Reserved Symbol NOL2 STEP Description Functionality Processor Stepping Frequency Divisor
Figure Processor State Observability Register (PSOR) (Models 8/[F:8], Standard-Power NOL2 This read-only indicates whether processor contains cache. Note: This always Model 8/[F:8]. Note: This always Models STEP Field This read-only field contains stepping This identical value returned CPUID standard function EAX[3:0]. This read-only field contains value signals sampled processor during falling transition RESET, which allows BIOS determine frequency host bus.
Field
core frequency must first known, which determined using Time Stamp Counter method (See "Time Stamp Counter (TSC)" page 16). core frequency then divided processor-clock bus-clock ratio determined field PSOR register (see Table Table page 35). result frequency processor bus.
Model 8/[F:8] Registers
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Table Processor-to-Bus Clock Ratios (Models 8/[F:8]
State BF[2:0]
100b 101b 110b 111b 000b 001b 010b 011b
Notes:
Processor-Clock Bus-Clock Ratio
2.5x 3.0x 6.0x1 3.5x 4.5x 5.0x 4.0x 5.5x
2.0x ratio that supported models 8/[7:0] supported models 8/[F:8] Instead, BF[2:0] equals 110b, ratio 6.0x selected.
Table Processor-to-Bus Clock Ratios (Model Standard-Power
State BF[2:0]
100b 101b 110b 111b 000b 001b 010b 011b
Notes:
Processor-Clock Bus-Clock Ratio
2.0x1 3.0x 6.0x 3.5x 4.5x 5.0x 4.0x 5.5x
2.5x ratio that supported model 8/[F:8] supported standard-power model Instead, BF[2:0] equals 100b, ratio 2.0x selected.
Model 8/[F:8] Registers
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Page Flush/Invalidate Register (PFIR)
Models 8/[F:8], contain Page Flush/Invalidate Register (PFIR) (see Figure that allows cache invalidation optional flushing specific 4-Kbyte page from linear address space. total amount cache processor Kbytes. Using this register result much lower cycle count flushing particular pages versus flushing entire cache. When PFIR written (using WRMSR instruction), invalidation and, optionally, flushing begins. PFIR register C000_0088h. Note: invalidate flush operations affect both caches models
LINPAGE
Reserved Symbol LINPAGE Description 20-bit Linear Page Address Page Fault Occurred Flush/Invalidate Command 31-12
Figure Page Flush/Invalidate Register (PFIR) (Models 8/[F:8], LINPAGE Field This 20-bit field must written with bits 31:12 linear address 4-Kbyte page that invalidated optionally flushed from cache. attempt invalidate flush page results page fault, processor sets invalidate flush operation performed (even though invalidate operations normally generate page faults). this case, actual page fault exception generated. equals after invalidate flush operation, then operation executed successfully. must read after every write PFIR register determine invalidate flush operation executed successfully. Model 8/[F:8] Registers
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This used control type action that occurs specified linear page. written this bit, operation flush, which case cache lines modified state within specified page written back memory, after which entire page invalidated. written this bit, operation invalidation, which case entire page invalidated without occurrence writebacks.
Model 8/[F:8] Registers
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Model Registers
AMD-K6-III processor (Model provides eleven modelspecific registers listed Table contents selects addressed RDMSR WRMSR instruction. AMD-K6-III processor contains split Level-1 (L1) 64-Kbyte writeback cache organized separate 32-Kbyte instruction cache 32-Kbyte data cache with two-way associativity. cache line size bytes, lines read from memory using efficient pipelined burst read cycle. addition, processor also contains 256-Kbyte, 4-way associative, unified level-2 (L2) cache. Further performance gains achieved implementation write allocation scheme. Table Model-Specific Registers Supported Model
Register Name Mnemonic Value Description Comments
Machine-Check Address Register Machine-Check Type Register Test Register Time Stamp Counter Extended Feature Enable Register Write Handling Control Register
MCAR MCTR TR12 EFER WHCR
C000_0080h C000_0082h C000_0081h C000_0085h C000_0087h C000_0088h C000_0089h
page page page page page page page page page page page
Identical models Identical models Identical models Identical models Adds Disable (L2D) Model 8/[F:8] implementation Identical Model 8/[F:8] Identical Model 8/[7:0] Identical Model 8/[F:8] Identical Model 8/[F:8] Identical Model 8/[F:8]. invalidate flush operations affect both caches AMD-K6-III processor. Model
SYSCALL/SYSRET Target Address RegisSTAR UC/WC Cacheability Control Register Processor State Observability Register Page Flush/Invalidate Register Level-2 Cache Array Access Register UWCCR PSOR PFIR L2AAR
Model Registers
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Extended Feature Enable Register (EFER)
Figure shows format EFER register models Table defines function each EFER register. EFER register C000_0080h. Note: Bits EFER register models identical implementation these bits Model 8/[F:8]. models Disable (L2D), EFER[4], added. complete register description included this section.
EWBEC
Reserved Symbol EWBEC Description Disable EWBE Control Data Prefetch Enable System Call Extension
Figure Extended Feature Enable Register (EFER) (Models Table Extended Feature Enable Register (EFER) Definition (Models
Description 63-5 Reserved Function
Disable (L2D)
EWBE Control (EWBEC)
Data Prefetch Enable (DPE) System Call Extension (SCE)
Writing reserved causes general protection fault occur. reserved bits always read cache completely disabled. This provided debug testing purposes. normal operation maximum performance, this must (this default setting following reset). This 2-bit field controls behavior processor with respect ordering write cycles EWBE# signal. EFER[3] EFER[2] Global EWBE# Disable (GEWBED) Speculative EWBE# Disable (SEWBED), respectively. must enable data prefetching (this default setting following reset). enabled, cache misses initiated memory read within 32-byte cache line conditionally followed cache-line fetches other line 64-byte sector. must enable usage SYSCALL SYSRET instructions.
Note: Setting does guarantee cache coherency. ensure coherency, processor's caches must disabled setting register then flushed prior setting Model Registers
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Level-2 Cache Array Access Register (L2AAR)
Models provide L2AAR register that allows direct access cache arrays. cache AMD-K6-III processor organized shown Figure
Four 64-Kbyte ways Each contains 1024 sets Each contains four 64-byte sectors (one sector each way) Each sector contains 32-byte cache lines Each cache line contains four 8-byte octets Each octet contains upper lower dword bytes)
Each line within sector contains MESI state bits, associated with each sector least recently used (LRU) information.
bytes bytes
Tag/LRU Line1/MESI Line0/MESI Tag/LRU
bytes
Line1/MESI Line0/MESI Tag/LRU
bytes
Line1/MESI Line0/MESI Tag/LRU
Line1/MESI
Line0/MESI
1024 sets
1023
Figure Cache Organization (AMD-K6TM-III Processor) L2AAR register C000_0089h. operation that performed cache function instruction executed RDMSR WRMSR contents register. register specifies location access, whether access cache data tags (see Figure page 41). Figure page shows cache sector line organization. (see Figure address cache line equals then this cache line stored Line sector. Similarly, address cache line equals then this cache line stored Line sector. Model Registers
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Octet Octet Octet Octet
Upper Dword
Lower Dword
Upper Dword
Lower Dword
Line Sector
Line
Figure Cache Sector Line Organization (T/D) determines whether access cache data tag. Table page describes operation that performed based instruction bit.
Symbol Description Selects Data access Selects desired cache 17-16
Octet
Reserved Symbol Line Octet Dword Description Selects desired cache Selects Line1 Line0 Selects four octets Selects upper lower dword 15-6
Figure Data Location (AMD-K6TM-III Processor)-EDX
Model Registers
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Table versus Data Selector
Instruction
RDMSR RDMSR WRMSR WRMSR
(EDX[20])
Operation
Read dword from data array into EAX. Dword location specified EDX. Read tag, line state information from array into EAX. Location specified EDX. Write dword data array using data EAX. Dword location specified EDX. Write tag, line state information into array from EAX. Location specified EDX.
When L2AAR read written, left unchanged. This facilitates multiple accesses when testing entire cache/tag array. cache data read opposed reading information), result (dword) placed format illustrated Figure Similarly, cache data written, write data taken from EAX.
Data
Figure Data-EAX read opposed reading cache data), result placed format illustrated Figure page Similarly, written, write data taken from EAX. When accessing tag, Line, Octet, Dword fields register ignored.
Model Registers
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Line1ST Line0ST
Reserved Symbol Line1ST Line0ST Description data read written Line state (M=11, E=10, S=01, I=00) Line state (M=11, E=10, S=01, I=00) bits each 31-15 11-10
Figure Information (AMD-K6TM-III Processor)-EAX (Least Recently Used) Field 4-way associative cache, each 2-bit field each sector. Values field 00b, 01b, 10b, 11b, where indicates that sector "most recently used," indicates that sector "least recently used" (see Figure 16). EAX[7:6] indicate information EAX[5:4] EAX[3:2] EAX[1:0]
Values Most Recently Used Used More Recently Than 10b, Less Recently Than Used More Recently Than 11b, Less Recently Than Least Recently Used
Figure Byte Writing AMD-K6TM-III Processor When writing AMD-K6-III processor, special consideration must given least significant field register- EAX[15]. length required support 256-Kbyte cache AMD-K6-III processor bits, which corresponds bits 31:16 register. However, AMD-K6-III processor provides total bits storing tag-that bits (EAX[31:16]), plus additional internal purposes (EAX[15]). During normal operation, AMD-K6-III processor ensures that this additional (bit always corresponds which resides. Note that bits
Model Registers
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15:6 address determine set, which case equal addresses sets through 511, equal addresses sets through 1023. order full 17-bit properly when using L2AAR register, EAX[15] must likewise correspond which being written-that EAX[15] must equal EDX[15] (refer Figure page Figure page 43). important note that this special consideration only required AMD-K6-III processor will subsequently expected properly execute instructions access data from cache following setup cache means L2AAR register. intent using L2AAR register solely test debug cache without subsequent intent executing instructions accessing data from cache, then this consideration required.
Model Registers
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Model Registers
AMD-K6-2E+ AMD-K6-IIIE+ processors (Model provide twelve model-specific registers listed Table contents selects addressed RDMSR WRMSR instruction. AMD-K6-2E+ AMD-K6-IIIE+ processors contain split Level-1 (L1) 64-Kbyte writeback cache organized separate 32-Kbyte instruction cache 32-Kbyte data cache with two-way associativity. cache line size bytes, lines read from memory using efficient pipelined burst read cycle. addition, these processors also contain 128Kbyte (AMD-K6-2E+ processor) 256-Kbyte (AMD-K6-IIIE+ processor), 4-way associative, unified Level-2 (L2) cache. Further performance gains achieved implementation write allocation scheme. Table Model-Specific Registers Supported Model
Register Name Mnemonic Value Description Comments
Machine-Check Address Register Machine-Check Type Register Test Register Time Stamp Counter Extended Feature Enable Register Write Handling Control Register UC/WC Cacheability Control Register Processor State Observability Register Page Flush/Invalidate Register Level-2 Cache Array Access Register Enhanced Power Management Register2
Notes:
MCAR MCTR TR12 EFER WHCR UWCCR PSOR PFIR L2AAR EPMR
page page page page
Identical models Identical models Identical models Identical models Adds Disable (L2D) Model 8/[F:8] implementation Identical Model 8/[F:8] Identical Model 8/[7:0] Identical Model 8/[F:8] Standard-power implementation identical Model 8/[F:8]. Lowpower implementation adds fields renames EBF. Identical Model 8/[F:8] Identical Model note differing cache sizes Model Model Supported low-power versions only.
C000_0080h page C000_0082h page C000_0081h page C000_0085h page page 341, C000_0087h page C000_0088h page C000_0089h page C000_0086h page
SYSCALL/SYSRET Target Address Register STAR
Standard-power versions only. Low-power versions only.
Model Registers
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Processor State Observability Register (PSOR) (Low-Power Versions)
low-power versions AMD-K6-2E+ AMD-K6-IIIE+ processors provide Processor State Observability Register (PSOR) defined Figure Note: Standard-power versions Model support PSOR defined page PSOR register C000_0087h.
Symbol
Description Frequency Divisor Voltage
Bits 23-21 20-16
STEP
EBF[2:0]
PBF[2:0]
Reserved Symbol NOL2 STEP Description Functionality Processor Stepping Effective Frequency Divisor Bits
Figure Processor State Observability Register (PSOR) (Model Low-Power Versions) PBF[2:0] Field This read-only field contains divisor values externally applied processor BF[2:0] pins. These input values sampled processor during falling transition RESET. Note: This divisor value different than divisor value supplied processor's internal PLL. Field This read-only field contains Voltage bits driven processor VID[4:0] pins RESET. These bits initialized 01010b driven VID[4:0] pins RESET. Note: Low-power AMD-K6-2E+ AMD-K6-IIIE+ processors support PowerNow! technology, which enables dynamic alteration processor's core voltage. "Enhanced Power Management Register (EPMR) (LowPower Versions)" page information programming VID[4:0] pins.
Model Registers
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NOL2
This read-only indicates whether processor contains cache. Note: This always Model
STEP Field EBF[2:0] Field
This read-only field contains stepping This identical value returned CPUID standard function EAX[3:0]. This read-only field contains effective value divisor supplied processor's internal PLL, which allows BIOS determine frequency host bus.
core frequency must first determined using Time Stamp Counter method (See "Time Stamp Counter (TSC)" page 16). core frequency then divided processor-to-bus clock ratio determined field PSOR register (see Table 23). result frequency processor bus.
Table Processor-to-Bus Clock Ratios (Low-Power Model
State EBF[2:0] 100b 101b 110b 111b 000b 001b 010b 011b
Notes:
Processor-to-Bus Clock Ratio 2.0x1 3.0x 6.0x 3.5x 4.5x 5.0x 4.0x 5.5x
2.5x ratio that supported Models supported low-power Model Instead, ratio 2.0x selected when EBF[2:0] equals 100b.
Model Registers
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Level-2 Cache Array Access Register (L2AAR)
Model also provides L2AAR register that allows direct access cache arrays. Note: L2AAR register identical Model implementation. Some information this section duplicated account different cache sizes AMD-K6-2E+ AMD-K6-IIIE+ processors. cache AMD-K6-2E+ AMD-K6-IIIE+ processors organized shown Figure
Four 32-Kbyte ways (AMD-K6-2E+ processor) four 64Kbyte ways (AMD-K6-IIIE+ processor) Each contains (AMD-K6-2E+ processor) 1024 (AMD-K6-IIIE+ processor) sets Each contains four 64-byte sectors (one sector each way) Each sector contains 32-byte cache lines Each cache line contains four 8-byte octets Each octet contains upper lower dword bytes)
Each line within sector contains MESI state bits, associated with each sector (Least Recently Used) information.
bytes bytes
Tag/LRU Line1/MESI Line0/MESI Tag/LRU
bytes
Line1/MESI Line0/MESI Tag/LRU
bytes
Line1/MESI Line0/MESI Tag/LRU
1024 sets
Line1/MESI
Line0/MESI
1023
Figure Cache Organization
Model Registers
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L2AAR register C000_0089h. operation that performed cache function instruction executed RDMSR WRMSR contents register. register specifies location access, whether access cache data tags (refer Figure page AMD-K6-2E+ processor Figure page AMD-K6-IIIE+ processor). Figure shows cache sector line organization. (refer Figure AMD-K6-2E+ processor Figure AMD-K6-IIIE+ processor) address cache line equals then this cache line stored Line sector. Similarly, address cache line equals then this cache line stored Line sector.
Octet Octet Octet Octet
Upper Dword
Lower Dword
Upper Dword
Lower Dword
Line Sector
Line
Figure Cache Sector Line Organization (same Figure EDX, which most significant field, used AMD-K6-2E+ because there half many sets implemented AMD-K6-2E+ (512 sets) AMD-K6-IIIE+ processor (1024 sets). (T/D) determines whether access cache data tag. Table page describes operation that performed based instruction bit.
Model Registers
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Symbol
Description Selects Data access Selects desired cache
17-16
Octet
Reserved Symbol Line Octet Dword Description Selects desired cache Selects Line1 Line0 Selects four octets Selects upper lower dword 14-6
Figure Data Location (AMD-K6TM-2E+ Processor)-EDX
Symbol
Description Selects Data access Selects desired cache
17-16
Octet
Reserved Symbol Line Octet Dword Description Selects desired cache Selects Line1 Line0 Selects four octets Selects upper lower dword 15-6
Figure Data Location (AMD-K6TM-IIIE+ Processor)-EDX
Model Registers
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Table versus Data Selector (same Table
Instruction
RDMSR RDMSR WRMSR WRMSR
(EDX[20])
Operation
Read dword from data array into EAX. Dword location specified EDX. Read tag, line state information from array into EAX. Location specified EDX. Write dword data array using data EAX. Dword location specified EDX. Write tag, line state information into array from EAX. Location specified EDX.
When L2AAR read written, left unchanged. This facilitates multiple accesses when testing entire cache/tag array. cache data read opposed reading information), result (dword) placed format illustrated Figure Similarly, cache data written, write data taken from EAX.
Data
Figure Data-EAX (same Figure read opposed reading cache data), result placed format illustrated Figure (AMD-K6-IIIE+ processor). Similarly, written, write data taken from EAX. When accessing tag, Line, Octet, Dword fields register ignored.
Model Registers
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Line1ST Line0ST
Reserved Symbol Line1ST Line0ST Description data read written Line state (M=11, E=10, S=01, I=00) Line state (M=11, E=10, S=01, I=00) bits each 31-14 11-10
Figure Information (AMD-K6TM-2E+ Processor)-EAX
Line1ST Line0ST
Reserved Symbol Line1ST Line0ST Description data read written Line state (M=11, E=10, S=01, I=00) Line state (M=11, E=10, S=01, I=00) bits each 31-15 11-10
Figure Information (AMD-K6TM-IIIE+ Processor)-EAX (Least Recently Used) Field 4-way associative cache, each 2-bit field each sector. Values field 00b, 01b, 10b, 11b, where indicates that sector "most recently used," indicates that sector "least recently used" (see Figure page 53). EAX[7:6] indicate information EAX[5:4] EAX[3:2] EAX[1:0]
Model Registers
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Values Most Recently Used Used More Recently Than 10b, Less Recently Than Used More Recently Than 11b, Less Recently Than Least Recently Used
Figure Byte (same Figure Writing AMD-K6-IIIE+ Processor When writing AMD-K6-IIIE+ processor, special consideration must given least significant field register- EAX[15]. length required support 256-Kbyte cache AMD-K6-III AMD-K6-IIIE+ bits, which corresponds bits 31:16 register. However, AMD-K6-IIIE+ processor provides total bits storing tag-that bits (EAX[31:16]), plus additional internal purposes (EAX[15]). During normal operation, AMD-K6-III AMD-K6-IIIE+ ensure that this additional (bit always corresponds which resides. Note that bits 15:6 address determine set, which case equal addresses sets through 511, equal addresses sets through 1023. order full 17-bit properly when using L2AAR register, EAX[15] must likewise correspond which being written-that EAX[15] must equal EDX[15] (refer Figure page Figure page 52). important note that this special consideration only required AMD-K6-IIIE+ processor will subsequently expected properly execute instructions access data from cache following setup cache means L2AAR register. intent using L2AAR register solely test debug cache without subsequent intent executing instructions accessing data from cache, then this consideration required. Note: This special consideration when writing applicable AMD-K6-2E+ processor.
Model Registers
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Enhanced Power Management Register (EPMR) (Low-Power Versions)
support PowerNow! technology, low-power versions AMD-K6-2E+ AMD-K6-IIIE+ processors Model designed with enhanced power management (EPM) features: dynamic divisor control, dynamic voltage control. EPMR register (see Figure defines base address 16-byte block address space. Enabling EPMR allows software access 16-byte block, which contains bits enabling, controlling, monitoring features. Table defines functions each EPMR register. EPMR register C000_0086h.
IOBASE
Reserved Symbol IOBASE GSBC Description Base Address Generate Special Cycle Enable PowerNow! Technology Management 15-4
Figure Enhanced Power Management Register (EPMR) (Low-Power Model Table Enhanced Power Management Register (EPMR) Definition (Low-Power Model
Description Function1
63-16 Reserved 15-4
reserved bits always read IOBASE defines base address 16-byte block address space accessible enabling, controlling, monitoring features. reserved bits always read
BASE Address (IOBASE) Reserved Generate Special Cycle (GSBC)
This controls whether special cycle generated upon dword accesses within 16-byte block. special cycle generated, where BE[7:0]# A[4:3] 00b.
Notes:
Enable PowerNow! Technology Management (EN)
This controls access mapped address space features. Clearing this does affect state bits defined 16-byte block.
bits default when RESET asserted.
Model Registers
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16-Byte Block (Low-Power Versions Only)
16-byte block contains 4-byte field-Bus controlling, monitoring features (see Figure 27). accesses 16-byte block must aligned dword accesses. Except special cycle, valid accesses 16-byte block generate cycles, while non-aligned non-dword accesses passed bus.
Reserved Symbol Description Divisor Voltage Control Bytes 11-8
Figure 16-Byte Block (Low-Power Model Table defines function byte-field within 16-byte block mapped EPMR. Table 16-Byte Block Definition (Low-Power Model
Byte 15-12 11-8
Notes:
Description
Function1
Reserved Divisor Voltage Control (BVC) Reserved
reserved bits always read fields within bytes allow software change processor divisor core voltage. reserved bits always read
bits default when RESET asserted.
Field
Figure page shows format Table defines function each field located within 16-byte block. Note: Stop Grant state low-power, clock-control state entered writing non-zero value SGTC field altering core voltage frequency settings. Systeminitiated inquire (snoop) cycles supported must prevented during Stop Grant clock control state.
Model Registers
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SGTC
IBF[2:0]
VIDO
Reserved Symbol SGTC BVCM VIDC IBF[2:0] VIDO Description Stop Grant Time-out Counter Divisor Change Mode Voltage Control Divisor Control Internal Divisor Voltage Output Bits 31-12
Figure Divisor Voltage Control (BVC) Field (Low-Power Model Table Divisor Voltage Control (BVC) Definition (Low-Power Model
Description Function1
Stop Grant Time-out Counter 31-12 (SGTC)
Writing non-zero value this field causes processor enter Stop Grant state internally. This 20-bit value multiplied 4096 determines duration Stop Grant state, measured processor clocks. This controls mode which bus-divisor voltage control bits allowed change. BVCM=0, Divisor Voltage changes take effect only upon entering Stop Grant state result SGTC field being programmed. BVCM=1 reserved. This controls mode Voltage control. VIDC=0, processor VID[4:0] pins unchanged upon entering Stop Grant state. VIDC=1, processor VID[4:0] pins programmed VIDO value upon entering Stop Grant state. BIOS should initialize this during POST routine. This 2-bit field controls mode divisor control. BDC[1:0]=00b, BF[2:0] pins sampled falling edge RESET. BDC[1:0]=1xb, IBF[2:0] field sampled upon entering Stop Grant state. BDC[1:0]=01b reserved. BIOS should initialize these bits during POST routine. BDC[1:0]=1xb, processor EBF[2:0] field PSOR programmed IBF[2:0] value upon entering Stop Grant state.
Divisor Change Mode (BVCM)
Voltage Control (VIDC)
Divisor Control (BDC)
Internal Divisor (IBF) Voltage Output (VIDO)
Notes:
This 5-bit value driven processor VID[4:0] pins upon enterR/W Stop Grant state VIDC bit=1. These bits initialized 01010b driven processor VID[4:0] pins RESET.
bits default when RESET asserted, except VIDO bits which default 01010b.
Model Registers
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Embedded Processor Recognition
CPUID instruction provides simple hardware software identify type processor feature set. After detecting processor capabilities, software accurately tuned system optimal performance benefit users.
example, game software test performance level available from particular processor detecting type speed processor. features warrant executing additional capabilities advanced algorithms, these enabled with software. Another example involves testing presence 3DNow! instructions processor. software finds these features present when checks feature bits, utilize these more powerful extensions dramatically better performance multimedia software.
example software source code detect processor information.
CPUID Instruction Overview
Software operating privilege level execute CPUID instruction identify processor feature set. addition, CPUID instruction implements multiple functions, each providing different information about processor, including vendor, model number, revision (stepping), features, cache organization, processor name. multiple-function approach allows CPUID instruction return complete picture about type processor capabilities more detailed information than could returned single function. CPUID instruction provides flexibility making only call obtain specific data requested. functions divided into types: standard functions extended functions. Embedded Processor Recognition
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Standard functions provide simple method software access information common processors. Extended functions provide information extensions specific vendor's processor (for example, AMD's processors).
flexibility CPUID instruction allows addition CPUID functions future generations processors. "Appendix page contains detailed description CPUID instruction.
Testing CPUID Instruction
Beginning with AMD-K6E processor Model processors support CPUID instruction. However, still recommended that software verify that CPUID instruction supported. CPUID instruction, software must first determine processor supports CPUID instruction. CPUID support determined following ways:
Execute CPUID instruction check whether illegal instruction exception occurs. exception occurs, processor does have CPUID support. Check (bit EFLAGS register writable. writable (that modified), CPUID instruction supported.
operating system (OS) environment determines which approach more appropriate. These techniques described following sections. Illegal Instruction Exception Method This technique requires user program detect handle illegal instruction exceptions. Where such capabilities present, this method represents reliable detecting support CPUID instruction. CPUID sample code described page uses this approach. This technique retrieves contents EFLAGS using PUSHFD instruction, toggles bit, uses POPFD instruction write modified value into EFLAGS register. then retrieves contents EFLAGS using second PUSHFD instruction checks whether value differs from original value.
EFLAGS ID-Bit Method
Embedded Processor Recognition
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value changed, CPUID instruction available identifying processor features. following code sample demonstrates program uses PUSHFD POPFD instructions test bit.
pushfd ebx, eax, 00200000h push popfd pushfd eax, NO_CPUID Save EFLAGS stack Store EFLAGS Save testing later Switch Copy changed value stack Save changed EFLAGS Push EFLAGS stack Store EFLAGS changed change, CPUID
potential problem with this approach that interrupt trap (such debug trap) occur between POPFD following PUSHFD, that interrupt trap handler code destroys value bit. Where possible, above code should preceded instruction followed instruction, which ensures that interrupts occur between POPFD PUSHFD. However, traps still occur, even code preceded instruction followed instruction.
Using CPUID Functions
When software uses CPUID instruction identify process impo uses inst appropriately. instruction been defined make easy manufactured many different vendors. standard functions (EAX=0 EAX=1) same processors. Having standard functions simplifies software's task testing implementing features common processors. Software test these features and, processors released, benefit from these capabilities immediately. Extended functions specific vendor's processor. These rovi iona processors that software identify enhanced features functions. test extended functions, software checks
Embedded Processor Recognition
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value least 8000_0001h register returned function 8000_0000h. Within AMD's family processors, different members execute different number functions. Table summarizes CPUI functio rently implem ente processors. Table CPUID Functions1 AMD-K6Processors2
Standard Function
Notes:
Extended Function Description Vendor String Largest Standard Function Value Processor Signature Standard Feature Bits
AMD-K6TME Processor (Model
AMD-K6TM-2 AMD-K6TM-2E Processors (Model
AMD-K6TM-2E+ AMD-K6TM-III AMD-K6TM-IIIE+ Processor Processors (Model (Model
8000_0000h Largest Extended Function Value Extended Processor Signature 8000_0001h Extended Feature Bits 8000_0002h Processor Name 8000_0003h Processor Name 8000_0004h Processor Name 8000_0005h Cache Information 8000_0006h TLB3 Cache Information 8000_0007h PowerNow! Technology
"Appendix page contains detailed descriptions functions. Future versions these processors implement additional functions. translation lookaside buffer Low-power versions only
Identifying Processor's Vendor
Software must execute standard function EAX=0. CPUID instruction returns 12-character string that identifies processor's vendor. instruction also returns largest standa function input value defined CPUID instruction processor. processors, function returns vendor string "AuthenticAMD". This string informs software follow Embedded Processor Recognition
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AMD's definition subsequent CPUID functions registers returned those functions. Once software identifies processor's vendor, knows definition functions supplied CPUID instruction. using these functions, software obtains processor information needed properly tune functionality capabilities processor.
Testing Extended Functions
Software must test extended functions with function 8000_0000h. register returns largest extended function input value defined CPUID instruction processor. this value least 8000_0001h, extended functions supported. With exception, extended feature flags include information provided standard feature flags well indicators additional processor-specific feature enhancements. duplication standard feature bits within extended feature bits minimize number function calls required software. exception which indicates that SYSENTER SYSEXIT instructions supported standard features that SYSCALL SYSRET instructions supported extended features.
Determining Processor Signature
Standard function (EAX=1) CPUID instruction returns standard processor signature feature bits. standard processor signature returned register provides information regarding specific revision (stepping) model processor instruction family level supported processor. revision level used determine processor supports specific features. However, recommended that revision level used this manner unless this information available through standard extended feature bits.
Embedded Processor Recognition
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AMD-K6 processor models belong instruction family returned function Athlonprocessor models belong instruction family returned function Figure shows contents register obtained function Table summarizes specific processor signature values returned processors.
Reserved Instruction Family Model Stepping 11-8
Figure Contents Register Returned Function Table
Processor
Processor Signatures AMD-K6Processors
Instruction Family 0101b (5h) 0101b (5h) 0101b (5h) 0101b (5h) Model 0111b (7h) 1000b (8h) 1001b (9h) 1101b (Dh) Stepping xxxx xxxx xxxx xxxx
AMD-K6E Processor (Model AMD-K6-2 Processor (Model AMD-K6-2E Processor (Model AMD-K6-III Processor (Model AMD-K6-2E+ Processor (Model AMD-K6-IIIE+ Processor (Model
Notes:
Contact your representative latest stepping information. Refer Table page range allowable stepping associated with each model number.
Embedded Processor Recognition
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Identifying Supported Features
feature bits returned register CPUID functions-standard function extended function 8000_0001h. Each corresponds specific feature indicates that feature present processor. Table summarizes standard extended feature bits. Table Standard Extended Feature Bits
Bit1 Feature Description Standard2 Extended2
Floating-Point Unit Virtual Mode Extensions Debugging Extensions (Page Size Extensions) Time Stamp Counter (with RDTSC disable bit) K86Family Processors' Model-Specific Registers (with RDMSR WRMSR) (Page Address Extensions) (Machine Check Exception) CMPXCHG8B Instruction APIC Reserved processors SYSENTER/SYSEXIT Instructions SYSCALL SYSRET Instructions
floating-point unit available. Virtual mode extensions available. breakpoint debug extensions supported. 4-Mbyte pages supported. time stamp counter available processor, RDTSC instruction supported. model-specific registers available processor, RDMSR WRMSR instructions supported. Page address extensions supported using 8-byte directory entry. machine check exception supported. CMPXCHG8B instruction supported. local APIC unit available. SYSENTER SYSEXIT instructions supported. SYSCALL SYSRET instructions associated extensions supported.
MTRR (Memory Type Range Memory type range registers available. Registers) Global Paging Extension Global paging extensions available. (Machine Check Architecture) Machine check architecture supported conditional move instructions CMOV, FCMOV, Conditional Move Instructions FCOMI supported. (Page Attribute Table) Page attribute tables supported. Page size extensions 36-bit addresses PSE-36 (Page Size Extension) supported using 4-byte directory entry. 18-21 Reserved processors additions original MMXinstruction Multimedia Instruction Extensions supported.3
Embedded Processor Recognition
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Table Standard Extended Feature Bits (continued)
Bit1 Feature Description Standard2 Extended2
Notes:
MMXInstructions FXSAVE/FXRSTOR Streaming SIMD extensions (SSE) Reserved processors 3DNow!Instruction Extensions 3DNow! Instructions
instruction supported. Fast floating-point save restore supported. Streaming single instruction multiple data (SIMD) extensions (SSE) supported Digital signal processing (DSP) extensions 3DNow! instruction supported.3 3DNow! instructions supported.
"Appendix page contains details values. definitions: Support, Support more information these instructions, Extensions 3DNow!and MMXInstructions Sets Manual, order# 22466.
Before using enhanced features added latest generation processors, software should test each feature returned functions 8000_0001h identify capabilities available processor. example, software must test feature determine processor executes technology instructions. Attempting execute unavailable feature cause errors exceptions. returned extended function 8000_0001h, designates presence 3DNow! technology. Other processor vendors have adopted this technology, considered open standard. "Appendix page "Appendix page contain details values.
Determining Instruction Support
preferable CPUID feature flags much possible, rather than deriving capabilities from vendor specifiers combined with CPUID model numbers. AMD-K6-2E+ AMD-K6-IIIE+ processors powerful extensions instruction 3DNow! extensions. Extensions 3DNow!and MMXInstruction Sets Manual, order# 22466 more information about these instructions.
Embedded Processor Recognition
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Detection Algorithm Determining Instruction Support
simplify detection instructions original 3DNow! instructions, following algorithm. code sample using CPUID instruction identify processor features available from AMD's website There other ways implement detection besides shown sample. CPUID Test Standard Function Test Establish that processor support CPUID. "Testing CPUID Instruction" page Execute CPUID function which returns processor vendor string highest standard function supported. Save vendor string later comparison. (See step step indicates that highest standard function least execute CPUID function which returns standard feature flags register. MMXTest standard feature flags technology supported. instruction support basic minimum processor feature required support other instruction extensions. Optionally, standard feature flags set, processor streaming single instruction multiple data (SIMD) extensions (SSE) capabilities. Further qualification done checking support. support might present processor, usable lack support additional architected registers. Execute CPUID extended function 8000_0000h. This function returns highest extended function supported EAX. EAX=0, there support extended functions. highest extended function supported least 8000_0001h, execute CPUID function 8000_0001h. This function returns extended feature flags EDX. 3DNow!Test Vendor Check extended feature flags 3DNow! instructions supported. previously saved vendor string (see step contains "AuthenticAMD", continue next step.
Optional Test
Extended Functions Test
Embedded Processor Recognition
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3DNow! Extensions Test Multimedia Instruction Extensions Test
extended feature flags additions 3DNow! instruction supported. extended feature flags multimedia enhancement instructions that augment instruction supported.
Processor Signature (Extended Function)
Extended function 8000_0001h returns embedded processor signature. signature returned register provides generation, model, stepping information processors. Figure shows contents returned register.
Reserved Generation/Family Model Stepping 11-8
Figure Contents Register Returned Extended Function 8000_0001h
Displaying Processor's Name
Extended functions 8000_0002h, 8000_0003h, 8000_0004h return ASCII string containing name processor (also called boot string name string). These functions eliminate need software search processor name lookup table, process requiring large block memory frequent updates. Instead, software simply call these three functions obtain name string ASCII characters little-endian format) display screen. Although name string characters length, shorter names have remaining byte locations filled with ASCII NULL character (00h). simplify display routines avoid using screen space, software only needs display characters until NULL character detected. Embedded Processor Recognition
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Note: Extended functions 8000_0002h, 8000_0003h, 8000_0004h return incorrect name string AMD-K6-2E+ AMD-K6-IIIE+ processors (Model "Functions 8000_0002h, 8000_0003h, 8000_0004h Processor Name String" page more information.
Displaying Cache Information
Extended functions 8000_0005h 8000_0006h provide cache information processor. Some diagnostic software displays information about system processor's configuration. common this type software provide cache size organization information. Functions 8000_0005h 8000_0006h provide simple software obtain information about on-chip caches translation lookaside buffer (TLB) structures. size organization information returned registers described "Appendix page Software simply display these values, eliminating need large pieces code test memory structures.
Determining PowerNow!Technology Information
Extended function 8000_0007h provides information regarding processor's support PowerNow! enhanced power management (EPM) features. Based status flags, software determine processor supports programmable frequency control programmable voltage control. each indicates that feature supported; however, feature must enabled software. "Function 8000_0007h PowerNow!Technology Information" page more detailed descriptions.
Sample Code
code sample using CPUID instruction identify processor features available from AMD's website
Embedded Processor Recognition
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AMD-K6Processor Instructions
models/steppings AMD-K6 processor family implement following instruction set:
MMXInstructions-57 instructions multimedia software. AMD-K6MMXEnhanced Processor Multimedia Technology Manual, order# 20726 more information.
AMD-K6-2E+, AMD-K6-III, AMD-K6-IIIE+ processors implement following additional instructions:
3DNow!Instructions-21 instructions multimedia software. 3DNow!Technology Manual, order# 21928 more information. SYSCALL SYSRET- SYSCALL SYSRET Instruction Specification Application Note, order# 21086 more information. (Note that Model processors support these instructions.)
AMD-K6-2E+ Model D/[7:4] AMD-K6-IIIE+ Model D/[3:0] processors implement following additional instructions:
3DNow!Instruction Extensions-5 instructions multimedia software. Extensions 3DNow!and MMXInstruction Sets Manual, order# 22466 more information.
AMD-K6Processor Instructions
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Additional Considerations
Software Timing Dependencies Relative Memory Controller Setup
Processors family differ from other processors with regards instruction latencies order priority processor cycles. Timing-dependent software that relies specific latencies other processors should re-tested proper operation with processor. addition, re-testing should performed components with variable timing (such memory modules, oscillators, timers). rticu attenti memory -set subroutines that determine type DRAM system. Some chipsets tolerate DRAM mode change (such SDRAM) same clock DRAM refresh cycle. example some chipsets tolerate having memory refresh enabled prior changing memory mode types. Refresh should only enabled after memory type been determined. Note: BIOS family processors should enable write allocate mechanisms only after performing memory sizing typing algorithms.
Pipelining Support
production models steppings AMD-K6 processor support WAELIM form write allocate, which only form write allocate that should enabled. does recommend enabling obsolete form write allocate (WCDE) because system performance degraded doing Early implementations AMD-K6 processor support WHCR register therefore support WAELIM form write allocate. WCDE only form write allocate supported, which required chipset assert KEN# cacheable memory write cycles. Because KEN# sampled processor clock edge which first BRDY# sampled asserted, some chipsets that supported WCDE form write allocate assert during write cycles order prevent processor from Additional Considerations
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sampling KEN# before valid this case, BRDY# used processor sample KEN#). asserted during memory write cycles, then processor does fully take advantage potential performance gains that pipelining achieve. proper functionality, always program WCDE models 8/[7:0]. Models 8/[F:8], support WCDE bit.
Read-Only Memory
processor's caches must flushed prior defining area memory cacheable read-only. (The BIOS typically "shadowed" into main memory defined cacheable read-only.) caches flushed, then line that resides processor's cache that falls within readonly area memory written which would place cache line modified state. this modified line subsequently replaced written back memory, then system hang other unpredictable effects occur) because writeback directed area memory defined read-only chipset.
Additional Considerations
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Appendix
CPUID
mnemonic CPUID Privilege: Registers Affected: Flags Affected: Exceptions Generated: opcode description
Identify processor feature none EAX, EBX, ECX, none none
CPUID instruction application-level instruction that software executes identify processor feature set. This instruction offers multiple functions, each providing different information about processor. CPUID instruction executed from privilege level. Software information returned this instruction tune functionality specific processor features. Beginning with AMD-K6E processor Model processors support CPUID instruction. However, still recommended that software verify that CPUID instruction supported. "Testing CPUID Instruction" page more information. CPUID instruction supports multiple functions. information associated with each function obtained executing CPUID instruction with function number register. Functions divided into types: standard functions extended functions. Standard functions found function space, 0000_0000h-7FFF_FFFFh. general, processors have same standard function definitions. Extended functions defined specifically processors supplied vendor listed vendor identification string. Extended functions found high function space, 8000_0000h-8FFF_FFFFh. Because vendors have defined extended functions, software must test their presence processor.
Appendix
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Standard Functions
Function Largest Standard Function Input Value Vendor Identification String Input:
Output: Largest function input value recognized CPUID instruction EBX, EDX, Vendor identification string This standard function found processors implementing CPUID instruction. returns values. first value returned register indicates largest standard function value recognized processor. second value vendor identification string. This 12-character ASCII string returned EBX, EDX, registers little-endian format. processors return vendor identification string "AuthenticAMD" follows:
Software uses vendor identification string follows:
identify processor processor apply AMD's definition CPUID instruction additional function calls
Function Processor Signature Standard Feature Flags Input:
Output: Processor Signature Reserved Reserved Standard Feature Flags Function returns values Processor Signature Standard Feature Flags. processor signature returned register identifies specific processor providing information type -instruction family, model, revision (stepping). information formatted follows:
EAX[3-0] EAX[7-4] EAX[11-8] EAX[31-12]
Stepping Model Instruction Family Reserved
Appendix
Preliminary Information
23913A/0-November 2000
Embedded AMD-K6Processors BIOS Design Guide
standard feature flags returned register indicate presence specific features. most cases, indicates feature present, indicates feature present. Table page contains list currently defined standard feature flags AMD-K6 family processors. Reserved bits will used features they added.
Appendix
Preliminary Information Embedded AMD-K6Processors BIOS Design Guide
23913A/0-November 2000
Table Standard Feature Flag Descriptions
AMD-K6-2 AMD-K6-2E Processors (Model AMD-K6-2E+ AMD-K6-III AMD-K6-IIIE+ Processor Processors (Model (Model
Feature1
AMD-K6E Processor (Model
Floating-Point Unit Virtual Mode Extensions Debugging Extensions Page Size Extensions (4-Mbyte pages) Time Stamp Counter (with RDTSC disable bit) Family Processors' Model-Specific Registers (with RDMSR WRMSR) (Page Address Extensions) Machine Check Exception CMPXCHG8B Instruction APIC Reserved processors SYSENTER/SYSEXIT Memory Type Range Registers Global Paging Extension
Machine Check Architecture Conditional Move Instruction (Page Attribute Table) PSE-36 (Page Size Extensions) 18-21 Reserved processors Multimedia Instruction Extensions Instructions FXSAVE/FXRSTOR Streaming SIMD Extensions (SSE) 26-29 Reserved processors 3DNow! Instruction Extensions 3DNow! Instructions
Notes:
definitions: Support, Support.
Appendix
Preliminary Information
23913A/0-November 2000
Embedded AMD-K6Processors BIOS Design Guide
Extended Functions
Function 8000_0000h Largest Extended Function Input Value Input: 8000_0000h
Output: Largest function input value recognized CPUID instruction Reserved Reserved Reserved Function 8000_0000h returns value register that indicates largest extended function value recognized processor. Function 8000_0001h Processor Signature Extended Feature Flags Input: 8000_0001h
Output: Processor Signature Reserved Reserved Extended Feature Flags Function 8000_0001h returns values Processor Signature Extended Feature Flags. processor signature returned register identifies specific processor providing information regarding type generation/family, model, revision (stepping). information formatted follows:
EAX[3-0] EAX[7-4] EAX[11-8] EAX[31-12]
Stepping Model Generation/Family Reserved
extended feature flags returned register indicate presence specific features found processors. most cases, indicates feature present, indicates feature present. Table page contains list currently defined extended feature flags AMD-K6 family processors. Reserved bits will used features they added.
Appendix
Preliminary Information Embedded AMD-K6Processors BIOS Design Guide
23913A/0-November 2000
Table Extended Feature Flag Descriptions
AMD-K6-2 AMD-K6-2E Processors (Model AMD-K6-2E+ AMD-K6-III AMD-K6-IIIE+ Processor Processors (Model (Model
Feature1
AMD-K6E Processor (Model
Floating-Point Unit Virtual Mode Extensions Debugging Extensions Page Size Extensions (4-Mbyte Pages) Time Stamp Counter (with RDTSC disable bit) Family Processors' Model-Specific Registers (with RDMSR WRMSR) (Page Address Extensions) Machine Check Exception CMPXCHG8B Instruction APIC Reserved processors SYSCALL SYSRET Instructions Memory Type Range Registers Global Paging Extension Machine Check Architecture Conditional Move Instruction (Page Attribute Table) PSE-36 (Page Size Extensions) 18-21 Reserved processors Multimedia Instruction Extensions Instructions FXSAVE/FXRSTOR Streaming SIMD Extensions (SSE) 26-29 Reserved processors 3DNow! Instruction Extensions 3DNow! Instructions
Notes:
definitions: Support, Support
Appendix
Preliminary Information
23913A/0-November 2000
Embedded AMD-K6Processors BIOS Design Guide
Functions 8000_0002h, 8000_0003h, 8000_0004h Processor Name String Input: 8000_0002h, 8000_0003h, 8000_0004h
Output: Processor Name String Processor Name String Processor Name String Processor Name String Functions 8000_0002h, 8000_0003h, 8000_0004h each return part processor name string EAX, EBX, ECX, registers. These three functions four registers return ASCII string characters little endian format. example, function 8000_0002h returns first characters processor name. first character resides least significant byte EAX, last character this group resides most significant byte EDX. NULL character (ASCII 00h) used indicate processor name string. This feature useful processor names that require fewer than characters. Note: Extended functions 8000_0002h, 8000_0003h, 8000_0004h return incorrect name string AMD-K6-2E+ AMD-K6-IIIE+ processors (Model returned name string should AMD-K6TM-2+ AMD-K6-2E+ processor AMD-K6TM-III+ AMD-K6-IIIE+ processor. However, actual value returned either processor AMD-K6TM-III. CPUID utility v2.07 should used display name string specified AMD-K6E, Model processors. This utility obtained from http: Feature bits returned standard extended function calls CPUID instruction should still used determine features capabilities supported processor use.
Appendix
Preliminary Information Embedded AMD-K6Processors BIOS Design Guide
23913A/0-November 2000
Function 8000_0005h Cache Information Input: 8000_0005h
Output: Reserved Information Data Cache Information Instruction Cache Information Function 8000_0005h returns information about processor's on-chip caches associated TLBs. Tables provide format information returned 8000_0005h function. Table Format Returned Function 8000_0005h
Data Associativity1
Notes:
Instruction Entries Bits 23-16 Associativity1 Bits 15-8 Entries Bits
Bits 31-24
"Associativity Caches TLBs" page more information.
Table
Format Returned Function 8000_0005h
Data Cache Size (Kbytes) Associativity1 Bits 23-16 Lines Bits 15-8 Line Size (bytes) Bits
Notes:
Bits 31-24
"Associativity Caches TLBs" page more information
Table
Format Returned Function 8000_0005h
Instruction Cache Size (Kbytes) Associativity1 Bits 23-16 Lines Bits 15-8 Line Size (bytes) Bits
Note
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