Processor Module Signal Power-Up Requirements Application No
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Athlon
Processor Module
Signal Power-Up Requirements
Application Note
Publication 23811 Rev: Issue Date: June 2000
2000 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, logo, Athlon, AMD-751, AMD-756, combinations thereof, trademarks Advanced Micro Devices, Inc. Other product names used this publication identification purposes only trademarks their respective companies.
23811B-June 2000
AthlonProcessor Module Signal Power-Up Requirements
Contents
Revision History Introduction Power-Up Requirements Sequence PROCRDY CONNECT Signals Processor Warm Reset Requirements AthlonProcessor System Controller Reset Pins Sample Current Motherboard Implementation Solution Description Power-Up Sequence Satisfaction Requirements Satisfaction Requirements Specific Warm Resets. Miscellaneous Sampling
Contents
AthlonProcessor Module Signal Power-Up Requirements
23811B-June 2000
Revision History
Date June 2000 June 2000 Initial public release. Description Changed power source signal name from VDDA VCCA throughout document.
Revision History
23811B-June 2000
AthlonProcessor Module Signal Power-Up Requirements
Application Note AthlonProcessor Module Signal Power-Up Requirements
Introduction
This document describes Athlonprocessor module power-up requirements during system turn-on warm resets. These requirements adhered with motherboard modifications and/or recommended system power supply specific motherboard. This document applicable current Slot motherboards.
Introduction
AthlonProcessor Module Signal Power-Up Requirements
23811B-June 2000
Power-Up Requirements
Sequence
Athlonprocessor requires that system clocks (SYSCLK/SYSCLK#) processor running prior PWROK. PWROK output voltage regulation circuit motherboard indicating that VCC_CORE valid processor. Figure shows relationship between signals system during power-up sequence. This figure details requirements processor. Note: Figure represents several signals generically using names necessarily consistent with lists schematics.
3.3V Supply (SRAM Core) VCCA (2.5V) (for PLL) 1.6V Supply (Processor Core) CPURESET# NBRESET#
PWROK
System Clock
Figure Signal Relationship during Power-Up Sequence Requirements Sequence NBRESET# (for example, PCIRESET#) soon possible after receiving power. system clock generator produces clock soon after valid power (see specific system clock data sheets more information). System clock generators Power-Up Requirements
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AthlonProcessor Module Signal Power-Up Requirements
Athlon processors generate system clocks after eivi ower motherboard. Athlon processor pulls open-drain clocks (SYSCLK/SYSCLK#) VCC_CORE module. Because Power Supply Specification requires 3.3V valid prior VCC_CORE, motherboard must assert PWROK only after valid system clock generated. recommended that PWROK should assert only after least past valid VCC_CORE valid system clock). When PWROK asserts, processor turns begins lock. After specified period, ensure locked, reset signals deasserted. Timing Requirements signal timing requirements follows: CPURESET# must asserted before PWROK asserts Athlon processor does correct clock multiplier PWROK asserted prior CPURESET# assertion. recommended that CPURESET# asserted least 10ns prior assertion PWROK. motherboard power supplies should ramped before assertion PWROK. processor core voltage, VCC_CORE, should have stable voltage (for example, 1.6V) indicated Voltage (VID) prior PWROK assertion. Before PWROK assertion, Athlon processor clocked ring oscillator. This minimum time specified. Athlon processor powered VCCA processor module. VCCA derived resistor divider powered VCC_SRAM from motherboard. processor does lock VCCA high enough processor logic switch some period time before PWROK asserts. recommended minimum time before PWROK assertion 5µs. system clock (SYSCLK/SYSCLK#) should running before PWROK asserts. When PWROK asserts, Athlon processor switches from driving internal processor clock grid from ring oscillator driving from PLL. reference system clock should valid this time. valid,
Power-Up Requirements
AthlonProcessor Module Signal Power-Up Requirements
23811B-June 2000
subsequent requirements undermined. recommended that PWROK asserted after system clocks running. PWROK assertion deassertion CPURESET# duration reset during cold boots intended satisfy time takes lock with less than 1-ns phase error. Athlon processor begins after PWROK asserts internal clock grid switched from ring oscillator PLL. lock time take from hundreds nanoseconds tens microseconds. recommended that minimum time between PWROK assertion deassertion CPURESET# least 100us. PWROK should monotonic. processor should switch between ring oscillator after initial assertion PWROK. NBRESET# should asserted before CPURESET# deasserted. NBRESET# does deassert until after CPURESET# deasserted, then when CONNECT asserts NBRESET# assertion, processor behavior undefined. There must sufficient overlap resets ensure that CONNECT chance sampled asserted processor advance processor coming reset.
PROCRDY CONNECT Signals
stream initialization process documented AthlonSystem Specification, order# 21902. However, this section documents some implementation details. CPURESET# asserted deasserts PROCRDY when CPURESET# deasserts. system controller asserts CONNECT during NBRESET# assertion deasserts when NBRESET# deasserts. this point, when samples PROCRDY deassert, system controller begins sending stream (start first). Athlon processor implementation interprets beginning stream when deasserts PROCRDY (some Power-Up Requirements
23811B-June 2000
AthlonProcessor Module Signal Power-Up Requirements
short time prior transitioning) sees Low-to-High transition CONNECT. system controller interprets Athlon processor being ready accept stream when sees PROCRDY deasserted after NBRESET# deasserts. Note: Some system controllers, like AMD-751system controller, look edge transition. However, current processor implementations impose requirements order CPURESET# NBRESET# deassertions.
Processor Warm Reset Requirements
AthlonProcessor System Controller Reset Pins
Warm resets different from cold resets because motherboard power supplies already stable locked. Therefore, requirements different warm resets because Athlon processor sleep state when CPURESET# asserts. Duration CPURESET# Function Power Ratio Although Athlon processor already locked, Athlon processor requires that CPURESET# asserted some period time ensure that PROCRDY assert without glitching. Athlon processor clock grid slowed down ratio little 1/128th normal frequency. Therefore, takes corresponding length time assert PROCRDY. addition, order avoid glitching PROCRDY, necessary assert CPURESET# long enough time that Athlon processor synchronize CPURESET# into processor clock domain.
Processor Warm Reset Requirements
AthlonProcessor Module Signal Power-Up Requirements
23811B-June 2000
Table shows minimum CPURESET# duration ensure proper PROCRDY behavior function power ratio. Table CPURESET# Minimum Duration
Power Divisor (recommended) CPURESET# assertion time 0.5µs @100Mhz SYSCLK 2.5µs @100MHz SYSCLK 2.5µs @100MHz SYSCLK
AthlonProcessor Module Version Athlon Processor Module Model Athlon Processor Module Model Athlon Processor Module Model
Assertion CPURESET# Deassertion NBRESET#
When system controller comes reset, processor must have PROCRDY asserted response CPURESET# assertion else system controller start sending stream (because some system controllers sample only PROCRDY level). This scenario implies dependency from CPURESET#=0 NBRESET#=1:
Processor Warm Reset Requirements
23811B-June 2000
AthlonProcessor Module Signal Power-Up Requirements
Sample Current Motherboard Implementation Solution
This section describes currently implemented motherboard solution, assuming AMD-756peripheral controller (Southbridge), describes solution meets requirements described "Power-Up Requirements" page "Processor Warm Reset Requirements" page motherboard following voltage regulators:
Athlon (VCC_CORE)
processor
core
voltage
regulator
This regulator uses provides processor core voltage determined voltage (VID). typical core voltage 1.6V. provided silver power supply. Current motherboards power resistor network.
SRAM core voltage regulator (VCC_SRAM) This regulator either passes 3.3V from power supply 2.5V. voltage determined VCC2SEL, which identifies SRAM requires core voltage 2.5V 3.3V.
Although system clock generator powered from 3.3V supply, outputs open drain pulled Athlon processor core voltage. Therefore, system clock does really toggle until processor core voltage ramped. resistor network processor module provides VCCA from VCC_SRAM. VCCA nominally should 2.5V therefore, network divide down from 3.3V.
Sample Current Motherboard Implementation Solution
AthlonProcessor Module Signal Power-Up Requirements
23811B-June 2000
Description Power-Up Sequence
power-up sequence follows: power supply ramps startup value becomes stable. this time, processor core regulator begins ramping VCC_CORE. addition, SRAM regulator begins ramping VCC_SRAM based value VCC2SEL system clock generator begins power resistor network powered VCC_SRAM begins provide VCCA. power supply asserts PWROK much 500ms after power supply begins provide stable 3.3V. (This same signal PowerGood signal Southbridge input). PWROK provided processor once processor core voltage regulator produces stable voltage based from power supply. addition, pullup resistors open-drain system clocks from clock generator become stable SYSCLK/SYSCLK# begins transitioning. PowerGood provided Southbridge once valid from power supply VCC_CORE valid. (PowerGood Southbridge based processor VCC_CORE, PWROK). Before PowerGood asserted, Southbridge drives CPURESET# NBRESET# asserted. When Southbridge sees assertion PowerGood, waits 1.8ms then deasserts NBRESET#. then waits 1.5µs before deasserting CPURESET#.
Sample Current Motherboard Implementation Solution
23811B-June 2000
AthlonProcessor Module Signal Power-Up Requirements
Satisfaction Requirements
satisfaction requirements follows:
CPURESET# must asserted before PWROK asserts. This requirement satisfied because Southbridge asserts CPURESET# before PowerGood asserted Southbridge. Southbridge gets power from supply begins driving CPURESET# many 500ms before supply asserts PowerGood. PWROK asserts once Athlon processor core regulator powered supply becomes stable. supplies should ramped before PWROK asserts. PWROK asserts only when processor VCC_CORE stable. requirement approximately 10µs pass from time processor VCC_CORE high enough voltage reset some flops until PWROK asserts, which accomplished network powered VCC_CORE driving PWROK. VCCA asserts once VCC_SRAM stable, which issue because PWROK function only processor core regulator providing stable voltage when should function SRAM core regulator well. time constant circuit that drives PWROK must large enough ensure that VCC_SRAM VCCA stable when PWROK asserts. system clock should running before PWROK asserts. system clock itself only runs when Athlon processor VCC_CORE ramped. PWROK asserts only when processor VCC_CORE stable. Therefore, theory, this requirement strictly satisfied. However, presumed that regulator ramped sufficiently High (that ~1.2V) substantial length time prior assertion PWROK. This requirement should provide enough swing system clock that running well enough advance assertion PWROK. recommended that elapsed prior assertion PWROK.
Sample Current Motherboard Implementation Solution
AthlonProcessor Module Signal Power-Up Requirements
23811B-June 2000
PWROK assertion deassertion CPURESET# system implementation only ensures time from Southbridge PowerGood deassertion CPURESET#. known that Southbridge PowerGood generated after processor core precisely after PWROK. This requirement satisfied
(AMD Athlon processor VCC_CORE Valid Southbridge PowerGood CPURESET# deassertion time) (AMD Athlon processor Core Valid PWROK lock time)
motherboard design such that delta time Southbridge PowerGood PWROK from processor core large lock time much smaller than 1.8ms reset duration, which satisfies this requirement. PWROK should monotonic Because PWROK asserts when processor VCC_CORE stable, should deasserted reasserted. NBRESET# should asserted prior deassertion CPURESET#. Southbridge asserts both CPURESET# NBRESET# when Southbridge PowerGood asserted, therefore, this requirement satisfied.
Satisfaction Requirements Specific Warm Resets:
satisfaction requirements specific warm boots follows:
Duration CPURESET# AMD-756 peripheral controllers from implement 1.8ms warm resets, which long enough Athlon processor. Assertion CPURESET# deassertion NBRESET# This requirement currently satisfied implementation, because CPURESET# NBRESET# asserted simultaneously. addition, NBRESET# always asserted least 1.8ms. AMD-756 peripheral controller must programmed such that port resets directed INIT# CPURESET# pin. addition, there some bits C3A50 AMD-756 peripheral controller register) that should never because they could force CPURESET# independent NBRESET#. Sample Current Motherboard Implementation Solution
23811B-June 2000
AthlonProcessor Module Signal Power-Up Requirements
Miscellaneous
Sampling
Athlon processor module Model Model transparently sample BP/FID pins from time PWROK asserts until deassertion CPURESET#. Athlon processor module Model transparently samples pads same manner Model Model parts. clock multiplier provided either external part resistors package.
Miscellaneous
AthlonProcessor Module Signal Power-Up Requirements
23811B-June 2000
Miscellaneous
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