Operating voltage: 2.4V~3.6V Eight input lines Eight input/output line
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HTG12B0 4-Bit Microcontroller
Operating voltage: 2.4V~3.6V Eight input lines Eight input/output lines Five working registers program (4096) bits data memory Sound effect circuit segment common, bias driver output fixed 4.4V
oscillator 32768Hz crystal oscillator 8-bit timer with internal external clock source Internal timer overflow instruction cycle with 1MHz system clock level subroutine nesting Halt feature reduces power consumption 8-bit table read instruction
General Description
HTG12B0 processor from 4-bit stand-alone single chip microcontroller specially designed display time piece product applications. ideally suited multiple time piece power applications among which calculators, scales, calendar hand held products.
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HTG12B0
Block Diagram
Note: ACC: Accumulator R0~R4: Working registers ROMB: bank switch RAMB: bank switch LCDC: control register ports Input ports
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HTG12B0
Assignment
substrate should connected layout artwork.
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Chip size: 3060 5140 (mm)2
HTG12B0
Coordinates
-1394.56 -1394.56 -1394.56 -1394.56 -1394.56 -1394.56 -1394.56 -1394.56 -1394.56 -1368.40 -1368.40 -1368.40 -1368.40 -1368.40 -1368.40 -1368.40 -1368.40 -1368.40 -1304.07 -1304.07 -1318.48 -1355.04 -1355.04 -1355.04 -1355.04 -1343.84 -1315.52 -1195.52 -1075.52 -955.52 -835.52 -715.52 2163.72 2043.72 1923.72 1803.72 1683.72 1563.72 1443.72 1323.72 1203.72 998.68 749.88 515.16 266.36 31.64 -217.16 -451.88 -700.68 -935.40 -1189.85 -1344.25 -1483.72 -1630.76 -1750.76 -1885.00 -2005.00 -2164.44 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 1204.48 1324.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2436.28 -2177.80 -1889.00 -1769.00 -1480.20 -1360.20 -1071.40 -951.40 -662.60 -542.60 -253.80 -133.80 155.00 275.00 563.80 683.80 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1398.48 1327.44 1207.44 1087.44 967.44 847.44 727.44 607.44 487.44 367.44 247.44 127.44 7.44 -112.56 -232.56 -352.56 -472.56 -592.56 -712.56 -832.56 -952.56 -1072.56 -1192.56 -1312.56 Unit: 972.60 1092.60 1381.40 1501.40 1790.20 1910.20 2199.00 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28 2436.28
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HTG12B0
Description
Name PS3~PS0 PM3~PM0 TMCLK Mask Option Description
Pull-high None. Input pins input only Note Pull-high None. Note Input TIMER clock TIMER clocked external clock internal frequency source. Input reset internal Reset active logical level.
17~14 10~13 27~30 31~34 35~50 51~90
PA3~PA0 PB3~PB0 OSCI OSCO XOUT VLC1~VLC4 VOUT1~VOUT4 COM15~COM0 SEG39~SEG0 T512 TEST1 TEST2
CMOS NMOS with Pull-high Input/output pins None. Note Note Sound effect outputs Positive power supply external resistor between OSCI OSCO needed internal system clock. 32768Hz crystal oscillator time base, clock Negative power supply, system power bias generated terminal Output panel common plate driver outputs panel segment test mode only TEST1 TEST2 left open when chip normal operation (with internal pull-high resistor).
Note: system clock provides different sources selectable mask option drive sound effect clock. Holtek sound library used, only 128K acceptable. Each ports trigger source HALT interrupt, selectable mask option. Each ports selected CMOS output only, NMOS with pull-high resistor none mask option. internal clock sources selected mask option drive TMCLK. Note that TMCLK should connected pull high resistor internal source used.
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HTG12B0
Absolute Maximum Ratings
Supply Voltage.-0.3V 5.5V Storage Temperature.-50°C 125°C Input Voltage .VSS-0.3 VDD+0.3 Operating Temperature .0°C 70°C
Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability.
D.C. Characteristics
Symbol ISTB IOL1 IOH1 IOL2 IOH2 VLCD Parameter Operating Voltage Operating Current Standby Current, (fSYS Input Voltage Input High Voltage Output Sink Current Output Source Current Segment Output Sink Current Segment Output Source Current Pull-high Resistor VLCD Output Voltage Test Conditions Conditions load, fSYS=512kHz Halt mode VOL=0.3V VOH=2.7V VOL=0.44V VLCD=4.4V VOH=4.0V VLCD=4.4V RES, TMCLK Min. 0.8VDD -0.5 3.96 Typ.
Ta=25°C Max. 0.2VDD 4.84 Unit
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HTG12B0
A.C. Characteristics
Symbol fSYS fTIMER tRES fSOUND Parameter System Clock Cycle Time Timer Frequency (TMCLK) Reset Pulse Width Sound Effect Clock Test Conditions Conditions R=620kW~51kW fSYS=1MHz Min. Typ. Max. 1000 1000 Ta=25°C Unit
Only these clocking signal frequencies supported Holtek sound library.
Functional Description
Program counter This counter addresses program arranged 12-bit binary counter from PC11 whose contents specify maximum 4096 addresses. program counter counts with increment with each execution instruction. When executing jump instruction (JMP, JNZ, JTMR,.), subroutine call, initial reset, internal interrupt, interrupt returning from subroutine, program counter loaded with corresponding instruction data shown table. Note: P0~P11: Instruction code PC11 keeps current value S0~S11: Stack register bits ROMB0 ROMB1 power reset. Program memory program memory executable memory arranged format. There four banks program memory HTG12B0, each bank shown figure switched assigning ROMB0 ROMB1 (bit0 bit1 ROMB). ROMB bank pointer written only executing ROMB, instruction. ROMB unused bits. address specified program counter (PC). Four special locations reserved described next.
Location 000H: (Bank
Activating processor causes first instruction fetched from location
itia
Program memory ROMB=XX00B
Program memory ROMB=XX01B
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HTG12B0
Location 004H: (Bank 0~3)
Contains timer interrupt resulting from TIMER overflow. interrupt enabled, begins execution location 004H.
Location 008H: (Bank 0~3)
execution instruction, program counter added before execution phase, careful manipulation READ MR0A READ required page margin.
Activating processor with interrupts enabled causes program jump this location.
Locations n00H nFFH: (Bank 0~3)
Each page program memory consists bytes. This area from n00H nFFH F00H FFFH used look-up table. Instructions such READ R4A, READ MR0A, READF R4A, READF MR0A read table transfer contents table data memory address specified register pair R1,R0. However R1,R0 only store bits, these instructions cannot fully specify full program memory address. this reason jump instruction should first used place program counter right page. above instructions then used read look table data. Note that page number must greater than zero since some locations page reserved specific usage. This area function normal program memory. program memory mapping shown diagram.
Mode Initial reset Internal interrupt interrupt Jump, call instruction Conditional branch PC13 PC12 PC11 PC10
Program memory ROMB=XX10B
Program memory ROMB=XX11B
Program Counter
ROMB1 ROMB0 ROMB1 ROMB0 ROMB1 ROMB0 ROMB1 ROMB0 ROMB1 ROMB0
Return from ROMB1 ROMB0 subroutine
Program memory
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HTG12B0
Temporary data memory Stack register stack register group registers used save contents program counter (PC) arranged into bits level. used store carry flag. interrupt will force contents carry flag onto stack register. subroutine call will also cause contents pushed onto stack; however carry flag will stored. subroutine interrupt routine which signaled return instruction, RETI restore program counter previous value from stack register. Executing instruction will restore carry flag from stack register, does not. Working registers There five working registers (R0, usually used store frequently accessed intermediate results. Using instructions working registers increment (+1) decrement (-1). (n=0, instruction makes efficient working registers program loop counter. Also register pairs R0,R1 R2,R3 used data memory pointer when memory transfer instruction executed. Data memory static data memory (RAM) arranged format used store data. data memory locations indirectly addressable through register pair R1,R0 R3,R2; example A,[R3R2] [R3R2],A. There areas data memory, temporary data area display data area. Access temporary data area from
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bank 0~RAM bank Access display data area from bank bank There eight banks temporary data memory HTG12B0, each bank shown figure switched assigning RAMB0~RAMB2 (bit 0~bit RAMB). RAMB bank pointer written only executing RAMB, instruction. RAMB unused bit. Each bank maps different area data memory. There banks displaying data memory, each bank switched assignment LCDC0 (bit LCDC). LCDC control register application written only executing LCDC, instruction. When data written into display data area, automatically read driver which then generates corresponding driving signals.
Display data memory
HTG12B0
locations between temporary display data areas undefined cannot used. Accumulator accumulator most important data register processor. sources input destination results operations performed ALU. Data from ports memory also passes through accumulator. Arithmetic logic unit This circuit performs following arithmetic logic operations
with without carry Subtract with without carry AND, Exclusive-OR Rotate right, left through carry decimal adjust addition Increment, decrement Data transfers Branch decisions
start timer, load counter with value then issue TIMER instruction. Note that desired start count immediate value bits. Once Timer/Counter started increments maximum count then overflows zero (00H). then continues count until stopped TIMER instruction reset. increment from maximum count zero (00H) triggers timer flag internal interrupt request. interrupt enabled disabled executing instructions. interrupt enabled, timer overflow will cause subroutine call location state timer flag also tested with conditional jump instruction JTMR. timer flag cleared after interrupt JTMR instruction executed. internal source used, frequency determined system clock parameter defined equation. frequency internal frequency source selected mask option. system clock Frequency TIMER clock where n=0, selectable mask option. There real time clock (RTC) function implemented HTG12B0. function used generate accurate time period. circuit clock source comes from 32768Hz crystal oscillator. block diagram shown follows.
only outputs results data operations, also sets status carry flag (CF) some instructions. Timer/counter HTG12B0 contains programmable 8-bit count-up counter which used count external events used clock generate accurate time base. 8-bit timer clock supplied external source from TMCLK, synchronization problems occur when reading data from timer. therefore recommended that timer stopped before retrieving data. 8-bit counter will increment rising edge clock whether internally externally generated. Timer/Counter read with software instructions stopped hardware reset TIMER instruction. re10
output selected mask option. n=0~7 Frequency output output used generate interrupt signal.
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HTG12B0
Interrupt HTG12B0 provides both TIMER interrupt modes. instructions used disable enable interrupts. When activated during enable interrupt mode program within CALL subroutine, this causes subroutine call location reset interrupt latch. Likewise when timer flag enable interrupt mode program within CALL subroutine, TIMER interrupt activated. This cause subroutine call location resets timer flag. both TIMER interrupts arrive same time, will serviced first. When running under CALL subroutine interrupt acknowledge hold until instruction invoked. CALL instruction should used within interrupt routine unpredictable results occur. within CALL subroutine both TIMER interrupt occur, matter what order they arrive interrupt will serviced first after leaving CALL subroutine. This also applies interrupt arrive same time. interrupts disabled hardware reset instruction. They remain disabled until instruction executed. Initial reset HTG12B0 provides system initialization. This equipped with internal pull high resistor combination with external 0.1m~1mF capacitor, provides internal reset pulse sufficient length guarantee reset internal circuits. reset pulse generated externally, must held least 5ms. When active, internal block will initialized shown below: TIMER Timer flag SOUND Output port output ROMB RAMB LCDC HALT This special feature HTG12B0 interrupt normal operation reduce power consumption. When HALT executed following happens
system clock will stopped contents on-chip regis-
000H Stop Reset (low) Sound sing mode High floating state) Enable XX00B X000B 1100B
output level
ters remain unchanged
oscillator keeps running maintain level output
system leave HALT mode through initial reset interrupt wake-up from following entry program counter value. Initial reset: Wake-up: next address HALT instruction
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HTG12B0
When halt status terminated interrupt, following procedure takes place: Case system interrupt-disable state before entering halt state:
system will awakened returns
sound library supports only sound clock frequency 128K 64K. sound library proper system clock mask option should selected. display memory mentioned data memory section, display memory embedded data memory. read written same normal data memory. figure illustrates mapping between display memory pattern HTG12B0. There ON/OFF switch display controlled LCDC (LCDC corresponding LCDC represents display display memory. display module have form long number commons does exceed number segments over
main program instruction following HALT command. receives enable interrupt command which interrupt will serviced.
interrupt will held until sys-
Case system interrupt enable state:
interrupt will awake system
execute interrupt subroutine.
HALT mode, each ports used wake-up signal mask option wake-up system. This signal active low-going transition. Sound effects HTG12B0 includes sound effect circuitry which offers sounds with tones, boom noise effects. Holtek supports sound library including melodies, alarms, machine guns etc. instruction executed, specified sound begins. Each time executed, terminates singing sound immediately. There singing modes, SONE mode SLOOP mode activated SOUND SOUND LOOP. SONE mode specified sound plays only once. SLOOP mode specified sound keeps re-playing.
Since sounds 0~11 contain notes sounds 12~15 include notes latter possesses better sound than former. frequency sound effect circuit selected mask option. system clock Frequency sound effect circuit .where m=0,1,2,3,4,5.
display memory (LCDC0=0)
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HTG12B0
System clock
Frequency clock .where n=0~5
driver output enabled disabled setting LCDC without influence related memory condition. driver output enabled setting LCDC3 disabled setting LCDC Register
Function Select bank 0=Bank (Com0~7) 1=Bank (Com8~15) Select clock source 0=RTC (32768Hz) 1=System clock edge latch control 1=Enabled 0=Disabled Control display 0=OFF 1=ON
LCDC
display memory (LCDC0=1) driver output segments random after initial clear. bias voltage circuits display built-in external resistor required. output number HTG12B0 driver which directly drive with 1/16 duty cycle bias. frequency driving clock source selected from system clock accessing LCDC. There many frequency division clock which selected mask option either from system clock.
LCDC Register example driving waveform (1/16 duty bias) shown below.
Frequency clock .where n=0~7
16384
VLCD fixed 4.4V when from 2.4V 3.6V.
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HTG12B0
Oscillator
Only external resistor required HTG12B0 system clock. system clock also used reference signal sound effect clock internal frequency source TIMER. Another crystal oscillator needed reference signal driving clock interrupt clock source. machine cycle consists sequence states numbered Each state lasts oscillator period. machine cycle system frequency 1MHz.
Input ports falling edge latch function selected mask option. Once falling edge signal latched, will remain state until clear instruction executed setting LCDC from high low. Input/output port used input/output output operation selecting NMOS CMOS mask option respectively, each configured with without pull-high resistor when NMOS selected. NMOS selected, should noted that, before reading, data from pads should output related bits disable NMOS device.
oscillator Interfacing HTG12B0 microcontrollers communicate with outside world through input pins output pins Input ports ports have internal pull high resistors determined mask option. Every input ports specified trigger source waking HALT interrupt mask option. high transition these pins will wake device from HALT status.
Input/output port
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HTG12B0
Mask options HTG12B0 provides following mask option different applications.
Each input ports with pull-high kinds sound clock frequencies:
fSYS/2m, m=0,
There eight kinds interrupt fre-
resistor
quencies. interrupt frequency=256/2n n=0~7.
Each input ports function
clock source division:
HALT wake-up trigger.
Each input/output port with
CMOS NMOS with pull-high none.
8-bit programmable TIMER with internal
selected, frequency clock=16384/2n n=0~7. system clock selected, frequency n=0~5. clock=
external frequency sources. There internal frequency sources which selected clocking signal. using internal frequency sources clocking signal TMCLK cannot connect with pull-high resistor.
falling edge latch function.
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HTG12B0
Application Circuits
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HTG12B0
Instruction Summary
Mnemonic Arithmetic A,[R1R0] A,[R1R0] A,[R1R0] A,[R1R0] A,XH A,XH Logic Operation A,[R1R0] A,[R1R0] A,[R1R0] [R1R0],A [R1R0],A [R1R0],A A,XH A,XH A,XH Increment Decrement [R1R0] [R3R2] [R1R0] [R3R2] Data Move ROMB, RAMB, LCDC, A,Rn Rn,A A,[R1R0] A,[R3R2] [R1R0],A [R3R2],A A,XH R1R0,XXH R3R2,XXH R4,XH ROMB RAMB LCDC Move register ACC, n=0~4 Move register, n=0~4 Move data memory Move data memory Move data memory Move data memory Move immediate data Move immediate data Move immediate data Move immediate data Increment Increment register, n=0~4 Increment data memory Increment data memory Decrement Decrement register, n=0~4 Decrement data memory Decrement data memory data memory data memory Exclusive-OR data memory data memory data memory Exclusive-OR data memory immediate data immediate data Exclusive-OR immediate data data memory data memory with carry Subtract data memory from Subtract data memory from with borrow immediate data Subtract immediate data from Decimal adjust addition
Description
Byte
Cycle
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HTG12B0
Mnemonic Rotate Input Output A,Pi Pi,A Branch addr addr addr JTMR addr addr A,addr A,addr Rn,addr Subroutine CALL addr RETI Flag Timer TIMER TIMER TIMER A,TMRL A,TMRH TMRL,A TMRH,A Table Read READ READ MR0A READF READF MR0A Read code current page Read code current page M(R1,R0), Read code page Read code page M(R1,R0), bits immediate data TIMER TIMER start counting TIMER stop counting Move nibble TIMER Move high nibble TIMER Move nibble TIMER Move high nibble TIMER Clear carry flag carry flag Enable interrupt Disable interrupt operation Subroutine call Return from subroutine interrupt Return from interrupt service routine Jump unconditionally Jump carry=1 Jump carry=0 Jump timer overflow Jump Jump zero Jump zero Jump register zero, n=0,1,4 Input port-i ,port-i=PM, Output port-i, port-i=PA, Rotate left Rotate left through carry Rotate right Rotate right through carry
Description
Byte
Cycle
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HTG12B0
Mnemonic Sound Control SOUND SOUND SOUND LOOP SOUND Miscellaneous HALT Enter power down mode Activate SOUND channel with Turn SOUND cycle Turn SOUND repeat cycle Turn SOUND Description Byte Cycle
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HTG12B0
Instruction Definition
A,[R1R0] Machine Code Description Operation A,XH Machine Code Description Operation A,[R1R0] Machine Code Description Operation A,XH Machine Code Description Operation A,[R1R0] Machine Code Description Operation [R1R0],A Machine Code Description Operation data memory contents carry accumulator 00001000 contents data memory addressed register pair carry added accumulator. Carry affected. ACC+M(R1,R0)+C immediate data accumulator 01000000 ACC+XH data memory contents accumulator 00001001 contents data memory addressed register pair added accumulator. Carry affected. ACC+M(R1,R0) Logical immediate data accumulator 01000010 0000dddd Data accumulator logically with immediate data specified code. Logical accumulator with data memory 00011010 Data accumulator logically with data memory addressed register pair M(R1,R0) Logical data memory with accumulator 00011101 Data data memory addressed register pair logically with accumulator M(R1,R0) M(R1,R0) 0000dddd specified data added accumulator. Carry affected.
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HTG12B0
CALL address Machine Code Description Operation Machine Code Description Operation Machine Code Description Subroutine call 1111aaaa aaaaaaaa program counter bits 0-11 saved stack. program counter then loaded from directly-specified address. Stack PC+2 address Clear carry flag 00101010 carry flag reset zero. Decimal-Adjust accumulator 00110110 accumulator value adjusted (Binary Code Decimal) code, contents accumulator greater, then (Carry flag) one. ACC>9 CF=1 then ACC+6, else ACC, Decrement accumulator 00111111 Data accumulator decremented one. Carry flag affected. ACC-1 Decrement register 0001nnn1 Data working register decremented one. Carry flag affected. Rn-1; Rn=R0, n=0,1,2,3,4 Decrement data memory 00001101 Data data memory specified register pair decremented one. Carry flag affected. M(R1, M(R1,R0)-1
Operation
Machine Code Description Operation Machine Code Description Operation [R1R0] Machine Code Description Operation
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HTG12B0
[R3R2] Machine Code Description Operation Machine Code Description Machine Code Description HALT Machine Code Description Operation A,Pi Machine Code Description Operation Machine Code Description Operation Machine Code Description Operation Decrement data memory 00001111 Data data memory specified register pair decremented one. Carry flag affected. M(R3,R2) M(R3,R2)-1 Disable interrupt 00100101 00000011 Internal time-out interrupt external interrupt disabled. Enable interrupt 00100101 00000010 Internal time-out interrupt external interrupt enabled. Halt system clock 00110111 (PC)+1 Input port accumulator 00101100 00110010 01001000 00110011 00111110 Turn system clock, enter power down mode.
data port transferred accumulator. Pi=PA, Increment accumulator 00110001 Data accumulator incremented one. Carry flag affected. ACC+1 Increment register 0001nnn0 Data working register incremented one. Carry flag affected. Rn+1; Rn=R0,R1,R2,R3,R4 n=0,1,2,3,4
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HTG12B0
[R1R0] Machine Code Description Operation [R3R2] Machine Code Description Operation address Machine Code Description Increment data memory 00001100 Data data memory specified register pair incremented one. Carry flag affected. M(R1,R0) M(R1,R0)+1 Increment data memory 00001110 Data memory specified register pair incremented one. Carry flag affected. M(R3,R2) M(R3,R2)+1 Jump accumulator 100nnaaa aaaaaaaa Bits 0-10 program counter replaced with address, program counter memory bank remain, accumulator one. (bit 0-10) address, PC+2, Jump carry 11000aaa aaaaaaaa Bits 0-10 program counter replaced with address, program counter memory bank remain, (Carry flag) one. (bit 0-10) address, PC+2, Direct Jump 1110aaaa aaaaaaaa Bits 0-11 program counter replaced with address. address Jump carry 11001aaa aaaaaaaa Bits 0-10 program counter replaced with address, program counter memory bank remain, (Carry flag) zero. (bit 0-10) address, PC+2,
Operation address Machine Code Description
Operation address Machine Code Description Operation address Machine Code Description
Operation
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HTG12B0
A,address Machine Code Description Jump accumulator zero 10111aaa aaaaaaaa Bits 0-10 program counter replaced with address, program counter memory bank remain, accumulator zero. (bit 0-10) address, PC+2, ACC=0 Jump register zero 10100aaa 10101aaa 11011aaa Description aaaaaaaa aaaaaaaa aaaaaaaa
Operation Rn,address Machine Code
Bits 0-10 program counter replaced with address, program counter memory bank remain, register zero. (bit 0-10) address, Rn=R0, PC+2, Rn=0 Jump time-out 11010aaa aaaaaaaa Bits 0-10 program counter replaced with address, program counter memory bank remain, (Timer flag) one. (bit 0-10) address, TF=1 PC+2, TF=0 Jump accumulator zero 10110aaa aaaaaaaa Bits 0-10 program counter replaced with address, program counter memory bank remain, accumulator zero. (bit 0-10) address, ACC=0 PC+2, Move register accumulator 0010nnn1 Data working register moved accumulator. Rn=R0, n=0,1,2,3,4
Operation JTMR address Machine Code Description
Operation A,address Machine Code Description
Operation A,Rn Machine Code Description Operation
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HTG12B0
A,TMRH Machine Code Description Operation A,TMRL Machine Code Description Operation A,XH Machine Code Description Operation A,[R1R0] Machine Code Description Operation A,[R3R2] Machine Code Description Operation LCDC, Machine Code Description Operation R1R0,XXH Machine Code Description Move timer accumulator 00111011 high nibble data Timer counter loaded accumulator. TIMER (high nibble) Move timer accumulator 00111010 nibble data Timer counter loaded accumulator. TIMER (low nibble) Move immediate data accumulator 0111dddd 4-bit data specified code loaded accumulator. Move data memory accumulator 00000100 Data data memory specified register pair moved accumulator. M(R1,R0) Move data memory accumulator 00000110 Data data memory specified register pair moved accumulator. M(R3,R2) Move accumulator LCDC register 00110000 Data accumulator moved LCDC register. LCDC Move immediate data 0101dddd 0000dddd 8-bit data specified code loaded working registers high nibble data loaded nibble data loaded (high nibble) (low nibble)
Operation
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HTG12B0
R3R2,XXH Machine Code Description Move immediate data 0110dddd 0000dddd 8-bit data specified code loaded working register high nibble data loaded nibble data loaded (high nibble) (low nibble) Move immediate data 01000110 Move accumulator register 0010nnn0 Data accumulator moved working register ACC; Rn=R0, n=0, Move accumulator RAMB register 00110100 Data accumulator moved RAMB register RAMB Move accumulator ROMB register 00110101 Data accumulator moved ROMB register ROMB Move accumulator timer 00111101 contents accumulator loaded high nibble timer counter. TIMER (high nibble) Move accumulator timer 00111100 contents accumulator loaded nibble timer counter. TIMER (low nibble) 0000dddd 4-bit data specified code loaded working register
Operation R4,XH Machine Code Description Operation Rn,A Machine Code Description Operation RAMB, Machine Code Description Operation ROMB, Machine Code Description Operation TMRH,A Machine Code Description Operation TMRL,A Machine Code Description Operation
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HTG12B0
[R1R0],A Machine Code Description Operation [R3R2],A Machine Code Description Operation Machine Code Description A,XH Machine Code Description Operation A,[R1R0] Machine Code Description Operation [R1R0],A Machine Code Description Operation Pi,A Machine Code Description Operation Move accumulator data memory 00000101 Data accumulator moved data memory specified register pair M(R1,R0) Move accumulator data memory 00000111 Data accumulator moved data memory specified register pair M(R3,R2) operation 00111110 nothing, instruction cycle delayed. Logical immediate data accumulator 01000100 0000dddd Data accumulator logically with immediate data specified code. Logical accumulator with data memory 00011100 Data accumulator logically with data memory addressed register pair M(R1,R0) Logical data memory with accumulator 00011111 Data data memory addressed register pair logically with accumulator. M(R1,R0) M(R1,R0) Output accumulator data port-i 00101101 01001001 data accumulator transferred port-i latched. ACC; Pi=PA
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HTG12B0
READ MR0A Machine Code Description Read code current page M(R1,R0) 01001101 8-bit code (current page) addressed moved data memory M(R1,R0) accumulator. high nibble code loaded M(R1,R0) nibble code loaded accumulator. address code specified below: Current page code address 12~8 code address code address M(R1,R0) code (high nibble) code (low nibble) Read code current page accumulator 01001100 8-bit code (current page) addressed M(R1,R0) moved working register accumulator. high nibble code loaded nibble code loaded accumulator. address code specified below: Current page code address 12~8 code address M(R1,R0) code address code (high nibble) code (low nibble) Read Code page M(R1,R0) 01001111 8-bit code (page addressed moved data memory M(R1,R0) accumulator. high nibble code loaded M(R1,R0) nibble code loaded accumulator. page code address 12~8 code address code address M(R1,R0) high nibble code (page nibble code (page
Operation READ Machine Code Description
Operation READF MR0A Machine Code Description
Operation
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HTG12B0
READF Machine Code Description Read code page accumulator 01001110 8-bit code (page addressed M(R1,R0) moved working register accumulator. high nibble code loaded nibble code loaded accumulator. page code address 12~8 code address M(R1,R0) code address high nibble code (page nibble code (page Return from subroutine interrupt 00101110 program counter bits 0~11 restored from stack. Stack Return from interrupt subroutine 00101111 program counter bits 0~11 restored from stack. carry flag before entering interrupt service routine restored. Stack (before interrupt service routine) Rotate accumulator left 00000001 contents accumulator rotated left. rotated carry flag. An+1 accumulator (n=0,1,2) Rotate accumulator left through carry 00000011 contents accumulator rotated left. replaces carry bit; carry rotated into position. An+1 Accumulator (n=0,1,2)
Operation Machine Code Description Operation RETI Machine Code Description Operation Machine Code Description Operation
Machine Code Description Operation
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HTG12B0
Machine Code Description Operation Rotate accumulator right 00000000 contents accumulator rotated right. rotated carry flag. An+1; Accumulator (n=0,1,2) Rotate accumulator right through carry 00000010 contents accumulator rotated right. replaces carry bit; carry rotated into position. An+1; Accumulator (n=0,1,2) Subtract data memory contents carry from 00001010 contents data memory addressed register pair carry subtracted from accumulator. Carry affected. ACC+M(R1,R0)+CF Active SOUND channel with accumulator 01001011 activated sound begins playing accordance with contents accumulator when specified sound channel matched. Turn sound repeat mode 01001001 00000001 activated sound plays repeatedly. Turn sound 01001010 singing sound will terminate immediately. Turn sound mode 01000101 00000000 activated sound plays only time.
Machine Code Description Operation
A,[R1R0] Machine Code Description Operation SOUND Machine Code Description SOUND LOOP Machine Code Description SOUND Machine Code Description SOUND Machine Code Description
September 1999
HTG12B0
Machine Code Description Operation A,XH Machine Code Description Operation A,[R1R0] Machine Code Description Operation TIMER Machine Code Description TIMER Machine Code Description TIMER Machine Code Description Operation A,XH Machine Code Description Operation carry flag 00101011 carry flag one. Subtract immediate data from accumulator 01000001 ACC+XH+1 Subtract data memory contents from accumulator 00001011 contents data memory addressed register pair subtracted from accumulator. Carry affected. ACC+M(R1,R0)+1 timer stop counting 00111001 Timer stop counting, when instruction executed. timer start counting 00111000 Timer starts counting, when instruction executed. immediate data timer counter 01000111 TIMER Logical immediate data accumulator 01000011 0000dddd Data accumulator Exclusive-OR with immediate data specified code. dddddddd data specified code loaded imer counter. 0000dddd specified data subtracted from accumulator. Carry affected.
September 1999
HTG12B0
A,[R1R0] Machine Code Description Operation [R1R0],A Machine Code Description Operation Logical accumulator with data memory 00011011 Data accumulator Exclusive-OR with data memory addressed register pair M(R1,R0) Logical data memory with accumulator 00011110 Data data memory addressed register pair logically Exclusive-OR with accumulator. M(R1,R0) M(R1,R0)
September 1999
HTG12B0
Holtek Semiconductor Inc. (Headquarters) No.3 Creation Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) No.576, Sec.7 Chung Hsiao Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Microelectronics Enterprises Ltd. RM.711, Tower Cheung Plaza, Cheung Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright 1999 HOLTEK SEMICONDUCTOR INC. information appearing this Data Sheet believed accurate time publication. However, Holtek assumes responsibility arising from specifications described. applications mentioned herein used solely purpose illustration Holtek makes warranty representation that such applications will suitable without further modification, recommends products application that present risk human life malfunction otherwise. Holtek reserves right alter products without prior notification. most up-to-date information, please visit site http://www.holtek.com.tw.
September 1999
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