PM7380 FREEDM-32P672 FRAME ENGINE DATA LINK MANAGER 32P672 P
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RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
PM7380
FREEDMTM-32P672
FRAME ENGINE DATALINK MANAGER 32P672
DATA SHEET
PROPRIETARY CONFIDENTIAL ISSUE AUGUST 2001
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
PUBLIC REVISION HISTORY Issue Issue Issue Issue Issue Issue Issue Date February, 1999 1999 July 2000 August 2001 Details Change Created Document. Added pinout.
Jan, 2000 Minor Corrections. Minor Corrections some timing parameters Added patent information legal footer.
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
CONTENTS FEATURES.1 APPLICATIONS.4 REFERENCES APPLICATION EXAMPLES BLOCK DIAGRAM.8 DESCRIPTION DIAGRAM DESCRIPTION FUNCTIONAL DESCRIPTION HIGH SPEED MULTI-VENDOR INTEGRATION PROTOCOL (H-MVIP) HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL.38 RECEIVE CHANNEL ASSIGNER 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 LINE INTERFACE TRANSLATOR (LIT) LINE INTERFACE.42 PRIORITY ENCODER CHANNEL ASSIGNER LOOPBACK CONTROLLER
RECEIVE HDLC PROCESSOR PARTIAL PACKET BUFFER.43 9.4.1 9.4.2 HDLC PROCESSOR PARTIAL PACKET BUFFER PROCESSOR
RECEIVE CONTROLLER 9.5.1 DATA STRUCTURES
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
9.5.2 9.5.3 9.5.4 9.5.5
TRANSACTION CONTROLLER.56 WRITE DATA PIPELINE/MUX DESCRIPTOR INFORMATION CACHE FREE QUEUE CACHE
CONTROLLER.57 9.6.1 9.6.2 9.6.3 9.6.4 9.6.5 MASTER MACHINE MASTER LOCAL INTERFACE.60 TARGET MACHINE INTERFACE ERROR CONTROL
TRANSMIT CONTROLLER.63 9.7.1 9.7.2 9.7.3 9.7.4 9.7.5 9.7.6 DATA STRUCTURES TASK PRIORITIES TRANSACTION CONTROLLER.76 READ DATA PIPELINE.76 DESCRIPTOR INFORMATION CACHE FREE QUEUE CACHE
TRANSMIT HDLC CONTROLLER PARTIAL PACKET BUFFER77 9.8.1 9.8.2 TRANSMIT HDLC PROCESSOR.77 TRANSMIT PARTIAL PACKET BUFFER PROCESSOR78
TRANSMIT CHANNEL ASSIGNER 9.9.1 9.9.2 9.9.3 LINE INTERFACE TRANSLATOR (LIT) LINE INTERFACE.82 PRIORITY ENCODER
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
9.9.4 9.10 9.11 9.12
CHANNEL ASSIGNER
PERFORMANCE MONITOR JTAG TEST ACCESS PORT INTERFACE.84 HOST INTERFACE
NORMAL MODE REGISTER DESCRIPTION 10.1 HOST ACCESSIBLE REGISTERS
CONFIGURATION REGISTER DESCRIPTION .252 11.1 CONFIGURATION REGISTERS.252
TEST FEATURES DESCRIPTION .263 12.1 12.2 TEST MODE REGISTERS .263 JTAG TEST PORT .264 12.2.1 12.2.2 IDENTIFICATION REGISTER .265 BOUNDARY SCAN REGISTER .265
OPERATIONS .282 13.1 13.2 TOCTL CONNECTIONS .282 JTAG SUPPORT.282
FUNCTIONAL TIMING .289 14.1 14.2 14.3 14.4 14.5 14.6 RECEIVE H-MVIP LINK TIMING .289 TRANSMIT H-MVIP LINK TIMING.290 RECEIVE H-MVIP LINK TIMING .291 TRANSMIT H-MVIP LINK TIMING .293 INTERFACE .294 BERT INTERFACE .303
ABSOLUTE MAXIMUM RATINGS.305
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
D.C. CHARACTERISTICS.306 FREEDM-32P672 TIMING CHARACTERISTICS.308 ORDERING THERMAL INFORMATION .318 MECHANICAL INFORMATION.319
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
LIST FIGURES FIGURE H-MVIP PROTOCOL FIGURE HDLC FRAME.39 FIGURE GENERATOR.39 FIGURE PARTIAL PACKET BUFFER STRUCTURE FIGURE RECEIVE PACKET DESCRIPTOR.47 FIGURE RECEIVE PACKET DESCRIPTOR TABLE.50 FIGURE RPDRF RPDRR QUEUES FIGURE RPDRR QUEUE OPERATION.54 FIGURE RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE.55 FIGURE GPIC ADDRESS FIGURE TRANSMIT DESCRIPTOR.64 FIGURE TRANSMIT DESCRIPTOR TABLE FIGURE TDRR TDRF QUEUES FIGURE TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE FIGURE LINKING.75 FIGURE PARTIAL PACKET BUFFER STRUCTURE FIGURE INPUT OBSERVATION CELL (IN_CELL) .279 FIGURE OUTPUT CELL (OUT_CELL) .280 FIGURE BI-DIRECTIONAL CELL (IO_CELL) .280 FIGURE LAYOUT OUTPUT ENABLE BI-DIRECTIONAL CELLS .281 FIGURE BOUNDARY SCAN ARCHITECTURE .283 FIGURE CONTROLLER FINITE STATE MACHINE .285
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
FIGURE RECEIVE 8.192 MBPS H-MVIP LINK TIMING .289 FIGURE RECEIVE 2.048 MBPS H-MVIP LINK TIMING .290 FIGURE TRANSMIT 8.192 MBPS H-MVIP LINK TIMING.290 FIGURE TRANSMIT 2.048 MBPS H-MVIP LINK TIMING.291 FIGURE UNCHANNELISED RECEIVE LINK TIMING .292 FIGURE CHANNELISED T1/J1 RECEIVE LINK TIMING .292 FIGURE CHANNELISED RECEIVE LINK TIMING .293 FIGURE UNCHANNELISED TRANSMIT LINK TIMING.293 FIGURE CHANNELISED T1/J1 TRANSMIT LINK TIMING .294 FIGURE CHANNELISED TRANSMIT LINK TIMING .294 FIGURE READ CYCLE .296 FIGURE WRITE CYCLE .297 FIGURE TARGET DISCONNECT .298 FIGURE TARGET ABORT.299 FIGURE REQUEST CYCLE .299 FIGURE INITIATOR ABORT TERMINATION .300 FIGURE EXCLUSIVE LOCK CYCLE .301 FIGURE FAST BACK BACK.303 FIGURE RECEIVE BERT PORT TIMING .303 FIGURE TRANSMIT BERT PORT TIMING .304 FIGURE RECEIVE DATA FRAME PULSE TIMING (2.048 MBPS H-MVIP MODE) .310 FIGURE RECEIVE DATA FRAME PULSE TIMING (8.192 MBPS H-MVIP MODE) .310 FIGURE RECEIVE DATA TIMING (NON H-MVIP MODE)
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
FIGURE BERT INPUT TIMING FIGURE TRANSMIT DATA FRAME PULSE TIMING (2.048 MBPS H-MVIP MODE).313 FIGURE TRANSMIT DATA FRAME PULSE TIMING (8.192 MBPS H-MVIP MODE).314 FIGURE TRANSMIT DATA TIMING (NON H-MVIP MODE) .314 FIGURE BERT OUTPUT TIMING .315 FIGURE INTERFACE TIMING .316 FIGURE JTAG PORT INTERFACE TIMING.317 FIGURE PLASTIC BALL GRID ARRAY (PBGA) .319
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
viii
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
LIST TABLES TABLE LINE SIDE INTERFACE SIGNALS (154) TABLE HOST INTERFACE SIGNALS (52) TABLE MISCELLANEOUS INTERFACE SIGNALS (58).32 TABLE PRODUCTION TEST INTERFACE SIGNALS MULTIPLEXED)33 TABLE POWER GROUND SIGNALS (65) TABLE RECEIVE PACKET DESCRIPTOR FIELDS.47 TABLE RPDRR QUEUE ELEMENT TABLE RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS TABLE TRANSMIT DESCRIPTOR FIELDS TABLE TRANSMIT DESCRIPTOR REFERENCE.71 TABLE TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS TABLE NORMAL MODE HOST ACCESSIBLE REGISTER MEMORY TABLE CONFIGURATION REGISTER MEMORY MAP.88 TABLE ENDIAN FORMAT. TABLE LITTLE ENDIAN FORMAT TABLE RECEIVE LINKS CONFIGURATION .130 TABLE RECEIVE LINKS CONFIGURATION .132 TABLE CRC[1:0] SETTINGS.139 TABLE RPQ_RDYN[2:0] SETTINGS .150 TABLE RPQ_LFN[1:0] SETTINGS.151 TABLE RPQ_SFN[1:0] SETTINGS .151
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RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
TABLE TDQ_RDYN[2:0] SETTINGS.185 TABLE TDQ_FRN[1:0] SETTINGS .185 TABLE CRC[1:0] SETTINGS.213 TABLE FLAG[2:0] SETTINGS .219 TABLE LEVEL[3:0]/TRANS SETTINGS .221 TABLE TRANSMIT LINKS CONFIGURATION .239 TABLE TRANSMIT LINKS CONFIGURATION .241 TABLE TEST MODE REGISTER MEMORY .264 TABLE INSTRUCTION REGISTER .265 TABLE BOUNDARY SCAN CHAIN .265 TABLE FREEDM-TOCTL CONNECTIONS .282 TABLE FREEDM-32P672 ABSOLUTE MAXIMUM RATINGS.305 TABLE FREEDM-32P672 D.C. CHARACTERISTICS.306 TABLE FREEDM-32P672 LINK INPUT (FIGURE FIGURE 46).308 TABLE FREEDM-32P672 LINK OUTPUT (FIGURE FIGURE TABLE INTERFACE (FIGURE .315 TABLE JTAG PORT INTERFACE (FIGURE 52).316 TABLE FREEDM-32P672 ORDERING INFORMATION.318 TABLE FREEDM-32P672 THERMAL INFORMATION .318
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
FEATURES Single-chip multi-channel HDLC controller with MHz, Peripheral Component Interconnect (PCI) Revision configuration, monitoring transfer packet data, with on-chip controller with scatter/ gather capabilities. Supports bi-directional HDLC channels assigned maximum H-MVIP digital telephony buses 2.048 Mbps link. links grouped into logical groups links. common clock type frame pulse shared among links each logical group. number time-slots assigned HDLC channel programmable from Supports bi-directional HDLC channels assigned maximum H-MVIP digital telephony buses 8.192 Mbps link. links share common clock type frame pulse. number time-slots assigned HDLC channel programmable from 128. Supports bi-directional HDLC channels assigned maximum channelised T1/J1 links. number time-slots assigned HDLC channel programmable from (for T1/J1) from (for E1). Supports bi-directional HDLC channels each assigned unchannelised arbitrary rate link, subject maximum aggregate link clock rate each direction. Channels assigned links support clock rate 51.84 MHz. Channels assigned links support clock rate MHz. Supports three bi-directional HDLC channels each assigned unchannelised arbitrary rate link 51.84 when SYSCLK running MHz. Supports channelised, unchannelised H-MVIP links, subject constraint maximum channels maximum aggregate link clock rate each direction. Links configured channelised T1/J1/E1 unchannelised operation support gapped-clock method determining time-slots which backwards compatible with FREEDM-8 FREEDM-32 devices. each channel, HDLC receiver supports programmable flag sequence detection, de-stuffing frame check sequence validation. receiver
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
supports validation both CRC-CCITT CRC-32 frame check sequences. each channel, receiver checks packet abort sequences, octet aligned packet length minimum maximum packet length. receiver supports filtering packets that larger than user specified maximum value. Alternatively, each channel, receiver supports transparent mode where each octet transferred transparently host memory. channelised links, octets aligned with receive time-slots. each channel, time-slots selectable kbits/s format kbits/s clear channel format. each channel, HDLC transmitter supports programmable flag sequence generation, stuffing frame check sequence generation. transmitter supports generation both CRC-CCITT CRC-32 frame check sequences. transmitter also aborts packets under direction host automatically when channel underflows. Supports levels non-preemptive packet priority each transmit channel. priority packets will begin transmission until high priority packets transmitted. Alternatively, each channel, transmitter supports transparent mode where each octet inserted transparently from host memory. channelised links, octets aligned with transmit time-slots. Provides Kbytes on-chip memory partial packet buffering both transmit receive directions. This memory configured support variety different channel configurations from single channel with Kbytes buffering channels, each with minimum bytes buffering. Supports burst sizes bytes transfers packet data. Provides standard signal P1149.1 JTAG test port boundary scan board test purposes. Supports Volt signaling environments. Supports Volt tolerant (except PCI). power Volt 0.25 CMOS technology.
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
plastic ball grid array (PBGA) package.
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
APPLICATIONS IETF interfaces routers switches Frame Relay interfaces Frame Relay switches multiplexors FUNI Frame Relay service inter-working interfaces Aswitches multiplexors. Internet/Intranet access equipment. Packet-based DSLAM equipment.
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
REFERENCES International Organization Standardization, Standard 3309-1993, "Information Technology Telecommunications information exchange between systems High-level data link control (HDLC) procedures Frame structure", December 1993. RFC-1662 "PPP HDLC-like Framing" Internet Engineering Task Force, July 1994. Special Interest Group, Local Specification, June 1995, Version 2.1. GO-MVIP, "MVIP-90 Standard", October 1994, release 1.1. GO-MVIP, "H-MVIP Standard", January 1997, release 1.1a.
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
APPLICATION EXAMPLES
H-MVIP
PM4354 COMET-QUAD
H-MVIP
PM4354 COMET-QUAD Switch Fabric PM7380 FREEDM32P672
Packet Memory
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
T1/E1/J1
PM4354 COMET-QUAD
Controller Arbite PM4354 COMET-QUAD
Packet Memory
PM8315 TEMUX
PM7380 FREEDM32P672 Controller Arbite
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED
DATA SHEET
PMC-1990262
SYSC
RBCLK
Receive HDLC Processor/ Partial Packet Buffer (RHDL672) Performance Monitor (PMON) Controller (GPIC672) Transm Controller (TMAC 672) Receive Controller (RMAC672) AD[31:0] C/BEB[3:0]
BLOCK DIAGRAM
RD[31:0] RCLK[31:0] RFPB[3:0] RMVCK[3:0] RMV8DC RMV8FPC RFP8B Receive Channel Assigner (RCAS672)
TD[31:0] TCLK [31:0] B[3:0] CK[3:0] TMV8FPC TFP8B Transm Channel Assigner (TCAS672) Transmit HDLC Processor/ Partial Packet Buffer (THDL672) JTAG Port
FRAMEB STOPB DEVSELB IDSE LOCKB REQB PERRB SERRB PCICLK PCICLK M66EN
ISSUE
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL FRAME ENGINE DATA LINK MANAGER 32P672
PM7380 FREEDM-32P672
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
DESCRIPTION PM7380 FREEDM-32P672 Frame Engine Datalink Manager device monolithic integrated circuit that implements HDLC processing, memory management functions maximum bi-directional channels. FREEDM-32P672 configured support H-MVIP, channelised T1/J1/E1 unchannelised traffic across physical links. FREEDM-32P672 configured interface with H-MVIP digital telephony buses 2.048 Mbps. 2.048 Mbps H-MVIP links, FREEDM32P672 allows bi-directional HDLC channels assigned individual time-slots within maximum H-MVIP links. channel assignment supports concatenation time-slots DS0) maximum concatenated time-slots each 2.048 Mbps H-MVIP link. Time-slots assigned particular channel need contiguous within H-MVIP link. When configured 2.048 Mbps H-MVIP operation, FREEDM-32P672 partitions physical links into logical groups links. Links through through through through make logical groups. Links each logical group share common clock common type frame pulse each direction. FREEDM-32P672 configured interface with H-MVIP digital telephony buses 8.192 Mbps. 8.192 Mbps H-MVIP links, FREEDM32P672 allows bi-directional HDLC channels assigned individual time-slots within maximum H-MVIP links. channel assignment supports concatenation time-slots DS0) maximum concatenated time-slots each 8.192 H-MVIP link. Time-slots assigned particular channel need contiguous within H-MVIP link. When configured 8.192 Mbps H-MVIP operation, FREEDM-32P672 partitions physical links into logical groups links. Only first link, which must located physical links numbered each logical group configured 8.192 Mbps operation. remaining physical links logical group (numbered 4m+1, 4m+2 4m+3) unused. links configured 8.192 Mbps H-MVIP operation will share common type frame pulse, common frame pulse clock common data clock. channelised T1/J1/E1 links, FREEDM-32P672 allows bidirectional HDLC channels assigned individual time-slots within maximum independently timed T1/J1 links. gapped clock method determine time-slot positions FREEDM-8 FREEDM-32 devices retained. channel assignment supports concatenation time-slots DS0) maximum concatenated time-slots T1/J1
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
link concatenated time-slots link. Time-slots assigned particular channel need contiguous within T1/J1 link. unchannelised links, FREEDM-32P672 processes bi-directional HDLC channels within independently timed links. links arbitrary frame format. When limited three unchannelised links, each link rated 51.84 provided SYSCLK running MHz. lower rate unchannelised links, FREEDM-32P672 processes links each rated MHz. this case, aggregate clock rate links limited MHz. FREEDM-32P672 supports mixing channelised T1/J1/E1, unchannelised H-MVIP links. total number channels each direction limited 672. aggregate instantaneous clock rate over possible links limited MHz. receive direction, FREEDM-32P672 performs channel assignment packet extraction validation. each provisioned HDLC channel, FREEDM-32P672 delineates packet boundaries using flag sequence detection, performs de-stuffing. Sharing opening closing flags, well sharing zeros between flags supported. resulting packet data placed into internal Kbyte partial packet buffer RAM. partial packet buffer acts logical FIFO each assigned channels. Partial packets DMA'd RAM, across into host packet memory. FREEDM-32P672 validates frame check sequence each packet, verifies that packet integral number octets length within programmable minimum maximum length. receive packet status updated before linking packet into receive ready queue. FREEDM32P672 alerts Host that there packets receive ready queue optionally, asserting interrupt bus. Alternatively, receive direction, FREEDM-32P672 supports transparent operating mode. each provisioned transparent channel, FREEDM-32P672 directly transfers received octets into host memory verbatim. transparent channel assigned channelised link, then octets aligned received time-slots. transmit direction, Host provides packets transmit using transmit ready queue. each provisioned HDLC channel, FREEDM32P672 DMA's partial packets across into transmit partial packet buffer. partial packets read packet buffer FREEDM-32P672 frame check sequence optionally calculated inserted each packet. stuffing performed before being assigned particular link. flag sequence automatically inserted when there packet data particular channel. Sequential packets
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
optionally separated flags opening flag closing flag) single flag (combined opening closing flag). Zeros between flags shared. latency cause more channels underflow, which case, packets aborted, host notified. normal traffic, abort sequence generated, followed inter-frame time fill characters (flags allones bytes) until packet sourced from host. attempt made automatically re-transmit aborted packet. Alternatively, transmit direction, FREEDM-32P672 supports transparent operating mode. each provisioned transparent channel, FREEDM-32P672 directly inserts transmitted octets from host memory. transparent channel assigned channelised link, then octets aligned transmitted time-slots. channel underflows excessive latency, abort sequence generated, followed inter-frame time fill characters (flags all-ones bytes) indicate idle channel. Data resumes immediately when FREEDM-32P672 receives data from host. FREEDM-32P672 configured, controlled monitored using interface. supports Volt signaling. FREEDM-32P672 implemented power Volt 0.25 CMOS technology. non-PCI FREEDM-32P672 pins volt tolerant. FREEDM-32P672 packaged plastic ball grid array (PBGA) package.
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
DIAGRAM FREEDM-32P672 manufactured plastic ball grid array package.
RMVCK[2]
RD[16]
RCLK[17] RCLK[19]
RD[21]
RD[22]
RD[23]
RD[24]
RCLK[25] RCLK[27] RCLK[29]
VDD2V5
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
RFPB[2] RCLK[16]
RD[18]
RD[20]
VDD2V5
RCLK[22] RFPB[3] RCLK[24] RCLK[26]
RD[28]
RD[30]
RCLK[31]
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VDD2V5
N.C.
N.C.
N.C.
N.C.
RD[15]
RSTB
RCLK[15] RCLK[18] RCLK[20] RCLK[21] RMVCK[3]
RD[25]
RD[27]
RCLK[28] RCLK[30]
RD[31]
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
RCLK[13]
RD[13]
RCLK[14]
RD[17]
RD[19]
VDD3V3
RCLK[23]
RD[26]
VDD3V3
RD[29]
N.C.
VDD3V3
N.C.
N.C.
VDD3V3
N.C.
N.C.
N.C.
N.C.
N.C.
RD[12]
VDD2V5
RCLK[12]
RD[14]
N.C.
N.C.
VDD2V5
N.C.
RD[11]
RCLK[10] RCLK[11]
N.C.
N.C.
N.C.
RD[10]
RD[9]
RCLK[8]
RCLK[9]
BOTTOM VIEW
PCICLKO
PCICLK
N.C.
PCIINTB
RD[8]
RMVCK[1] RFPB[1]
VDD3V3
VDD3V3
AD[31]
REQB
GNTB
RCLK[7]
RCLK[6]
RD[6]
RD[7]
AD[29]
AD[27]
AD[28]
AD[30]
SYSCLK
RCLK[5]
RD[5]
AD[24]
AD[25]
AD[26]
RD[4]
RD[3]
RCLK[3]
RCLK[4]
CBEB[3]
AD[22]
AD[23]
IDSEL
VDD2V5
RCLK[2]
RD[2]
VDD3V3
VDD3V3
AD[21]
AD[20]
VDD2V5
RCLK[0]
RD[1]
RCLK[1]
RD[0]
AD[16]
AD[18]
AD[19]
AD[17]
RMV8FPC
RFPB[0] RMVCK[0]
CBEB[2]
FRAMEB
IRDYB
RMV8DC
RFP8B
RBCLK
STOPB
TRDYB
DEVSELB
LOCKB
TRSTB
VDD3V3
VDD3V3
PERRB
SERRB
TFP8B
TMV8DC
AD[14]
CBEB[1]
AD[15]
AD[13]
TFPB[0]
TMV8FPC TMVCK[0]
AD[10]
AD[12]
AD[11]
TD[0]
VDD2V5
TCLK[0]
TD[2]
AD[6]
AD[8]
VDD2V5
AD[9]
TCLK[1]
TD[1]
TCLK[2]
TD[4]
TMVCK[1]
VDD3V3
TD[12]
TCLK[15]
VDD3V3
TCLK[17]
TD[22]
VDD3V3
TD[24]
TCLK[27]
VDD3V3
N.C.
AD[5]
CBEB[0]
AD[7]
TCLK[3]
TD[3]
TCLK[6]
TFPB[1]
TD[9]
TD[10]
TD[13]
TCLK[14] TMVCK[2]
TD[17]
TCLK[18]
TD[20]
TCLK[20] TCLK[22] TFPB[3]
TD[25]
TCLK[26] TCLK[29] TCLK[30]
TBCLK
AD[2]
AD[4]
AD[3]
TD[5]
TCLK[4]
TCLK[7]
TCLK[8]
VDD2V5
TD[11]
TCLK[12]
TD[14]
TFPB[2] TCLK[16]
TD[19]
TCLK[19]
TD[21]
TD[23]
TMVCK[3] TCLK[25]
TD[27]
TCLK[28]
VDD2V5
TD[31]
PMCTEST
N.C.
AD[1]
TCLK[5]
TD[6]
TD[7]
TD[8]
TCLK[9] TCLK[10] TCLK[11] TCLK[13]
TD[15]
TD[16]
TD[18]
VDD2V5
TCLK[21] TCLK[23] TCLK[24]
TD[26]
TD[28]
TD[29]
TD[30]
TCLK[31]
N.C.
M66EN
AD[0]
PROPRIETARY CONFIDENTIAL PMC-SIERRA,INC., CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1990262 ISSUE
PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
DESCRIPTION Table Line Side Interface Signals (154) Name RCLK[0] RCLK[1] RCLK[2] RCLK[3] RCLK[4] RCLK[5] RCLK[6] RCLK[7] RCLK[8] RCLK[9] RCLK[10] RCLK[11] RCLK[12] RCLK[13] RCLK[14] RCLK[15] RCLK[16] RCLK[17] RCLK[18] RCLK[19] RCLK[20] RCLK[21] RCLK[22] RCLK[23] RCLK[24] RCLK[25] RCLK[26] RCLK[27] RCLK[28] RCLK[29] RCLK[30] RCLK[31] Type Input Function receive line clock signals (RCLK[31:0]) contain recovered line clock independently timed links. Processing receive links priority basis, descending order from RCLK[0] RCLK[31]. Therefore, highest rate link should connected RCLK[0] lowest RCLK[31]. channelised T1/J1 links, RCLK[n] must gapped during framing (for T1/J1 interfaces) during time-slot (for interfaces) RD[n] stream. FREEDM-32P672 uses gapping information determine time-slot alignment receive stream. RCLK[31:0] nominally duty cycle clock frequency 1.544 T1/J1 links 2.048 links. unchannelised links, RCLK[n] must externally gapped during bits timeslots that part transmission format payload (i.e. part HDLC packet). RCLK[2:0] nominally duty cycle clock between 51.84 MHz. RCLK[31:3] nominally duty cycle clock between MHz. RCLK[n] inputs invalid should forced state when their associated link configured operation H-MVIP mode.
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name RD[0] RD[1] RD[2] RD[3] RD[4] RD[5] RD[6] RD[7] RD[8] RD[9] RD[10] RD[11] RD[12] RD[13] RD[14] RD[15] RD[16] RD[17] RD[18] RD[19] RD[20] RD[21] RD[22] RD[23] RD[24] RD[25] RD[26] RD[27] RD[28] RD[29] RD[30] RD[31]
Type Input
Function receive data signals (RD[31:0]) contain recovered line data independently timed links normal mode (PMCTEST low). Processing receive links priority basis, descending order from RD[0] RD[31]. Therefore, highest rate link should connected RD[0] lowest RD[31]. H-MVIP links, RD[n] contains 32/128 time-slots, depending H-MVIP data rate configured (2.048 8.192 Mbps). When configured 2.048 Mbps H-MVIP operation, RD[31:24], RD[23:16], RD[15:8] RD[7:0] sampled every rising edge RMVCK[3], RMVCK[2], RMVCK[1] RMVCK[0] respectively point interval). When configured 8.192 Mbps H-MVIP operation, RD[4m] sampled every rising edge RMV8DC point interval). channelised links, RD[n] contains (T1/J1) (E1) time-slots that comprise channelised link. RCLK[n] must gapped during T1/J1 framing position frame alignment signal (time-slot FREEDM-32P672 uses location determine channel alignment RD[n]. RD[31:0] sampled rising edge corresponding RCLK[31:0]. unchannelised links, RD[n] contains HDLC packet data. certain transmission formats, RD[n] contain place holder bits time-slots. RCLK[n] must externally gapped during place holder positions RD[n] stream. FREEDM-32P672 supports maximum data rate Mbit/s
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name
Type
Function individual RD[31:3] link maximum data rate 51.84 Mbit/s RD[2:0]. RD[31:0] sampled rising edge corresponding RCLK[31:0].
RMVCK[0] RMVCK[1] RMVCK[2] RMVCK[3]
Input
receive MVIP data clock signals (RMVCK[3:0]) provide receive data clock links when configured operate 2.048 Mbps H-MVIP mode. When configured 2.048 Mbps H-MVIP operation, links partitioned into groups each group links share common data clock. RMVCK[0], RMVCK[1], RMVCK[2] RMVCK[3] sample data links RD[7:0], RD[15:8], RD[23:16] RD[31:24] respectively. Each RMVCK[n] nominally duty cycle clock with frequency 4.096 MHz. RMVCK[n] ignored should tied when physical link within associated logical group links configured operation 2.048 Mbps H-MVIP mode.
RFPB[0] RFPB[1] RFPB[2] RFPB[3]
Input
receive frame pulse signals (RFPB[3:0]) reference beginning each frame links when configured operation 2.048 Mbps H-MVIP mode. When configured 2.048 Mbps H-MVIP operation, links partitioned into groups each group links share common frame pulse. RFPB[0], RFPB[1], RFPB[2] RFPB[3] reference beginning frame links RD[7:0], RD[15:8], RD[23:16] RD[31:24] respectively. When configured operation 2.048 Mbps H-MVIP mode, RFPB[n] sampled falling edge RMVCK[n]. Otherwise, RFPB[n] ignored should tied low.
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name RFP8B
Type Input
Function receive frame pulse 8.192 Mbps HMVIP signal (RFP8B) references beginning each frame links configured operation 8.192 Mbps H-MVIP mode. RFP8B references beginning frame link configured 8.192 Mbps HMVIP operation. Only links configured 8.192 Mbps H-MVIP operation. When more links configured 8.192 Mbps H-MVIP operation, RFP8B sampled falling edge RMV8FPC. When links configured 8.192 Mbps H-MVIP operation, RFP8B ignored should tied low.
RMV8FPC
Input
receive 8.192 Mbps H-MVIP frame pulse clock signal (RMV8FPC) provides receive frame pulse clock links configured operation 8.192 Mbps HMVIP mode. RMV8FPC used sample RFP8B. RMV8FPC nominally duty cycle, clock with frequency 4.096 MHz. falling edge RMV8FPC must aligned with falling edge RMV8DC with more than skew. RMV8FPC ignored should tied when physical links configured operation 8.192 Mbps H-MVIP mode.
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name RMV8DC
Type Input
Function receive 8.192 Mbps H-MVIP data clock signal (RMV8DC) provides receive data clock links configured operate 8.192 Mbps H-MVIP mode. RMV8DC used sample data RD[4m] when link configured 8.192 Mbps H-MVIP operation. RMV8DC nominally duty cycle clock with frequency 16.384 MHz. RMV8DC ignored should tied when physical links configured operation 8.192 Mbps H-MVIP mode.
Tristate Output
receive BERT data signal (RBD) contains receive error rate test data. reports data selected receive data signals (RD[31:0]) updated falling edge RBCLK. tristated setting RBEN FREEDM-32P672 Master BERT Control register low. BERT supported H-MVIP links. receive BERT clock signal (RBCLK) contains receive error rate test clock. RBCLK buffered version selected receive clock signals (RCLK[31:0]). RBCLK tristated setting RBEN FREEDM32P672 Master BERT Control register low. BERT supported H-MVIP links.
RBCLK
Tristate Output
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name TCLK[0] TCLK[1] TCLK[2] TCLK[3] TCLK[4] TCLK[5] TCLK[6] TCLK[7] TCLK[8] TCLK[9] TCLK[10] TCLK[11] TCLK[12] TCLK[13] TCLK[14] TCLK[15] TCLK[16] TCLK[17] TCLK[18] TCLK[19] TCLK[20] TCLK[21] TCLK[22] TCLK[23] TCLK[24] TCLK[25] TCLK[26] TCLK[27] TCLK[28] TCLK[29] TCLK[30] TCLK[31]
Type Input
AA23 AB22 AC23 AA21 AB21 AB20 AC19 AC18 AC17 AB17 AC16 AA16 AB14 AA13 AB12 AA11 AC11 AA10 AC10
Function transmit line clock signals (TCLK[31:0]) contain transmit clocks independently timed links. Processing transmit links priority basis, descending order from TCLK[0] TCLK[31]. Therefore, highest rate link should connected TCLK[0] lowest TCLK[31]. channelised T1/J1 links, TCLK[n] must gapped during framing (for T1/J1 interfaces) during time-slot (for interfaces) TD[n] stream. FREEDM-32P672 uses gapping information determine time-slot alignment transmit stream. unchannelised links, TCLK[n] must externally gapped during bits timeslots that part transmission format payload (i.e. part HDLC packet). TCLK[2:0] nominally duty cycle clock between 51.84 MHz. TCLK[31:3] nominally duty cycle clock between MHz. Typical values TCLK[31:0] include 1.544 (for T1/J1 links) 2.048 (for links). TCLK[n] inputs invalid should tied when their associated link configured operation H-MVIP mode.
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name TD[0] TD[1] TD[2] TD[3] TD[4] TD[5] TD[6] TD[7] TD[8] TD[9] TD[10] TD[11] TD[12] TD[13] TD[14] TD[15] TD[16] TD[17] TD[18] TD[19] TD[20] TD[21] TD[22] TD[23] TD[24] TD[25] TD[26] TD[27] TD[28] TD[29] TD[30] TD[31]
Type Output
AA22 AB23 AC22 AC21 AC20 AA19 AA18 AB18 AA17 AB16 AC15 AC14 AA14 AC13 AB13 AA12 AB11 AB10
Function transmit data signals (TD[31:0]) contain transmit data independently timed links normal mode (PMCTEST low). Processing transmit links priority basis, descending order from TD[0] TD[31]. Therefore, highest rate link should connected TD[0] lowest TD[31]. H-MVIP links, TD[n] contain 32/128 time-slots, depending H-MVIP data rate configured (2.048 8.192 Mbps). When configured 2.048 Mbps H-MVIP operation, TD[31:24], TD[23:16], TD[15:8] TD[7:0] updated every falling edge TMVCK[3], TMVCK[2], TMVCK[1] TMVCK[0] respectively. When configured 8.192 Mbps H-MVIP operation, TD[4m] updated every falling edge TMV8DC. channelised links, TD[n] contains (T1/J1) (E1) time-slots that comprise channelised link. TCLK[n] must gapped during T1/J1 framing position during frame alignment signal (time-slot FREEDM-32P672 uses location determine channel alignment TD[n]. TD[31:0] updated falling edge corresponding TCLK[31:0]. unchannelised links, TD[n] contains HDLC packet data. certain transmission formats, TD[n] contain place holder bits time-slots. TCLK[n] must externally gapped during place holder positions TD[n] stream. FREEDM-32P672 supports maximum data rate Mbit/s individual TD[31:3] link maximum data rate 51.84 Mbit/s TD[2:0].
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name
Type
Function TD[31:0] updated falling edge corresponding TCLK[31:0] clock.
TMVCK[0] TMVCK[1] TMVCK[2] TMVCK[3]
Input
AA15
transmit MVIP data clock signals (TMVCK[3:0]) provide transmit data clocks links when configured operate 2.048 Mbps H-MVIP mode. When configured 2.048 Mbps H-MVIP operation, links partitioned into groups each group links share common clock. TMVCK[0], TMVCK[1], TMVCK[2] TMVCK[3] update data links TD[7:0], TD[15:8], TD[23:16] TD[31:24] respectively. Each TMVCK[n] nominally duty cycle clock with frequency 4.096 MHz. TMVCK[n] ignored should tied when physical link within associated group logical links configured operation 2.048 Mbps H-MVIP mode.
TFPB[0] TFPB[1] TFPB[2] TFPB[3]
Input
AA20 AB15
transmit frame pulse signals (TFPB[3:0]) reference beginning each frame when configured operation 2.048 Mbps H-MVIP mode. When configured 2.048 Mbps H-MVIP operation, links partitioned into groups each group links share common frame pulse. TFPB[0], TFPB[1], TFPB[2] TFPB[3] reference beginning frame links TD[7:0], TD[15:8], TD[23:16] TD[31:24] respectively. When configured operation 2.048 Mbps H-MVIP mode, TFPB[n] sampled falling edge TMVCK[n]. Otherwise, TFPB[n] ignored should tied low.
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name TFP8B
Type Input
Function transmit frame pulse 8.192 Mbps HMVIP signal (TFP8B) references beginning each frame links configured operate 8.192 Mbps H-MVIP mode. TFP8B references beginning frame link configured 8.192 Mbps HMVIP operation. Only links configured 8.192 Mbps H-MVIP operation. When more links configured 8.192 Mbps H-MVIP operation, TFP8B sampled falling edge TMV8FPC. When links configured 8.192 Mbps H-MVIP operation, TFPB[n] ignored should tied low.
TMV8FPC
Input
transmit 8.192 Mbps H-MVIP frame pulse clock signal (TMV8FPC) provides transmit frame pulse clock links configured operation 8.192 Mbps HMVIP mode. TMV8FPC used sample TFP8B. TMV8FPC nominally duty cycle, clock with frequency 4.096 MHz. falling edge TMV8FPC must aligned with falling edge TMV8DC with more than skew. TMV8FPC[n] ignored should tied when physical links configured operation 8.192 Mbps H-MVIP mode.
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name TMV8DC
Type Input
Function transmit 8.192 Mbps H-MVIP data clock signal (TMV8DC) provides transmit data clock links configured operate 8.192 Mbps H-MVIP mode. TMV8DC used update data TD[4m] when link configured 8.192 Mbps H-MVIP operation. TMV8DC nominally duty cycle clock with frequency 16.384 MHz. TMV8DC ignored should tied when physical links configured operation 8.192 Mbps H-MVIP mode.
Input
transmit BERT data signal (TBD) contains transmit error rate test data. When TBERTEN BERT Control register high, data transmitted selected transmit data signals (TD[31:0]). sampled rising edge TBCLK. BERT supported H-MVIP links. transmit BERT clock signal (TBCLK) contains transmit error rate test clock. TBCLK buffered version selected transmit clock signals (TCLK[31:0]). TBCLK tristated setting TBEN FREEDM32P672 Master BERT Control register low. BERT supported H-MVIP links.
TBCLK
Tristate Output
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Table Host Interface Signals (52) Name PCICLK Type Input Function clock signal (PCICLK) provides timing accesses. PCICLK nominally duty cycle, clock. clock output signal (PCICLKO) buffered version PCICLK. PCICLKO used derive SYSCLK input. command byte enable (C/BEB[3:0]) contains command byte valid indications. During first clock cycle transaction, C/BEB[3:0] contains command code. subsequent clock cycles, C/BEB[3:0] identifies which bytes AD[31:0] carry valid data. C/BEB[3] associated with byte (AD[31:24]) while C/BEB[0] associated with byte (AD[7:0]). When C/BEB[n] high, associated byte invalid. When C/BEB[n] low, associated byte valid. When FREEDM-32P672 initiator, C/BEB[3:0] output bus. When FREEDM-32P672 target, C/BEB[3:0] input bus. When FREEDM-32P672 involved current transaction, C/BEB[3:0] tristated. output bus, C/BEB[3:0] updated rising edge PCICLK. input bus, C/BEB[3:0] sampled rising edge PCICLK.
PCICLKO
Output
C/BEB[0] C/BEB[1] C/BEB[2] C/BEB[3]
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31]
Type
Function address data (AD[31:0]) carries multiplexed address data. During first clock cycle transaction, AD[31:0] contains physical byte address. During subsequent clock cycles transaction, AD[31:0] contains data. transaction defined address phase followed more data phases. When Little-Endian byte formatting selected, AD[31:24] contain most significant byte DWORD while AD[7:0] contain least significant byte. When Big-Endian byte formatting selected. AD[7:0] contain most significant byte DWORD while AD[31:24] contain least significant byte. When FREEDM-32P672 initiator, AD[31:0] output during first (address) phase transaction. write transactions, AD[31:0] remains output data phases transaction. read transactions, AD[31:0] input during data phases. When FREEDM-32P672 target, AD[31:0] input during first (address) phase transaction. write transactions, AD[31:0] remains input during data phases transaction. read transactions, AD[31:0] output during data phases. When FREEDM-32P672 involved current transaction, AD[31:0] tristated. output bus, AD[31:0] updated rising edge PCICLK. input bus, AD[31:0] sampled rising edge PCICLK.
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name
Type
Function parity signal (PAR) indicates parity AD[31:0] C/BEB[3:0] buses. Even parity calculated over signals buses regardless whether bytes AD[31:0] valid. always reports parity previous PCICLK cycle. Parity errors detected FREEDM-32P672 indicated output PERRB FREEDM-32P672 Interrupt Status register. When FREEDM-32P672 initiator, output writes input reads. When FREEDM-32P672 target, input writes output reads. When FREEDM-32P672 involved current transaction, tristated. output signal, updated rising edge PCICLK. input signal, sampled rising edge PCICLK.
FRAMEB
active cycle frame signal (FRAMEB) identifies transaction cycle. When FRAMEB transitions low, start transaction indicated. FRAMEB remains define duration cycle. When FRAMEB transitions high, last data phase current transaction indicated. When FREEDM-32P672 initiator, FRAMEB output. When FREEDM-32P672 target, FRAMEB input. When FREEDM-32P672 involved current transaction, FRAMEB tristated. output signal, FRAMEB updated rising edge PCICLK. input signal, FRAMEB sampled rising edge PCICLK.
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name TRDYB
Type
Function active target ready signal (TRDYB) indicates when target ready start continue with transaction. TRDYB works conjunction with IRDYB complete transaction data phases. During transaction progress, TRDYB high indicate that target cannot complete current data phase force wait state. TRDYB indicate that target complete current data phase. data phase completed when TRDYB initiator ready signal (IRDYB) also low. When FREEDM-32P672 initiator, TRDYB input. When FREEDM-32P672 target, TRDYB output. During accesses FREEDM-32P672 registers, TRDYB high extend data phases over multiple PCICLK cycles. When FREEDM-32P672 involved current transaction, TRDYB tristated. output signal, TRDYB updated rising edge PCICLK. input signal, TRDYB sampled rising edge PCICLK.
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name IRDYB
Type
Function active initiator ready (IRDYB) signal used indicate whether initiator ready start continue with transaction. IRDYB works conjunction with TRDYB complete transaction data phases. When IRDYB high transaction progress, initiator indicating cannot complete current data phase forcing wait state. When IRDYB transaction progress, initiator indicating completed current data phase. data phase completed when IRDYB target ready signal (IRDYB) also low. When FREEDM-32P672 initiator, IRDYB output. When FREEDM-32P672 target, IRDYB input. When FREEDM-32P672 involved current transaction, IRDYB tristated. IRDYB updated rising edge PCICLK sampled rising edge PCICLK depending whether output input.
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name STOPB
Type
Function active stop signal (STOPB) requests initiator stop current transaction. When STOPB high target, initiator continues with transaction. When STOPB low, initiator will stop current transaction. When FREEDM-32P672 initiator, STOPB input. When STOPB sampled low, FREEDM-32P672 will terminate current transaction next PCICLK cycle. When FREEDM-32P672 target, STOPB output. FREEDM-32P672 only issues transaction stop requests when responding reads writes configuration space (disconnecting after DWORD transferred) initiator introduces wait states during transaction. When FREEDM-32P672 involved current transaction, STOPB tristated. STOPB updated rising edge PCICLK sampled rising edge PCICLK depending whether output input.
IDSEL
Input
initialization device select signal (IDSEL) enables read write access configuration registers. When IDSEL high during address phase transaction C/BEB[3:0] code indicates register read write, FREEDM-32P672 performs configuration register transaction asserts DEVSELB signal next PCICLK period. IDSEL sampled rising edge PCICLK.
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name DEVSELB
Type
Function active device select signal (DEVSELB) indicates that target claims current transaction. During address phase transaction, targets decode address AD[31:0] bus. When target, recognizes address own, sets DEVSELB indicate initiator that address valid. target claims address clock cycles, initiator assumes that target does exist cannot respond aborts transaction. When FREEDM-32P672 initiator, DEVSELB input. target responds address PCICLK cycles, FREEDM32P672 will abort current transaction alerts Host interrupt. When FREEDM-32P672 target, DEVSELB output. DELSELB when address AD[31:0] recognised. When FREEDM-32P672 involved current transaction, DEVSELB tristated. FREEDM-32P672 updated rising edge PCICLK sampled rising edge PCICLK depending whether output input.
LOCKB
Input
active lock signal (LOCKB) locks target device. When LOCKB FRAME low, FREEDM-32P672 target, initiator locking FREEDM-32P672 "owned" target. Under these circumstances, FREEDM-32P672 will reject transaction with other initiators. FREEDM-32P672 will continue reject other initiators until owner releases lock forcing both FRAMEB LOCKB high. initiator, FREEDM32P672 will never lock target. LOCKB sampled using rising edge PCICLK.
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name REQB
Type Tristate Output
Function active request signal (REQB) requests external arbiter control bus. REQB when FREEDM32P672 desires access host memory. REQB high when access desired. REQB updated rising edge PCICLK. active grant signal (GNTB) indicates granting control over response request REQB output. When GNTB high, FREEDM-32P672 does have control over bus. When GNTB low, external arbiter granted FREEDM-32P672 control over bus. However, FREEDM-32P672 will proceed until FRAMEB signal sampled high, indicating current transactions progress. GNTB sampled rising edge PCICLK. active interrupt signal (PCIINTB) when FREEDM-32P672 interrupt source active, that source unmasked. FREEDM-32P672 enabled report many alarms events interrupts. PCIINTB returns high when interrupt acknowledged appropriate register access. PCIINTB open drain output asynchronous PCICLK.
GNTB
Input
PCIINTB
Output
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name PERRB
Type
Function active parity error signal (PERRB) indicates parity error over AD[31:0] C/BEB[3:0] buses. Parity error signalled when even parity calculations match signal. PERRB cycle immediately following offending cycle. PERRB high when parity error detected. PERRB enabled setting PERREN Control/Status register Configuration registers space. Regardless setting PERREN, parity errors always reported PERR Control/Status register Configuration registers space. PERRB updated rising edge PCICLK.
SERRB
Output
active system error signal (SERRB) indicates address parity error. Address parity errors detected when even parity calculations during address phase match signal. When FREEDM32P672 detects system error, SERRB PCICLK period. SERRB enabled setting SERREN Control/Status register Configuration registers space. Regardless setting SERREN, parity errors always reported SERR Control/Status register Configuration registers space. SERRB open drain output updated rising edge PCICLK.
M66EN
Input
active high mode enable signal (M66EN) reflects speed operation bus. M66EN should high operation bus. M66EN should operation bus.
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Table Miscellaneous Interface Signals (58) Name SYSCLK Type Input Function system clock (SYSCLK) provides timing core logic. SYSCLK nominally duty cycle, clock. active reset signal (RSTB) signal provides asynchronous FREEDM-32P672 reset. RSTB asynchronous input. When RSTB low, FREEDM-32P672 registers forced their default states. addition, TD[31:0] forced high output pins forced tristate will remain high tristated, respectively, until RSTB high. production test enable signal (PMCTEST) places FREEDM-32P672 test mode. When PMCTEST high, production test vectors executed verify manufacturing test mode interface signals TA[11:0], TA[12]/TRS, TRDB, TWRB TDAT[15:0]. PMCTEST must tied normal operation. test clock signal (TCK) provides timing test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. updated falling edge TCK. test mode select signal (TMS) controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor. test data input signal (TDI) carries test data into FREEDM-32P672 IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor.
RSTB
Input
PMCTEST
Input
Input
Input
Input
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PM7380 FREEDM-32P672
FRAME ENGINE DATA LINK MANAGER 32P672
Name
Type
Function test data output signal (TDO) carries test data FREEDM-32P672 IEEE P1149.1 test access port. updated falling edge TCK. tristate output which inactive except when scanning data progress. active test reset signal (TRSTB) provides asynchronous FREEDM-32P672 test access port reset IEEE P1149.1 test access port. TRSTB asynchronous input with integral pull resistor. Note that when TRSTB being used, must connected RSTB input.
Tristate Output
TRSTB
Input
NC1-50
Open
These pins must left unconnected.
Table Production Test Interface Signals Multiplexed) Name TA[0] TA[1] TA[2] TA[3] TA[4] TA[5] TA[6] TA[7] TA[8] TA[9] TA[10] TA[11] TA[12]/TR Type Input Function test mode address (TA[11:0]) selects specific registers during production test (PMCTEST high) read write accesses. TA[11:0] replace RD[21:10] when PMCTEST high.
Input
test register select signal (TA[12]/TRS) selects between normal test mode register accesses during production test (PMCTEST high). high select test registers select normal registers. TA[12]/TRS replaces RD[24] when PMCTEST high.
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Name TRDB
Type Input
Function test mode read enable signal (TRDB) during FREEDM-32P672 register read accesses during production test (PMCTEST high). FREEDM-32P672 drives test data (TDAT[15:0]) with contents addressed register while TRDB low. TRDB replaces RD[22] when PMCTEST high. test mode write enable signal (TWRB) during FREEDM-32P672 register write accesses during production test (PMCTEST high). contents test data (TDAT[15:0]) clocked into addressed register rising edge TWRB. TWRB replaces RD[23] when PMCTEST high. bi-directional test mode data (TDAT[15:0]) carries data read from written FREEDM-32P672 registers during production test. TDAT[15:0] replace TD[31:16] when PMCTEST high.
TWRB
Input
TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15]
AA14 AB13 AA12 AB11 AB10
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Table Power Ground Signals (65) Name VDD3V3[1] VDD3V3[2] VDD3V3[3] VDD3V3[4] VDD3V3[5] VDD3V3[6] VDD3V3[7] VDD3V3[8] VDD3V3[9] VDD3V3[10] VDD3V3[11] VDD3V3[12] VDD3V3[13] VDD3V3[14] VDD2V5[1] VDD2V5[2] VDD2V5[3] VDD2V5[4] VDD2V5[5] VDD2V5[6] VDD2V5[7] VDD2V5[8] VDD2V5[9] VDD2V5[10] VDD2V5[11] VDD2V5[12] Type Power AB19 Function VDD3V3[14:1] power pins should connected well decoupled +3.3 supply. These power pins provide current pads.
Power
VDD2V5[12:1] power pins should connected well decoupled +2.5 supply. These power pins provide current digital core.
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Name VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39]
Type Ground
Function VSS[14:1] ground pins should connected ground. They provide ground reference rail. They also provide ground reference rail.
VSS[39:15] ground pins should connected ground. They provide improved thermal properties PBGA package.
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Notes Description: FREEDM-32P672 non-PCI inputs bi-directionals present minimum capacitive loading Volt tolerant. signals conform Volt signaling environment. FREEDM-32P672 non-PCI outputs bi-directionals have drive capability, except PCICLKO, RBCLK, TBCLK outputs which have drive capability. FREEDM-32P672 outputs tristated under control IEEE P1149.1 test access port, even those which tristate under normal operation. non-PCI outputs bi-directionals tolerant when tristated. non-PCI inputs Schmitt triggered. Inputs TMS, TRSTB have internal pull-up resistors. Power VDD3V3 pins should applied before power VDD2V5 pins applied. Similarly, power VDD2V5 pins should removed before power VDD3V3 pins removed.
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FUNCTIONAL DESCRIPTION High Speed Multi-Vendor Integration Protocol (H-MVIP) H-MVIP defines synchronous, time division multiplexed (TDM) Nx64 Kbps constant rate (CBR) data streams. Each Kbps data stream (timeslot) carries 8-bit byte HDLC traffic, described following section, characterised framing. H-MVIP supports higher bandwidth applications existing telephony networks fitting more time-slots into frame. FREEDM-32P672 supports H-MVIP data rates 2.048 Mbps 8.192 Mbps with time-slots frame associated clocking frequencies 4.096 16.384 respectively. Figure shows diagram H-MVIP protocol supported FREEDM-32P672 device. Figure H-MVIP Protocol
Data Clock
Fram Pulse lock MHz)
Fram ulse KHz)
Serial Data
31/127
31/127
High-Level Data Link Control (HDLC) Protocol Figure shows diagram synchronous HDLC protocol supported FREEDM-32P672 device. incoming stream examined flag bytes (01111110 pattern) which delineate opening closing HDLC packet. packet de-stuffed which discards which directly follows five contiguous bits. resulting HDLC packet size must multiple octet bits) within expected minimum maximum packet length limits. minimum packet length that packet containing information bytes (address control) bytes. packets with CRC-CCITT FCS, minimum packet length four bytes while those with CRC-32 FCS, minimum length bytes. HDLC packet aborted when seven contiguous bits (with inserted bits) received. least
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flag byte must exist between HDLC packets delineation. Contiguous flag bytes, ones bytes between packets used "inter-frame time fill". Adjacent flag bytes share zeros. Figure HDLC Frame
Flag Information HDLC Packet Flag Flag
algorithm frame checking sequence (FCS) field either CRC-CCITT CRC-32 function. Figure shows encoder block diagram using generating polynomial g(X) g2X2 gn-1Xn-1 CRC-CCITT bytes size generating polynomial g(X) X16. CRC-32 four bytes size generating polynomial g(X) X32. first received residue highest term. Figure Generator
gn-1 Dn-1 Message
Parity Check Digits
Receive Channel Assigner Receive Channel Assigner block (RCAS672) processes serial links. Links configured support 2.048 8.192 Mbps H-MVIP traffic, support T1/J1/E1 channelised traffic support unchannelised traffic. When configured support 2.048 Mbps H-MVIP traffic, each group links share clock frame pulse. links configured 8.192 Mbps H-MVIP traffic share common clock frame pulse. T1/J1/E1 channelised traffic unchannelised traffic, each link independent associated clock. each link, RCAS672 performs serial parallel conversion form data bytes. data bytes multiplexed, byte serial format, delivery Receive HDLC Processor Partial Packet Buffer block (RHDL672) SYSCLK
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rate. event where multiple streams have accumulated byte data, multiplexing performed fixed priority basis with link having highest priority link lowest. From point view RCAS672, links configured H-MVIP traffic behave identically links configured T1/J1/E1 channelised unchannelised traffic back end, only differing link side described herein. First, number time-slots each frame programmable associated data clock frequency that double data rate. This provides more bandwidth link applications requiring higher data densities single link. Second, H-MVIP links reference start each frame with frame pulse, thereby avoiding having link clock during framing bits/bytes each frame. frame pulse provided H-MVIP master ensures that agents sharing H-MVIP remain synchronized. When configured operation 2.048 Mbps mode, frame pulse sampled using same clock which samples data. When configured operation 8.192 Mbps H-MVIP mode, frame pulse sampled using separate frame pulse clock provided H-MVIP master. frame pulse clock synchronous timing relationship data clock. Third, links independent. When configured operation 2.048 Mbps H-MVIP mode, each group links share clock frame pulse. Links through through through through each share clock frame pulse. links within each group need configured operation 2.048 Mbps H-MVIP mode. However, link within each logical group which configured 2.048 Mbps H-MVIP operation will share same clock frame pulse. When configured operation 8.192 Mbps H-MVIP mode, links share frame pulse, data clock frame pulse clock. Again, eight links need configured operation 8.192 Mbps H-MVIP mode, however, link which configured 8.192 Mbps H-MVIP operation will share same frame pulse, data clock frame pulse clock. link configured 8.192 Mbps H-MVIP operation, then data transferred that link "spread" over links 4m+1, 4m+2 4m+3 from channel assigner point view. Accordingly, when link configured operation 8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 4m+3 must also configured operation 8.192 Mbps H-MVIP mode. back end, RCAS672 extracts processes time-slots same channelised T1/J1/E1 traffic. Links containing T1/J1 stream channelised. Data each time-slot independently assigned different channel. RCAS672 performs table lookup associate link time-slot identity with channel. T1/J1 framing bits/bytes identified observing link clock which squelched during framing bits/bytes. unchannelised links, clock rates limited 51.84 links limited remaining links. data each link belongs
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channel. case mixture channelised, unchannelised H-MVIP links, total instantaneous link rate over links limited MHz. RCAS672 performs table lookup using only link number determine associated channel, time-slots non-existent unchannelised links. RCAS672 provides diagnostic loopback that selectable channel basis. RCAS672 does support diagnostic loopback links configured H-MVIP. When channel diagnostic loopback, stream data received links originally destined that channel ignored. Transmit data that channel substituted place. 9.3.1 Line Interface Translator (LIT) block translates information physical links into suitable format interpretation Line Interface block. block performs three functions: data translation, clock translation frame pulse generation. When link configured operation 8.192 Mbps H-MVIP mode, block translates time-slots link Line Interface block across links 4m+1, 4m+2 4m+3. block provides time-slots through through through through Line Interface block links 4m+1, 4m+2 4m+3 respectively. When link configured operation 8.192 Mbps H-MVIP mode, data cannot received inputs RD[4m+3:4m+1]. However, links 4m+1, 4m+2 4m+3 must programmed RCAS672 Link Configuration register 8.192 Mbps H-MVIP operation. When links configured operation 2.048 Mbps HMVIP mode, channelised T1/J1/E1 mode unchannelised mode, block does perform translation link data. When link configured operation H-MVIP mode, block divides appropriate clock (RMVCK[n] 2.048 Mbps H-MVIP RMV8DC 8.192 Mbps H-MVIP) provides this divided down clock Line Interface block. When link configured operation channelised T1/J1/E1 unchannelised mode, block does perform translation link clock. When link configured operation H-MVIP mode, block samples appropriate frame pulse (RFPB[n] 2.048 Mbps H-MVIP RFP8B 8.192 Mbps H-MVIP) presents sampled frame pulse Line Interface block. When link configured operation channelised T1/J1/E1 unchannelised mode, gapped clock passed block unmodified.
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9.3.2 Line Interface There identical line interface blocks RCAS672. Each line interface block contains sub-blocks; supporting channelised T1/J1/E1 streams other H-MVIP streams. Based configuration, only sub-blocks active time; other held reset. Each sub-block contains counter, 8-bit shift register holding register. Each sub-block performs serial parallel conversion. Whenever holding register updated, request service sent priority encoder block. When acknowledged priority encoder, line interface would respond with data residing holding register active sub-block. support H-MVIP links, each line interface block contains time-slot counter. time-slot counter incremented each time holding register updated. When frame pulse occurs, time-slot counter initialised indicate that next most significant first time-slot. support H-MVIP channelised links, each line interface block contains time-slot counter clock activity monitor. time-slot counter incremented each time holding register updated. clock activity monitor counter that increments system clock (SYSCLK) rate cleared rising edge receive clock (RCLK[n]). framing (T1/J1) framing byte (E1) detected when counter reaches programmable threshold, which case, time-slot counters initialised indicate that next most significant first time-slot. unchannelised links, time-slot counter clock activity monitor held reset. 9.3.3 Priority Encoder priority encoder monitors line interfaces requests synchronises them SYSCLK timing domain. Requests serviced fixed priority scheme where highest lowest priority assigned from line interface attached RD[0] that attached RD[31]. Thus, simultaneous requests from RD[m] will serviced ahead RD[n], When there pending requests, priority encoder generates idle cycle. addition, once every fourth SYSCLK cycle, priority encoder inserts null cycle where requests serviced. This cycle used channel assigner downstream host microprocessor accesses provisioning RAMs. 9.3.4 Channel Assigner channel assigner block determines channel number data byte currently being processed. block contains 1024 word channel provision RAM. address constructed from concatenating link
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number time-slot number current data byte. fields each word include channel number time-slot enable flag. time-slot enable flag labels current time-slot belonging channel indicted channel number field. 9.3.5 Loopback Controller loopback controller block implements channel based diagnostic loopback function. Every valid data byte belonging channel with diagnostic loopback enabled from Transmit HDLC Processor Partial Packet Buffer block (THDL672) written into word FIFO. loopback controller monitors idle time-slot time-slot carrying channel with diagnostic loopback enabled. either conditions hold, current data byte replaced data retrieved from loopback data FIFO. Receive HDLC Processor Partial Packet Buffer Receive HDLC Processor Partial Packet Buffer block (RHDL672) processes synchronous transmission HDLC data streams. Each channel individually configured perform flag sequence detection, de-stuffing CRC-CCITT CRC-32 verification. packet data written into partial packet buffer. frame, packet status including error, octet alignment error maximum length violation also loaded into partial packet buffer. Alternatively, channel provisioned transparent, which case, HDLC data stream passed partial packet buffer processor verbatim. There natural precedence alarms detectable receive packet. Once packet exceeds programmable maximum packet length, further processing performed Thus, octet alignment detection, verification abort recognition squelched packets with maximum length violation. abort indication squelches octet alignment detection, minimum packet length violations, verification. addition, verification only performed packets that have octet alignment errors, order allow RHDL672 perform calculations byte-basis. partial packet buffer Kbyte that divided into 16-byte blocks. Each block associated pointer which points another block. logical FIFO created each provisioned channel programming block pointers form circular linked list. channel FIFO assigned minimum blocks bytes) maximum 2048 blocks Kbytes). depth channel FIFOs monitored round-robin fashion. Requests made Receive Controller block (RMAC672) transfer, host memory, data channel FIFOs with depths exceeding their associated threshold.
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9.4.1 HDLC Processor HDLC processor time-slice state machine which process independent channels. state vector provisioning information each channel stored RAM. Whenever channel data arrives, appropriate state vector read from RAM, processed written back RAM. HDLC state-machine configured perform flag delineation, de-stuffing, verification length monitoring. resulting HDLC data status information passed partial packet buffer processor stored appropriate channel FIFO buffer. configuration HDLC processor accessed using indirect channel read write operations. When indirect operation performed, information accessed from during null clock cycle generated upstream Receive Channel Assigner block (RCAS672). Writing provisioning data channel resets channel's entire state vector. 9.4.2 Partial Packet Buffer Processor partial packet buffer processor controls Kbyte partial packet which divided into byte blocks. block pointer used chain partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous sections allocated partial packet buffer create channel FIFO. System software responsible assignment blocks individual channel FIFOs. Figure shows example three blocks (blocks 200) linked together form byte channel FIFO. partial packet buffer processor divided into three sections: writer, reader roamer. writer time-sliced state machine which writes HDLC data status information from HDLC processor into channel FIFO packet buffer RAM. reader transfers channel FIFO data from packet buffer downstream Receive Controller block (RMAC672). roamer time-sliced state machine which tracks channel FIFO buffer depths signals reader service particular channel. buffer over-run occurs, writer ends current packet from HDLC processor channel FIFO with over-run flag ignores rest packet.
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Figure Partial Packet Buffer Structure
Partial Packet Buffer
Block Block Block Block bytes bytes bytes bytes Block Block Block Block
Block Pointer
0x03 0xC8
Block
bytes
Block
0x01
Block 2047
bytes
Block 2047
FIFO algorithm partial packet buffer processor based programmable per-channel transfer size. Instead tracking number full blocks channel FIFO, processor tracks number transactions. Whenever partial packet writer fills transfer-sized number blocks writes end-of-packet flag channel FIFO, transaction created. Whenever partial packet reader transmits transfer-size number blocks end-of-packet flag RMAC672 block, transaction deleted. Thus, small packets less than transfer size will naturally transferred RMAC672 block without having precisely track number full blocks channel FIFO. partial packet roamer performs transaction accounting channel FIFOs. roamer increments transaction count when writer signals transaction sets per-channel flag indicate non-zero transaction count. roamer searches flags round-robin fashion decide which channel FIFO request transfer RMAC672 block. roamer informs partial packet reader channel process. reader transfers data RMAC672 until channel transfer size reached
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packet detected. reader then informs roamer that transaction consumed. roamer updates transaction count clears non-zero transaction count flag required. roamer then services next channel with transaction flag high. writer reader determine empty full FIFO conditions using flags. Each block partial packet buffer associated flag. writer sets flag after block written reader clears flag after block read. flags initialized (cleared) when block pointers written using indirect block writes. writer declares channel FIFO overrun whenever writer tries store data block with flag. order support optional removal from packet data, writer does declare block filled (set block flag increment transaction count) until first double word next block channel FIFO filled. packet resides first double word, writer declares both blocks full same time. When reader finishes processing transaction, examines first double word next block end-of-packet flag. first double word next block contains only bytes, reader would, optionally, process next transaction (end-of-packet) consume block, contains information transferred RMAC672 block.
Receive Controller
Receive Controller block (RMAC672) controller which stores received packet data host computer memory. RMAC672 directly connected host memory bus. Memory accesses serviced downstream controller block (GPIC). RMAC672 host exchange information using receive packet descriptors (RPDs). descriptor contains size location buffers host memory packet status information associated with data each buffer. RPDs transferred from RMAC672 host vice versa using descriptor reference queues. RMAC672 maintains pointers operation queues. RMAC672 provides receive packet descriptor reference (RPDR) free queues support small large buffers. RMAC672 acquires free buffers reading RPDRs from free queues. After packet received, RMAC672 places associated RPDR onto RPDR ready queue. minimize host accesses, RMAC672 maintains descriptor reference table store current information. This table contains separate information entries receive channels.
9.5.1 Data Structures
packet data, RMAC672 communicates with host using Receive Packet Descriptors (RPD), Receive Packet Descriptor References (RPDR),
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Receive Packet Descriptor Reference Ready (RPDRR) queue Receive Packet Descriptor Reference Small Large Buffer Free (RPDRF) queues. RMAC672 copies packet data data buffers host memory. RPD, RPDR, RPDRR queue, Small Large RPDRF queues data structures which used transfer host memory data buffer information. five data structures manipulated both RMAC672 host computer. holds data buffer size, data buffer address, packet status information. RPDR pointer which used index into table RPDs. RPDRR queue RPDRF queues allow RMAC672 host pass RPDRs back forth. These data structures described more detail following sections.
Receive Packet Descriptor
Receive Packet Descriptors (RPDs) pass buffer packet information between RMAC672 host. Both RMAC672 host read write information RPDs. host writes fields which describe size address data buffers host memory. RMAC672 writes fields which provide number bytes used each data buffer, link information, status received packet. RPDs stored host memory Receive Packet Descriptor Table which described later section. Receive Packet Descriptor structure shown Figure
Figure Receive Packet Descriptor
Data Start Address Bytes Buffer [15:0] Reserved RCC[9:0] Reserved (16) Status [5:0] Offset[1:0] Reserved
Next Pointer [14:0] Receive Buff Size
Table Receive Packet Descriptor Fields Field Data Buffer Start Address[31:0] Description Data Buffer Start Address[31:0] bits point data buffer host memory. This field expected configured Host during initialisation.
Data Buffer Start Address field valid RPDs.
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Field
Description Chain (CE) indicates linked list RPDs. When logic one, current last linked list RPDs. When logic zero, current last linked list.
valid RPDs written RMAC672 Receive Ready Queue. When packet requires only RPD, logic one. ignored RPDs read RMAC672 from Receive Free Queues, each which assumed point only buffer, i.e. chain.
Offset[1:0]
Offset[1:0] bits indicate byte offset data packet from start buffer. this value nonzero, there will `dummy' (i.e. undefined) bytes start data buffer prior packet data proper. linked list RPDs, only first RPD's Offset field valid. other Offset fields linked list
Status [5:0]
Status[5:0] bits indicate status received packet. Status[0] Status[1] Status[2] Status[3] Status[4] Status[5] buffer overrun Packet exceeds max. allowed size error Packet Length exact bytes HDLC abort detected Unused (set
linked list RPDs, only last RPD's Status field valid. other Status fields linked list invalid should ignored. When packet requires only RPD, Status field valid. Bytes Buffer [15:0] Bytes Buffer[15:0] bits indicate number bytes actually used current RPD's data buffer store packet data. count excludes 'dummy' bytes inserted result non-zero Offset field. count greater than 32767 bytes indicates packet that shorter than expected length field. Bytes Buffer field invalid when Status[0] Status[4] asserted
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Field Next Pointer [14:0]
Description Next Pointer[14:0] bits store RPDR which enables RMAC672 support linked lists RPDs. This field, which only valid when equal logic zero, contains RPDR next linked list. RMAC672 links RPDs when more than buffer needed store packet.
Next Pointer valid last linked list (when CE=1). When packet requires only RPD, Next Pointer field valid.
RCC[9:0]
Receive Channel Code (RCC[9:0]) bits used RMAC672 associate with channel. linked list RPDs, RPDs' RCC[9:0] fields valid. i.e. contain same channel value.
Receive Buffer Size Receive Buffer Size[15:0] bits indicate size [15:0] bytes current RPD's data buffer. This field expected configured Host during initialisation. Receive Buffer Size must non-zero integer multiple sixteen less than equal 32752. Receive Buffer Size field valid RPDs. Receive Buffer Size Data Buffer Start Address fields written only host. RMAC672 reads these fields determine where store packet data. other fields written only RMAC672.
Receive Packet Descriptor Table
Receive Packet Descriptor Table resides host memory stores RPDs. Table contain maximum 32768 RPDs. base table user programmable using Packet Descriptor Table Base (RPDTB) register. table indexed Receive Packet Descriptor Reference (RPDR) which 15-bit pointer defining offset from table base. Thus, shown following diagram, located adding RPDR Packet Descriptor Table Base register.
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Figure Receive Packet Descriptor Table
RPDTB[31:4] Packet Descriptor Table Base register RPDR[14:0] Receive Packet Descriptor Reference RPD_ADDR[31:0] Receive Packet Descriptor Address
RPDTB[31:4]
0000
RPDR[14:0]
0000
RPD_ADDR[31:0]
RPDTB RPD_ADDR
Dword Dword Dword Dword Dword Dword
Dword 32768 Dword
Receive Packet Descriptor Table resides host memory. Packet Descriptor Table Base register resides RMAC672; this register initialised host. RPDRs reside host memory accessed using receive packet queues which described next section.
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Receive Packet Queues
Receive Packet Queues used transfer RPDRs between host RMAC672. There three queues: RPDR Large Buffer Free Queue (RPDRLFQ), RPDR Small Buffer Free Queue (RPDRSFQ) RPDR Ready Queue (RPDRRQ). free queues contain RPDRs referencing RPDs that define free buffers. ready queue contains RPDRs referencing RPDs that define buffers ready host processing. RMAC672 pulls RPDRs from free queues when needs free data buffers. RMAC672 places RPDR onto ready queue after filled buffers with data from each complete packet. host removes RPDRs from ready queue process data buffers. host places RPDRs back onto free queues after finishes reading data from buffers. When starting process packet, RMAC672 uses small buffer store first buffer packet data. packet data requires more than buffer, RMAC672 uses large buffer RPDs store remainder packet. RMAC672 links together RPDs required store packet returns RPDR associated with first onto ready queue. receive packet queues reside host memory defined Queue Base (RQB) register index registers which reside RMAC672. Queue Base base address receive packet queues. Each packet queue four index registers which define start queue read write locations queue. Each index register bits length defines offset from Queue Base. Thus, shown Figure host address RPDR calculated adding index register Queue Base register. host initializes Queue Base register index registers. When entity (either RMAC672 host) removes elements from queue, entity updates read pointer that queue. When entity (either RMAC672 host) places elements onto queue, entity updates write pointer that queue. read index each queue points last valid RPDR read while write index points where next RPDR written. start index points first valid location within queue; RPDR written this location. However, index points location that beyond queue; RPDR written this location. Note however, start index queue index another queue. queue empty when read index less than write index; queue also empty read index less than index write index equals start index. queue full when read index equal write index. Figure shows RPDR reference queues.
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Figure RPDRF RPDRR Queues
Receive Packet Descriptor (RPD) Reference Queues Base Address:
RQB[3 1:2] ueue Base register
Index Registers:
Large Buffer Free ueue: RPDRLFQS[15:0] RPDR arge Free Queue Start register RPDRLFQW [15:0] Large Queue rite regis RPDRLFQ R[15:0 Large Free Queu Read register RPDRLFQE [15:0] Large register Ready ueue: RPDRRQS[15:0] RPDR eady ueue Start register RPDRRQ [15:0] RPDR Ready ueue rite register RPDRRQ R[15:0] eady ueue Read register RPDRRQ E[15:0 RPDR Ready Queue register ffer Free Queue: RPDRSFQS[15:0] RPDR Queue Start register RPDRSFQW [15:0] Free Queue rite register RPDRSFQ R[15:0] Free Queue Read register RPDRSFQE [15:0] RPDR Free Queue register
Base Address Index Register -Host Address
RQB[31:2] Index[1 AD[31:0]
Packet Descriptor Reference Queue
RPDRRQS RPDRRQR Status Status Status
Host
RPDRRQW
Status Status Status
RPDRRQE RPDRLF RPDRLF RPDR RPDR RPDR eference Queues 256KB
RPDRLF
RPDR RPDR RPDR
RPDRLFQE RPDRSFQS RPDRSFQR
RPDR RPDR RPDR
Valid RPDRSFQW RPDR RPDR RPDRSFQE RPDR
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PM7380 FREEDM-32P672
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Note that maximum value which pointer FFFF hex, resulting maximum offset from queue base address (4*(FFFF-1)) 3FFF8 hex. pointer must attempt include offset 3FFFC queue. shown Figure ready queue elements have status field well RPDR field. RMAC672 fills status field mark whether packet successfully received not. host reads status field. ready queue element shown Table below along with definition status bits. RMAC672 requires buffer particular size (i.e. small large) RPDR available corresponding free queue, RPDR from other free queue substituted. host may, therefore, force RMAC672 store received data buffers only size setting free queues zero length, i.e. setting start index registers queues equal values. RMAC672 requires buffer neither free queue contains RPDRs, RPQ_ERRI interrupt generated.
Table RPDRR Queue Element
STATUS[1:0] RPDR[14:0]
Field
STATUS[1:0]
Description
encoding status field follows: Successful reception packet. Unsuccessful reception packet. Unprovisioned partial packet. Partial packet returned RAWMAX limit being reached.
RPDR[14:0]
RPDR[14:0] field defines offset first linked chain RPDs, each pointing buffer containing received data.
described previously, RMAC672 links RPDs together more than buffer needed packet. RMAC672 links additional buffer RPDs chain required until entire packet copied host memory (provided that host disabled both small large free queues setting them length zero). After storing packet data, RMAC672 places STATUS+RPDR first onto ready queue. Only RPDR associated with first placed onto ready queue. other required RPDs linked first shown Figure
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Although STATUS+RPDR only totals bits, each queue entry dword, i.e. bits. When RMAC672 block writes STATUS+RPDR ready queue, sets remaining bits third byte zero fourth byte unmodified.
Figure RPDRR Queue Operation
Packet Descriptor Reference Ready Queue
DRRQ _START _ADDR RPDR AD_ADDR bytes
RPDR RPDR
buffer -packet
RPDRRQ_W RITE_ADDR
RPDR
bytes
buffer -packet
bytes
buffer -start packet
bytes buffer iddle packet bytes buffer -end packet
DRRQ D_ADDR
Receive Channel Descriptor Reference Table
per-channel basis, RMAC672 caches information such current information Receive Channel Descriptor Reference (RCDR) Table. RMAC672 process channels stores three dwords information channel. This information cached internally order
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decrease number host accesses required process each data packet. structure RCDR table shown Figure
Figure Receive Channel Descriptor Reference Table
Bytes Avail. Buffer[14:0] RBC[1:0] Buffer Size[14:0]
Pointer[14:0] Start Pointer[14:0] Pointer[14:0] Start Pointer[14:0]
Current Address[31:0] Bytes Avail. Buffer[14:0] RBC[1:0] Buffer Size[14:0]
Current Address[31:0]
Bytes Avail. Buffer[14:0] RBC[1:0] Buffer Size[14:0]
Pointer[14:0] Start Pointer[14:0]
Current Address[31:0]
Table Receive Channel Descriptor Reference Table Fields Field
Bytes Available Buffer[15:0]
Description
This field used keep track number bytes available current data buffer. RMAC672 initialises Bytes Available Buffer Receive Buffer Size minus offset head buffer. field decremented each time byte written into buffer. This field used keep track number buffers used when storing `raw' (i.e. packet delimited) data. RMAC672 initialises field value RAWMAX[1:0] field RMAC Control Register. field decremented each time buffer filled with data. field reaches zero, chain RPDs placed ready queue chain started. This field contains pointer current RPD.
RBC[1:0]
Pointer[14:0]
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Field
Buffer Size[14:0]
Description
This field contains size bytes buffer currently being written This (Valid) indicates whether packet currently being received channel. When other fields RCDR table entry channel contain valid information. This field contains pointer first packet being received. Current Address [31:0] bits holds host address next dword current buffer. RMAC672 increments this field each access buffer.
Start Pointer[14:0] Current Address[31:0]
9.5.2 Transaction Controller
Transaction Controller coordinates reception data packets from Receive Packet Interface their subsequent storage host memory. packet received over number separate transactions, interleaved with transactions belonging other channels. well sending received data host memory, Transaction Controller initiates data transactions purposes maintaining data structures (queues, descriptors, etc.) host memory.
9.5.3 Write Data Pipeline/Mux
Write Data Pipeline/Mux performs functions. First, pipelines receive data between RHDL672 block GPIC block, inserting enough delay enable Transaction Controller generate appropriate control signals GPIC interface. Second, provides multiplexor data lines GPIC interface, allowing Transaction Controller output data relating transactions controller itself initiates.
9.5.4 Descriptor Information Cache
Descriptor Information Cache provides storage Receive Channel Descriptor Reference (RCDR) Table described above (Figure
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9.5.5 Free Queue Cache
Free Queue Cache block implements element RPDR Small Buffer Free Queue cache element RPDR Large Buffer Free Queue cache. These caches used store free small buffer large buffer RPDRs. Caching RPDRs reduces number host accesses that RMAC672 makes. Each cache managed independently. elements cache consumed time they needed RMAC672. RPDR small buffer cache reloaded when empty RMAC672 requires small buffer RPDR. large buffer RPDR cache reloaded when empty RMAC672 requires large buffer RPDR. When reloading either caches, appropriate cache controller will read elements. cache controller read fewer than elements there fewer than elements available, read pointer index within elements free queue. read pointer near free queue, cache controller reads only queue does start reading from queue until next time reload required. would require host memory transactions would benefit.
Controller
General-Purpose Peripheral Component Interconnect Controller block (GPIC) provides 32-bit Master Target interface core which contains required control functions full Peripheral Component Interconnect (PCI) Revision compliance. Communications between other FREEDM-32P672 blocks made through either internal asynchronous16-bit through synchronous FIFO interfaces. FIFO interfaces dedicated servicing Receive Controller block (RMAC672) other Transmit Controller block (TMAC672). GPIC supports 32-bit operating bridges between timing domain controllers (SYSCLK) timing domain (PCICLK). GPIC backwards compatible will operate when connected bus. itself, GPIC does generate accesses. transactions initiated another master core device. GPIC transforms each access from intended target initiator core device. Except configuration space registers parity generating/checking, GPIC performs operations data. GPIC made four sections: master state machine, target state machine, internal microprocessor interface error/bus controller.
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target master blocks operate independent each other. error/bus control block monitors control signals from target master blocks determine state pads. This block also generates and/or checks parity data going coming from bus. internal microprocessor interface block contains configuration status registers together with production test logic GPIC block.
9.6.1 Master Machine
GPIC master machine translates requests from RMAC672 TMAC672 block interfaces into transactions. GPIC initiates four types cycles: memory read (burst single), memory read multiple, memory read line memory write (burst single). number data transfers cycle controlled controllers. maximum burst size determined particular data path. read cycle RMAC672 restricted maximum burst size dwords write cycle limited maximum TMAC672 interface limit dwords read cycle write cycle. response controller requesting cycle, GPIC must arbitrate control bus. event that RMAC672 TMAC672 request service simultaneously, GPIC66 processes RMAC672 operation first. When external arbitrator issues Grant response Request from GPIC, master state machine monitors insure that previous master completed transaction released before beginning cycle. Once GPIC control bus, will assert FRAME signal drive with address command. value address provided selected controller. After initial data transfer, GPIC tracks address remaining transfers burst internally case GPIC disconnected target must retry transaction. target GPIC master burst cycle option stopping disconnecting burst point. event target disconnect GPIC will terminate present cycle release bus. GPIC asserting REQUEST line time disconnect, will remove REQUEST clock cycles then reassert When arbitrator returns GRANT, GPIC will restart burst access next address continue until burst completed repeat sequence target disconnects again. During burst reads, GPIC accepts data without inserting wait states. Data written directly into read FIFO where RMAC672 TMAC672
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remove rate. During burst writes, GPIC will output data without inserting wait states, terminate transaction early local master fails fill write FIFO with data before GPIC requires write transaction terminated early data starvation, GPIC will automatically initiate further transaction write remaining data when becomes available.) Normally, GPIC will begin requesting write transaction shortly after data starts loaded into write FIFO RMAC672 TMAC672. RMAC672, however, required supply transaction length when writing packet data addition, insert pauses during transfer. case packet data writes RMAC672, GPIC will hold requesting until write FIFO filled with number dwords equal programmable threshold. FIFO empties without reaching transition, GPIC will terminate current transaction restart transaction transfer remaining data when RMAC672 signals transaction. Beginning transaction before data write FIFO allows GPIC reduce impact latency core device. Each master cycle generated GPIC terminated three ways: Completion, Timeout Master Abort. normal mode operation GPIC terminate after transferring data from master FIFO selected. noted above this involve multiple accesses because inability target accept full burst data starvation during writes. After completion burst transfer GPIC will release unless another FIFO requesting service, which case GRANT asserted GPIC will insert idle cycle then start transfer. maximum duration master burst cycle controlled value LATENCY TIMER register GPIC Configuration Register block. This value host boot loaded into counter GPIC master state start each access. counter reaches zero GRANT signal been removed GPIC will release regardless whether completed present burst cycle. This type termination referred Master Time-out. case Master Time-out GPIC will remove REQUEST signal clocks then reassert complete burst cycle. target responds address placed GPIC after clocks GPIC will terminate cycle flag cycle Command/ Status Configuration Register Master Abort. Stop Error enable (SOE_E) GPIC Command Register, GPIC will process more requests until error condition cleared. SOE_E set, GPIC will discard REQUEST indicate local master that cycle
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complete. This action will result write data being lost read data being erroneous.
9.6.2 Master Local Interface
master local data which connects local master device GPIC. GPIC contains local master interface blocks, with supporting RMAC672 other TMAC672. Each local master interface been optimised support traffic pattern generated RMAC672 TMAC672 interchangeable. data path between GPIC local master device provides mechanism segregate system timing domain core from bus. Transfers each RMAC672 TMAC672 interfaces timed system clock. controllers isolated from aspects protocol, instead "sees" simple synchronous protocol. Read write cycles local master will initiate request service GPIC which will then transfer data bus. GPIC maximises data throughput between local device paralleling local data transfers with access latency. GPIC allows either controller write data independent each other independent control. GPIC temporarily buffers data from each controller while arbitrating control bus. After completion write transfer, controller then released perform other tasks. GPIC buffer only single transaction from each controller. Read accesses local optimised allowing controllers access data from soon first data becomes available. After initial synchronisation latency data transferred slower rate core logic SYSCLK rate. Once read transaction started, controller held waiting ready signal while GPIC arbitrating bus. data passed between GPIC controllers little Endian format and, default mode operation, GPIC expects data also little Endian format. GPIC provides selection internal Control register which allows Endian format data changed. enabled, GPIC will swizzle packet data (but descriptor references contents descriptors). swizzling performed according "byte address invariance" rule, i.e. only change data mirror-imaging byte lanes. interface RMAC672 provides byte addressability write transactions whereas interface TMAC672 provides byte
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addressability read transactions. Other transactions must dword aligned. byte-addressable transactions, data transferred between local device GPIC need dword aligned with data presented bus. GPIC will perform byte-realignment required. order complete transfer involving byte re-alignment, GPIC need extra burst cycle transaction.
9.6.3 Target Machine
GPIC target machine performs required functions stand alone target device. target block performs three main functions. first target state machine which controls protocol target accesses GPIC. second function provide Configuration registers. Last, target block provides Target Interface registers other FREEDM-32P672 blocks. GPIC tracks decodes addresses commands placed determine whether respond access. GPIC responds following types commands only: Configuration read write, memory read write, memory-read-multiple memory-read-line which aliased memory read memory-write-and-invalidate which aliased memory write. GPIC will ignore access that falls within address range other command type. After accepting target access medium speed device, FREEDM32P672 inserts wait state configuration read/write five wait states other command types before completing transaction asserting TRDYB. Burst accesses GPIC accepted provided they linear type. master makes memory access GPIC with lower address bits value "00" (linear burst type) GPIC ignores cycle. Burst accesses length accepted, FREEDM-32P672 will disconnect master inserts wait states during transaction. FREEDM-32P672 will also disconnect every read write access configuration space after transferring Dword data. Figure illustrates GPIC address space.
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Figure GPIC Address
ADDRESS
Registers Base Address
Registers
GPIC responds with medium timing master accesses. (i.e. DEVSELB asserted PCICLK cycles after FRAMEB asserted). GPIC inserts five wait states reads internal register space (six wait states subsequent dwords burst read). target machine will only terminate access with Retry target locked another master tries access GPIC. GPIC will terminate access non-burst area with Disconnect always with data transferred. target does support delayed transactions. GPIC will perform Target-Abort termination only case address parity error address that GPIC claims.
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9.6.4 Interface
interface provides access address space FREEDM-32P672 blocks. address space associated Configuration registers. Write transfers space always write bits provided that least byte enable asserted. write command with byte enables negated will ignored. Read transfers always return bits regardless status byte enables, long least byte enable asserted. read command with byte enables negated will ignored.
9.6.5 Error Control
Error/Bus Control block monitors signals from both Target block Master Block determine direction pads generate check parity. After reset, GPIC sets bi-directional pads inputs monitors accesses. Error/Bus control unit remains this state unless either Master requests Target responds Master Access. Error/Bus control unit decodes state each state machine determine direction each signal. devices required check generate even parity across AD[31:0] C/BEB[3:0] signals. GPIC generates parity Master address write data phases; target generates parity read data phases. GPIC required check parity phases even participating cycle. But, GPIC will report parity errors only GPIC involved cycle GPIC detects address parity error data parity detected special cycle. GPIC updates Configuration Status register detected error conditions.
Transmit Controller
Transmit Controller block (TMAC672) controller which retrieves packet data from host computer memory transmission. minimum packet data length bytes. TMAC672 communicates with host computer through master interface connected Controller block (GPIC) which translates host specific signals from host master interface format. TMAC672 uses master interface whenever wishes initiate host read write; this case, TMAC672 initiator host memory target. TMAC672 host exchange information using transmit descriptors (TDs). descriptor contains size location buffers host memory
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packet status information associated with data each buffer. transferred from TMAC672 host vice versa using descriptor reference queues. TMAC672 maintains pointers operation queues. TMAC672 acquires buffers with data ready transmission reading TDRs from ready queue. After packet been transmitted, TMAC672 places associated onto free queue. minimise host accesses, TMAC672 maintains descriptor reference table store current information. This table contains separate information entries transmit channels. TMAC672 also performs per-channel sorting packets received ready queue eliminate head-of-line blocking.
9.7.1 Data Structures
TMAC672 communicates with host using Transmit Descriptors (TD), Transmit Descriptor References (TDR), Transmit Data Reference Ready (TDRR) queue Transmit Data Reference Free (TDRF) queue. TMAC672 reads packet data from data buffers host memory. TDR, TDRR queue, TDRF queue data structures which used transfer host memory data buffer information. four data structures manipulated both TMAC672 host computer. holds data buffer size, data buffer address, other packet information. pointer which used index into table TDs. TDRR queue TDRF queue allow TMAC672 host pass TDRs back forth. These data structures described more detail following sections.
Transmit Descriptor
Transmit Descriptors (TDs) pass buffer packet information between TMAC672 host. Both TMAC672 host read write information TDs. stored host memory Transmit Descriptor Table. Transmit Descriptor structure shown Figure
Figure Transmit Descriptor
Data Start Address [31:0] Bytes Buffer [15:0] Next ointer[14:0] Reserved (16) TCC[9:0]
Next ointer[14 Transm Size[15:0]
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Table Transmit Descriptor Fields Field
Data Buffer Start Address [31:0] Bytes Buffer [15:0]
Description
Data Buffer Start Address[31:0] bits point data buffer host memory. Data Buffer Start Address field valid Bytes Buffer[15:0] field used host indicate total number bytes transmitted current Zero length buffers illegal. Priority host indicate priority associated packet level quality service scheme. Packets with high queued high priority queue TMAC672. Packets with queued priority queue. Packets priority queue will begin transmission until high priority queue empty. Abort (ABT) used host abort transmission packet. When logic packet will aborted after data buffer been transmitted. logic current must must high. Interrupt Complete (IOC) used host instruct TMAC672 interrupt host when current TD's data buffer been read. When logic TMAC672 asserts IOCI interrupt when data buffer been read. Additionally, Free Queue FIFO will flushed. logic zero, TMAC672 will generate interrupt Free Queue FIFO will operate normally.
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Field
Description
Chain (CE) used host indicate linked list presented TMAC672. linked list contain more packets delineated (see above). When logic current last linked list TDs. When logic current last linked list. When current last linked list, Host Next Pointer[14:0] field valid, otherwise field valid. Note: When logic only valid value logic Note: When presenting (i.e. unpacketised) data transmission, host should code bits single packet chain, i.e. M=1, CE=0 except last chain M=0, CE=1 last chain.
TCC[9:0]
Transmit Channel Code (TCC[9:0]) bits used host associate channel with pointed TDR. TCC[9:0] fields linked list must same value.
used indicate that TMAC Next Pointer field valid. When logic TMAC Next Pointer[14:0] field valid. When logic TMAC Next Pointer[14:0] field invalid. used host reclaim data buffers event that data presented TMAC672 returned host channel becoming unprovisioned. expected initialised logic host.
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Field
TMAC Next Pointer [14:0]
Description
TMAC Next Pointer[14:0] bits used store TDRs which permits TMAC672 create linked lists passed TDRR queue. linked with other belonging same channel same priority level. case that data presented TMAC672 returned host channel becoming unprovisioned, pointing start per-channel linked list placed TDRF queue. responsibility host follow TMAC672 host links order recover buffers. More used host support packets that require multiple TDs. logic current just several current packet. logic this either describes entire packet single packet case) describes packet multiple packet case). Note: When logic only valid value logic
Host Next Pointer [14:0]
Host Next Pointer[14:0] bits used store TDRs which permits host support linked lists TDs. described above, linked lists terminated setting logic Linked lists used host pass multiple packets multiple packets associated with same channel priority level TMAC672. Transmit Buffer Size[15:0] field used indicate size bytes current TD's data buffer. (N.B. TMAC672 does make this field.)
Transmit Buffer Size [15:0]
Transmit Descriptor Table
Transmit Descriptor Table, which resides host memory, contains Transmit Descriptors referenced TMAC672. access TMAC672 takes from TDRR queue from TCDR table adds times value (because each bytes size) Transmit Descriptor Table Base (TDTB) pointer form actual address host memory. Each must reside Transmit Descriptor Table.
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Transmit Descriptor Table contain maximum 32768 TDs. base Transmit Descriptor Table user programmable using TMAC Descriptor Table Base register. Thus, shown below, each located using Transmit Descriptor Reference (TDR) combined with TMAC Descriptor Table Base register.
Figure Transmit Descriptor Table
TDTB[31:4] Descriptor Table Base register TDR[14:0] Transmit Descriptor Reference TD_ADDR[31:0] Transmit Descriptor Address
TDTB[31:4]
0000
TDR[14:0]
0000
TD_ADDR[31:0]
TDTB TD_ADDR
Dword Dword Dword Dword Dword Dword
Dword 32768 Dword
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Transmit Queues
Pointers transmit descriptors (TDs) containing packet(s) ready transmission passed from host TMAC672 using Transmit Descriptor Reference Ready (TDRR) queue, which resides host memory. Pointers transmit descriptor structures whose buffers have been read TMAC672 passed from TMAC672 host using Transmit Descriptor Reference Free (TDRF) queue, which also resides host memory. TMAC672 contains Free Queue cache which store TDRs. caching enabled, free TDRs written into TDRF queue time, reduce number host memory accesses. Free Queue cache flushed TDRF queue Interrupt Completion (IOC) which sends corresponding directly TDRF queue. Free Queue cache also flushed TDRF queue FQFLUSH register high. FQFLU
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