PM7364 FREEDM-32 FRAME ENGINE DATA LINK MANAGER PM7364
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
PM7364
FREEDMTM-32
FRAME ENGINE DATALINK MANAGER
DATA SHEET
ISSUE AUGUST 2001
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMER'S INTERNAL
RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
PUBLIC REVISION HISTORY Issue Issue Date August 2001 1998 April 1998 October 1997 April 1997 Details Change Patent information added legal footer. Document re-issue. Document re-issue. Document re-formatted. Diagram page replaced. entries added table diagram. Added Timing section mechanical package information. July 1996 Creation Data Sheet
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMER'S INTERNAL
RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
CONTENTS FEATURES.1 APPLICATIONS.3 REFERENCES APPLICATION EXAMPLES BLOCK DIAGRAM.6 DESCRIPTION DIAGRAM DESCRIPTION FUNCTIONAL DESCRIPTION HIGH-LEVEL DATA LINK CONTROL PROTOCOL.31 RECEIVE CHANNEL ASSIGNER 9.2.1 9.2.2 9.2.3 9.2.4 LINE INTERFACE.33 PRIORITY ENCODER CHANNEL ASSIGNER LOOPBACK CONTROLLER
RECEIVE HDLC PROCESSOR PARTIAL PACKET BUFFER.34 9.3.1 9.3.2 HDLC PROCESSOR PARTIAL PACKET BUFFER PROCESSOR
RECEIVE CONTROLLER 9.4.1 9.4.2 9.4.3 DATA STRUCTURES TRANSACTION CONTROLLER.47 WRITE DATA PIPELINE/MUX
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMER'S INTERNAL
RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
9.4.4 9.4.5
DESCRIPTOR INFORMATION CACHE FREE QUEUE CACHE
CONTROLLER.48 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 MASTER MACHINE MASTER LOCAL INTERFACE.51 TARGET MACHINE INTERFACE ERROR CONTROL
TRANSMIT CONTROLLER.54 9.6.1 9.6.2 9.6.3 9.6.4 9.6.5 9.6.6 DATA STRUCTURES TASK PRIORITIES TRANSACTION CONTROLLER.67 READ DATA PIPELINE.67 DESCRIPTOR INFORMATION CACHE FREE QUEUE CACHE
TRANSMIT HDLC CONTROLLER PARTIAL PACKET BUFFER68 9.7.1 9.7.2 TRANSMIT HDLC PROCESSOR.68 TRANSMIT PARTIAL PACKET BUFFER PROCESSOR69
TRANSMIT CHANNEL ASSIGNER 9.8.1 9.8.2 9.8.3 LINE INTERFACE.72 PRIORITY ENCODER CHANNEL ASSIGNER
9.10
PERFORMANCE MONITOR JTAG TEST ACCESS PORT INTERFACE.73
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMER'S INTERNAL
RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
9.11
HOST INTERFACE
NORMAL MODE REGISTER DESCRIPTION 10.1 HOST ACCESSIBLE REGISTERS
CONFIGURATION REGISTER DESCRIPTION .251 11.1 CONFIGURATION REGISTERS.251
TEST FEATURES DESCRIPTION .262 12.1 12.2 TEST MODE REGISTERS .262 JTAG TEST PORT .263 12.2.1 12.2.2 IDENTIFICATION REGISTER .264 BOUNDARY SCAN REGISTER .264
OPERATIONS .278 13.1 13.2 13.3 EQUAD CONNECTIONS.278 TOCTL CONNECTIONS .278 JTAG SUPPORT.279
FUNCTIONAL TIMING .285 14.1 14.2 14.3 14.4 RECEIVE LINK INPUT TIMING .285 TRANSMIT LINK OUTPUT TIMING.286 INTERFACE .288 BERT INTERFACE .297
ABSOLUTE MAXIMUM RATINGS.299 D.C. CHARACTERISTICS.300 FREEDM-32 TIMING CHARACTERISTICS .302 ORDERING THERMAL INFORMATION .308 MECHANICAL INFORMATION.309
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMER'S INTERNAL
RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
LIST REGISTERS REGISTER 0X000 FREEDM-32 MASTER RESET.80 REGISTER 0X004 FREEDM-32 MASTER INTERRUPT ENABLE REGISTER 0X008 FREEDM-32 MASTER INTERRUPT STATUS REGISTER 0X00C FREEDM-32 MASTER CLOCK BERT ACTIVITY MONITOR ACCUMULATION TRIGGER REGISTER 0X010 FREEDM-32 MASTER LINK ACTIVITY MONITOR.93 REGISTER 0X014 FREEDM-32 MASTER LINE LOOPBACK #1.97 REGISTER 0X018 FREEDM-32 MASTER LINE LOOPBACK #2.99 REGISTER 0X020 FREEDM-32 MASTER BERT CONTROL.101 REGISTER 0X024 FREEDM-32 MASTER PERFORMANCE MONITOR CONTROL .103 REGISTER 0X040 GPIC CONTROL .107 REGISTER 0X100 RCAS INDIRECT LINK TIME-SLOT SELECT. REGISTER 0X104 RCAS INDIRECT CHANNEL DATA REGISTER 0X108 RCAS FRAMING THRESHOLD. REGISTER 0X10C RCAS CHANNEL DISABLE REGISTER 0X180 RCAS LINK CONFIGURATION REGISTER 0X184 0X188 RCAS LINK CONFIGURATION.120 REGISTER 0X18C RCAS LINK CONFIGURATION .122 REGISTER 0X190-0X1FC RCAS LINK LINK CONFIGURATION124 REGISTER 0X200 RHDL INDIRECT CHANNEL SELECT .126 REGISTER 0X204 RHDL INDIRECT CHANNEL DATA REGISTER .128 REGISTER 0X208 RHDL INDIRECT CHANNEL DATA REGISTER .131
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
REGISTER 0X210 RHDL INDIRECT BLOCK SELECT .134 REGISTER 0X214 RHDL INDIRECT BLOCK DATA .136 REGISTER 0X220 RHDL CONFIGURATION .138 REGISTER 0X224 RHDL MAXIMUM PACKET LENGTH .140 REGISTER 0X280 RMAC CONTROL.142 REGISTER 0X284 RMAC INDIRECT CHANNEL PROVISIONING .145 REGISTER 0X288 RMAC PACKET DESCRIPTOR TABLE BASE .147 REGISTER 0X28C RMAC PACKET DESCRIPTOR TABLE BASE MSW.148 REGISTER 0X290 RMAC QUEUE BASE .150 REGISTER 0X294 RMAC QUEUE BASE .151 REGISTER 0X298 RMAC PACKET DESCRIPTOR REFERENCE LARGE BUFFER FREE QUEUE START.153 REGISTER 0X29C RMAC PACKET DESCRIPTOR REFERENCE LARGE BUFFER FREE QUEUE WRITE .155 REGISTER 0X2A0 RMAC PACKET DESCRIPTOR REFERENCE LARGE BUFFER FREE QUEUE READ .157 REGISTER 0X2A4 RMAC PACKET DESCRIPTOR REFERENCE LARGE BUFFER FREE QUEUE END.159 REGISTER 0X2A8 RMAC PACKET DESCRIPTOR REFERENCE SMALL BUFFER FREE QUEUE START.161 REGISTER 0X2AC RMAC PACKET DESCRIPTOR REFERENCE SMALL BUFFER FREE QUEUE WRITE .163 REGISTER 0X2B0 RMAC PACKET DESCRIPTOR REFERENCE SMALL BUFFER FREE QUEUE READ .165 REGISTER 0X2B4 RMAC PACKET DESCRIPTOR REFERENCE SMALL BUFFER FREE QUEUE END.167 REGISTER 0X2B8 RMAC PACKET DESCRIPTOR REFERENCE READY QUEUE START .169
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
REGISTER 0X2BC RMAC PACKET DESCRIPTOR REFERENCE READY QUEUE WRITE .171 REGISTER 0X2C0 RMAC PACKET DESCRIPTOR REFERENCE READY QUEUE READ .173 REGISTER 0X2C4 RMAC PACKET DESCRIPTOR REFERENCE READY QUEUE .175 REGISTER 0X300 TMAC CONTROL .177 REGISTER 0X304 TMAC INDIRECT CHANNEL PROVISIONING.180 REGISTER 0X308 TMAC DESCRIPTOR TABLE BASE LSW.182 REGISTER 0X30C TMAC DESCRIPTOR TABLE BASE .183 REGISTER 0X310 TMAC QUEUE BASE .185 REGISTER 0X314 TMAC QUEUE BASE .186 REGISTER 0X318 TMAC DESCRIPTOR REFERENCE FREE QUEUE START .188 REGISTER 0X31C TMAC DESCRIPTOR REFERENCE FREE QUEUE WRITE .190 REGISTER 0X320 TMAC DESCRIPTOR REFERENCE FREE QUEUE READ .192 REGISTER 0X324 TMAC DESCRIPTOR REFERENCE FREE QUEUE .194 REGISTER 0X328 :TMAC DESCRIPTOR REFERENCE READY QUEUE START .196 REGISTER 0X32C TMAC DESCRIPTOR REFERENCE READY QUEUE WRITE .198 REGISTER 0X330 TMAC DESCRIPTOR REFERENCE READY QUEUE READ200 REGISTER 0X334 TMAC DESCRIPTOR REFERENCE READY QUEUE .202 REGISTER 0X380 THDL INDIRECT CHANNEL SELECT.204 REGISTER 0X384 THDL INDIRECT CHANNEL DATA .206
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
REGISTER 0X388 THDL INDIRECT CHANNEL DATA .209 REGISTER 0X38C THDL INDIRECT CHANNEL DATA .212 REGISTER 0X3A0 THDL INDIRECT BLOCK SELECT .217 REGISTER 0X3A4 THDL INDIRECT BLOCK DATA .219 REGISTER 0X3B0 THDL CONFIGURATION .221 REGISTER 0X400 TCAS INDIRECT LINK TIME-SLOT SELECT .223 REGISTER 0X404 TCAS INDIRECT CHANNEL DATA .225 REGISTER 0X408 TCAS FRAMING THRESHOLD .227 REGISTER 0X40C TCAS IDLE TIME-SLOT FILL DATA.229 REGISTER 0X410 TCAS CHANNEL DISABLE .231 REGISTER 0X480 TCAS LINK CONFIGURATION .233 REGISTER 0X484-0X488 TCAS LINK LINK CONFIGURATION .235 REGISTER 0X48C TCAS LINK CONFIGURATION .237 REGISTER 0X490-0X4FC TCAS LINK LINK CONFIGURATION239 REGISTER 0X500 PMON STATUS .241 REGISTER 0X504 PMON RECEIVE FIFO OVERFLOW COUNT.243 REGISTER 0X508 PMON RECEIVE FIFO UNDERFLOW COUNT .245 REGISTER 0X50C PMON CONFIGURABLE COUNT #1.247 REGISTER 0X510 PMON CONFIGURABLE COUNT .249 REGISTER 0X00 VENDOR IDENTIFICATION/DEVICE IDENTIFICATION.252 REGISTER 0X04 COMMAND/STATUS .253 REGISTER 0X08 REVISION IDENTIFIER/CLASS CODE.257 REGISTER 0X0C CACHE LINE SIZE/LATENCY TIMER/HEADER TYPE .258 REGISTER 0X10 MEMORY BASE ADDRESS REGISTER.259
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
REGISTER 0X3C INTERRUPT LINE INTERRUPT MIN_GNT MAX_LAT.261
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
LIST FIGURES FIGURE HDLC FRAME.31 FIGURE GENERATOR.32 FIGURE PARTIAL PACKET BUFFER STRUCTURE FIGURE RECEIVE PACKET DESCRIPTOR.38 FIGURE RECEIVE PACKET DESCRIPTOR TABLE.41 FIGURE RPDRF RPDRR QUEUES FIGURE RPDRR QUEUE OPERATION.45 FIGURE RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE.46 FIGURE GPIC ADDRESS FIGURE TRANSMIT DESCRIPTOR FIGURE TRANSMIT DESCRIPTOR TABLE FIGURE TDRR TDRF QUEUES FIGURE TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE FIGURE LINKING.66 FIGURE PARTIAL PACKET BUFFER STRUCTURE FIGURE INPUT OBSERVATION CELL (IN_CELL) .275 FIGURE OUTPUT CELL (OUT_CELL) .276 FIGURE BI-DIRECTIONAL CELL (IO_CELL) .276 FIGURE LAYOUT OUTPUT ENABLE BI-DIRECTIONAL CELLS .277 FIGURE BOUNDARY SCAN ARCHITECTURE .279 FIGURE CONTROLLER FINITE STATE MACHINE .281 FIGURE UNCHANNELISED RECEIVE LINK TIMING .285
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
FIGURE CHANNELISED RECEIVE LINK TIMING .286 FIGURE CHANNELISED RECEIVE LINK TIMING .286 FIGURE UNCHANNELISED TRANSMIT LINK TIMING.287 FIGURE CHANNELISED TRANSMIT LINK TIMING.287 FIGURE CHANNELISED TRANSMIT LINK TIMING .288 FIGURE READ CYCLE .289 FIGURE WRITE CYCLE .291 FIGURE TARGET DISCONNECT .292 FIGURE TARGET ABORT.292 FIGURE REQUEST CYCLE .293 FIGURE INITIATOR ABORT TERMINATION .294 FIGURE EXCLUSIVE LOCK CYCLE .295 FIGURE FAST BACK BACK.297 FIGURE RECEIVE BERT PORT TIMING .297 FIGURE TRANSMIT BERT PORT TIMING .298 FIGURE RECEIVE LINK INPUT TIMING .303 FIGURE BERT INPUT TIMING .303 FIGURE TRANSMIT LINK OUTPUT TIMING.305 FIGURE BERT OUTPUT TIMING .305 FIGURE INTERFACE TIMING .306 FIGURE JTAG PORT INTERFACE TIMING.307 FIGURE ENHANCED BALL GRID ARRAY (SBGA) .309
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
LIST TABLES TABLE LINE SIDE INTERFACE SIGNALS (132) TABLE HOST INTERFACE SIGNALS (51) TABLE MISCELLANEOUS INTERFACE SIGNALS (13).24 TABLE PRODUCTION TEST INTERFACE SIGNALS MULTIPLEXED)26 TABLE POWER GROUND SIGNALS (60) TABLE RECEIVE PACKET DESCRIPTOR FIELDS.38 TABLE RPDRR QUEUE ELEMENT TABLE RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS TABLE TRANSMIT DESCRIPTOR FIELDS TABLE TRANSMIT DESCRIPTOR REFERENCE.62 TABLE TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS TABLE NORMAL MODE HOST ACCESSIBLE REGISTER MEMORY TABLE CONFIGURATION REGISTER MEMORY MAP.78 TABLE ENDIAN FORMAT.108 TABLE LITTLE ENDIAN FORMAT .108 TABLE CRC[1:0] SETTINGS.130 TABLE RPQ_RDYN[2:0] SETTINGS .143 TABLE RPQ_LFN[1:0] SETTINGS.144 TABLE RPQ_SFN[1:0] SETTINGS .144 TABLE TDQ_RDYN[2:0] SETTINGS.178 TABLE TDQ_FRN[1:0] SETTINGS .178
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
TABLE CRC[1:0] SETTINGS.207 TABLE FLAG[2:0] SETTINGS .213 TABLE LEVEL[3:0]/TRANS SETTINGS .215 TABLE TEST MODE REGISTER MEMORY .263 TABLE INSTRUCTION REGISTER .264 TABLE BOUNDARY SCAN CHAIN .265 TABLE FREEDM-EQUAD CONNECTIONS .278 TABLE FREEDM-TOCTAL CONNECTIONS .278 TABLE FREEDM-32 ABSOLUTE MAXIMUM RATINGS .299 TABLE FREEDM-32 D.C. CHARACTERISTICS .300 TABLE FREEDM-32 LINK INPUT (FIGURE FIGURE .302 TABLE FREEDM-32 LINK OUTPUT (FIGURE FIGURE .304 TABLE INTERFACE (FIGURE .305 TABLE JTAG PORT INTERFACE (FIGURE 43).306 TABLE FREEDM-32 ORDERING INFORMATION .308 TABLE FREEDM-32 THERMAL INFORMATION .308
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
FEATURES Single-chip Peripheral Component Interconnect (PCI) multi-channel HDLC controller. Supports bi-directional HDLC channels assigned maximum channelised links. number time-slots assigned HDLC channel programmable from (for from (for E1). Supports bi-directional HDLC channels each assigned unchannelised arbitrary rate link; subject maximum aggregate link clock rate each direction. Channels assigned links have clock rate when SYSCLK above when SYSCLK MHz. Channels assigned links have clock rate MHz. Supports bi-directional HDLC channels each assigned unchannelised arbitrary rate link when SYSCLK above when SYSCLK MHz. Supports channelised unchannelised links; subject constraint maximum channels maximum aggregate link clock rate each direction. each channel, HDLC receiver performs flag sequence detection, de-stuffing, frame check sequence validation. receiver supports validation both CRC-CCITT CRC-32 frame check sequences. receiver also checks packet abort sequences, octet aligned packet length minimum maximum packet length. Alternatively, each channel, receiver supports transparent mode where each octet transferred transparently host memory. channelised links, octets aligned with receive time-slots. each channel, time-slots selectable kbits/s format kbits/s clear channel format. each channel, HDLC transmitter performs flag sequence generation, stuffing, and, optionally, frame check sequence generation. transmitter supports generation both CRC-CCITT CRC-32 frame check sequences. transmitter also aborts packets under direction host automatically when channel underflows.
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
Supports levels non-preemptive packet priority each transmit channel. priority packets will begin transmission until high priority packets transmitted. Alternatively, each channel, transmitter supports transparent mode where each octet inserted transparently from host memory. channelised links, octets aligned with transmit time-slots. Directly supports 32-bit, interface configuration, monitoring transfer packet data, with on-chip controller with scatter/gather capabilities. Provides kbytes on-chip memory partial packet buffering each direction. This memory configured support variety different channel configurations from single channel with kbytes buffering channels, each with minimum bytes buffering. Supports burst sizes bytes transfers packet data. compatible with PM7366 (FREEDM-8) device. Provides standard signal P1149.1 JTAG test port boundary scan board test purposes. Supports Volt signaling environments. power CMOS technology. enhanced ball grid array (SBGA) package mm).
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
APPLICATIONS IETF interfaces routers Frame Relay interfaces Frame Relay switches multiplexors FUNI Frame Relay service inter-working interfaces Aswitches multiplexors. D-channel processing ISDN terminals switches. Internet/Intranet access equipment. Packet-based DSLAM equipment.
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
REFERENCES International Organization Standardization, Standard 3309-1993, "Information Technology Telecommunications information exchange between systems High-level data link control (HDLC) procedures Frame structure", December 1993. RFC-1662 "PPP HDLC-like Framing" Internet Engineering Task Force, July 1994. Special Interest Group, Local Specification, June 1995, Version 2.1.
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
APPLICATION EXAMPLES
ACCESS SIDE HDLC BASED UPLINK SIDE
PM8313 D3MX
PM4388 TOCTL PM7364 FREEDM FREEDM-32 HSSI Module DS3/E3 Framer Microprocessor HDLC Based Uplink Module HSSI
Access Module PM4314 QDSX PM4388 TOCTL
Access Modu PM4314 QDSX PM6344 EQUAD
Packet Memory
DS3/E3/J2
Processor Module
Access Module
ACCESS SIDE
ACELL BASED UPLINK SIDE
PM7345 S/UNI-PDH
T3/E3
PM7364 FREEDM-32
DS-3/E3 ASAR
PM5346 PM5348 S/UNI-LITE S/UNI-DUAL
XDSL xDSL Access Module
PM7322 RCMP
OC-3
STS-3c AUNI Packet Memory Microprocessor
PM5347 S/UNI-PLUS
xDSL
OC-3
STS-3c ANNI
PM5355 S/UNI-622
OC-12
Processor Module
STS-12c AUNI/NNI
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMER'S INTERNAL
RELEASED
DATA SHEET
PMC-1960758
BLOCK DIAGRAM
RBCLK RSTB
RD[31:0]
ISSUE
RCLK[31:0]
Receive Channel Assigner (RCAS) Receive HDLC Processor Partial Packet Buffer (RHDL) Receive Controller (RMAC) Controller (GPIC) Performance Monitor (PMON)
AD[31:0] C/BEB[3:0] FRAMEB TRDYB IRDYB STOPB DEVSELB IDSEL LOCKB
TD[31:0]
TCLK[31:0]
Transmit Channel Assigner (TCAS) Transmit HDLC Processor Partial Packet Buffer (THDL) Transmit Controller (TMAC)
REQB GNTB PERRB SERRB PCIINTB PCICLK PCICLKO SYSCLK JTAG Port
TRSTB
TBCLK
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMER'S INTERNAL
PMCTEST
FRAME ENGINE DATA LINK MANAGER
PM7364 FREEDM-32
RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
DESCRIPTION PM7364 FREEDM-32 Frame Engine Datalink Manager device monolithic integrated circuit that implements HDLC processing, memory management functions maximum bi-directional channels. channelised links, FREEDM-32 allows bi-directional HDLC channels assigned individual time-slots within maximum independently timed links. channel assignment supports concatenation time-slots DS0) maximum concatenated timeslots link concatenated time-slots link. Time-slots assigned particular channel need contiguous within link. unchannelised links, FREEDM-32 processes bi-directional HDLC channels within independently timed links. links arbitrary frame format. When limited unchannelised links, each link rated when SYSCLK when SYSCLK MHz. lower rate unchannelised links, FREEDM-32 processes links, where aggregate clock rate links limited MHz, links have clock rate when SYSCLK above when SYSCLK links have clock rate MHz. FREEDM-32 supports mixing channelised unchannelised links. total number channels each direction limited 128. aggregate clock rate over possible links limited MHz. receive direction, FREEDM-32 performs channel assignment packet extraction validation. each provisioned HDLC channel, FREEDM-32 delineates packet boundaries using flag sequence detection, performs de-stuffing. Sharing opening closing flags, well sharing zeros between flags supported. resulting packet data placed into internal kbyte partial packet buffer RAM. partial packet buffer acts logical FIFO each assigned channels. Partial packets DMA'd RAM, across into host packet memory. FREEDM-32 validates frame check sequence each packet, verifies that packet integral number octets length within programmable minimum maximum length. receive packet status updated before linking packet into receive ready queue. FREEDM-32 alerts Host that there packets receive ready queue optionally, asserting interrupt bus.
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
Alternatively, receive direction, FREEDM-32 supports transparent operating mode. each provisioned transparent channel, FREEDM-32 directly transfers received octets into host memory verbatim. transparent channel assigned channelised link, then octets aligned received time-slots. transmit direction, Host provides packets transmit using transmit ready queue. each provisioned HDLC channel, FREEDM-32 DMA's partial packets across into transmit partial packet buffer. partial packets read packet buffer FREEDM-32 frame check sequence optionally calculated inserted each packet. stuffing performed before being assigned particular link. flag sequence automatically inserted when there packet data particular channel. Sequential packets optionally separated flags opening flag closing flag) single flag (combined opening closing flag). Zeros between flags shared. latency cause more channels underflow, which case, packets aborted, host notified. normal traffic, abort sequence generated, followed inter-frame time fill characters (flags all-ones bytes) until packet sourced from host. attempt made automatically re-transmit aborted packet. Alternatively, transmit direction, FREEDM-32 supports transparent operating mode. each provisioned transparent channel, FREEDM-32 directly inserts transmitted octets from host memory. transparent channel assigned channelised link, then octets aligned transmitted time-slots. channel underflows excessive latency, abort sequence generated, followed inter-frame time fill characters (flags all-ones bytes) indicate idle channel. Data resumes immediately when FREEDM-32 receives data from host. FREEDM-32 configured, controlled monitored using interface. FREEDM-32 implemented power CMOS technology. compatible inputs outputs packaged enhanced ball grid array (SBGA) package.
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RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
DIAGRAM FREEDM-32 manufactured enhanced ball grid array package.
RCLK[8] RCLK[10]
RD[12]
RD[14]
RD[17]
RD[19]
RCLK[21] RCLK[23] RCLK[25]
RD[27]
RD[29]
RD[8]
RD[10]
RCLK[11] RCLK[13] RCLK[15] RCLK[16] RCLK[18]
RD[20]
RCLK[20] RCLK[22]
RD[24]
RD[26]
RCLK[27] RCLK[29]
RD[7]
RD[9]
RD[11]
RCLK[12] RCLK[14]
RD[16]
RD[18]
RCLK[19]
RD[21]
RD[23]
RD[25]
RCLK[26] RCLK[28]
PCICLK
RD[5]
RCLK[5]
RCLK[6]
EN5V
RCLK[7]
RCLK[9]
RD[13]
RD[15]
RCLK[17]
RD[22]
RCLK[24]
RD[28]
PCICLKO VBIAS[2]
GNTB
AD[31]
AD[30]
RD[3]
RCLK[3]
RCLK[4]
RD[6]
REQB
AD[29]
AD[27]
AD[26]
RCLK[1]
RD[2]
RCLK[2]
RD[4]
AD[28]
AD[25]
AD[24]
CBEB[3]
RBCLK
RD[0]
RD[1]
IDSEL
AD[22]
AD[21]
VBIAS[1]
SYSCLK
RCLK[0]
AD[23]
AD[20]
AD[18]
TRSTB
AD[19]
AD[17]
AD[16]
CBEB[2]
BOTTOM VIEW
FRAMEB
IRDYB
TRDYB
DEVSELB
TD[0]
TCLK[0]
TD[1]
TCLK[1]
STOPB
LOCKB
TD[2]
TCLK[2]
TD[3]
TD[4]
CBEB[1]
SERRB
PERRB
TCLK[3]
TCLK[4]
TD[6]
AD[11]
AD[14]
AD[15]
TD[5]
TCLK[5]
TCLK[6]
AD[10]
AD[12]
AD[13]
TD[7]
TCLK[7]
TD[8]
TCLK[9]
AD[5]
CBEB[0]
AD[8]
AD[9]
TCLK[8]
TD[9]
TD[10]
TCLK[11]
AD[1]
AD[4]
AD[6]
AD[7]
TCLK[10]
TD[11]
TD[12]
TD[13]
TD[15]
TCLK[18]
TD[21]
TCLK[25]
TD[28]
TD[30]
PMCTEST RCLK[30] VBIAS[3]
AD[0]
AD[2]
AD[3]
TCLK[12] TCLK[14] TCLK[16]
TD[18]
TD[20]
TD[22]
TCLK[23]
TD[25]
TD[27]
TCLK[28] TCLK[30]
PCIINTB
RD[30]
TCLK[13] TCLK[15]
TD[17]
TD[19]
TCLK[20] TCLK[22]
TD[23]
TCLK[24] TCLK[26] TCLK[27] TCLK[29] TCLK[31]
RSTB
RD[31]
TD[14]
TD[16]
TCLK[17] TCLK[19] TCLK[21]
TD[24]
TD[26]
TD[29]
TD[31]
TBCLK
RCLK[31]
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMER'S INTERNAL
RELEASED DATA SHEET PMC-1960758 ISSUE
PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
DESCRIPTION Table Line Side Interface Signals (132) Name RCLK[0] RCLK[1] RCLK[2] RCLK[3] RCLK[4] RCLK[5] RCLK[6] RCLK[7] RCLK[8] RCLK[9] RCLK[10] RCLK[11] RCLK[12] RCLK[13] RCLK[14] RCLK[15] RCLK[16] RCLK[17] RCLK[18] RCLK[19] RCLK[20] RCLK[21] RCLK[22] RCLK[23] RCLK[24] RCLK[25] RCLK[26] RCLK[27] RCLK[28] RCLK[29] RCLK[30] RCLK[31] Type Input Function receive line clock signals (RCLK[31:0]) contain recovered line clock independently timed links. Processing receive links priority basis, descending order from RCLK[0] RCLK[31]. Therefore, highest rate link should connected RCLK[0] lowest RCLK[31]. RD[31:0] sampled rising edge corresponding RCLK[31:0] clock. channelised links, RCLK[n] must gapped during framing (for interfaces) during time-slot (for interfaces) RD[n] stream. FREEDM-32 uses gapping information determine time-slot alignment receive stream. RCLK[31:0] nominally duty cycle clock 1.544 links 2.048 links. unchannelised links, RCLK[n] must externally gapped during bits timeslots that part transmission format payload (i.e. part HDLC packet). RCLK[2:0] nominally duty cycle clock between MHz. RCLK[31:3] nominally duty cycle clock between MHz.
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FRAME ENGINE DATA LINK MANAGER
Name RD[0] RD[1] RD[2] RD[3] RD[4] RD[5] RD[6] RD[7] RD[8] RD[9] RD[10] RD[11] RD[12] RD[13] RD[14] RD[15] RD[16] RD[17] RD[18] RD[19] RD[20] RD[21] RD[22] RD[23] RD[24] RD[25] RD[26] RD[27] RD[28] RD[29] RD[30] RD[31]
Type Input
Function receive data signals (RD[31:0]) contain recovered line data independently timed links normal mode (PMCTEST low). Processing receive links priority basis, descending order form RD[0] RD[31]. Therefore, highest rate link should connected RD[0] lowest RD[31]. channelised links, RD[n] contains (T1) (E1) time-slots that comprise channelised link. RCLK[n] must gapped during framing position frame alignment signal (time-slot FREEDM-32 uses location determine channel alignment RD[n]. unchannelised links, RD[n] contains HDLC packet data. certain transmission formats, RD[n] contain place holder bits time-slots. RCLK[n] must externally gapped during place holder positions RD[n] stream. FREEDM-32 supports maximum data rate Mbit/s individual RD[31:3] link maximum data rate Mbit/s RD[2:0]. RD[31:0] sampled rising edge corresponding RCLK[31:0] clock.
Tristate Output
receive BERT data signal (RBD) contains receive error rate test data. reports data selected receive data signals (RD[31:0]) updated falling edge RBCLK. tri-stated setting RBEN FREEDM-32 Master BERT Control register low.
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FRAME ENGINE DATA LINK MANAGER
Name RBCLK
Type Tristate Output
Function receive BERT clock signal (RBCLK) contains receive error rate test clock. RBCLK buffered version selected receive clock signals (RCLK[31:0]). RBCLK tri-stated setting RBEN FREEDM-32 Master BERT Control register low. transmit line clock signals (TCLK[31:0]) contain transmit clocks independently timed links. Processing transmit links priority basis, descending order from TCLK[0] TCLK[31]. Therefore, highest rate link should connected TCLK[0] lowest TCLK[31]. TD[31:0] updated falling edge corresponding TCLK[31:0] clock. channelised links, TCLK[n] must gapped during framing (for interfaces) during time-slot (for interfaces) TD[n] stream. FREEDM-32 uses gapping information determine time-slot alignment transmit stream. unchannelised links, TCLK[n] must externally gapped during bits timeslots that part transmission format payload (i.e. part HDLC packet). TCLK[31:3] nominally duty cycle clock between MHz. TCLK[2:0] nominally duty cycle clock between MHz. Typical values TCLK[31:0] include 1.544 (for links) 2.048 (for links).
TCLK[0] TCLK[1] TCLK[2] TCLK[3] TCLK[4] TCLK[5] TCLK[6] TCLK[7] TCLK[8] TCLK[9] TCLK[10] TCLK[11] TCLK[12] TCLK[13] TCLK[14] TCLK[15] TCLK[16] TCLK[17] TCLK[18] TCLK[19] TCLK[20] TCLK[21] TCLK[22] TCLK[23] TCLK[24] TCLK[25] TCLK[26] TCLK[27] TCLK[28] TCLK[29] TCLK[30] TCLK[31]
Input
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PM7364 FREEDM-32
FRAME ENGINE DATA LINK MANAGER
Name TD[0] TD[1] TD[2] TD[3] TD[4] TD[5] TD[6] TD[7] TD[8] TD[9] TD[10] TD[11] TD[12] TD[13] TD[14] TD[15] TD[16] TD[17] TD[18] TD[19] TD[20] TD[21] TD[22] TD[23] TD[24] TD[25] TD[26] TD[27] TD[28] TD[29] TD[30] TD[31]
Type Output
Function transmit data signals (TD[31:0]) contains transmit data independently timed links normal mode (PMCTEST low). Processing transmit links priority basis, descending order from TD[0] TD[31]. Therefore, highest rate link should connected TD[0] lowest TD[31]. channelised links, TD[n] contains (T1) (E1) time-slots that comprise channelised link. TCLK[n] must gapped during framing position frame alignment signal (time-slot FREEDM-32 uses location determine channel alignment TD[n]. unchannelised links, TD[n] contains HDLC packet data. certain transmission formats, TD[n] contain place holder bits time-slots. TCLK[n] must externally gapped during place holder positions TD[n] stream. FREEDM-32 supports maximum data rate Mbit/s individual TD[31:3] link maximum data rate Mbit/s TD[2:0] TD[31:0] updated falling edge corresponding TCLK[31:0] clock.
Input
transmit BERT data signal (TBD) contains transmit error rate test data. When TBERTEN BERT Control register high, data transmitted selected transmit data signals (TD[31:0]). sampled rising edge TBCLK.
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FRAME ENGINE DATA LINK MANAGER
Name TBCLK
Type Tristate Output
Function transmit BERT clock signal (TBCLK) contains transmit error rate test clock. TBCLK buffered version selected transmit clock signals (TCLK[31:0]). TBCLK tri-stated setting TBEN FREEDM-32 Master BERT Control register low.
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FRAME ENGINE DATA LINK MANAGER
Table Host Interface Signals (51) Name PCICLK Type Input Function clock signal (PCICLK) provides timing accesses. PCICLK nominally duty cycle, clock. clock output signal (PCICLKO) buffered version PCICLK. PCICLKO used drive SYSCLK input. address data (AD[31:0]) carries multiplexed address data. During first clock cycle transaction, AD[31:0] contains physical byte address. During subsequent clock cycles transaction, AD[31:0] contains data. transaction defined address phase followed more data phases. When Little-Endian byte formatting selected, AD[31:24] contain most significant byte DWORD while AD[7:0] contain least significant byte. When Big-Endian byte formatting selected. AD[7:0] contain most significant byte DWORD while AD[31:24] contain least significant byte. When FREEDM-32 initiator, AD[31:0] output during first (address) phase transaction. write transactions, AD[31:0] remains output data phases transaction. read transactions, AD[31:0] input during data phases. When FREEDM-32 target, AD[31:0] input during first (address) phase transaction. write transactions, AD[31:0] remains input during data phases transaction. read transactions, AD[31:0] output during data phases. When FREEDM-32 involved current transaction, AD[31:0] tri-stated.
PCICLKO
Output
AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30]
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FRAME ENGINE DATA LINK MANAGER
Name AD[31]
Type
Function output bus, AD[31:0] updated rising edge PCICLK. input bus, AD[31:0] sampled rising edge PCICLK. command byte enable (C/BEB[3:0]) contains command byte valid indications. During first clock cycle transaction, C/BEB[3:0] contains command code. subsequent clock cycles, C/BEB[3:0] identifies which bytes AD[31:0] carry valid data. C/BEB[3] associated with byte (AD[31:24]) while C/BEB[0] associated with byte (AD[7:0]). When C/BEB[n] high, associated byte invalid. When C/BEB[n] low, associated byte valid. When FREEDM-32 initiator, C/BEB[3:0] output bus. When FREEDM-32 target, C/BEB[3:0] input bus. When FREEDM-32 involved current transaction, C/BEB[3:0] tri-stated. output bus, C/BEB[3:0] updated rising edge PCICLK. input bus, C/BEB[3:0] sampled rising edge PCICLK.
C/BEB[0] C/BEB[1] C/BEB[2] C/BEB[3]
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FRAME ENGINE DATA LINK MANAGER
Name
Type
Function parity signal (PAR) indicates parity AD[31:0] C/BEB[3:0] buses. Even parity calculated over signals buses regardless whether bytes AD[31:0] valid. always reports parity previous PCICLK cycle. Parity errors detected FREEDM-32 indicated output PERRB FREEDM-32 Interrupt Status register. When FREEDM-32 initiator, output writes input reads. When FREEDM-32 target, input writes output reads. When FREEDM-32 involved current transaction, tri-stated. output signal, updated rising edge PCICLK. input signal, sampled rising edge PCICLK.
FRAMEB
active cycle frame signal (FRAMEB) identifies transaction cycle. When FRAMEB transitions low, start transaction indicated. FRAMEB remains define duration cycle. When FRAMEB transitions high, last data phase current transaction indicated. When FREEDM-32 initiator, FRAMEB output. When FREEDM-32 target, FRAMEB input. When FREEDM-32 involved current transaction, FRAMEB tri-stated. output signal, FRAMEB updated rising edge PCICLK. input signal, FRAMEB sampled rising edge PCICLK.
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Name TRDYB
Type
Function active target ready signal (TRDYB) indicates when target ready start continue with transaction. TRDYB works conjunction with IRDYB complete transaction data phases. During transaction progress, TRDYB high indicate that target cannot complete current data phase force wait state. TRDYB indicate that target complete current data phase. data phase completed when TRDYB initiator ready signal (IRDYB) also low. When FREEDM-32 initiator, TRDYB input. When FREEDM-32 target, TRDYB output. During accesses FREEDM-32 registers, TRDYB high extend data phases over multiple PCICLK cycles. When FREEDM-32 involved current transaction, TRDYB tri-stated. output signal, TRDYB updated rising edge PCICLK. input signal, TRDYB sampled rising edge PCICLK.
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FRAME ENGINE DATA LINK MANAGER
Name IRDYB
Type
Function active initiator ready (IRDYB) signal used indicate whether initiator ready start continue with transaction. IRDYB works conjunction with TRDYB complete transaction data phases. When IRDYB high transaction progress, initiator indicating cannot complete current data phase forcing wait state. When IRDYB transaction progress, initiator indicating completed current data phase. data phase completed when IRDYB target ready signal (IRDYB) also low. When FREEDM-32 initiator, IRDYB output. When FREEDM-32 target, IRDYB input. When FREEDM-32 involved current transaction, IRDYB tri-stated. IRDYB updated rising edge PCICLK sampled rising edge PCICLK depending whether output input.
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Name STOPB
Type
Function active stop signal (STOPB) requests initiator stop current transaction. When STOPB high target, initiator continues with transaction. When STOPB low, initiator will stop current transaction. When FREEDM-32 initiator, STOPB input. When STOPB sampled low, FREEDM-32 will terminate current transaction next PCICLK cycle. When FREEDM-32 target, STOPB output. FREEDM-32 only issues transaction stop requests when responding reads writes configuration space (disconnecting after DWORD transferred) initiator introduces wait states during transaction. When FREEDM-32 involved current transaction, STOPB tri-stated. STOPB updated rising edge PCICLK sampled rising edge PCICLK depending whether output input.
IDSEL
Input
initialization device select signal (IDSEL) enables read write access configuration registers. When IDSEL high during address phase transaction C/BEB[3:0] code indicates register read write, FREEDM-32 performs configuration register transaction asserts DEVSELB signal next PCICLK period. IDSEL sampled rising edge PCICLK.
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Name DEVSELB
Type
Function active device select signal (DEVSELB) indicates that target claims current transaction. During address phase transaction, targets decode address AD[31:0] bus. When target, recognizes address own, sets DEVSELB indicate initiator that address valid. target claims address clock cycles, initiator assumes that target does exist cannot respond aborts transaction. When FREEDM-32 initiator, DEVSELB input. target responds address PCICLK cycles, FREEDM32 will abort current transaction alerts Host interrupt. When FREEDM-32 target, DEVSELB output. DELSELB when address AD[31:0] recognised. When FREEDM-32 involved current transaction, DEVSELB tri-stated. FREEDM-32 updated rising edge PCICLK sampled rising edge PCICLK depending whether output input.
LOCKB
Input
active lock signal (LOCKB) locks target device. When LOCKB FRAME low, FREEDM-32 target, initiator locking FREEDM-32 "owned" target. Under these circumstances, FREEDM-32 will reject transaction with other initiators. FREEDM-32 will continue reject other initiators until owner releases lock forcing both FRAMEB LOCKB high. initiator, FREEDM-32 will never lock target. LOCKB sampled using rising edge PCICLK.
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Name REQB
Type Output
Function active request signal (REQB) requests external arbiter control bus. REQB when FREEDM32 desires access host memory. REQB high when access desired. REQB updated rising edge PCICLK. active grant signal (GNTB) indicates granting control over response request REQB output. When GNTB high, FREEDM-32 does have control over bus. When GNTB low, external arbiter granted FREEDM-32 control over bus. However, FREEDM-32 will proceed until FRAMEB signal sampled high, indicating current transactions progress. GNTB sampled rising edge PCICLK. active interrupt signal (PCIINTB) when FREEDM-32 interrupt source active, that source unmasked. FREEDM-32 enabled report many alarms events interrupts. PCIINTB returns high when interrupt acknowledged appropriate register access. PCIINTB open drain output updated rising edge PCICLK.
GNTB
Input
PCIINTB
Output
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Name PERRB
Type
Function active parity error signal (PERRB) indicates parity error over AD[31:0] C/BEB[3:0] buses. Parity error signalled when even parity calculations match signal. PERRB cycle immediately following offending cycle. PERRB high when parity error detected. PERRB enabled setting PERREN Control/Status register Configuration registers space. Regardless setting PERREN, parity errors always reported PERR Control/Status register Configuration registers space. PERRB updated rising edge PCICLK.
SERRB
Output
active system error signal (SERRB) indicates address parity error. Address parity errors detected when even parity calculations during address phase match signal. When FREEDM-32 detects system error, SERRB PCICLK period. SERRB enabled setting SERREN Control/Status register Configuration registers space. Regardless setting SERREN, parity errors always reported SERR Control/Status register Configuration registers space. SERRB open drain output updated rising edge PCICLK.
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Table Miscellaneous Interface Signals (13) Name SYSCLK Type Input Function system clock (SYSCLK) provides timing core logic. SYSCLK nominally duty cycle clock. active reset signal (RSTB) signal provides asynchronous FREEDM-32 reset. RSTB asynchronous input. When RSTB low, FREEDM-32 registers forced their default states. addition, TD[31:0] forced high output pins forced tri-state will remain high tri-stated, respectively, until RSTB high. production test enable signal (PMCTEST) places FREEDM-32 test mode. When PMCTEST high, production test vectors executed verify manufacturing test mode interface signals TA[10:0], TA[11]/TRS, TRDB, TWRB TDAT[15:0]. PMCTEST must tied normal operation. test clock signal (TCK) provides timing test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. updated falling edge TCK. test mode select signal (TMS) controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor. test data input signal (TDI) carries test data into FREEDM-32 IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor.
RSTB
Input
PMCTEST
Input
Input
Input
Input
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Name
Type
Function test data output signal (TDO) carries test data FREEDM-32 IEEE P1149.1 test access port. updated falling edge TCK. tri-state output which inactive except when scanning data progress. active test reset signal (TRSTB) provides asynchronous FREEDM-32 test access port reset IEEE P1149.1 test access port. TRSTB asynchronous input with integral pull resistor. Note that when TRSTB being used, must connected RSTB input.
Tristate Output
TRSTB
Input
VBIAS[3:1]
Input
bias signals (VBIAS[3:1]) provide Volt bias input pads allow FREEDM-32 tolerate connections Volt devices. avoid damage device, VBIAS[3:1] signals must connected together externally must times kept voltage that equal higher than VDD[28:1] power supplies. 3.3V operating environment, VBIAS[3:1] VDD[28:1] connected together. operating environment, VBIAS[3:1] should powered before VDD[28:1] powered 3.3V. Volt signalling enable signal (EN5V) causes Host Interface Signals operate signalling environment when high 3.3V signalling environment when low. EN5V asynchronous input with integral pull resistor. This must left unconnected.
EN5V
Input
Open
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Table Production Test Interface Signals Multiplexed) Name TA[0] TA[1] TA[2] TA[3] TA[4] TA[5] TA[6] TA[7] TA[8] TA[9] TA[10] TA[11]/TR Type Input Function test mode address (TA[10:0]) selects specific registers during production test (PMCTEST high) read write accesses. TA[10:0] replace RD[20:10] when PMCTEST high.
Input
test register select signal (TA[11]/TRS) selects between normal test mode register accesses during production test (PMCTEST high). high select test registers select normal registers. TA[11]/TRS replaces RD[21] when PMCTEST high. test mode read enable signal (TRDB) during FREEDM-32 register read accesses during production test (PMCTEST high). FREEDM-32 drives test data (TDAT[15:0]) with contents addressed register while TRDB low. TRDB replaces RD[22] when PMCTEST high. test mode write enable signal (TWRB) during FREEDM-32 register write accesses during production test (PMCTEST high). contents test data (TDAT[15:0]) clocked into addressed register rising edge TWRB. TWRB replaces RD[23] when PMCTEST high.
TRDB
Input
TWRB
Input
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Name TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15]
Type
Function bi-directional test mode data (TDAT[15:0]) carries data read from written FREEDM-32 registers during production test. TDAT[15:0] replace TD[31:16] when PMCTEST high.
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Table Power Ground Signals (60) Name VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 Type Power Function power pins should connected well decoupled +3.3 supply.
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Name VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32
Type Ground
Function ground pins should connected ground.
Notes Description: FREEDM-32 inputs bi-directionals present minimum capacitive loading operate compatible logic levels. signals conform Volt signaling environment depending setting EN5V input.
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Most FREEDM-32 non-PCI digital outputs bi-directionals have drive capability, except PCICLKO, RBCLK, TBCLK, PCIINTB outputs which have drive capability TD[0], TD[1], TD[2] outputs which have drive capability. FREEDM-32 non-PCI digital outputs bi-directionals tolerant when tristated except those with drive capability, i.e. TD[2:0]. (TD[2:0] never tristated normal operation only under JTAG boundary scan control.) Inputs TMS, TDI, TRSTB EN5V Schmitt triggered have internal pull-up resistors. Inputs RD[31:0], RCLK[31:0], TCLK[31:0], SYSCLK, PCICLK, TBD, RSTB, GNTB, IDSEL, LOCKB, PMCTEST Schmitt triggered.
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FUNCTIONAL DESCRIPTION High-Level Data Link Control Protocol Figure shows diagram synchronous HDLC protocol supported FREEDM-32. incoming stream examined flag bytes (01111110 pattern) which delineate opening closing HDLC packet. packet de-stuffed which discards which directly follows five contiguous bits. resulting HDLC packet size must multiple octet bits) within expected minimum maximum packet length limits. minimum packet length that packet containing information bytes (address control) bytes. packets with CRC-CCITT FCS, minimum packet length four bytes while those with CRC-32 FCS, minimum length bytes. HDLC packet aborted when seven contiguous bits (with inserted bits) received. least flag byte must exist between HDLC packets delineation. Contiguous flag bytes, ones bytes between packets used "inter-frame time fill". Adjacent flag bytes share zeros. Figure HDLC Frame
Flag Information HDLC Packet Flag Flag
algorithm frame checking sequence (FCS) field either CRC-CCITT CRC-32 function. Figure shows encoder block diagram using generating polynomial g(X) g2X2 gn-1Xn-1 CRC-CCITT bytes size generating polynomial g(X) X16. CRC-32 four bytes size generating polynomial g(X) X32. first received residue highest term.
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Figure Generator
gn-1 Dn-1 Message
Parity Check Digits
Receive Channel Assigner Receive Channel Assigner block (RCAS) processes serial links. Each link independent associated clock. each link, RCAS performs serial parallel conversion form data bytes. data bytes multiplexed, byte serial format, delivery Receive HDLC Processor Partial Packet Buffer block (RHDL) SYSCLK rate. event where multiple streams have accumulated byte data, multiplexing performed fixed priority basis with link having highest priority link lowest. Links containing stream channelised. Data each timeslot independently assigned different channel. RCAS performs table lookup associate link time-slot identity with channel. framing bits/bytes identified observing link clock which squelched during framing bits/bytes. unchannelised links, clock rates limited link limited remaining links. data each link belongs channel. case unchannelised links, maximum link rate SYSCLK SYSCLK MHz. case more numerous unchannelised links mixture channelise with unchannelised links, total instantaneous link rate over links limited MHz. RCAS performs table lookup using only link number determine associated channel, time-slots non-existent unchannelised links. RCAS provides diagnostic loopback that selectable channel basis. When channel diagnostic loopback, stream data received links originally destined that channel ignored. Transmit data that channel substituted place.
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9.2.1 Line Interface There identical line interface blocks RCAS. Each line interface contains counter, 8-bit shift register holding register, that, together, perform serial parallel conversion. Whenever holding register updated, request service sent priority encoder block. When acknowledged priority encoder, line interface would respond with data residing holding register. support channelised links, each line interface block contains time-slot counter clock activity monitor. time-slot counter incremented each time holding register updated. clock activity monitor counter that increments system clock (SYSCLK) rate cleared rising edge receive clock (RCLK[n]). framing (T1) framing byte (E1) detected when counter reaches programmable threshold. which case, time-slot counters initialised indicate that next most significant first time-slot. unchannelised links, time-slot counter clock activity monitor held reset. 9.2.2 Priority Encoder priority encoder monitors line interfaces requests synchronises them SYSCLK timing domain. Requests serviced fixed priority scheme where highest lowest priority assigned from line interface attached RD[0] that attached RD[31]. Thus, simultaneous requests from RD[m] will serviced ahead RD[n], When there pending requests, priority encoder generates idle cycle. addition, once every fourth SYSCLK cycle, priority encoder inserts null cycle where requests serviced. This cycle used channel assigner downstream host microprocessor accesses provisioning RAMs. 9.2.3 Channel Assigner channel assigner block determines channel number data byte currently being processed. block contains 1024 word channel provision RAM. address constructed from concatenating link number time-slot number current data byte. fields each word include channel number time-slot enable flag. time-slot enable flag labels current time-slot belonging channel indicted channel number field.
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9.2.4 Loopback Controller loopback controller block implements channel based diagnostic loopback function. Every valid data byte belonging channel with diagnostic loopback enabled from Transmit HDLC Processor Partial Packet Buffer block (THDL) written into word FIFO. loopback controller monitors idle time-slot time-slot carrying channel with diagnostic loopback enabled. either conditions hold, current data byte replaced data retrieved from loopback data FIFO. Receive HDLC Processor Partial Packet Buffer Receive HDLC Processor Partial Packet Buffer block (RHDL) processes synchronous transmission HDLC data streams. Each channel individually configured perform flag sequence detection, de-stuffing CRC-CCITT CRC-32 verification. packet data written into partial packet buffer. frame, packet status including error, octet alignment error maximum length violation also loaded into partial packet buffer. Alternatively, channel provisioned transparent, which case, HDLC data stream passed partial packet buffer processor verbatim. There natural precedence alarms detectable receive packet. Once packet exceeds programmable maximum packet length, further processing performed Thus, octet alignment detection, verification abort recognition squelched packets with maximum length violation. abort indication squelches octet alignment detection, minimum packet length violations, verification. addition, verification only performed packets that have octet alignment errors, order allow RHDL perform calculations byte-basis. partial packet buffer Kbyte that divided into 16-byte blocks. Each block associated pointer which points another block. logical FIFO created each provisioned channel programming block pointers form circular linked list. channel FIFO assigned minimum blocks bytes) maximum blocks Kbytes). depth channel FIFOs monitored round-robin fashion. Requests made Receive Controller block (RMAC) transfer, host memory, data channel FIFOs with depths exceeding their associated threshold. 9.3.1 HDLC Processor HDLC processor time-slice state machine which process independent channels. state vector provisioning information each
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channel stored RAM. Whenever channel data arrives, appropriate state vector read from RAM, processed written back RAM. HDLC state-machine configured perform flag delineation, de-stuffing, verification length monitoring. resulting HDLC data status information passed partial packet buffer processor stored appropriate channel FIFO buffer. configuration HDLC processor accessed using indirect channel read write operations. When indirect operation performed, information accessed from during null clock cycle generated upstream Receive Channel Assigner block (RCAS). Writing provisioning data channel resets channel's entire state vector. 9.3.2 Partial Packet Buffer Processor partial packet buffer processor controls Kbyte partial packet which divided into byte blocks. block pointer used chain partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous sections allocated partial packet buffer create channel FIFO. System software responsible assignment blocks individual channel FIFOs. Figure shows example three blocks (blocks 200) linked together form byte channel FIFO. partial packet buffer processor divided into three sections: writer, reader roamer. writer time-sliced state machine which writes HDLC data status information from HDLC processor into channel FIFO packet buffer RAM. reader transfers channel FIFO data from packet buffer downstream Receive Controller block (RMAC). roamer time-sliced state machine which tracks channel FIFO buffer depths signals reader service particular channel. buffer over-run occurs, writer ends current packet from HDLC processor channel FIFO with over-run flag ignores rest packet.
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Figure Partial Packet Buffer Structure Partial Packet Buffer
Block Block Block Block bytes bytes bytes bytes Block Block Block Block
Block Pointer
0x03 0xC8
Block
bytes
Block
0x01
Block
bytes
Block
FIFO algorithm partial packet buffer processor based programmable per-channel transfer size. Instead tracking number full blocks channel FIFO, processor tracks number transactions. Whenever partial packet writer fills transfer-sized number blocks writes end-of-packet flag channel FIFO, transaction created. Whenever partial packet reader transmits transfer-size number blocks end-of-packet flag RMAC block, transaction deleted. Thus, small packets less than transfer size will naturally transferred RMAC block without having precisely track number full blocks channel FIFO. partial packet roamer performs transaction accounting channel FIFOs. roamer increments transaction count when writer signals transaction sets per-channel flag indicate non-zero transaction count. roamer searches flags round-robin fashion decide which channel FIFO request transfer RMAC block. roamer informs partial packet reader channel process. reader transfers data RMAC until channel transfer size reached packet
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detected. reader then informs roamer that transaction consumed. roamer updates transaction count clears non-zero transaction count flag required. roamer then services next channel with transaction flag high. writer reader determine empty full FIFO conditions using flags. Each block partial packet buffer associated flag. writer sets flag after block written reader clears flag after block read. flags initialized (cleared) when block pointers written using indirect block writes. writer declares channel FIFO overrun whenever writer tries store data block with flag. order support optional removal from packet data, writer does declare block filled (set block flag increment transaction count) until first double word next block channel FIFO filled. packet resides first double word, writer declares both blocks full same time. When reader finishes processing transaction, examines first double word next block end-of-packet flag. first double word next block contains only bytes, reader would, optionally, process next transaction (end-of-packet) consume block, contains information transferred RMAC block. Receive Controller Receive Controller block (RMAC) controller which stores received packet data host computer memory. RMAC directly connected host memory bus. Memory accesses serviced downstream controller block (GPIC). RMAC host exchange information using receive packet descriptors (RPDs). descriptor contains size location buffers host memory packet status information associated with data each buffer. RPDs transferred from RMAC host vice versa using descriptor reference queues. RMAC maintains pointers operation queues. RMAC provides receive packet descriptor reference (RPDR) free queues support small large buffers. RMAC acquires free buffers reading RPDRs from free queues. After packet received, RMAC places associated RPDR onto RPDR ready queue. minimise host accesses, RMAC maintains descriptor reference table store current information. This table contains separate information entries receive channels. 9.4.1 Data Structures packet data, RMAC communicates with host using Receive Packet Descriptors (RPD), Receive Packet Descriptor References (RPDR), Receive
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Packet Descriptor Reference Ready (RPDRR) queue Receive Packet Descriptor Reference Small Large Buffer Free (RPDRF) queues. RMAC copies packet data data buffers host memory. RPD, RPDR, RPDRR queue, Small Large RPDRF queues data structures which used transfer host memory data buffer information. five data structures manipulated both RMAC host computer. holds data buffer size, data buffer address, packet status information. RPDR pointer which used index into table RPDs. RPDRR queue RPDRF queues allow RMAC host pass RPDRs back forth. These data structures described more detail following sections. Receive Packet Descriptor Receive Packet Descriptors (RPDs) pass buffer packet information between RMAC host. Both RMAC host read write information RPDs. host writes fields which describe size address data buffers host memory. RMAC writes fields which provide number bytes used each data buffer, link information, status received packet. RPDs stored host memory Receive Packet Descriptor Table which described later section. Receive Packet Descriptor structure shown Figure Figure Receive Packet Descriptor
Data Buffer Start Address [31:0] Bytes Buffer [15:0] Reserved (18) Reserved (16) Status [5:0] Offset[1:0] [6:0]
Next Pointer [13:0] Receive Buffer Size [15:0]
Table Receive Packet Descriptor Fields Field Data Buffer Start Address[31:0] Description Data Buffer Start Address[31:0] bits point data buffer host memory. This field expected configured Host during initialisation. Data Buffer Start Address field valid RPDs.
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Field RCC[6:0]
Description Receive Channel Code (RCC[6:0]) bits used RMAC indicate which channel associated with. linked list RPDs, RPDs' fields valid, i.e. contain same channel value.
Chain (CE) indicates linked list RPDs. When logic one, current last linked list RPDs. When logic zero, current last linked list. valid RPDs written RMAC Receive Ready Queue. When packet requires only RPD, logic one. ignored RPDs read RMAC from Receive Free Queues, each which assumed point only buffer, i.e. chain.
Offset[1:0]
Offset[1:0] bits indicate byte offset data packet from start buffer. this value nonzero, there will `dummy' (i.e. undefined) bytes start data buffer prior packet data proper. linked list RPDs, only first RPD's Offset field valid. other Offset fields linked list
Status [5:0]
Status[5:0] bits indicate status received packet. Status[0] Status[1] Status[2] Status[3] Status[4] Status[5] buffer overrun Packet exceeds max. allowed size error Packet Length exact bytes HDLC abort detected Unused (set
linked list RPDs, only last RPD's Status field valid. other Status fields linked list invalid should ignored. When packet requires only RPD, Status field valid.
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Field Bytes Buffer [15:0]
Description Bytes Buffer[15:0] bits indicate number bytes actually used current RPD's data buffer store packet data. count excludes 'dummy' bytes inserted result non-zero Offset field. count greater than 32767 bytes indicates packet that shorter than expected length field. Bytes Buffer field invalid when Status[0] Status[4] asserted
Next Pointer [13:0]
Next Pointer[13:0] bits store RPDR which enables RMAC support linked lists RPDs. This field, which only valid when equal logic zero, contains RPDR next linked list. RMAC links RPDs when more than buffer needed store packet. Next Pointer valid last linked list (when CE=1). When packet requires only RPD, Next Pointer field valid.
Receive Buffer Size Receive Buffer Size[15:0] bits indicate size [15:0] bytes current RPD's data buffer. This field expected configured Host during initialisation. Receive Buffer Size must non-zero integer multiple four less than equal 32764. Receive Buffer Size field valid RPDs. Receive Buffer Size Data Buffer Start Address fields written only host. RMAC reads these fields determine where store packet data. other fields written only RMAC. Receive Packet Descriptor Table Receive Packet Descriptor Table resides host memory stores RPDs. Table contain maximum 16384 RPDs. base table user programmable using Packet Descriptor Table Base (RPDTB) register. table indexed Receive Packet Descriptor Reference (RPDR) which 14-bit pointer defining offset from table base. Thus, shown following diagram, located adding RPDR Packet Descriptor Table Base register.
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Figure Receive Packet Descriptor Table
RPDTB[31:4] Packet Descriptor Table Base register RPDR[13:0] Receive Packet Desriptor Reference RPD_ADDR[31:0] Receive Packet Descriptor Address
RPDTB[31:4]
0000
RPDR[13:0]
0000
RPD_ADDR[31:0]
RPDTB RPD_ADDR
Dword Dword Dword Dword Dword Dword
Dword 16384 Dword
Receive Packet Descriptor Table resides host memory. Packet Descriptor Table Base register resides RMAC; this register initialised host. RPDRs reside host memory accessed using receive packet queues which described next section.
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Receive Packet Queues Receive Packet Queues used transfer RPDRs between host RMAC. There three queues: RPDR Large Buffer Free Queue (RPDRLFQ), RPDR Small Buffer Free Queue (RPDRSFQ) RPDR Ready Queue (RPDRRQ). free queues contain RPDRs referencing RPDs that define free buffers. ready queue contains RPDRs referencing RPDs that define buffers ready host processing. RMAC pulls RPDRs from free queues when needs free data buffers. RMAC places RPDR onto ready queue after filled buffers with data from each complete packet. host removes RPDRs from ready queue process data buffers. host places RPDRs back onto free queues after finishes reading data from buffers. When starting process packet, RMAC uses small buffer store packet data. packet requires more than buffer, RMAC uses large buffer RPDs store remainder packet. RMAC links together RPDs required store packet returns RPDR associated with first onto ready queue. receive packet queues reside host memory defined Queue Base (RQB) register index registers which reside RMAC. Queue Base base address receive packet queues. Each packet queue four index registers which define start queue read write locations queue. Each index register bits length defines offset from Queue Base. Thus, shown Figure host address RPDR calculated adding index register Queue Base register. host initialises Queue Base index registers. When entity (either RMAC host) removes elements from queue, entity updates read pointer that queue. When entity (either RMAC host) places elements onto queue, entity updates write pointer that queue. read index each queue points last valid RPDR read while write index points where next RPDR written. start index points first valid location within queue; RPDR written this location. However, index points location that beyond queue; RPDR written this location. Note however, start index queue index another queue. queue empty when read index less than write index; queue also empty read index less than index write index equals start index. queue full when read index equal write index. Figure shows RPDR reference queues.
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Figure RPDRF RPDRR Queues
Receive Packet Descriptor (RPD) Reference Queues Base Address:
RQB[31:2] Queue Base register
Index Registers:
Large Buffer Free Queue: RPDRLFQS[15:0] RPDRLFQW[15:0] RPDRLFQR[15:0] RPDRLFQE[15:0] Ready Queue: RPDRRQS[15:0] RPDRRQW[15:0] RPDRRQR[15:0] RPDRRQE[15:0] RPDR Ready Queue Start register RPDR Ready Queue Write register RPDR Ready Queue Read register RPDR Ready Queue register RPDR Large Free Queue Start register RPDR Large Free Queue Write register RPDR Large Free Queue Read register RPDR Large Free Queue register Small Buffer Free Queue: RPDRSFQS[15:0] RPDRSFQW[15:0] RPDRSFQR[15:0] RPDRSFQE[15:0] RPDR Small Free Queue Start register RPDR Small Free Queue Write register RPDR Small Free Queue Read register RPDR Small Free Queue register
Base Address Index Register -Host Address
RQB[31:2] Index[15:0] AD[31:0]
Packet Descriptor Reference Queue Memory
RPDRRQS RPDRRQR Status RPDR Status RPDR Status RPDR
Host Memory
Status RPDR RPDRRQW Status RPDR Status RPDR RPDRRQE RPDRLFQS RPDRLFQR RPDR RPDR RPDR Reference Queues 256KB
RPDRLFQW
RPDR RPDR RPDR
RPDRLFQE RPDRSFQS RPDRSFQR
RPDR RPDR RPDR
Valid RPDR RPDRSFQW RPDR RPDR RPDR
RPDRSFQE
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Note that maximum value which pointer FFFF hex, resulting maximum offset from queue base address (4*(FFFF-1)) 3FFF8 hex. pointer must attempt include offset 3FFFC queue. shown Figure ready queue elements have status field well RPDR field. RMAC fills status field mark whether packet successfully received not. host reads status field. ready queue element shown Table below along with definition status bits. RMAC requires buffer particular size (i.e. small large) RPDR available corresponding free queue, RPDR from other free queue substituted. host may, therefore, force RMAC store received data buffers only size setting free queues zero length, i.e. setting start index registers queues equal values. RMAC requires buffer neither free queue contains RPDRs, RPQ_ERRI interrupt generated. Table RPDRR Queue Element STATUS[1:0] Field STATUS[1:0] Description encoding status field follows: Successful reception packet. Unsuccessful reception packet. Unprovisioned partial packet. Reserved. RPDR[13:0] RPDR[13:0] field defines offset first linked chain RPDs, each pointing buffer containing received data. RPDR[13:0]
described previously, RMAC links large buffer small buffer more than buffer needed packet. RMAC links additional large buffer RPDs chain required until entire packet copied host memory (provided that host disabled both free queues setting them length zero). After storing packet data, RMAC places STATUS+RPDR first onto ready queue. Only RPDR associated with first placed onto ready queue. other required RPDs linked first shown Figure
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Although STATUS+RPDR only totals bits, each queue entry dword, i.e. bits. When RMAC block writes STATUS+RPDR ready queue, sets third byte fourth (most significant) byte unmodified. Figure RPDRR Queue Operation Packet Descriptor Reference Ready Queue
RPDRRQ_START_ADDR RPDRRQ_READ_ADDR
STATUS RPDR STATUS RPDR
buffer -packet bytes buffer -packet
RPDRRQ_WRITE_ADDR
STATUS RPDR
bytes
bytes
buffer -start packet
bytes buffer -middle packet bytes buffer -end packet RPDRRQ_END_ADDR
Receive Channel Descriptor Reference Table per-channel basis, RMAC caches information such current information Receive Channel Descriptor Reference (RCDR) Table. RMAC process channels stores three dwords information channel. This information cached internally order decrease number host accesses required process each data packet. structure RCDR table shown Figure
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Figure Receive Channel Descriptor Reference Table
Bytes Available Buffer[15:0] RBC[1:0] Buffer Size[15:0]
Pointer[13:0] Start Pointer[13:0] Pointer[13:0] Start Pointer[13:0]
Current Address[31:0] Bytes Available Buffer[15:0] RBC[1:0] Buffer Size[15:0]
Current Address[31:0]
Bytes Available Buffer[15:0] RBC[1:0] Buffer Size[15:0]
Pointer[13:0] Start Pointer[13:0]
Current Address[31:0]
Table Receive Channel Descriptor Reference Table Fields Field Bytes Available Buffer[15:0] Description This field used keep track number bytes available current data buffer. RMAC initialises Bytes Available Buffer Receive Buffer Size minus offset head buffer. field decremented each time byte written into buffer. This field used keep track number buffers used when storing `raw' (i.e. packet delimited) data. RMAC initialises field value RAWMAX[1:0] field RMAC Control Register. field decremented each time buffer filled with data. field reaches zero, chain RPDs placed ready queue chain started. This field contains pointer current RPD. This field contains size bytes buffer currently being written
RBC[1:0]
Pointer[13:0] Buffer Size[15:0]
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Field
Description This (Valid) indicates whether packet currently being received channel. When other fields RCDR table entry channel contain valid information. This field contains pointer first packet being received. Current Address [31:0] bits holds host address next dword current buffer. RMAC increments this field each access buffer.
Start Pointer[13:0] Current Address[31:0]
9.4.2 Transaction Controller Transaction Controller coordinates reception data packets from Receive Packet Interface their subsequent storage host memory. packet received over number separate transactions, interleaved with transactions belonging other channels. well sending received data host memory, Transaction Controller initiates data transactions purposes maintaining data structures (queues, descriptors, etc.) host memory. 9.4.3 Write Data Pipeline/Mux Write Data Pipeline/Mux performs functions. First, pipelines receive data between RHDL block GPIC block, inserting enough delay enable Transaction Controller generate appropriate control signals GPIC interface. Second, provides multiplexor data lines GPIC interface, allowing Transaction Controller output data relating transactions controller itself initiates. 9.4.4 Descriptor Information Cache Descriptor Information Cache provides storage Receive Channel Descriptor Reference (RCDR) Table described above (Figure 9.4.5 Free Queue Cache Free Queue Cache block implements element RPDR Small Buffer Free Queue cache element RPDR Large Buffer Free Queue cache. These caches used store free small buffer large buffer RPDRs.
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Caching RPDRs reduces number host accesses that RMAC makes. Each cache managed independently. elements cache consumed time they needed RMAC. RPDR small buffer cache reloaded when empty RMAC requires small buffer RPDR. large buffer RPDR cache reloaded when empty RMAC requires large buffer RPDR. When reloading either caches, appropriate cache controller will read elements. cache controller read fewer than elements there fewer than elements available, read pointer index within elements free queue. read pointer near free queue, cache controller reads only queue does start reading from queue until next time reload required. would require host memory transactions would benefit. Controller General-Purpose Peripheral Component Interconnect Controller block (GPIC) provides 32-bit Master Target interface core which contains required control functions Peripheral Component Interconnect (PCI) Revision interfacing. Communications between other FREEDM-32 blocks made through either internal asynchronous16-bit through synchronous FIFO interfaces. FIFO interfaces dedicated servicing Receive Controller block (RMAC) other Transmit Controller block (TMAC). GPIC supports 32-bit operating bridges between timing domain controllers (SYSCLK) timing domain (PCICLK). itself, GPIC does generate accesses. transactions initiated another master core device. GPIC transforms each access from intended target initiator core device. Except configuration space registers parity generating/checking, GPIC performs operations data. GPIC made four sections: master state machine, target state machine, internal microprocessor interface error/bus controller. target master blocks operate independent each other. error/bus control block monitors control signals from target master blocks determine state pads. This block also generates and/or checks parity data going coming from bus. internal microprocessor interface block contains configuration status registers together with production test logic GPIC block.
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9.5.1 Master Machine GPIC master machine translates requests from RMAC TMAC block interfaces into transactions. GPIC initiates four types cycles: memory read (burst single), memory read multiple, memory read line memory write (burst single). number data transfers cycle controlled controllers. maximum burst size determined particular data path. read cycle RMAC restricted maximum burst size dwords write cycle limited maximum TMAC interface limit dwords read cycle write cycle. response controller requesting cycle, GPIC must arbitrate control bus. Before asserting Request line, GPIC first does internal arbitration determine priority service event that both RMAC TMAC requesting service. GPIC arbitrates between four FIFOs based either RMAC priority round-robin scheme that software selectable. possible four FIFOs (RMAC read, TMAC read, RMAC write, TMAC write) request service simultaneously. When external arbitrator issues Grant response Request from GPIC, master state machine monitors insure that previous master completed transaction released before beginning cycle. Once GPIC control bus, will assert FRAME signal drive with address command. value address provided selected controller. After initial data transfer, GPIC tracks address remaining transfers burst internally case GPIC disconnected target must retry transaction. target GPIC master burst cycle option stopping disconnecting burst point. event target disconnect GPIC will terminate present cycle release bus. GPIC asserting REQUEST line time disconnect, will remove REQUEST clock cycles then reassert When arbitrator returns GRANT, GPIC will restart burst access next address continue until burst completed repeat sequence target disconnects again. During burst reads, GPIC accepts data without inserting wait states. Data written directly into read FIFO where RMAC TMAC remove rate. During burst writes, GPIC will output data without inserting wait states, terminate transaction early local master fails fill write FIFO with data before GPIC requires write transaction terminated early data starvation, GPIC will automatically
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initiate further transaction write remaining data when becomes available.) Normally, GPIC will begin requesting write transaction shortly after data starts loaded into write FIFO RMAC TMAC. RMAC, however, required supply transaction length when writing packet data addition, insert pauses during transfer. case packet data writes RMAC, GPIC will hold requesting until write FIFO filled with number dwords equal programmable threshold. FIFO empties without reaching transition, GPIC will terminate current transaction restart transaction transfer remaining data when RMAC signals transaction. Beginning transaction before data write FIFO allows GPIC reduce impact latency core device. Each master cycle generated GPIC terminated three ways: Completion, Timeout Master Abort. normal mode operation GPIC terminate after transferring data from master FIFO selected. noted above this involve multiple accesses because inability target accept full burst data starvation during writes. After completion burst transfer GPIC will release unless another FIFO requesting service, which case GRANT asserted GPIC will insert idle cycle then start transfer. maximum duration master burst cycle controlled value LATENCY TIMER register GPIC Configuration Register block. This value host boot loaded into counter GPIC master state start each access. counter reaches zero GRANT signal been removed GPIC will release regardless whether completed present burst cycle. This type termination referred Master Time-out. case Master Time-out GPIC will remove REQUEST signal clocks then reassert complete burst cycle. target responds address placed GPIC after clocks GPIC will terminate cycle flag cycle Command/ Status Configuration Register Master Abort. Stop Error enable (SOE_E) GPIC Command Register, GPIC will process more requests until error condition cleared. SOE_E set, GPIC will discard REQUEST indicate local master that cycle complete. This action will result write data being lost read data being erroneous.
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9.5.2 Master Local Interface master local data which connects local master device GPIC. GPIC contains local master interface blocks, with supporting RMAC other TMAC. Each local master interface been optimised support traffic pattern generated RMAC TMAC interchangeable. data path between GPIC local master device provides mechanism segregate system timing domain core from bus. Transfers each RMAC TMAC interfaces timed system clock. controllers isolated from aspects protocol, instead "sees" simple synchronous protocol. Read write cycles local master will initiate request service GPIC which will then transfer data bus. GPIC maximises data throughput between local device paralleling local data transfers with access latency. GPIC allows either controller write data independent each other independent control. GPIC temporarily buffers data from each controller while arbitrating control bus. After completion write transfer, controller then released perform other tasks. GPIC buffer only single transaction from each controller. Read accesses local optimised allowing controllers access data from soon first data becomes available. After initial synchronisation latency data transferred slower rate core logic SYSCLK rate. Once read transaction started, controller held waiting ready signal while GPIC arbitrating bus. data passed between GPIC controllers little Endian format and, default mode operation, GPIC expects data also little Endian format. GPIC provides selection internal Control register which allows Endian format data changed. enabled, GPIC will swizzle packet data (but descriptor references contents descriptors). swizzling performed according "byte address invariance" rule, i.e. only change data mirror-imaging byte lanes. interface RMAC provides byte addressability write transactions whereas interface TMAC provides byte addressability read transactions. Other transactions must dword aligned. byte-addressable transactions, data transferred between local device GPIC need dword aligned with data presented bus. GPIC
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will perform byte-realignment required. order complete transfer involving byte re-alignment, GPIC need extra burst cycle transaction. 9.5.3 Target Machine GPIC target machine performs required functions stand alone target device. target block performs three main functions. first target state machine which controls protocol target accesses GPIC. second function provide Configuration registers. Last, target block provides Target Interface registers other FREEDM-32 blocks. GPIC tracks decodes addresses commands placed determine whether respond access. GPIC responds following types commands only: Configuration read write, memory read write, memory-read-multiple memory-read-line which aliased memory read memory-write-and-invalidate which aliased memory write. GPIC will ignore access that falls within address range other command type. After accepting target access medium speed device, FREEDM inserts wait state configuration read/write five wait states other command types before completing transaction asserting TRDYB. Burst accesses GPIC accepted provided they linear type. master makes memory access GPIC with lower address bits value "00" (linear burst type) GPIC ignores cycle. Burst accesses length accepted, FREEDM will disconnect master inserts wait states during transaction. FREEDM will also disconnect every read write access configuration space after transferring Dword data. Figure illustrates GPIC address space.
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Figure GPIC Address
ADDRESS
Registers Base Address
Registers
GPIC responds with medium timing master accesses. (I.e. DEVSELB asserted PCICLK cycles after FRAMEB asserted) inserts three wait states reads internal register space (four wait states subsequent dwords burst read). target machine will only terminate access with Retry target locked another master tries access GPIC. GPIC will terminate access non-burst area with Disconnect always with data transferred. target does support delayed transactions. GPIC will perform Target-Abort termination only case address parity error address that GPIC claims.
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9.5.4 Interface interface provides access address space FREEDM-32 blocks. address space associated Configuration registers. Write transfers space always write bits provided that least byte enable asserted. write command with byte enables negated will ignored. Read transfers always return bits regardless status byte enables, long least byte enable asserted. read command with byte enables negated will ignored. 9.5.5 Error Control Error/Bus Control block monitors signals from both Target block Master Block determine direction pads generate check parity. After reset, GPIC sets bi-directional pads inputs monitors accesses. Error/Bus control unit remains this state unless either Master requests Target responds Master Access. Error/Bus control unit decodes state each state machine determine direction each signal. devices required check generate even parity across AD[31:0] C/BEB[3:0] signals. GPIC generates parity Master address write data phases; target generates parity read data phases. GPIC required check parity phases even participating cycle. But, GPIC will report parity errors only GPIC involved cycle GPIC detects address parity error data parity detected special cycle. GPIC updates Configuration Status register detected error conditions. Transmit Controller Transmit Controller block (TMAC) controller which retrieves packet data from host computer memory transmission. minimum packet data length bytes. TMAC communicates with host computer through master interface connected Controller block (GPIC) which translates host specific signals from host master interface format. TMAC uses master interface whenever wishes initiate host read write; this case, TMAC initiator host memory target. TMAC host exchange information using transmit descriptors (TDs). descriptor contains size location buffers host memory
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packet status information associated with data each buffer. transferred from TMAC host vice versa using descriptor reference queues. TMAC maintains pointers operation queues. TMAC acquires buffers with data ready transmission reading TDRs from ready queue. After packet been transmitted, TMAC places associated onto free queue. minimise host accesses, TMAC maintains descriptor reference table store current information. This table contains separate information entries transmit channels. TMAC also performs per-channel sorting packets received ready queue eliminate head-of-line blocking. 9.6.1 Data Structures TMAC communicates with host using Transmit Descriptors (TD), Transmit Descriptor References (TDR), Transmit Data Reference Ready (TDRR) queue Transmit Data Reference Free (TDRF) queue. TMAC reads packet data from data buffers host memory. TDR, TDRR queue, TDRF queue data structures which used transfer host memory data buffer information. four data structures manipulated both TMAC host computer. holds data buffer size, data buffer address, other packet information. pointer which used index into table TDs. TDRR queue TDRF queue allow TMAC host pass TDRs back forth. These data structures described more detail following sections. Transmit Descriptor Transmit Descriptors (TDs) pass buffer packet information between TMAC host. Both TMAC host read write information TDs. stored host memory Transmit Descriptor Table. Transmit Descriptor structure shown Figure Figure Transmit Descriptor
Data Buffer Start Address [31:0] Bytes Buffer [15:0] Res(2) TMAC Next Pointer [13:0] Reserved (16) Reserved TCC[6:0]
Host Next Pointer [13:0] Transmit Buffer Size [15:0]
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Table Transmit Descriptor Fields Field Data Buffer Start Address [31:0] Bytes Buffer [15:0] Description Data Buffer Start Address[31:0] bits point data buffer host memory. Data Buffer Start Address field valid Bytes Buffer[15:0] field used host indicate total number bytes transmitted current Zero length buffers illegal. Priority host indicate priority associated packet level quality service scheme. Packets with high queued high priority queue TMAC. Packets with queued priority queue. Packets priority queue will begin transmission until high priority queue empty. used indicate that TMAC Next Pointer field valid. When logic TMAC Next Pointer[13:0] field valid. When logic TMAC Next Pointer[13:0] field invalid. used host reclaim data buffers event that data presented TMAC returned host channel becoming unprovisioned. expected initialised logic host. More used host support packets that require multiple TDs. logic current just several current packet. logic this either describes entire packet single packet case) describes packet multiple packet case). Note: When logic only valid value logic
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Field
Description Chain (CE) used host indicate linked list presented TMAC. linked list contain more packets delineated (see above). When logic current last linked list TDs. When logic current last linked list. When current last linked list, Host Next Pointer[13:0] field valid, otherwise field valid. Note: When logic only valid value logic Note: When presenting (i.e. unpacketised) data transmission, host should code bits single packet chain, i.e. M=1, CE=0 except last chain M=0, CE=1 last chain.
TCC[6:0]
Transmit Channel Code (TCC[6:0]) field used host indicate with which channel associated. chain must associated with same channel, i.e. have this field same value. TMAC Next Pointer[13:0] bits used store TDRs which permits TMAC create linked lists passed TDRR queue. linked with other belonging same channel same priority level. case that data presented TMAC returned host channel becoming unprovisioned, pointing start per-channel linked list placed TDRF queue. responsibility host follow TMAC host links order recover buffers. Abort (ABT) used host abort transmission packet. When logic packet will aborted after data buffer been transmitted. logic current must must high.
TMAC Next Pointer [13:0]
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Field
Description Interrupt Complete (IOC) used host instruct TMAC interrupt host when current TD's data buffer been read. When logic TMAC asserts IOCI interrupt when data buffer been read. Additionally, Free Queue FIFO will flushed. logic zero, TMAC will generate interrupt Free Queue FIFO will operate normally. Host Next Pointer[13:0] bits used store TDRs which permits host support linked lists TDs. described above, linked lists terminated setting logic Linked lists used host pass multiple packets multiple packets associated with same channel priority level TMAC. Transmit Buffer Size[15:0] field used indicate size bytes current TD's data buffer. (N.B. TMAC does make this field.)
Host Next Pointer [13:0]
Transmit Buffer Size [15:0]
Transmit Descriptor Table Transmit Descriptor Table, which resides host memory, contains Transmit Descriptors referenced TMAC. access TMAC takes from TDRR queue from TCDR table adds times value (because each bytes size) Transmit Descriptor Table Base (TDTB) pointer form actual address host memory. Each must reside Transmit Descriptor Table. Transmit Descriptor Table contain maximum 16384 TDs. base Transmit Descriptor Table user programmable using TMAC Descriptor Table Base register. Thus, shown below, each located using Transmit Descriptor Reference (TDR) combined with TMAC Descriptor Table Base register.
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Figure Transmit Descriptor Table
TDTB[31:4] Descriptor Table Base register TDR[13:0] Transmit Descriptor Reference TD_ADDR[31:0] Transmit Descriptor Address
TDTB[31:4]
0000
TDR[13:0]
0000
TD_ADDR[31:0]
TDTB TD_ADDR
Dword Dword Dword Dword Dword Dword
Dword 16384 Dword
Transmit Queues Pointers transmit descriptors (TDs) containing packet(s) ready transmission passed from host TMAC using Transmit Descriptor Reference Ready (TDRR) queue, which resides host memory. Pointers transmit descriptor structures whose buffers have been read TMAC passed from TMAC host using Transmit Descriptor Reference Free (TDRF) queue, which also resides host memory. TMAC contains Free Queue cache which store TDRs. caching
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enabled, free TDRs written into TDRF queue time, reduce number host memory accesses. Free Queue cache also flushed TDRF queue Interrupt Completion (IOC) which sends corresponding directly TDRF queue. queues, shown Figure defined common base pointer residing Transmit Queue Base register eight offset pointers, four queue. each queue, pointers define start queue, pointers keep track current read write locations within queue. read pointer each queue points offset last valid read, write pointer points offset where next written. queue valid location read written. queue empty when read pointer less than write pointer read pointer less than pointer write pointer equals start pointer. queue full when read pointer equal write pointer. Each queue element bits size, only least significant bits valid. least significant bits consist 14-bit three status bits. status bits used TMAC inform host success failure transmission (see Table 10). When TMAC writes TDRs TDRF queue, sets bits [23:17] queue element Once placed TDRF queue, FREEDM-32 will make further accesses associated buffer. Note that maximum value which pointer FFFF hex, resulting maximum offset from queue base address (4*(FFFF-1)) 3FFF8 hex. pointer must attempt include offset 3FFFC queue.
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Figure TDRR TDRF Queues
Transmit Descriptor Referance Queues Base Address:
TQB[31:2] Queue Base register
Index Registers:
Ready: TDRRQS[15:0] TDRRQW[15:0] TDRRQR[15:0] TDRRQE[15:0] Free: TDRFQS[15:0] TDRFQW[15:0] TDRFQR[15:0] TDRFQE[15:0] Free Queue Start register Free Queue Write register Free Queue Read register Free Queue register Ready Queue Start register Ready Queue Write register Ready Queue Read register Ready Queue register
Base Address Index Register -PCI Address
TQB[31:2]
Index[15:0] AD[31:0]
Descriptor Reference Queue Memory
TDRFQS TDRFQR Status Status Status
Host Memory
Status TDRFQW Status Status TDRFQE TDRRQS TDRRQR Reference Queues 256KB
TDRRQW TDRRQE
Valid TDR. Only least significant bits valid.
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Table Transmit Descriptor Reference STATUS[2:0] Field Status[2:0] Description TMAC fills Status field indicate host results processing encoding Status[1:0] Status[2] TDR[13:0] Description Last only buffer packet, buffer read. Buffer partial packet, buffer read. Unprovisioned channel, buffer read. Malformed packet (e.g. Bytes Buffer field buffer read. Description underflow detected. Underflow detected. TDR[13:0]
TDR[13:0] field contains offset returned.
returned host with status field "10" (unprovisioned channel), point binary tree buffers indicated bits TDs). responsibility host traverse tree reclaim buffers. returned host with status field other value, will only point buffer regardless values that underflow status (Status[2]) normally attached belonging packet experiencing underflow. long packets spanning multiple buffers, underflow reported only once first available that channel. subsequent TDRs that packet will returned normally without underflow status. rare cases, internal buffering FREEDM-32, packet experience underflow very packet, just being returned free queue. underflow status will then reported first immediate next packet that channel. Because uncertainty with reporting underflows between current verse subsequent packet, underflow status should only used gather
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performance statistics channels initiating packet specific responses such retransmission. Transmit Channel Descriptor Reference Table TMAC maintains Transmit Channel Descriptor Reference (TCDR) table which stored certain information relating activity each channel together with pointers which used TMAC sort packet chains supplied host into per-channel linked lists (see below). caching DMA-related information reduces number host accesses required process each data packet, while sorting into per-channel linked lists eliminates head line blocking. Each channel provided with entries TCDR table, high priority packets (Pri priority packets (Pri structure TCDR table shown Figure below. Figure Transmit Channel Descriptor Reference Table
Last Pointer [13:0] Bytes [15:0] Current Pointer [13:0] Host Pointer [13:0]
Abrt
Current Address [31:0] Reserved
Last
Next Pointer [13:0] Current Pointer [13:0] Host Pointer [13:0]
Last Pointer [13:0] Bytes [15:0]
Abrt
Current Address [31:0] Reserved
Last
Next Pointer [13:0]
127,
Last Pointer [13:0] Bytes [15:0]
Current Pointer [13:0] Host Pointer [13:0]
Abrt
Current Address [31:0] Reserved
Last
Next Pointer [13:0]
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Table Transmit Channel Descriptor Reference Table Fields Field Last Pointer [13:0] Description copy currently being read. copy currently being read. Offset head last host-linked chain read. (See Figure Indicates this channel active (i.e. provisioned). channel active, logic channel inactive, logic Indicates whether linked list packets this channel empty not. logic list empty current pointer field valid (i.e., points valid TD). logic list empty current pointer field invalid. Offset currently being read. Bytes Tx[15:0] bits used indicate total number bytes that remain read current buffer. Each access data buffer decrements this value. value zero this field indicates buffer been completely read. copy ABRT currently being read. copy currently being read. Packet Transfer Progress indicates that packet currently being transmitted this channel this priority level. Indicates that `null abort' sent downstream block when next requests data this channel. mal-formed encountered while searching down host chain. Indicates that underflow occurred this channel. This response underflow indication downstream THDL block cleared when written Free Queue free queue cache).
Current Pointer [13:0] Bytes Tx[15:0]
ABRT
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Field
Description
Host Pointer [13:0] copy Host Next Pointer field currently being read, i.e. pointer next chain currently being read. (See Figure Current Address[31:0] Current Address [31:0] bits hold address next dword current buffer. This field incremented each access buffer. Indicates linked list packets this channel contains more than host-linked chain (See Figure 14). logic list contains more than chain next last pointer fields valid. logic list either empty contains only host-linked chain next last pointer fields invalid.
Next Pointer [13:0] Offset head next host-linked chain read. (See Figure Transmit Descriptor Linking described above, TCDR table contains pointers which TMAC uses construct linked lists data packets transmitted. After host places Ready queue, TMAC retrieves links pointed Last Pointer field. TMAC create linked lists, viz. high-priority list low-priority list each channel. Whenever data packet requested downstream block, TMAC picks packet from high-priority linked list unless empty, which case, packet from low-priority linked list used.
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Figure Linking
Curr. Next Last Host
CE=0 TMAC Link
CE=0 TMAC Link
CE=1
TCDR Table
Host Link
Data
Host Link
Data
CE=0
CE=1
Data
Host Link
Data
CE=0
Data
Host Link
CE=1
Data
host links vertically while TMAC links horizontally. Figure shows packets linked host before placed TDRR queue, packet Packet linked packet TMAC, packet linked packet TMAC indicates valid horizontal links setting logic
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9.6.2 Task Priorities TMAC must perform number tasks concurrently order maintain steady flow data through system. main tasks TMAC managing Ready Queue (i.e. removing chains data packets from queue attaching them appropriate per-channel linked list) servicing requests data from Transmit Packet Interface. priority service each tasks fixed TMAC priority given servicing `expedited' read requests from Transmit HDLC Processor Partial Packet Buffer block (THDL). Second priority given removing chains data packets from TDRR queue attaching them appropriate per-channel linked list. Third priority given servicing non-expedited read requests from THDL.
9.6.3 Transaction Controller Transaction Controller coordinates processing requests from THDL with reading data stored host memory. reading data packet require number separate host memory transactions, interleaved with transactions other channels. well reading data from Host Master Interface, Transaction Controller initiates read write transactions Controller block (GPIC) purposes maintaining data structures (queues, descriptors, etc.) host memory. 9.6.4 Read Data Pipeline Read Data Pipeline inserts delay data stream between GPIC interface THDL interface enable Transaction Controller generate appropriate control signals Transmit Packet Interface. 9.6.5 Descriptor Information Cache Descriptor Information Cache provides storage Transmit Channel Descriptor Reference (TCDR) Table. 9.6.6 Free Queue Cache Free Queue Cache block implements element Free Queue cache. Caching TDRs reduces number host accesses that TMAC makes.
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TDRs written cache time they released TMAC. cache then flushed host memory when becomes full, when with high released when released result unprovisioning channel. cache controller also flush cache when contains fewer than elements pointer index within elements free queue. write pointer near free queue, cache controller writes only queue does start writing from queue until next time flush required. would require host memory transactions would benefit. Transmit HDLC Controller Partial Packet Buffer Transmit HDLC Controller Partial Packet Buffer block (THDL) contains partial packet buffer latency control transmit HDLC controller. Packet data retrieved from host memory Transmit Controller block (TMAC) stored channel specific FIFOs residing partial packet buffer. When amount data FIFO reaches programmable threshold, HDLC controller enabled initiate transmission. HDLC controller performs flag generation, stuffing and, optionally, frame check sequence (FCS) insertion. software selectable CRC-CCITT CRC-32. minimum packet size, excluding FCS, bytes. single byte payload illegal. HDLC controller delivers data Transmit Channel Assigner block (TCAS) demand. packet progress aborted under-run occurs. THDL programmable operate transparent mode where packet data retrieved from host transmitted verbatim. 9.7.1 Transmit HDLC Processor HDLC processor time-slice state machine which process independent channels. state vector provisioning information each channel stored RAM. Whenever TCAS requests data, appropriate state vector read from RAM, processed finally written back RAM. HDLC state-machine configured perform flag insertion, stuffing generation. HDLC processor requests data from partial packet processor whenever request channel data arrives. However, HDLC processor does start transmitting packet until entire packet stored channel FIFO until FIFO free space less than software programmable limit. channel FIFO under-runs, HDLC processor aborts packet. configuration HDLC processor accessed using indirect channel read write operations. When indirect operation performed, information accessed from during null clock cycle inserted TCAS
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block. Writing provisioning data channel resets channel's entire state vector. 9.7.2 Transmit Partial Packet Buffer Processor partial packet buffer processor controls Kbyte partial packet which divided into byte blocks. block pointer used chain partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous sections allocated partial packet buffer create channel FIFOFigure shows example three blocks (blocks 200) linked together form byte channel FIFO. three pointer values would written sequentially using indirect block write accesses. When channel provisioned with this FIFO, state machine initialised point three blocks. partial packet buffer processor divided into three sections: reader, writer roamer. roamer time-sliced state machine which tracks each channel's FIFO buffer free space signals writer service particular channel. writer requests data from TMAC block transfers packet data from TMAC associated cha
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