PM73487 Long Form Data Sheet PMC-980618 Issue Mbps
|
|
|
Top Searches for this datasheet
PM73487
Long Form Data Sheet
PMC-980618
Issue
Mbps ATraffic Management Device
PM73487 Mbps ATraffic Management Device
DATASHEET
Released Issue 1999
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
AAL1gator, AAL1gator2, Evil Twin Switching, QRT, QSE, SATURN trademarks PMC-Sierra, Inc. AMCC registered trademark Applied MicroCircuits Corporation. i960 registered trademark Intel Corporation. National Semiconductor registered trademark National Semiconductor Corporation. trademark PMC-Sierra, Inc. Vitesse trademark Vitesse Semiconductor Corporation. other brand product names trademarks their respective companies organizations.
U.S. Patents 5,557,607, 5,570,348, 5,583,861
Copyright 1998 PMC-Sierra, Inc. Rights Reserved
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Public Revision History
Issue Number
Issue Issue
Issue Date
March 1998 October 1998
Details Change
Creation Document This data sheet includes: registers added version device: RX_QUEUE_ENGINE_TEST bits 26:16 TX_QUEUE_ENGINE_TEST bits 22:15 QUEUE_ENGINE_CONDITION_PRES_BIT QUEUE_ENGINE_CONDITION_LATCH_B QUEUE_ENGINE_INT_MASK RX_LOWER16_SCG_CONFIG RX_LOWER16_SCG_STATE RX_LOWER32_SCG_CONFIG RX_LOWER32_SCG_STATE RX_LOWER48_SCG_CONFIG RX_LOWER48_SCG_STATE TX_LOWER4_SCG_CONFIG TX_LOWER4_SCG_STATE TX_LOWER8_SCG_CONFIG TX_LOWER8_SCG_STATE TX_LOWER12_SCG_CONFIG TX_LOWER12_SCG_STATE Updated RX_SERVICE_TABLE Production Release Version
Issue
June 1999
1999 PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby Canada Phone: 604.415.6000 FAX: 604.415.6200
event, part this document reproduced form without express written consent
PM73487
Long Form Data Sheet
PMC-980618
Issue
Mbps ATraffic Management Device
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Table Contents
System Applications System Overview Mbps Switch Configuration. Switch Application Gbps) Switch Application Gbps) Gbps Gbps Application Example Seamless Growth Gbps Gbps Application Example LAN-to-WAN Theory Operations Overview. Interface Descriptions 2.2.1 Switch Fabric Interface. 2.2.2 Phase Aligners 2.2.3 UTOPIA Interface 2.2.4 Cell Buffer SDRAM Interface 2.2.5 Channel (CH_RAM) Interface 2.2.6 Address Lookup (AL_RAM) Interface 2.2.7 AB_RAM Interface 2.2.8 Host Processor Interface 2.2.9 SE_SOC Encodings 2.2.10 BP_ACK Encodings 2.2.11 Relation Between External CELL_START Local CELL_START Cell Flow Overview UTOPIA Operation. 2.4.1 General 2.4.2 UTOPIA Interface Receiver Operation 2.5.1 Receive Channel Lookup 2.5.2 Receive (Channel) Queuing 2.5.3 Receive Channel Ring 2.5.4 Receive Congestion Management 2.5.5 Receive Queue Service Algorithm 2.5.6 Receive Sequencing Algorithm Transmitter Operation. 2.6.1 Transmit Queuing 2.6.2 Transmit Congestion Management. 2.6.3 Transmit Queue Service Algorithm 2.6.4 Transmit Resequencing Algorithm. 2.6.5 Transmit Recovery Algorithm 2.6.6 Transmit Multicast Cell Background Process 2.6.7 Transmit Multicast Congestion Management. System Diagram Internal Blocks External
Fault Tolerance
viii
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Data Path 3.1.1 UTOPIA Interface 3.1.2 Switch Fabric Interface. Fault Detection Isolation 3.2.1 Memory Parity Checking 3.2.2 UTOPIA Interface Fault Detection Recovery Mechanisms 3.2.3 Switch Fabric Fault Detection Recovery Mechanisms 3.2.4 Tables Switch Fabric Interface Failure Behaviors Descriptions Package Diagram Signal Locations Signal Descriptions (372 Signal Pins) 4.3.1 Processor Interface Signals. 4.3.2 Statistics Interface Signal 4.3.3 Switch Element Interface Signals. 4.3.4 CH_RAM Interface Signals 4.3.5 AL_RAM Interface Signals 4.3.6 ABR_RAM Interface Signals 4.3.7 Receive Cell Buffer DRAMs 4.3.8 Transmit Cell Buffer DRAMs 4.3.9 UTOPIA ALayer Interface Signals 4.3.10 Boundary Scan Signals 4.3.11 Miscellaneous Signals Timing Diagrams UTOPIA Timing DRAM External Memory Timing SRAM Timings. QRT-QSE Interface Timing 6.4.1 Switch Fabric Cell Formats Processor Interface Timing Miscellaneous Timing.
Physical Characteristics
Microprocessor Ports Microprocessor Ports Summary Microprocessor Ports Definitions 7.2.1 REVISION 7.2.2 RESET 7.2.3 TEST_CONFIG 7.2.4 SRAM_CONFIG 7.2.5 SWITCH_CONFIG 7.2.6 BIST RESULT 7.2.7 MARKED_CELLS_COUNT 7.2.8 CONDITION_PRES_BITS 7.2.9 CONDITION_LATCH_BITS
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
7.2.10 INTR_MASK 7.2.11 UTOPIA_CONFIG. 7.2.12 UT_PRIORITY. 7.2.13 UT_ENABLE 7.2.14 TX_UT_STAT 7.2.15 TX_UT_WD_ALIVE 7.2.16 RX_CELL_START_ALIGN (Internal Structure) 7.2.17 RX_QUEUE_ENGINE_TEST. 7.2.18 TX_QUEUE_ENGINE_TEST QUEUE ENGINE CONDITION_PRES_BITS QUEUE_ENGINE_INT_MASK 7.2.22 RX_DIR_CONFIG 7.2.23 RX_DIR_STATE (Internal Structure) 7.2.24 TX_DIR_CONFIG 7.2.25 TX_DIR_STATE (Internal Structure) 7.2.26 RX_SENT_CELLS 7.2.27 RX_DROPPED_CELLS 7.2.28 TX_SENT_CELLS. 7.2.29 TX_DROPPED_CELLS RX_LOWER16_SCG_CONFIG RX_LOWER16_SCG_STATE (Internal State) RX_LOWER32_SCG_CONFIG RX_LOWER32_SCG_STATE (Internal State) RX_LOWER48_SCG_CONFIG RX_LOWER48_SCG_STATE (Internal State) TX_LOWER4_SCG_CONFIG TX_LOWER4_SCG_STATE (Internal State) TX_LOWER8_SCG_CONFIG TX_LOWER8_SCG_STATE (Internal State) TX_LOWER12_SCG_CONFIG TX_LOWER12_SCG_STATE (Internal State) Internal Memory Internal Summary Transmit Service Class (TSC_RAM) Summary. 8.2.1 Transmit Service Class Queue SCQ) Control Block Receive Service Class (RSC_RAM) Summary 8.3.1 Receive Service Class Control Block Virtual Output Control (VO_RAM) Summary. 8.4.1 Transmit Control Block 8.4.2 Transmit Control Block 8.4.3 Transmit Multicast Control Block Summary Receive Switch Fabric Control (RSF_CONTROL) Summary. 8.5.1 RX_RSF_CONFIG (Internal Structure)
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
8.5.2 RX_RSF_TAG (Internal Structure) 8.5.3 RX_RSF_NEW_VPI_VCI (Internal Structure) 8.5.4 RX_RSF_SN_CHAN (Internal Structure) 8.5.5 RX_RSF_ER_CELL_PTR (Internal Structure) Transmit Switch Fabric Control (TSF_CONTROL_RAM) Summary 8.6.1 TX_TSF_SN_CHAN (Internal Structure) Test Access Receive UTOPIA (RU_RAM) Test Access Transmit UTOPIA (TU_RAM) Test Access Receive Switch Element (RS_RAM) 8.10 Test Access Transmit Swith Element (TS_RAM) External Memory External Summary Address Lookup (AL_RAM) 9.2.1 VI_VPI_TABLE. 9.2.2 VCI_TABLE. 9.2.3 Multicast Cell Instance Control Block (Internal Structure) 9.2.4 RX_NEXT_CELL (Internal Structure) 9.2.5 Transmit Cell Buffer Control Block (Internal Structure) 9.2.6 Service Order Control Block (Internal Structure) Channel (CH_RAM). 9.3.1 Channel Control Block 9.3.2 Multicast Control Block ABR_RAM 9.4.1 Receive Channel Queue Block 9.4.2 Receive Channel Statistics Block SDRAM/SGRAM Interface Description 9.5.1 RX_DRAM_REGISTER 9.5.2 TX_DRAM_REGISTER 9.5.3 Receive Cell Buffer SDRAM/SGRAM Summary (Internal Structure) 9.5.4 Transmit Cell Buffer SDRAM/SGRAM Summary (Internal Structure)
JTAG Application Notes 11.1 Connecting QRTs QSEs Using Gigabit Ethernet Transceivers 11.2 Connecting Standard Serializer/Deserializer Chipsets 11.3 Connecting S/UNI-ATLAS PM7324. 11.4 Relationships Among Various Clock Domains 11.4.1 Relationship Among SYSCLK, SE_CLK, Switch Speed-Up Factor 11.4.2 Phase Aligner SE_CLK Frequency Constraint 11.4.3 SYSCLK DRAM Refresh Constraint 11.4.4 Relationship Between ATM_CLK SYSCLK 11.4.5 Relationship Between PCLK SYSCLK
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
List Figures
Figure System Block Diagram Figure System Overview. Figure Mbps Switch Configuration. Figure Switch Application Gbps) Figure Switch Application Gbps) Figure Gbps ASwitch Using Dual S/UNIs, QRTs, Figure Gbps ASwitch Using Dual S/UNIs, QRTs, QSEs Figure Gbps ASwitch Using Dual S/UNIs, QRTs, QSEs Figure Gbps Gbps Switches Modeled Using Only Cards Figure Gbps ASwitch. Figure Gbps ASwitch. Figure Gbps ASwitch. Figure Gbps ASwitch. Figure System Overview. Figure SE_SOC Encodings Figure BP_ACK Encodings Figure Cell-Level Timing Figure Data Flow Diagram Figure Receive UTOPIA Operation. Figure Transmit UTOPIA Operation Figure Receive Standard Single Cell Available Polling Figure Transmit Standard Single Cell Available Polling. Figure Receive UTOPIA Multiplexed Status Polling (MSP), Including Cell Transfer. Figure Transmit UTOPIA Multiplexed Status Polling (MSP), Including Cell Transfer. Figure Channel Lookup Figure Channel Lookup. Figure Channel Linked List Figure Channel Linked List Cell Arrives Figure Channel Linked List Cell Sent Fabric. Figure Receive Channel Ring Figure Receive Channel Ring after Channel_A Becomes Run-Limited Figure Receive Channel Ring after Channel_B Served Run-Limited. Figure Receive Channel Ring After Channel_A Gets Cell Through Fabric Added Ring. Figure Receive Congestion Limits. Figure EPD/PTD Operation Figure EPD/PTD with Operation. Figure EFCI Operation. Figure Steps Send Cell Fabric. Figure Receive Service Class (SC) Map. Figure Transmit Per-SCQ Linked List. Figure Transmit Maximum Congested Threshold Checks Figure Transmit Service Class (SC) (Per
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Figure Cell Playout Steps. Figure Transmit Resequencing Operation Figure Multicast Background Process Figure Multicast Pointer FIFO Operation Figure System Diagram Internal Blocks External Figure Basic Data Path Through Switch Figure 503-Pin EPBGA Side Views (Part Figure 503-Pin EPBGA Bottom View (Part Figure Receive UTOPIA Timing. Figure Transmit UTOPIA Timing Figure Receive DRAM External Memory Read Timing. Figure Receive DRAM External Memory Write Timing Figure Transmit DRAM External Memory Read Timing Figure Transmit DRAM External Memory Write Timing Figure Address Lookup Read Timing Figure Address Lookup Write Timing. Figure Channel Read Timing. Figure Channel Write Timing Figure Read Timing. Figure Write Timing Figure Bit-Level Timing Figure Microprocessor Read Timing Figure Reset Timing. Figure JTAG Timing Figure Transmit Service Class (TSC_RAM) Memory Figure Receive Service Class (RSC_RAM) Memory Figure Virtual Output Control (VO_RAM) Memory Figure Boundary Scan Architecture. Figure Controller Finite State Machine Figure Connecting Gigabit Ethernet Transceivers Figure Connecting RCMP-800
xiii
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
List Tables
Table Backpressure Acknowledgment Encodings Table Failure Conditions, IRT-to-Switch Fabric Interface Table Failure Conditions, Receive Interface Table Failure Conditions, Transmit Interface Table Failure Conditions, Switch Fabric-to-ORT Interface Table Faults Effects Network Table Signal Locations Table Processor Interface Signals Pins) Table Statistics Interface Signal Pin) Table Switch Element Interface Signals Pins) Table Interface Signals Pins) Table Address Lookup Interface Signals Pins) Table ABR_RAM Interface Signals Pins) Table Receive Cell Buffer Interface Signals Pins) Table Transmit Cell Buffers Interface Signals Pins) Table Transmit UTOPIA ALayer Interface Signals Pins) Table Receive UTOPIA ALayer Interface Signals Pins) Table Test Signals Signal Pins) Table Miscellaneous Signals Signal Pins) Table Estimated Package Thermal Characteristics Table QRT-QSE Interface Cell Format. Table QRT-QSE Interface Idle Cell Format Table Microprocessor Ports Summary Table Various ways configure UTOPIA interface. Table Internal Summary Table Transmit Service Class Queue SCQ) Control Block Summary Table Receive Service Class Control Block Summary. Table Transmit Control Block Summary Table Transmit Control Block Summary Table Transmit Multicast Control Block Summary. Table Receive Switch Fabric Control (RSF_CONTROL) Summary Table Receive UTOPIA Cell Buffers Summary Table Transmit UTOPIA Cell Buffers Summary Table Address Lookup (AL_RAM) Summary Table Determining NUM_VPI Value Table VI_VPI_TABLE Entry VPC_ENTRY Table VI_VPI_TABLE Entry VPC_ENTRY Table Service Order Control Block Summary Table Channel (CH_RAM) Summary Table Channel Control Block Summary Table Multicast Control Block Summary Table AB_RAM Summary
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Table Receive Channel Queue Block Summary Table Receive Channel Queue Block Summary Table Receive Cell Buffers SDRAM/SGRAM Summary Table Transmit Cell Buffers SDRAM/SGRAM Summary Table Boundary Scan Order Table Prefixes Associated Functions Table Selection Table Ordering Information
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Product Overview
PM73487 Mbps ATraffic Management Device (QRTTM) advanced communications device capable supporting very large, high-performance Aswitching systems. rich feature enables systems offer many sophisticated network services. provides Mbps UTOPIA (Level Level access switch fabrics composed PM73488 Gbps ASwitch Fabric Elements (QSEs). Together, these devices used build architectures with capacities from Mbps Gbps. also standalone Mbps switch. QRT/QSE architecture virtually eliminates head-of-line blocking means QRT's perVirtual Channel (VC) receive queues congestion feedback from QSEswitch fabric. distributed architecture acts output-buffered switch incorporating Evil Twin Switching(a congestion-reducing routing algorithm switch fabric) speed-up factor switch fabric (running fabric faster than line rate). uses per-VC receive queues, receive Service Classes (SCs), transmit each Virtual Outputs (VOs) enable flexible multi-priority scheduling algorithms. scheduler used ensure Quality-of-Service (QoS) guarantees Constant Rate (CBR), Variable Rate (VBR), Unspecified Rate (UBR) VCs. also provides five separate congestion thresholds, each with hysteresis, that selectively control AAL5 Early Packet Discard (EPD) and/or Cell Loss Priority (CLP)-based cell dropping support. Additional highlights include full Virtual Path Indicator (VPI)/Virtual Channel Indicator (VCI) header translation, separate input output cell buffers each), Virtual Path (VP)/VC switching, support both receive transmit sides. PMC-Sierra also offers Device Control Package, which software package that harnesses QRT's rich feature shortens system development times. FEATURES
QUEUING ALGORITHMS
Receive
Maintains weighted, bandwidth-controlled with per-VC queues. Provides round-robin servicing queues within each Provides per-channel VC), per-SC, per-direction congested maximum queue depth limits. Provides cell buffers. Provides VOs. Maintains each with per-VC accounting.
Transmit
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Provides per-channel VC), per-SC Queue (SCQ), per-SC, per-VO, perdirection congested maximum queue depth limits. Provides cell buffers. Supports Partial Packet Discard (PPD) traffic, backup traffic. Supports CLP-based cell discard Explicit Forward Congestion Indicator (EFCI) cell marking. Supports three congestion limits well EPD, CLP, EFCI, and/or backpressure) logical multicast transmit side. Supports switching. Supports VCs. Supports bits through double, indirect lookup table. Performs header translation both input (receive) output (transmit) directions. Input header translation used pass output queue channel number through switch. Supports logical multicast with superior queue-clearing algorithm. Checks header parity. Counts tagged cells. Runs error checks continually fabric lines. Checks liveness control signal lines both switch fabric UTOPIA interfaces, working around partial fabric failures. Checks Static Random Access Memory (SRAM) Dynamic Random Access Memory (DRAM) parity. receive direction, counts cells transmitted dropped. transmit direction, counts cells transmitted dropped per-VC basis. Provides four switch element interfaces with phase aligners. phase aligners allow external serialization data stream enabling systems built that support device separation meters. Provides UTOPIA Level Multi-PHY (MPHY) 16-bit, interface. Provides 2-level priority servicing algorithm high bandwidth UTOPIA layer devices. Provides multiplexed address/data interface.
CONGESTION MANAGEMENT ALGORITHMS
SWITCHING
ADDRESS MAPPING
MULTICAST
DIAGNOSTIC/ROBUSTNESS FEATURES
STATISTICS FEATURES
FEATURES
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Provides MHz, 32-bit, synchronous DRAM cell buffer interfaces. Provides three MHz, synchronous SRAM control interfaces. Provides JTAG boundary scan interface. Compatible with AForum 3.0, 3.1, specifications. Compatible with AForum UTOPIA Level Level specifications. Compatible with PM73488 AQSE. supply voltage. tolerant inputs microprocessor UTOPIA interfaces. Available 503-pin Enhanced Plastic Ball Grid Array (EPBGA) package.
COMPATIBILITY FEATURES
PHYSICAL CHARACTERISTICS
BLOCK DIAGRAM Figure shows system block diagram.
Receive Cell SDRAM
Receive UTOPIA
Control SSRAM
Transmit UTOPIA
Mbps ATraffic Device (QRT) PM73487
Switch Fabric Host Interface From Switch Fabric
Transmit Cell SDRAM
Figure System Block Diagram
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
SYSTEM APPLICATIONS QRT, together with QSE, support wide range high-performance Aswitching systems. These systems range size from Mbps Gbps. systems developed such that this scalability provided with linear cost. Another feature QRT/QSE architecture that exceptionally fault-tolerant, both switch fabric UTOPIA interface. This section contains quick overview several example applications: stand-alone Mbps switch using single QRT, Gbps switch using QRTs QSE, Gbps switch using QRTs QSEs, switch architecture using QRTs QSEs that scales from Gbps Gbps, switch architecture using QRTs QSEs that scales from 5Gbps Gbps
System Overview
provides Mbps input output buffered access switch fabrics composed QSEs PM73488s). addition, supports stand-alone, purely output-buffered Mbps switch mode. Head-of-line blocking, commonly associated with input buffers, virtually eliminated per-VC receive queues, three types per-cell switch fabric feedback, perVC cell selection algorithms. also provides eight separate congestion thresholds, each with hysteresis, that selectively control AAL5 Early Packet Discard (EPD)/Packet Tail Discard (PTD), CLP-based cell dropping, and/or EFCI marking. Eight separate maximum thresholds also supported. Additional highlights include full VPI/VCI header translation, separate input output cell buffers each), Virtual Path Connection (VPC)/Virtual Channel Connection (VCC) connections, VCs. provides bidirectional connection between UTOPIA Level interface 4-nibble wide, switch fabric interfaces, shown Figure page significant switch speed-up factor, times line rate, used support full throughput many switch fabric configurations.
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Cells stored per-VC queues input respond per-cell Receive UTOPIA Level Interface Physical and/or ALayers Control SSRAM Transmit UTOPIA Level Interface
Input Cell SDRAM Receive (PM73487) Receive Nibble Data Transmit Nibble Data Transmit Feedback
Multicast SRAM
(PM73488)
Cells stored perpriority queues output with per-VC accounting
Output Cell SDRAM
Figure System Overview
Mbps Switch Configuration
used stand-alone application that supports Aswitching Mbps, shown Figure four switch fabric interfaces looped back QRT, allowing UTOPIA interface fully used. this application, operates output buffered switch.
UTOPIA Level Multi-PHY Interface
AAL1 Processor (PM73121)
(PM73487)
155M
S/UNI-QUAD (PM5349)
155M
Figure Mbps Switch Configuration
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Switch Application Gbps)
Figure shows basic switch application Gbps) using eight QRTs QSE.
Mbps Aggregate (PM73487) Receive Input Receive UTOPIA Level Mbps Aggregate (PM73487) Receive Input
(PM73487)
Mbps Aggregate
Transmit Output Transmit UTOPIA Level (PM73487) Transmit Output Mbps Aggregate
(PM73488)
Figure Switch Application Gbps)
Switch Application Gbps)
Figure shows switch application Gbps) using QRTs QSEs. This application uses QSEs 3-stage fabric. This sized system implemented single 19-inch rack.
Mbps Aggregate Receive UTOPIA Level Mbps Aggregate (PM73487) Receive Input
(PM73487) Transmit Output
Mbps Aggregate Transmit UTOPIA Level
(PM73487) Receive Input
(PM73488)
(PM73488)
(PM73488)
(PM73487) Transmit Output
Mbps Aggregate
Mbps Aggregate
(PM73487) Receive Input
(PM73488)
(PM73488)
(PM73488)
(PM73487) Transmit Output
Mbps Aggregate
Receive UTOPIA Level Mbps Aggregate (PM73487) Receive Input
Transmit UTOPIA Level (PM73487) Transmit Output Mbps Aggregate
Figure Switch Application Gbps)
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Gbps Gbps Application Example Seamless Growth
This section illustrates modularity (PM73487) (PM73488) architecture. Gbps system immediately created shown Figure page then upgraded Gbps shown Figure page Gbps shown Figure page Since these systems based single-stage switch fabric, per-port cost each system will remain same.
Eight Mbps Interfaces
Port Card QRTs (PM73487s)
Eight Mbps Interfaces
Port Card QRTs (PM73487s) Switch Card (PM73488) Port Card QRTs (PM73487s)
Eight Mbps Interfaces
Eight Mbps Interfaces
Port Card QRTs (PM73487s)
Figure Gbps ASwitch Using Dual S/UNIs, QRTs,
Eight Mbps Interfaces
Port Card QRTs (PM73487s) Switch Card (PM73488)
Eight Mbps Interfaces Port Card QRTs (PM73487s)
Switch Card (PM73488)
Figure Gbps ASwitch Using Dual S/UNIs, QRTs, QSEs
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Eight Mbps Interfaces
Port Card QRTs (PM73487s)
Switch Card (PM73488)
Eight Mbps Interfaces Port Card QRTs (PM73487s)
Switch Card (PM73488)
Switch Card (PM73488)
Switch Card (PM73488)
Figure Gbps ASwitch Using Dual S/UNIs, QRTs, QSEs
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Gbps Gbps Application Example LAN-to-WAN
powerful application devices creation modules that used range switches with only interconnection changing between different sizes. Aswitches from Gbps Gbps realized with only unique cards. port card QRT, switch card QSEs. switch fabric consists three stages, each with QSEs switch cards). plan future scalability, middle stage must built-in upfront. This one-time cost. Then, order scale Gbps increments, switch card accompanying eight port cards should added. Finer bandwidth scaling possible populating additional switch card with port cards needed increments Mbps). With this switch fabric topology, scaling possible Gbps. Once initial middle stage cost been incurred, per-port cost Gbps through Gbps systems remains almost constant
Port Card UTOPIA Level Interface (PM73487
Switch Card QSEs (PM73488 (PM73488
Figure Gbps Gbps Switches Modeled Using Only Cards
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Mbps
Port Card Input Port Card Input
Mbps
Switch Card Stage Switch Card
Switch Card Stage
Port Card Output Port Card Output
Mbps
Mbps
Switch Card
Switch Card
Figure Gbps ASwitch
Figure shows Gbps Aswitch using port cards QRTs) switch cards QSEs). middle stage composed switch cards. Gbps bandwith achieved adding switch card (which depicted using boxes: stage stage QSE), eight port cards (each which depicted using boxes: input side, output side). Lines between stage stage stage stage switch cards represent sets wires, each QSEs middle stage switch cards.
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
.Figure shows Gbps Aswitch using port cards QRTs) switch cards QSEs). Here, another switch card eight port cards have been added Gbps switch depicted Figure
Mbps Port Card Input Port Card Input Port Card Input Port Card Input Port Card Output Port Card Output Port Card Output Port Card Output Mbps
Mbps
Switch Card Stage Switch Card
Switch Card Stage
Mbps
Mbps
Mbps
Mbps
Switch Card Stage
Switch Card Stage
Mbps
Switch Card
Switch Card
Figure Gbps ASwitch
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Figure shows Gbps Aswitch using port cards QRTs) switch cards QSEs).Here, once again, another switch card eight port cards have been added
Mbps Mbps
Port Card Input Port Card Input Port Card Input Port Card Input Port Card Input Port Card Input
Mbps
Switch Card Stage Switch Card
Switch Card Stage
Port Card Output Port Card Output Port Card Output Port Card Output Port Card Output Port Card Output
Mbps
Mbps
Mbps
Mbps
Switch Card Stage
Switch Card Stage
Mbps
Mbps
Mbps
Mbps
Switch Card Stage Switch Card
Switch Card Stage
Mbps
Switch Card
Figure Gbps ASwitch
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Figure shows Gbps Aswitch composed port cards QRTs) switch cards QSEs). adding additional sets switch card eight port cards same manner, this system scale Gbps.
Mbps Mbps
Port Card Input Port Card Input Port Card Input Port Card Input Port Card Input Port Card Input Port Card Input Port Card Input
Mbps
Switch Card Stage Switch Card
Switch Card Stage
Port Card Output Port Card Output Port Card Output Port Card Output Port Card Output Port Card Output Port Card Output Port Card Output
Mbps
Mbps
Mbps
Mbps
Switch Card Stage
Switch Card Stage
Mbps
Mbps
Mbps
Mbps
Switch Card Stage Switch Card Switch Card Stage
Switch Card Stage
Mbps
Mbps
Mbps
Mbps
Switch Card Stage
Mbps
Switch Card
Figure Gbps ASwitch
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
THEORY OPERATIONS
Overview
Mbps, full duplex, intelligent routing table which, when used with switch fabric composed either devices, implement Aswitches from Mbps Gbps. supports 16-bit UTOPIA Level interface ease connection layer devices. Four nibble-wide data interfaces connect switch interface. External DRAM memory devices provide receive transmit cell buffering, external SRAM devices provide control data QRT. This section explains algorithms data flow. Figure shows overview system.
Receive Cell SDRAM
Receive UTOPIA Level Interface Control SSRAM Transmit UTOPIA Level Interface (PM73487)
Host Interface
From
Transmit Cell SDRAM
Figure System Overview
Interface Descriptions 2.2.1 Switch Fabric Interface
switch fabric interface consists four groups signals from both ingress (receive side) egress (transmit side). Each group consists Start-Of-Cell (SE_SOC_OUT) signal, nibble-wide data bus, backpressure acknowledgment (BP_ACK_IN) signal. Start-Of-Cell (SE_SOC_OUT) signal transmitted ingress same time beginning cell. SE_SOC_OUT ingress common four groups. BP_ACK_OUT signal flows from egress through switch fabric, direction opposite data, indicates whether cell successfully passed through switch fabric. Other signals associated with switch fabric interface switch element clock (SE_CLK) RX_CELL_START. support highest possible throughput various switch fabric configurations, clock speed-up factor used. That switch fabric rate that effectively times faster than line rate.
PM73487
PMC-980618 2.2.2 Phase Aligners
Issue
Mbps ATraffic Management Device
Phase aligners used allow extended device separation. technique used clock recovery mechanism that requires only switch fabric frequency synchronous. master clock distributed devices associated with switch fabric, phase clock each interface dynamically adjusted account skew introduced signals. phase aligner circuitry each interface responds cell start feedback signals, which contain high number transitions ensure accurate phase adjustment clock data signal sampling.
2.2.3 UTOPIA Interface
QRT's UTOPIA interface implements AForum standardized 16-bit, Level configuration, which supports Virtual Outputs (VOs) five address bits. layer devices with 16-bit UTOPIA Level functionality connected this interface, providing full duplex throughputs Mbps.
2.2.4 Cell Buffer SDRAM Interface
supports Synchronous DRAM (SDRAM SGRAM) interfaces providing cell buffering both receive transmit directions. Each interface consists 32bit data bus, 9-bit address bus, chip select signals, associated control signals. frequency these interfaces MHz. Both Synchronous Graphic (SGRAM) SDRAM devices supported. Clocking these interfaces provided through device.
2.2.5 Channel (CH_RAM) Interface
supports channels through Synchronous SRAM (SSRAM) interface. interface consists 32-bit data bus, 16-bit address bus, associated control signals. frequency this interface MHz. Clocking this interface provided through device.
2.2.6 Address Lookup (AL_RAM) Interface
data structures AL_RAM, including VPI/VCI address translation. interface consists 6-bit data bus, 17-bit address bus, associated control signals. frequency this interface MHz. Clocking this interface provided through device.
2.2.7 AB_RAM Interface
stores head tail pointers sent dropped counters receive direction AB_RAM. Each interface consists 17-bit multiplexed address/data associated control signals. frequency this interface MHz.
2.2.8 Host Processor Interface
host processor interface allows connection microprocessor through multiplexed 32-bit address/data bus. suggested microprocessor this interface Intel i960®. microprocessor direct access control registers.
PM73487
PMC-980618 2.2.9 SE_SOC Encodings
Issue
Mbps ATraffic Management Device
SE_SOC BP_ACK signals have guaranteed transitions special encodings, which defined this section "BP_ACK Encodings" which follows. SE_SOC_IN SE_SOC_OUT signals have guaranteed transitions encodings shown Figure SE_SOC signals carry repeating pattern four zeros four ones guarantee transitions required phase aligner. "Start-Of-Cell" data lines associated with SE_SOC line indicated change this pattern. valid SE_SOC, change pattern followed reset background pattern such that followed four zeros four ones. first nibble (PRES) header coincident with SE_SOC (change pattern).
SE_CLK SE_SOC_OUT ones. zeros ones zeros ones zeros. ones zeros. zeros ones zeros.
Tsesu Magnified Magnified Data Magnified SE_SOC_OUT ones
Tseho
Tsesu
PRES. zeros one. zeros
Figure SE_SOC Encodings
2.2.10
BP_ACK Encodings
Figure shows BP_ACK encodings.
Mode Data1 Data0 Inversion1 Data2 Inversion2 Code BP_ACK Base Pattern BP_ACK Signaling ones zeros zeros ones
Figure BP_ACK Encodings
BP_ACK_IN BP_ACK_OUT signals have guaranteed transitions, encodings. BP_ACK signal used signal backpressure/cell acknowledgment fabric (QSE) egress receive backpressure/cell acknowledgment ingress from fabric (QSE). ensure transitions required phase aligner, BP_ACK signal carries repeating four zeros, four ones pattern. actual information transferred through encoded 7-bit packets that start with change this background pattern. change inversion) line followed mode bit, followed bits coded message, second inversion (inverse first inversion). acknowledgment packet, this followed bits code exten-
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
sion (these bits future currently required "00"). case backpressure packet, next backpressure priority multicast cells, followed code extension bit. background reset four zeros four ones after transmission each packet. allow back-to-back acknowledgment backpressure packets. case back-to-back acknowledgment backpressure packets, receiving device inverted "1") followed rest packet instead reset background pattern. backpressure packet either none acknowledgment packet expected received during cell time. receipt multiple acknowledgment backpressure packets failure condition. Table describes backpressure acknowledgment encodings.
Table Backpressure Acknowledgment Encodings Mode Data Backpressure high priority multicast cell. Data Backpressure medium priority multicast cell. Data Backpressure priority multicast cell. Code Description Backpressure information. This signal present each cell time, regardless whether cell transmitted that link). This signal withheld problem detected input port. Signals response. Treated acknowledgment. Signals Mid-switch Negative ACKnowledgment (MNACK). Signals Output Negative ACKnowledgment (ONACK). Signals ACKnowledgment (ACK).
2.2.11
Relation Between External CELL_START Local CELL_START
Figure shows relationship between external RX_CELL_START local CELL_START signals.
RX_CELL_START Clock Cycle SE_CLK External RX_CELL_START Delta Delta Local CELL_START CELL_START Delay RX_CELL_START High
Figure Cell-Level Timing
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Delay between external RX_CELL_START local CELL_START programmable through RX_CELL_START_ALIGN register (refer "RX_CELL_START_ALIGN (Internal Structure)" page 122). local CELL_START impacts start cell transmission fabric. also determines period within cell time during which BP_ACK_IN(3:0) ingress valid. such, programmable CELL_START delay allows flexibility synchronize QRTs QSEs system.
Cell Flow Overview
functions Mbps port Aswitch fabric composed either devices. transfers cells between UTOPIA Level interface switch fabric interface. device supports header translation congestion management. basic flow cells through follows (see Figure page 19):
cell enters receive side from UTOPIA interface channel number looked cell then either dropped transferred receive cell buffer DRAM queued receive queue controller depending congestion management checks (both maximum congested thresholds device, Service Class Group (SCG), connection). When available cell time occurs, four cells selected receive-side scheduler, which reads cells from receive cell buffer DRAM transmits them from into switch fabric. Once cell received from switch fabric transmit side, again either dropped transferred transmit cell buffer DRAM queued transmit queue controller, depending congestion management checks (both maximum congested thresholds device, Service Class Group (SCG),Service Class Queue (SCQ), connection). When cell selected transmission transmit-side scheduler, removed from transmit cell buffer DRAM processed transmit multicast/header mapper corresponding header translation distribution.
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
cell then sent UTOPIA interface exits transmit side.
Receive SDRAM Cell Buffer Receive UTOPIA Level Interface
Receive UTOPIA Cell Buffer
Receive SDRAM Controller
Receive Channel Lookup Receive Queue Controller Transmit Queue Controller
Receive Switch Cell Buffer
Data
Feedback from
Control SSRAM
SSRAM Controller
Feedback
Transmit Multicast Background
Transmit Switch Cell Buffer
Data from
Transmit UTOPIA Level Interface
Transmit UTOPIA Cell Buffer
Transmit SDRAM Controller
Transmit SDRAM Cell Buffer
Figure Data Flow Diagram
UTOPIA Operation 2.4.1 General
Cells received from UTOPIA interface first processed receive channel lookup block then queued transmission within receive queue controller. cell waits receive cell buffer DRAM instruction from receive queue controller proceed switch fabric interface.
2.4.2 UTOPIA Interface
interfaces directly UTOPIA interface device without needing external FIFO. receive side UTOPIA 4-cell internal FIFO, transmit side contains another 4-cell internal FIFO. UTOPIA interface bits wide operates frequencies MHz. provides following modes: UTOPIA Level single-PHY interface UTOPIA Level multi-PHY interface
PM73487
PMC-980618 2.4.2.1
Issue UTOPIA Level Polling
Mbps ATraffic Management Device
UTOPIA interface offers three modes polling, UTOPIA Level specification: Standard single cell available polling Multiplexed Status Polling (MSP) using four cell available signals Direct status indication using four cell available signals These polling modes allow communicate with many different devices. Figure shows polling devices receive UTOPIA operation.
polls PHYs determine they have cells. Serial Device Serial Device Data Address Cell Available Serial Device (PM73487) Switch Fabric
Figure Receive UTOPIA Operation
Figure shows polling devices transmit UTOPIA operation.
Serial Device Serial Device Data Address Cell Available Serial Device (PM73487) From Switch Fabric polls PHYs determine they accept cells.
Figure Transmit UTOPIA Operation
PM73487
PMC-980618 2.4.2.1.1
Issue Standard Single Cell Available Polling
Mbps ATraffic Management Device
standard single cell available polling mode, cell available response occurs every clocks. Figure shows receive standard single cell available polling.
ATM_CLK RATM_DATA(15:0) RATM_ADD(4:0) /RATM_READ_EN RATM_CLAV(3:0) RATM_SOC
Figure Receive Standard Single Cell Available Polling
Figure shows transmit standard single cell available polling.
ATM_CLK TATM_DATA(15:0) TATM_ADD(4:0) /TATM_WRITE_EN TATM_CLAV(3:0) TATM_SOC TATM_PARITY
Figure Transmit Standard Single Cell Available Polling
PM73487
PMC-980618 2.4.2.1.2
Issue
Mbps ATraffic Management Device
Multiplexed Status Polling (MSP) Using Four Cell Available Signals
With using four cell available signals, four cell available responses occur every clocks. advantage offered mode improved response time service selection. With this method, possible poll devices single cell time. devices, however, must comply with this optional part UTOPIA Level specification. standard device configured this mode even though does support directly. effect this, eight devices configured with addresses Figure shows receive UTOPIA MSP, including cell transfer.
ATM_CLK RATM_DATA(15:0) RATM_ADD(4:0) /RATM_READ_EN RATM_CLAV(3:0) RATM_SOC
Figure Receive UTOPIA Multiplexed Status Polling (MSP), Including Cell Transfer
Figure shows transmit UTOPIA including cell transfer.
ATM_CLK TATM_DATA(15:0) TATM_ADD(4:0) /TATM_WRITE_EN TATM_CLAV(3:0) TATM_SOC TATM_PARITY
Figure Transmit UTOPIA Multiplexed Status Polling (MSP), Including Cell Transfer
PM73487
PMC-980618 2.4.2.1.3
Issue
Mbps ATraffic Management Device
Direct Status Indication Using Four Cell Available Signals
When configuring device, setting mode implicitly turns direct status indication, since subset implemented method.
2.4.2.2 Priority Encoding Table
Transmit UTOPIA selects devices service based upon: assigned PRIORITY PHY(refer "UT_PRIORITY" page 119). configuration (Time Division Multiplex) table presence cells QEngine cell available assertions received from PHYs. priority servicing beneficial when using multi-phy configurations UTOPIA bandwidth nearly fully subscribed.
2.4.2.2.1 Basic Level Priority Algorithm
When disabled (refer section 7.2.10 UTOPIA_CONFIG) device assigned either high UTOPIA priority based bandwidth device. Within priority level (high low), further control over service algorithm implemented assigning lowest numbered addresses highest bandwidth PHYs. general algorithm deciding which service follows:
High priority encoder highest service priority. From high priority PHYs, lowest address that indicated accept cell (and which cell present QEngine) selected. high priority selected, then priority considered next. priority encoder next highest service priority. lowest address that indicated accept cell (and which cell present QEngine) selected. priority selected then cell time wasted unless Watchdog configured operation, which case stale priority considered next. Watchdog only available Transmit side. Transmit Stale priority encoder lowest priority created devices that Watchdog deems stale. lowest address that been detected dead "stale" WatchDog (and which cell present Qengine) selected. cell played interface order relieve queue depth congestion. Watchdog plays role making best effort delivery, even though considered dead.
Caveat: Service selection performed each cell time with CLAV information gathered from previous cell time. This particularly important, when standard polling method used phy's polled single cell time. this mode, UTOPIA Priorities have relative meaning within address groups (0to7, 8to15, 16to24 25to31). example high priority address=1 will compete service with priority address=7, will compete service against priority address=10 since they different groups. conceivable that priority receive much service high priority phy. This could case address=10 only address group. will entire cell time bandwidth simply because there other phys compete with.
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
This problem does exist mode since CLAV information gathered cell time.
2.4.2.2.2 Basic Level Priority Algorithm
When enabled, (refer section 7.2.10 UTOPIA_CONFIG section 7.2.12 UT_ENABLE configuring Pool) another level added Basic Level Priority Algorithm. table primary service priority UTOPIA interface configured feature. Each cell time, pointer advanced through Pool round-robin fashion. When pointed cell present QEngine PHY, will selected. selected cell present QEngine PHY, selection process deferred Basic Level Priority Algorithm that cell time wasted. table most useful when configurations require uniformally distributed bandwidths, such 4xOC3 configurations. event that UTOPIA_CONFIG then servicing algorithm reduces Basic level Priority encoding scheme consisting above. Receive side operates same fashion Transmit side with exception Stale Priority level since there Watchdog present Receive side. UTOPIA Level specification designed support oversubscription lack multi-priority cell presence indications. interface assumes this case order operate correctly.
2.4.2.3 Independently Configurable Interfaces
receive transmit sides UTOPIA interface independently configurable either single-PHY OC-12 multi-PHY operation. RX_OC_12C_MODE, TX_OC_12C_MODE, UTOPIA_2 bits (refer section 7.2.11 "UTOPIA_CONFIG" starting page 117) configure device such operation. This allows versatility types environments that supported (for example, environments that contain high-speed, single-PHY devices supported, well environments which must perform single-chip, multi-PHY high-speed, single-PHY muxing operations). This versatility particularly helpful when interfacing PMC-Sierra, Inc. PM7322 RCMP-800 Operations, Administration, Maintenance (OAM) processor, since output that device interface similar single-PHY SATURN interface.
2.4.2.4 Output Channel Number Insertion
transmit side UTOPIA configured insert output channel identifier HEC/UDF field outgoing cells. output channel identifier value used transmit portion identify cells particular cell stream they come from fabric. Insertion configured means setting UTOPIA_CONFIG(7) register. configuration UTOPIA inserts value FFFFh HEC/UDF field. transmit UTOPIA does calculate outgoing cells.
PM73487
PMC-980618 Receiver Operation
Issue
Mbps ATraffic Management Device
2.5.1 Receive Channel Lookup
receive channel lookup uses tables: VI_VPI_TABLE (refer "VI_VPI_TABLE" page 175) VCI_TABLE (refer "VCI_TABLE" page 176) generate channel number incoming cell. channel number turn used access Channel Control Block (CCB), connection table. contains configuration state connection. Figure shows method used generate channel number VCCs: Virtual Input (VI) number bits used index into VI_VPI_TABLE entries Each entry contains base address block VCI_TABLE that size that block. VCI_TABLE entry contains channel number that VCC. other hand, channel VPC, VI_VPI_TABLE contains channel number directly (see Figure 26). number active bits modified during operation creating VCI_TABLE then changing VC_BASE VCI_BITS (refer "VCI_BITS" page 176) values point table write. This possible since BLOCK_OFFSET (refer "BLOCK_OFFSET" page 176) just pointer VCI_TABLE, VCI_TABLE holds state information. Thus, when first connection arrives, eventual size block initially guessed. Later, guess proves table grows big, there penalty: VCI_TABLE created on-the-fly. This method determining allows flexible wide range active bits without requiring expensive Content-Addressable Memory (CAM) causing fragmentation CCBs.
BLOCK_OFFSET, VCI_BITS Channel Number Channel Control Block (CCB)
VI_VPI_TABLE
VCI_TABLE (one table
Connection Table
Figure Channel Lookup
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Figure shows mapping VPCs.
Channel Number
Channel Control Block (CCB)
VI_VPI_TABL
Connection Table
Figure Channel Lookup
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
2.5.2 Receive (Channel) Queuing
Receive cells enqueued per-VC (channel) basis. This means that there queues. Singly-linked lists used queue cells. head pointers, tail pointers, linked lists external RAM. Figure Figure Figure show operation channel linked list structure.
Per-VC Linked List Channel Link
Head Tail
Link
Link
Figure Channel Linked List
Per-VC Linked List Link Channel
Head Tail
Link
Link Link
Figure Channel Linked List Cell Arrives
Per-VC Linked List Channel
Head Tail
Link
Link Link
Figure Channel Linked List Cell Sent Fabric
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
2.5.3 Receive Channel Ring
list channels eligible send cell fabric kept per-SC rings. ring kept external memory pointers previous current channels each kept internal memory. channel number entered into ring when first cell that channel arrives. While cells that channel present queuing system, channel removed from ring dequeue process channel run-limited because resequencing algorithm explained "Receive Sequencing Algorithm" page sometimes re-added ring process that updates data structures with results last cell time. Figure Figure Figure Figure page show operation receive channel ring.
Channel_B
Channel_A Service Class (SC) Current Channel Previous Channel_E
Channel_C
Channel_D
Figure Receive Channel Ring
Channel_B Service Class (SC) Current Channel Previous Channel_E Channel_C
Channel_D
Figure Receive Channel Ring after Channel_A Becomes Run-Limited
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Service Class (SC) Current Channel Previous Channel_E
Channel_B
Channel_C
Channel_D
Figure Receive Channel Ring after Channel_B Served Run-Limited
Channel_B Service Class (SC) Channel_A Current Channel Previous Channel_E Channel_C
Channel_D
Figure Receive Channel Ring After Channel_A Gets Cell Through Fabric Added Ring
2.5.4 Receive Congestion Management
receive queue controller maintains current, congested, maximum queue depth counts cells per-VC, per-SC, per-device basis. Three congestion management algorithms available per-channel basis. each channel's RX_CH_CONFIG word (refer section 9.3.1.1 "RX_CH_CONFIG" starting page 184) there bits that enable EPD, CLPbased discard, EFCI. These used combination. addition, supported mode operation.
Service Class (SC)
Channel
Device (DIR)
Figure Receive Congestion Limits
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
congestion hysteresis kept each threshold. This whenever queue depth exceeds congestion limit that threshold. This remains asserted until queue depth falls below one-half congestion threshold. Figure illustrates operation EPD/PTD.
Tail drop this frame
Maximum Threshold
Drop these frames Queue Depth
Congested Threshold
Congested Queue Depth
Always send last cell each
Time Cells arriving rate greater than rate which they being played out. End-Of-Frame (EOF) cell
Figure EPD/PTD Operation
Figure shows operation combination with CLP-based dropping.
Tail drop this frame
Maximum Threshold
Drop these frames Queue Depth
Congested Threshold
Congested Queue Depth
Always send last cell each
Time Cells arriving rate greater than rate which they being played out. End-Of-Frame (EOF) cell Cell Loss Priority (CLP)
Figure EPD/PTD with Operation
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Figure shows operation EFCI.
EFCI Codepoints Queue Depth From Here Here Congestion Threshold
Congestion Threshold
Time Time
Figure EFCI Operation
congestion limits kept exponential form. interpretation limits same measurements, except device limit. other measurements, value causes measurement always find congestion. value used. value causes congestion found limit when queue depth 31744. This allows 15-bit value used store state each measurement except device measurement, which 16-bit value.
2.5.5 Receive Queue Service Algorithm
Each switch fabric cell time, receive queue controller selects four cells transmission switch fabric. controller supports per-channel (per-VC) queues with SCs. controller addresses following issues: QoS, Cell Delay Variation (CDV) minimization, Minimum Cell Rate (MCR) guarantees, fairness maximization. flexibility controller ensures that receive their expected bandwidth timely fashion depending upon their traffic requirements.
Queue Service Algorithm determine Service Class (SC)
Read from ring determine channel
Find pointer cell from channel linked list
Fetch cell
Send cell fabric
Update structures with results transmission
Figure Steps Send Cell Fabric
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
controller scheduler that selects cells placed pipelined, "ping-pong" buffers. Once cell selected, placed these buffers. Each four outputs switch fabric buffers: while cell buffer being transmitted, another cell selected placed into buffer subsequent switch fabric cell time, buffers "ping-ponged", cell buffer sent. Meanwhile, another cell selected buffer exception this process when controller receives negative acknowledgment (NACK) transmission cell. There cases: NACK MNACK, indicating cell transmission failed collision middle network, else NACK ONACK, indicating cell transmission failed collision output network. former case, cell's switch fabric priority (assigned during setup) compared with that cell any) other ping-pong buffer. Call first cell second cell priority cell greater than equal that cell buffers ping-ponged, cell will resent next time. priority cell less than that cell cell remains buffer, buffers ping-ponged usual, with cell being sent next. latter case, cell requeued head VC's queue. Thus, cell will retransmitted, later time than cell MNACKed. switch fabric been specially designed minimize possibility consecutive collisions same place middle network, thus cell's transmission that failed that manner stands good probability being successful immediately subsequent transmission attempt. Collisions output network more likely recurring period time, thus next transmission attempt delayed. scheduler that places cells ping-pong buffers operates follows: arranged tabular fashion seen Figure designated either unicast multicast traffic. Additionally, designated either strict priority SC1, strict priority SC2, General Purpose (GP). Associated with each weight either This information
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
used controller decide which service. Following this decision, selected SC's serviced round-robin manner. selected then transmits first cell queue.
Unicast Traffic
Strict Priority Strict Priority Timeslot-Based Priority
Multicast Traffic
S125 S126
General Purpose (GP) Weighted RoundRobin
Round-Robin among within
Figure Receive Service Class (SC)
general algorithm deciding which service follows (certain multicast ineligible selection particular modes operating conditions; these will described after numbered list that follows):
Strict priority primary service priority. there with cell, will selected. service classes serviced weighted round-robin manner, alternating between unicast multicast classes (Q0, Q32, Q33, Q34, Q35, round-robin pointer will remain pointed cell selections, where SC's weight. cells available round-robin pointer advanced. Thus, most time-critical should placed service class. pointer service classes separate from pointer service classes. Strict priority secondary service priority. treated same fashion SC1, except independent round-robin pointer weighted round-robin order Q36, Q37, Q38, Q39, cell exists strict priority classes, then controller accesses timeslot-based priority table round-robin manner. Each entry this table contains number. pointed active entry cells, that selected. active entry incremented next timeslot each time timeslot table accessed. table entries wraps around. This servicing mechanism provides guarantee per-SC basis. number times placed timeslot table used determine MCR. cell exists strict priority classes, cell exists pointed active entry timeslot-based priority table, then serviced weighted round-robin manner similar classes (Q8, Q40, Q41, Q10, Q42, Q11, Q43, Q12, Q44, Q31, Q63, Again this separate round-robin pointer than that kept service classes.
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Certain multicast ineligible selection aggregate mode backpressure from switch fabric. multicast aggregate mode either aggregate mode each switch fabric outputs treated distinct outputs. Multicast connections must specifically assigned corresponding column multicast (there multicast SCs, with four columns eight classes each), since cells multicast must same output. this mode, only column (eight) multicast will eligible selection (for example, service classes Q32, Q36, Q40, Q44, Q48, Q52, Q56, correspond port service classes Q33, Q37, Q41, Q45, Q49, Q53, Q57, correspond port other three columns (total SCs) will ineligible. aggregate mode four outputs treated logical output, thus multicast selected four outputs. Additional ineligible backpressure from switch fabric. There three types backpressure: high, medium low. High backpressure renders eight multicast ineligible (Q32 Q39). Medium backpressure renders first eight ineligible (Q40 Q47, rows four). backpressure renders last ineligible (Q48 Q63, four rows four). receive queue controller scheduler provides following benefits: strict priority scheme between SC1, SC2, SCs, weighted roundrobin algorithms allow satisfaction guarantees. minimization treatment strict priority ensure cells within these timely service. guarantee timeslot table ensures will receive minimum amount servicing (clearly, aggregate bandwidth given affects remaining bandwidth divided between SCs). Fairness maximization weighted allows different support different bandwidth requirements (for example, high bandwidth assigned serviced times often bandwidth SCs, which assigned
2.5.6 Receive Sequencing Algorithm
service guarantees Aoffers FIFO delivery cells. Since send multiple cells from channel simultaneously across fabric, those cells will through first try, must support algorithm make sure cells back into order. algorithm supports classic window algorithm where only cells allowed outstanding without acknowledgment. QRT, either This limits data rate individual connection approximately Mbps. cells sequence numbered reordered transmit side. This algorithm implemented removing channel from ring eligible channels whenever cells outstanding. channel then called run-limited. also removes channel from ring last cell present been sent switch fabric. channel then called cell-limited. former case, will remain ring until fabric transmission results
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
run-completing cell known. every cell completes run. cell with modulo lower Sequence Number (SN) run-completing cell. that time will added back onto ring there more cells send that cell ONACKed, which case that cell resent. pointers these cells stored locations CCB. When starting from cells fabric, first cell sent always POINTER0 second cell always POINTER1. multicast unicast cells, setting available use, lower utility than setting virtually situations.
Transmitter Operation 2.6.1 Transmit Queuing
Transmit cells enqueued per-SC, per-VO basis. there VOs, VOs, there total queues. Singly linked lists used queue cells. head tail pointers internal linked lists external RAM. Figure shows example transmit per-SCQ linked list.
Per-SCQ Linked List Link Channel
Head Tail
Link
Link
Figure Transmit Per-SCQ Linked List
2.6.2 Transmit Congestion Management
cell received from switch fabric interface queued transmit queue controller passes buffer threshold checks: both maximum congested thresholds device, queue, channel shown Figure page cell waits transmit cell buffer DRAM until transmit queue controller selects transmit multicast/header mapping. cell then exits device through UTOPIA interface. congestion hysteresis kept each threshold. This whenever queue depth exceeds congestion limit that threshold. This remains asserted until queue depth falls below one-half congestion threshold. congestion limits kept exponential form. interpretation limits same measurements except device limit. other measurements, value causes measurement always find congestion. value used. value
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
causes congestion found limit when queue depth 31744. This allows 15-bit value used store state each measurement except device measurement, which 1-bit value.
Channel Service Class (SC) Queue
Virtual Output (VO)
Virtual Outputs (VOs)
Device Service Classes (SCs)
Figure Transmit Maximum Congested Threshold Checks
Three congestion management algorithms available per-channel basis. each channel's TX_CH_CONFIG word (refer section 9.3.1.7 "TX_CH_CONFIG" starting page 189) bits that enable EPD, CLP-based discard, EFCI. These used combination. addition, Packet Tail Discard (PTD) supported mode operation. Figure page illustrates operation EPD/PTD. Figure page illustrates operation EPD/PTD with CLP. described "Transmit Resequencing Algorithm" page there interaction between resequencing algorithm. Refer that section complete description.
2.6.3 Transmit Queue Service Algorithm
transmit queue controller supports each (the per-VO structure shown Figure page 38). with receive queue controller, transmit queue controller addresses following issues: QoS, minimization, guarantee, fairness maximization, output isolation.
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
which cell sent determined first doing bit-wise vectors: vector indicates presence cell other vector indicates willingness accept cell. matching VOs, lowest numbered high priority selected possible; otherwise, lowest numbered selected. Once known, controller scheduler that selects cell transmitted UTOPIA interface. scheduler operates follows: arranged tabular fashion seen Figure page designated either unicast multicast traffic. Additionally, designated either strict priority SC1, strict priority SC2, Associated with each weight either This information used controller decide which service. Following this decision, selected SC's cells serviced FIFO manner. general algorithm deciding which service similar that used receive queue controller, follows:
Strict priority primary service priority. there service class with cell, will selected. service classes serviced weighted round-robin manner, alternating between unicast multicast classes (Q0, round-robin pointer will remain pointed cell selections, where SC's weight. cells available round-robin pointer advanced. Thus, most time-critical should placed service class. Strict priority secondary service priority. treated same fashion SC1, except independent round-robin pointer, alternates: cell exists strict priority classes, then controller accesses timeslot-based priority table round-robin manner. Each entry this table contains number. pointed active entry cells, that selected. active entry incremented next timeslot each time timeslot table accessed. table entries wraps around. This servicing mechanism provides guarantee per-SC basis. number times placed timeslot table used determine MCR. cell exists strict priority classes, cell exists pointed active entry timeslot-based priority table, then serviced weighted round-robin manner simi-
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
classes (Q2, Q10, Q41, Q11, Q15,
Unicast Traffic
Strict Priority Strict Priority Timeslot-Based Priority General Purpose Weighted RoundRobin
Multicast Traffic
S125 S126
Cells FIFO-Queued within
Figure Transmit Service Class (SC) (Per
transmit queue controller scheduler provides following benefits: strict priority scheme among SC1, SC2, SCs, weighted roundrobin algorithms allows satisfaction guarantees. minimization treatment strict priority ensure that cells within these timely service. guarantee timeslot table ensures will receive minimum amount servicing (clearly, aggregate bandwidth given affects remaining bandwidth divided between SCs). Fairness maximization weights allow different support different bandwidth requirements (for example, high bandwidth assigned serviced times often bandwidth SCs, which assigned Output isolation cells channels destined different kept separate data structures. This helps isolate effects congestion from causing congestion another
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Figure illustrates steps that taken when playing cell.
Determine Queue Service Algorithm determine Service Class (SC) Find pointer cell from linked list
Fetch cell
Read OUTCHAN from cell buffer
Play cell update channel state
Figure Cell Playout Steps
2.6.4 Transmit Resequencing Algorithm
guarantee FIFO delivery cells, supports algorithm make sure cells back into order. algorithm supports classic window algorithm where only cells allowed outstanding without acknowledgment. QRT, either This limits data rate individual connection approximately Mbps. transmit reorders cells according their resequencing algorithm ignores incoming accepts cells their were correct. This used multicast cells delivers them FIFO order. resequencing algorithms inspects incoming cell determine expected does, cell immediately processed. then stored await run-completing cell (that cell with original expected neither recovery algorithm started which gets channel back into sequence. This described "Transmit Recovery Algorithm" page
Cell ONACKed Cells arrive receive UTOPIA
Cells numbered sent across fabric
Cells sent from transmit UTOPIA
Figure Transmit Resequencing Operation
resequencing algorithms interacts with EPD. When cell missing, algorithm cannot determine missing cell End-Of-Frame (EOF) cell. then necessary defer choice whether send both cells until run-completing cell received.
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
choice whether send drop more cells affected information, because frame that being dropped end, another frame that dropped start.
2.6.5 Transmit Recovery Algorithm
recovery algorithm needed resequencing algorithm since ignored. resequencing algorithms, when cell with received, neither equal expected cell number equal then cell dropped. expected (for next cell) next time consecutive cells received ascending order, channel will have recovered sequence. Using this algorithm, some legitimate cells dropped while recovering. example, next cells legitimate, received descending order, they will both dropped.
2.6.6 Transmit Multicast Cell Background Process
transmit multicast background process traverses linked list that channel prepares list pointers cells pointers headers multicast cells. This allows dequeue process replicate cell with headers each entry linked list. This necessary because multicast cells bound different destinations need different headers. Figure shows replication process that occurs, according fields MC_LIST word set.
Multicast cell available input FIFO.
Look NEXT_MC_HEADER_PTR entry TX_CHANNEL_TABLE pointed OUT_CHAN. Make entry cell output FIFO that indicated Increment MC_COUNT state bit. Check REPLICATE_CELL bit.
Look NEXT_MC_ADD multicast control block.
Move head pointer input FIFO clear ENQ_PEND state bit.
Figure Multicast Background Process
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Figure shows operation multicast pointer FIFOs. When multicast cell arrives, immediately stored RAM. pointer that cell buffer OUTCHAN that cell onto eight input FIFOs. There FIFO input multicast background pointer replication process which runs UTOPIA rate copies pointers from input FIFOs output FIFOs. does traversing linked list that OUTCHAN copying pointer cell buffer output FIFO that proper background process dynamically identifies output FIFOs full. become full, process records which full that ceases transferring cells that Transfers still free occur other SCs. Once dequeue process serves cell instance from that bottlenecked background process free continue replications that background process runs exactly same rate UTOPIA interface. This allows transmit multicast cells full rate interface, even each multicast cell only going destination this QRT.
Channel Linked List Per-SC, Per-VO Output Pointer FIFOs
Eight Per-SC Input Pointer FIFOs
Cell Pointer, Channel
Background Pointer Replication Process
Header
Cell
Cell Pointer
Cell SDRAM
Cell header translation flow Cell pointer control flow Cell payload flow
Figure Multicast Pointer FIFO Operation
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
2.6.7 Transmit Multicast Congestion Management
transmit multicast have congestion management applied Three five congestion measurements apply: device, channel. queue limits apply multicast cells they make sense. This because only copy cell kept DRAM, regardless number destinations which cell headed. Those counts contain only number unicast cells present. configured either generate generate backpressure per-SC basis. backpressure desired, configure TX_EXP_MAX_SC_QD (refer "TX_EXP_MAX_SC_QD" page 163) one-half input pointer FIFO depth that AL_RAM_CONFIG (refer "AL_RAM_CONFIG" page 105). This will drop cells depth deeper than this, preventing backpressure from reaching back into switch fabric. setting this system-level decision. Preventing backpressure prevents failure congestion card from affecting performance fabric whole. other hand, using backpressure allows more multicast cells passed without fear dropping egress QRT. high priority backpressure derived from near-fullness queues medium priority backpressure derived from near-fullness queue priority backpressure derived from near-fullness queues EPD, CLP-based dropping, EFCI valid multicast cells configured TX_CH_CONFIG word (refer section 9.3.1.7 "TX_CH_CONFIG" starting page 189) using same bits unicast connections.
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
System Diagram Internal Blocks External
Figure shows system diagram internal blocks external RAM.
DRAM Cell Buffer
Receive UTOPIA
Receive DRAM Control
Control
Microprocessor
Microprocessor Interface
Control UTOPIA Loopback
BP/Ack from
Queue Engine
BP/Ack
Control
Transmit UTOPIA
DRAM Control
From
DRAM Cell Buffer
Figure System Diagram Internal Blocks External
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
FAULT TOLERANCE
Data Path
Figure shows basic data path through switch. SE_D_OUT/IN SE_SOC_OUT/ signals used forward path, BP_ACK_OUT/IN signals used backward path. Data enters switch ingress receive side UTOPIA interface queued Input half (the IRT). receive queue controller selects cells that then played switch fabric, which consists more stages QSEs. cell finally enters egress where queued again Output half (the ORT). transmit queue controller selects cell which then played switch egress transmit side UTOPIA interface.
UTOPIA Interface QRT/QSE Interface QSE/QRT Interface UTOPIA Interface
(IRT Portion)
(Switching Matrix)
(ORT Portion)
(Switching Matrix)
(IRT Portion)
QSE/QSE Interface
(ORT Portion)
Forward Cell Path Backward BP/ACK Path
Figure Basic Data Path Through Switch
3.1.1 UTOPIA Interface
UTOPIA interface compatible with UTOPIA Level specification revision 2.01 UTOPIA Level specification 16-bit mode with cell-level handshaking. external Aclock must provided this interface with frequency between MHz. lower bound determined ATM_CLK failure detection circuitry. receive transmit sides interface independently configurable operate either single OC-12 multi-PHY fashion. interface also provides several options polling methods, bandwidth, servicing fairness, response time optimized given layer device arrangement.
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
3.1.2 Switch Fabric Interface
switch fabric interface four nibble-wide, interfaces with backpressure interface QSEs (PM73488s). device avoid head-of-line blocking receiving forms negative acknowledgment from switch fabric. form negative acknowledgment indicates congestion that likely resolved next cell time. This termed Mid-switch NACK Medium Negative ACKnowledgment MNACK). When receives MNACK, resends same cell. other form negative acknowledgment indicates congestion that likely resolved next cell time. This termed Output Negative ACKnowledgment (ONACK). When receives ONACK, skips another channel sends cell from that different channel.
Fault Detection Isolation
data transfers internally between various RAMs between checked following mechanisms: Memory parity checking UTOPIA interface fault detection recovery mechanisms Switch fabric fault detection recovery mechanisms
3.2.1 Memory Parity Checking
receive transmit buffer SDRAMs checked multibit parity. external SRAMs have parity checking. parity conditions checked. There kinds flags (sticky non-sticky) each these parity error conditions. sticky error bits error cleared processor. corresponding non-sticky bits used debugging purposes.
3.2.2 UTOPIA Interface Fault Detection Recovery Mechanisms
uses several mechanisms ensure cell integrity through UTOPIA interface expediently detect, isolate, rectify fault conditions.
3.2.2.1 Header Error Check (HEC)
receive ingress UTOPIA interface configured perform calculation using CHK_HEC UTOPIA_CONFIG register (refer section 7.2.11 "UTOPIA_CONFIG" starting page 117). When failure detected checking enabled, interrupt signaled processor interface cell dropped UTOPIA interface. Some Segmentation Reassembly (SAR) Physical layer (PHY) devices produce correct other purposes. connect these devices, clear CHK_HEC bit.
3.2.2.2 Start Cell (SOC) Recovery
receive UTOPIA interface flexible when dealing with signal sent from layer device QRT. accept delay four Aclock cycles aligned data signals after assertion Receive UTOPIA A
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Layer Enable signal (/RATM_READ_EN). signal arrive anywhere within this window data will accepted. Customers will find this feature useful glue logic used special layer device adaptations. however, signal arrives after four-cycle window, will dump cell enter recovery mode. Recovery mode implemented both single multi-PHY configurations provides robustness event late resulting from reset double resulting from renegade devices. recovery mode performs precession Acell cycles that follow. This necessary bring device back into synchronization slotted cell-level handshaking. recovery performs same functions stuck-at faults signal. When failure detected, interrupt signaled processor interface.
3.2.2.3 Transmit Watchdog
transmit egress UTOPIA interface function called "watchdog". watchdog exists protect queues from overflow sink goes offline stops requesting cells. watchdog configured UTOPIA_CONFIG register processor interface (refer "WD_TIME" page 118). watchdog turned tolerate either OC-3-, DS1-, DS0-level outputs. watchdog operates observing liveliness Transmit UTOPIA ALayer Cell Available signals (TATM_CLAV(3:0)). determines device stopped accepting cells, cells intended that device played out. Otherwise, device accept these cells TATM_CLAV(3:0) signal dormancy stuck-at fault, normal UTOPIA signaling lowest priority occurs whenever spare bandwidth available.
3.2.2.4 Transmit Parity
transmit UTOPIA interface performs UTOPIA Level parity calculation over Transmit UTOPIA ALayer Data signals (TATM_DATA(15:0)) devices error checking.
3.2.2.5 AClock Failure Detection
UTOPIA interface contains Aclock failure detection circuit. detection circuit samples Aclock with high-frequency system clock determines Aclock possess signal changes. clock failure detection circuit tripped, interrupt signaled processor interface.
3.2.2.6 Receive Cell Available Signal Stuck
When interface device's cell available signal stuck receive UTOPIA Level interface limits approximately one-half receive side bandwidth. This condition result from floating cell available line should avoided designing pull-down resistors cell available lines. transmit direction, this such issue, because cell service dependent presence cell bound that device. However, this condition should minimized transmit direction also.
PM73487
PMC-980618 3.2.2.7
Issue
Mbps ATraffic Management Device
Highest Bandwidth Device Support UTOPIA Level Mode
UTOPIA Level-2 interface designed operate with device possessing bandwidth greater than that OC-3. higher bandwidth requirements, user must single-PHY UTOPIA Level-1 mode operation.
3.2.3 Switch Fabric Fault Detection Recovery Mechanisms
uses several mechanisms ensure cell integrity through switch fabric expediently detect, isolate, rectify fault conditions.
3.2.3.1 Coding
Coding special background pattern "0000111100001." generated ingress propagated QSE. This background pattern checked egress QRT. this pattern inconsistent missing, forward cell path declared SE_INPUT_PORT_FAIL interrupt (refer "SE_INPUT_PORT_FAIL" page 112) asserted.
3.2.3.2 Inversions
indicated inversion background pattern. Also, pattern reset valid will always followed "000011110000.". This pattern reset checked egress QRT, inconsistent, forward path declared SE_INPUT_PORT_FAIL interrupt (refer "SE_INPUT_PORT_FAIL" page 112) asserted.
3.2.3.3 Redundant Cell Present Coding
first nibble each valid cell predetermined format. This format checked cell received egress QRT. format inconsistent, forward cell path declared SE_INPUT_PORT_FAIL interrupt (refer "SE_INPUT_PORT_FAIL" page 112) asserted. This also increases robustness cell presence detection, preventing all-1s input from creating cells.
3.2.3.4 Idle Cell Pattern Checking
idle cell ingress predetermined format. This pattern checked egress when idle cell received. format inconsistent, forward cell path declared SE_INPUT_PORT_FAIL interrupt (refer "SE_INPUT_PORT_FAIL" page 112) asserted.
3.2.3.5 Dropping Cells with Header Parity
parity generated over first nibbles every valid cell. parity embedded twelfth nibble. Parity checking disabled asserting PARITY_FAIL_DIS (refer "PARITY_FAIL_DIS" page 107). When parity checking enabled, cells with parity dropped failure reported microprocessor TX_PARITY_FAIL flag (refer "TX_PARITY_FAIL" page 111).
PM73487
PMC-980618 3.2.3.6 Forced Parity
Issue
Mbps ATraffic Management Device
header parity detection logic checked clearing RX_CH_TAG word (refer "RX_CH_TAG" page 185). This forces parity (even parity) created.
3.2.3.7 Marked Cell Counting
Mark (MB) RX_CH_TAG word (refer "RX_CH_TAG" page 185) sent between QSE. NO_RESP feedback received, RX_MARKED_CELLS counters count enabled cells (modulo ingress QRT. TX_MARKED_CELLS counters count marked cells (modulo that received egress QRT. RX_MARKED_CELLS TX_MARKED_CELLS counters (refer "MARKED_CELLS_COUNT" page 110) help identify subtle failures fabric used create strong diagnostic routines. These counters separate four switch fabric interfaces each transmit receive directions.
3.2.3.8 Remote Data Path Failure Indication
When cell path determined bad, egress indicates remote failure violating syntax BP_ACK_OUT signal. This indication ingress that fabric fault forward cell path been detected. Also, SE_INPUT_PORT_FAIL interrupt (refer "SE_INPUT_PORT_FAIL" page 112) flagged microprocessor. cell being received this time discarded. This detected BP_REMOTE_FAIL (refer "BP_REMOTE_FAIL" page 112) other link. Withholding backpressure from ingress prompts send only idle cells forward cell path until recognizes valid backpressure pattern again.
3.2.3.9 Unacknowledged Cell Detection
acknowledgment received cell, ACK_LIVE_FAIL interrupt (refer "ACK_LIVE_FAIL" page 111) asserted. This indication problem end-to-end path through switch fabric.
3.2.3.10 Switch Fabric Loopback
internal loopback feature also helps detect isolate fabric faults. When dribbling errors other faults detected, internal loopback help isolate fault.
3.2.3.11 Fabric Clock Failure Detection
switch fabric interface contains clock failure detection circuit. detection circuit samples fabric clock with high-frequency system clock determines whether possess signal changes. clock failure detection circuit tripped, interrupt signaled processor interface.
3.2.3.12 Liveness Backpressure Signal
backpressure signal checked "10" pattern start backpressure signal. each QSEs, Backpressure (BP) liveness indication called BP_ACK_FAIL (refer "BP_ACK_FAIL" page 112). There bits
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
port called ACK_LIVE_FAIL BP_REMOTE_FAIL (refer "ACK_LIVE_FAIL" "BP_REMOTE_FAIL" page 112) that check response from switch fabric liveness data line. liveness signal alone will determine that faulty.
3.2.3.13 BP_ACK_IN Pattern Checking
Backpressure acknowledgment transmitted from egress ingress packets BP_ACK_OUT line. format packets follows: background pattern "0000111100001. Generated egress propagated QSE. This pattern checked ingress QRT. First Inversion background pattern) Indicates beginning packet. Mode Indicates nature packet (that acknowledge backpressure). Data1 Indicates Most Significant (MSB) data. Data0 Indicates Least Significant (LSB) data acknowledgment second data backpressure. Second Inversion Verify first inversion glitch fabric stuck. Code Ext1 backpressure data; otherwise, must acknowledgment accepted valid. Code Ext0 Must accepted valid. This reserved future use. part coding missing inconsistent, BP/ACK path indicated asserting BP_ACK_FAIL interrupt (refer "BP_ACK_FAIL" page 112).
3.2.3.14 BP_ACK Inversion Checking
first inversion second inversion packet separated three bits ensure fabric fault, such stuck "0", glitch will result false packet. second inversion consistent (inverse) with first inversion, path indicated asserting BP_ACK_FAIL interrupt (refer "BP_ACK_FAIL" page 112). When BP/ACK path determined bad, ingress withholds issuing valid cells instead transmits idle cells until fabric recovers from fault.
PM73487
PMC-980618 3.2.3.15
Issue BP_ACK Remote Failure Detection
Mbps ATraffic Management Device
missing corrupted (bad second inversion) backpressure packet reported microprocessor BP_REMOTE_FAIL flag (refer "BP_REMOTE_FAIL" page 112). BP_REMOTE_FAIL flag indication broken cell path ingress QRT. missing corrupted acknowledgment packet reported microprocessor ACK_LIVE_FAIL (refer "ACK_LIVE_FAIL" page 111).
3.2.3.16 Detection Hysteresis
fault detected result missing background pattern, takes minimum maximum switch fabric clocks recover after pattern been restored. backpressure packet withheld detected during cell time because built-in hysteresis, takes valid backpressure packets successive cell times recover. acknowledgment packet detected bad, takes cell time recover.
3.2.4 Tables Switch Fabric Interface Failure Behaviors 3.2.4.1 IRT-to-Switch Fabric Interface
Figure page interface consists figure, refers each four SE_SOC_OUT SE_D_OUT#(3:0) data ports, while refers corresponding BP_ACK_IN signals QRT. Table summarizes failure conditions detected actions taken.
Table Failure Conditions, IRT-to-Switch Fabric Interface Fault Detected Cannot lock special coding guaranteed transitions BP_ACK_IN. Action Taken Idle cells sent data interface Internally IRT, cells that would have gone ACKed ports failing; else they ONACKed. multicast cells generated port. BP_ACK_FAIL (refer "BP_ACK_FAIL" page 112) signaled microprocessor. Idle cells sent data interface Internally IRT, cells that would have gone ACKed ports fail; else they ONACKed. multicast cells generated port. BP_REMOTE_FAIL (refer "BP_REMOTE_FAIL" page 112) signaled microprocessor. Cell that transmitted treated sent. ACK_LIVE_FAIL (refer "ACK_LIVE_FAIL" page 111) signaled microprocessor. Comment Port treated dead. Problem probably with BP_ACK_IN line.
backpressure received BP_ACK_IN.
Port treated dead. Problem with forward data flow, signaling this back IRT.
ACK, MNACK, ONACK received, although unicast cell sent out.
PM73487
PMC-980618 3.2.4.2
Issue Interface, Receive Data Direction
Mbps ATraffic Management Device
Figure page receive interface consists figure, refers each four SE_SOC_IN SE_D_IN#(3:0) data ports, while refers corresponding BP_ACK_OUT signals QSE. Table summarizes failure conditions detected actions taken.
Table Failure Conditions, Receive Interface Fault Detected Cannot lock special coding guaranteed transitions SE_SOC_IN. Invalid cell present coding SE_D_IN#(3:0). Action Taken backpressure sent data discarded. SE_INPUT_PORT_FAIL (refer "SE_INPUT_PORT_FAIL" page 112) signaled microprocessor. backpressure sent data discarded. SE_INPUT_PORT_FAIL signaled microprocessor. Comment Withholding backpressure signals previous stage that port should used. Probably unconnected input lines that pulled down. Withholding backpressure signals previous stage that port should used. Withholding backpressure signals previous stage that port should used. does necessarily have time drop cell time detected parity error.
idle cell coding SE_D_IN#(3:0). Parity fail.
backpressure sent data discarded. SE_INPUT_PORT_FAIL signaled microprocessor. ONACK sent unicast data. Multicast data dropped. PARITY_ERROR (refer Long Form Data Sheet) signaled microprocessor.
PM73487
PMC-980618 3.2.4.3
Issue Interface, Transmit Data Direction
Mbps ATraffic Management Device
Figure page transmit interface consists figure, refers each SE_SOC_OUT SE_D_OUT#(3:0) data ports, while refers corresponding BP_ACK_IN signals QSE. Table summarizes failure conditions detected actions taken.
Table Failure Conditions, Transmit Interface Fault Detected Cannot lock special coding guaranteed transitions BP_ACK_IN. Action Taken Idle cells sent data interface possible, data routed around port. Multicast data dropped possible port choices dead off. Unicast data optionally dropped possible port choices dead off. BP_ACK_FAIL (refer "BP_ACK_FAIL" page 112) signaled microprocessor. Idle cells sent data interface possible, data routed around port. Multicast data dropped possible port choices dead off. Unicast data optionally dropped possible port choices dead off. BP_REMOTE_FAIL (refer "BP_REMOTE_FAIL" page 112) signaled microprocessor. action taken. Comment Port treated dead. Problem probably with BP_ACK_IN line.
backpressure received BP_ACK_IN.
Port treated dead. Problem with forward data flow.
ACK, MNACK, ONACK received, although cell sent currently monitored QSE.
Lack ACK, MNACK, ONACK monitored QSE.
3.2.4.4
Switch Fabric-to-ORT Interface
Figure page interface consists figure, refers each four SE_SOC_IN SE_D_IN#(3:0) data ports, while refers corresponding BP_ACK_OUT signals QRT. Table summarizes failure conditions detected actions taken.
Table Failure Conditions, Switch Fabric-to-ORT Interface Fault Detected Cannot lock special coding guaranteed transitions SE_SOC_IN. Invalid cell present coding SE_D_IN#(3:0). Action Taken backpressure sent data discarded. SE_INPUT_PORT_FAIL (refer "SE_INPUT_PORT_FAIL" page 112) signaled microprocessor. backpressure sent data discarded. SE_INPUT_PORT_FAIL signaled microprocessor. backpressure sent data discarded. SE_INPUT_PORT_FAIL signaled microprocessor. Comment Withholding backpressure signals previous stage that port should used. Probably unconnected input lines that pulled down. Withholding backpressure signals previous stage that port should used. Withholding backpressure signals previous stage that port should used.
idle cell coding SE_D_IN#(3:0).
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Table Failure Conditions, Switch Fabric-to-ORT Interface (Continued) Fault Detected Parity fail. Action Taken sent Parity errored cell dropped. TX_PARITY_FAIL (refer "TX_PARITY_FAIL" page 111) signaled microprocessor. Comment already sent time detected parity error. this case, cell that dropped ACKed.
3.2.4.5
Types Failures Their Manifestations
Table shows possible faults, their effects, they affect network.
Table Faults Effects Network Fault Wire Connection Data line from SE_D_IN#(3:0) stuck Manifestation Invalid idle cell, cells with missing Cell Present parity error. Effect Network Port shut down interrupt generated backpressure withheld) receipt first consecutive idle cells until condition fixed, port failure sent source data lack backpressure indication. only idel cell received, round-trip delay between QSE, source could send another (user) cell, causing destination (QRT) come shut down state. This means interrupt (SE_INPUT_PORT_FAIL) will asserted deasserted. lateched interrupt (SE_INPUT_PORT_FAIL_LATC will still asserted. Port shut down until condition fixed, port failure sent source data lack backpressure indication. Port shut down until condition fixed. Port shut down receipt first idle cell until condition fixed, port failure sent source data lack backpressure indication.
SE_SOC_IN(3:0) line stuck
Loss-of-lock special coding SE_SOC_IN(3:0).
BP_ACK_IN(3:0) line stuck Bridging fault within port.
Loss-of-lock special coding BP_ACK_IN(3:0). Invalid idle cell with some 10/01 fail parity error.
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Table Faults Effects Network (Continued) Fault Port Failures SE_SOC_OUT generation. Manifestation Loss-of-lock special coding SE_SOC_IN(3:0). Effect Network Port shut down until condition fixed, port failure sent source data lack backpressure indication. Port shut down receipt first idle cell until condition fixed, port failure sent source data lack backpressure indication. Port shut down until condition fixed. Detection possible using marked cell count.
data invalid data generated.
Invalid idle cell with some 10/01 fail parity error.
BP_ACK_OUT(3:0) generation. Chip Failures Multicast handling. Multicast cell pool buffer. Partial cell buffers. Multicast unicast selection networks.
Loss-of-lock special coding BP_ACK_IN(3:0). Cell loss generation.
Parity error header cell. Detection only header; payload. Parity error header cell. Cell gets wrong port, cell duplicated, cell lost. Parity error. Cell wrong port noticed receiving QRT, that active. Cell duplication cell loss detection possible using marked cell count. Detection possible using marked cell count.
Arbiter.
Cell lost.
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
DESCRIPTIONS
Package Diagram
Figure (parts shows 503-pin Enhanced Plastic Ball Grid Array (EPBGA) package used QRT. package measurements shown millimeters.
Measurements shown millimeters. drawn scale.
40.00 0.20
26.00 MAX.
PM73487-PI
L2A0961 Lyyww
1.14 ±0.125 0.86 ±0.15
2.98 Max.
NOTES: "L_B" wafer batch code. "Lyyww" assembly date code. Dimensions reference. Controlling dimension: millimeter. Parallelism tolerance. need measurement shown this figure, contact PMC-Sierra.
Figure 503-Pin EPBGA Side Views (Part
0.25 0.10
0.60 ±0.10
26.00 MAX.
40.00 0.20
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Measurements shown millimeters. drawn scale.
40.00 0.20 35.56 0.75 0.15 1.27
40.00 0.20
35.56
0.30 0.10 NOTES: Controlling dimension: millimeter. Regardless feature size. material: high temperature glass/epoxy resin cloth (that driclad, MCL-679, equivalent). Solder resist: photoimagable (that vacrel 8130, DSR3241, PSR4000, equivalent). need measurement shown this figure, contact PMC-Sierra.
Figure 503-Pin EPBGA Bottom View (Part
PM73487
PMC-980618 Signal Locations
Issue
Mbps ATraffic Management Device
Table Signal Locations
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
(KEY) ADDRDATA(6) RATM_DATA(1
JTAG_TDO JTAG_TDI JTAG_TCK /INTR ADDRDATA(30 ADDRDATA(31 ADDRDATA(20 ADDRDATA(22 ADDRDATA(12 ADDRDATA(11 ADDRDATA(8) ADDRDATA(5) ADDRDATA(1) SYS_CLK RATM_DATA(1 RATM_DATA(1 RATM_DATA(7 RATM_DATA(8 RATM_ADD(2) RATM_DATA(0
ABR_RAM_AD( ABR_RAM_AD( ABR_RAM_AD( /SCAN_EN W_/RD ADDRDATA(24 ADDRDATA(26 ADDRDATA(17 ADDRDATA(18 ADDRDATA(16 ADDRDATA(2) ADDRDATA(0) RATM_DATA(2 RATM_DATA(1 RATM_DATA(3 RATM_CLAV(2 RATM_ADD(1)
ABR_RAM_AD( /RESET /JTAG_RESET JTAG_TMS PCLK /ADS ADDRDATA(28 ADDRDATA(21 ADDRDATA(25 ADDRDATA(19 ADDRDATA(14 ADDRDATA(9) ADDRDATA(7) ADDRDATA(4) RATM_DATA(9 RATM_DATA(1 RATM_DATA(4 RATM_ADD(4) RATM_READ_ RATM_ADD(3) RATM_CLAV(3
ABR_RAM_AD( ABR_RAM_AD( /TEST_MODE STATS_STRB /READY ADDRDATA(27 ADDRDATA(29 ADDRDATA(23 ADDRDATA(15 ADDRDATA(10 ADDRDATA(13 ADDRDATA(3) RATM_DATA(1 RATM_DATA(6 RATM_DATA(1 RATM_DATA(5
RATM_ADDR(0 RATM_CLAV(0 RATM_SOC RX_DRAM_DA TA(29)
RX_DRAM_DA TA(30) RX_DRAM_DA TA(25)
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Table Signal Locations (Continued)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
RATM_CLAV(1
RX_DRAM_DA TA(31) RX_DRAM_DA TA(28) RX_DRAM_DA TA(27) RX_DRAM_DA TA(22) RX_DRAM_DA TA(19) RX_DRAM_DA TA(12)
RX_DRAM_DA TA(26) RX_DRAM_DA TA(24) RX_DRAM_DA TA(21) RX_DRAM_DA TA(17) RX_DRAM_DA TA(14) RX_DRAM_DA TA(10)
RX_DRAM_DA TA(23) RX_DRAM_DA TA(20) RX_DRAM_DA TA(15) RX_DRAM_DA TA(8) RX_DRAM_DA TA(7)
RX_DRAM_DA TA(16) RX_DRAM_DA TA(18) RX_DRAM_DA TA(11) RX_DRAM_DA TA(9) RX_DRAM_DA TA(5)
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Table Signal Locations (Continued)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
ABR_RAM_WE
RX_DRAM_AD D(6) RX_DRAM_AD D(2) RX_DRAM_RA RX_DRAM_AD D(0) CH_RAM_ADD /CH_RAM_WE1 CH_RAM_ADS /ABR_RAM_OE DRAM_CKE SE_D_OUT3(3) SE_SOC_OUT SE_D_OUT3(0)
CH_RAM_DAT A(0) CH_RAM_ADD CH_RAM_ADD CH_RAM_ADD SE_D_OUT0(3) SE_D_OUT1(1) SE_D_OUT1(0) SE_D_OUT1(2)
SE_SOC_IN(0) BP_ACK_OUT( BP_ACK_OUT( BP_ACK_IN(1) BP_ACK_IN(2) CH_RAM_DAT A(10) CH_RAM_DAT A(13) CH_RAM_DAT A(9) CH_RAM_DAT A(16) SE_SOC_IN(1) SE_SOC_IN(3) ATM_CLK BP_ACK_OUT( CH_RAM_DAT A(11) CH_RAM_DAT A(17) CH_RAM_DAT A(14) CH_RAM_PARI
CH_RAM_DAT A(18) CH_RAM_DAT A(19) CH_RAM_DAT A(27) CH_RAM_DAT A(22) SE_D_IN0(2) SE_CLK SE_D_IN3(1) SE_D_IN3(2)
ABR_RAM_AD( ABR_RAM_AD( ABR_RAM_AD( ABR_RAM_AD( RX_DRAM_DA TA(6) RX_DRAM_DA TA(3) RX_DRAM_DA TA(1) RX_DRAM_AD D(7) RX_DRAM_DA TA(2)
CH_RAM_DAT A(4) CH_RAM_ADD (16) CH_RAM_ADD (15) CH_RAM_ADD (17)
CH_RAM_DAT A(29) CH_RAM_DAT A(26) CH_RAM_DAT A(25) CH_RAM_DAT A(31) TX_DRAM_DA TA(31) SE_D_IN0(3) SE_D_IN1(3) SE_D_IN1(0)
ABR_RAM_AD( ABR_RAM_AD( ABR_RAM_AD( ABR_RAM_AD( RX_DRAM_DA TA(13) RX_DRAM_DA TA(4) RX_DRAM_DA TA(0) RX_DRAM_AD D(5)
SE_D_OUT0(1)
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Table Signal Locations (Continued)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
CH_RAM_ADD ABR_RAM_AD
CH_RAM_ADD (11) CH_RAM_ADD CH_RAM_ADD CH_RAM_ADD
SE_D_OUT0(0) BP_ACK_IN(3)
CH_RAM_DAT A(28) CH_RAM_DAT A(30) /ALRAM_ADSC ALRAM_ADD(4 TX_DRAM_DA TA(22) TX_DRAM_DA TA(27) TX_DRAM_DA TA(30) SE_D_IN0(1) ALRAM_CLK ALRAMADD18 CH_RAM_PARI ALRAMADD17 TX_DRAM_DA TA(26) TX_DRAM_DA TA(28) SE_D_IN0(0) SE_D_IN1(1)
ABR_RAM_AD( ABR_RAM_AD( RX_DRAM_CS( RX_DRAM_AD D(4) RX_DRAM_WE RX_DRAM_CS( /CH_RAM_OE /CH_RAM_WE0 ABR_RAM_AD
SE_D_OUT0(2)
SE_D_IN2(0)
RX_DRAM_CA SE_D_OUT2(2) SE_D_OUT2(0) SE_D_OUT3(1)
CH_RAM_DAT A(6) CH_RAM_DAT A(3) CH_RAM_DAT A(2) CH_RAM_DAT A(1) SE_SOC_IN(2) PROC_MON BP_ACK_OUT( BP_ACK_IN(0)
SE_D_IN2(3) SE_D_IN3(3) RX_CELL_STA CH_RAM_DAT A(20) CH_RAM_DAT A(23) CH_RAM_DAT A(21) CH_RAM_DAT A(24) SE_D_IN2(2) SE_D_IN1(2) SE_D_IN2(1) SE_D_IN3(0)
CH_RAM_ADD (14) CH_RAM_ADD (13) CH_RAM_ADD (12) CH_RAM_ADD (10) CH_RAM_ADD RX_DRAM_BA
ABR_RAM_AD( RX_DRAM_AD D(1) RX_DRAM_AD D(8) RX_DRAM_AD D(3) RX_DRAM_CL
CH_RAM_DAT A(5) CH_RAM_DAT A(7) CH_RAM_DAT A(8) CH_RAM_DAT A(12) CH_RAM_DAT A(15)
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Table Signal Locations (Continued)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
CH_RAM_ADD CH_RAM_CLK ABR_RAM_CL CH_RAM_ADD
SE_D_OUT3(2) SE_D_OUT2(3) SE_D_OUT1(3) SE_D_OUT2(1)
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Table Signal Locations (Continued)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
/ALRAM_OE
/ALRAM_WE
ALRAM_DATA TATM_DATA(6
ALRAM_ADD(1 ALRAM_ADD(6 ALRAM_ADD(1 ALRAM_ADD(1 ALRAM_ADD(1 ALRAM_ADD(1 ALRAM_DATA ALRAM_DATA (14) ALRAM_DATA (10) ALRAM_DATA (16) TATM_CLAV(1 TATM_DATA(3 TATM_DATA(2 TATM_DATA(7 TATM_DATA(1 TATM_ADD(3) TATM_ADD(0) TX_DRAM_RA TX_DRAM_AD D(3)
ALRAM_ADD(0 ALRAM_ADD(5
ALRAM_ADD(2 ALRAM_ADD(3 ALRAM_ADD(7 ALRAM_ADD(1 ALRAM_ADD(1 ALRAM_DATA ALRAM_DATA ALRAM_DATA ALRAM_DATA (12) TATM_CLAV(0 TATM_DATA(1 TATM_CLAV(2 TATM_DATA(8 TATM_DATA(1 TX_DRAM_BA TATM_ADD(2) TX_DRAM_CA TX_DRAM_AD D(7)
ALRAM_ADD(1 ALRAM_ADD(1 ALRAM_DATA ALRAM_DATA ALRAM_DATA ALRAM_DATA (15) ALRAM_DATA (13) TATM_CLAV(3 TATM_DATA(0 TATM_DATA(5 TATM_DATA(4 TATM_DATA(1 TATM_DATA(1 TATM_DATA(1 TX_DRAM_CL TATM_ADD(4)
ALRAM_ADD(8 ALRAM_ADD(9 ALRAM_ADD(1 ALRAM_DATA ALRAM_DATA (11) ALRAM_DATA TATM_SOC TATM_PARITY TATM_WRITE_ TATM_DATA(9 TATM_DATA(1 TX_DRAM_AD D(0) TX_DRAM_AD D(1) TX_DRAM_WE TX_DRAM_DA TA(0)
TATM_ADD(1)
TX_DRAM_AD D(5)
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Table Signal Locations (Continued)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
TX_DRAM_AD D(6) TX_DRAM_DA TA(4) TX_DRAM_DA TA(18) TX_DRAM_DA TA(11) TX_DRAM_DA TA(20) TX_DRAM_DA TA(25) TX_DRAM_DA TA(29)
TX_DRAM_DA TA(2) TX_DRAM_CS( TX_DRAM_DA TA(9) TX_DRAM_DA TA(8) TX_DRAM_DA TA(16) TX_DRAM_DA TA(17) TX_DRAM_DA TA(23) TX_DRAM_DA TA(24)
TX_DRAM_AD D(8) TX_DRAM_AD D(4) TX_DRAM_DA TA(5) TX_DRAM_DA TA(6) TX_DRAM_DA TA(14) TX_DRAM_DA TA(13) TX_DRAM_DA TA(19) TX_DRAM_DA TA(21)
TX_DRAM_DD( TX_DRAM_DA TA(3) TX_DRAM_CS( TX_DRAM_DA TA(1) TX_DRAM_DA TA(10) TX_DRAM_DA TA(12) TX_DRAM_DA TA(15)
TX_DRAM_DA TA(7)
Signal Descriptions (372 Signal Pins)
inputs Bidirectional inputs have internal pull circuit except input. internal pull down circuit. tolerant/ LVTTL inputs have Schmitt Trigger Hysteresis circuit. CMOS inputs tolerant.
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
4.3.1 Processor Interface Signals
Table Processor Interface Signals Pins) Signal Name PCLK ADDRDATA(31:0) Ball E10, C10, D10, B10, C11, E12, E11, E13, D11, C12, D13, B11, B12, D12, C13, B13, C14, A13, B14, C15, D14, E14, B15, Type Bidir Drive/ Input Level CMOS Moderate (Mod) Slew Rate Description Processor Clock Address/Data Bits part 32-bit processor address/data bus.
/ADS W_/RD /READY
Address/Data Status active signal that indicates address state. Write_/Read active high signal that selects write cycle when high. Ready active signal that indicates processor cycle finished. When this signal deasserted, driven high, then tristated. Chip Select active signal that selects device processor access. Interrupt active signal that indicates interrupt present.
/INTR
4.3.2 Statistics Interface Signal
Table Statistics Interface Signal Pin) Signal Name STATS_STRB Ball Type Drive/ Input Level Slew Rate Description STATS_STRB active high signal that indicates fixed position cell time SYS_CLK domain. This used trigger external circuitry.
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
4.3.3 Switch Element Interface Signals
Table Switch Element Interface Signals Pins) Signal Name SE_CLK RX_CELL_START Ball AA26 Type Drive/ Input Level CMOS Slew Rate Description Switch Element Clock clock nibble transfer. Receive Cell Start indicates time receive direction. should driven high every cell time (118 SE_CLKs). Backpressure Input down carries cell acknowledge backpressure from switch fabric. Switch Fabric Start Cell indicates four SE_D_OUT signals. This signal precedes first nibble cell clock. cells leaving entering switch fabric, this signal indicates SOC. Switch Element Data Ports down Bits down four nibble-wide pathways that carry cell QSEs (PM73488).
BP_ACK_IN(3:0)
R27, U29, U28,
SE_SOC_OUT
SE_D_OUT0(3:0) SE_D_OUT1(3:0) SE_D_OUT2(3:0) SE_D_OUT3(3:0) BP_ACK_OUT(3:0)
P25, R28, R25, N28, P28, P26, N27, M26, N29, L26, N26, M28, U27, T27, U26, V26, T25, V25,
Backpressure Output down asserts multipriority backpressure cell acknowledge toward switch fabric. Switch Fabric Start Cell indicates time transmit direction four incoming SE_D_IN3, SE_D_IN2, SE_D_IN1 SE_D_IN0, respectively. Switch Element Data Ports Bits down part nibble-wide, data pathway that carries cell from switch fabric.
SE_SOC_IN(3:0)
SE_D_IN0(3:0) SE_D_IN1(3:0) SE_D_IN2(3:0) SE_D_IN3(3:0)
AB26, AA25, AC28, AD28 AB27, Y26, AD29, AB28 W26, Y25, Y27, W27, AA28, AA27,
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
4.3.4 CH_RAM Interface Signals
Table Interface Signals Pins) Signal Name CH_RAM_ADD(17:0) Ball AB5, AC3, AB2, AC2, AA4, AB3, AB4, AA5, AA3, AA2, Type Drive/ Input Level Slew Rate Description Address Bits part 18-bit SRAM address bus. CH_RAM Data Bits part 32-bit SRAM data bus.
CH_RAM_DATA(31:0)
Bidir
ma/CMOS
CH_RAM_PARITY0 CH_RAM_PARITY1 CH_RAM_CLK
Bidir Bidir
ma/CMOS ma/CMOS
Fast
parity CH_RAM_DATA(15:0). parity CH_RAM_DATA(31:16). CH_RAM Clock provides clock CH_RAM.This signal should terminated with series resistor before connecting modules CH_RAM Address reverses CH_RAM_ADD(17:0). CH_RAM Output Enable active signal that enables SRAM drive CH_RAM_DATA(31:0), CH_RAM_PARITY0, CH_RAM_PARITY1.This signal should terminated with series resistor before connecting modules CH_RAM Write Enable active signal that strobes CH_RAM_DATA(15:0) CH_RAM_PARITY0 into external SRAM. CH_RAM Write Enable active signal that strobes CH_RAM_DATA(31:16) CH_RAM_PARITY1 into external SRAM.
CH_RAM_ADD17N
/CH_RAM_OE
Fast
/CH_RAM_WE0
/CH_RAM_WE1
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Table Interface Signals Pins) (Continued) Signal Name /CH_RAM_ADSC Ball Type Drive/ Input Level Slew Rate Description CH_RAM Synchronous Address Status Controller active signal that causes addresses registered within external SSRAM.
4.3.5 AL_RAM Interface Signals
Table Address Lookup Interface Signals Pins) Signal Name ALRAM_ADD(18:0) Ball AE8, AG7, AG6, AH5, AF7, AF6, AH4, AG5, AG4, AE7, AE6, AF5, AG3, AE4, AC5, AF4, AF3, AG2, AG11, AH9, AG9, AH10, AF11, AE10, AG10, AE11, AF9, AG8, AF10, AJ6, AH8, AF8, AE9, AH7, Type Drive/ Input Level Slew Rate Description Address Bits part 19-bit SRAM address bus.
ALRAM_DATA(16:0)
Bidir
ma/CMOS
Data Bits part 16-bit SRAM data bus. parity.
ALRAM_CLK
Fast
Clock provides clock ALRAM. This signal should terminated with series resistor before connecting modules Address reverses ALRAM_ADD(18:0). Address reverses ALRAM_ADD(18:0). Output Enable active signal that enables SRAM drive AL_RAM_DATA(16:0).This signal should terminated with series resistor before connecting modules Write Enable active signal that strobes data into external SRAM. Synchronous Address Status Controller active signal that causes addresses registered within external SSRAM.
ALRAMADD17N ALRAMADD18N /ALRAM_OE
Fast
/ALRAM_WE
/ALRAM_ADSC
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
4.3.6 ABR_RAM Interface Signals
Table ABR_RAM Interface Signals Pins) Signal Name Ball Type Bidir Drive/ Input Level ma/CMOS Slew Rate Description Address Data Bits form time division multiplexed address data bus.
ABR_RAM_AD(16:0) ABR_RAM_CLK
Fast
Clock provides clock RAM.This signal should terminated with series resistor before connecting modules Address Data Selection defines type information address/data (ADDRDATA(31:0)). ABR_RAM Output Enable active signal that enables drive ABR_RAM_AD(16:0).This signal should terminated with series resistor before connecting modules ABR_RAM Advance active signal that signals external SSRAM advance address. Write Enable active signal that enables write into ABR_RAM.
/ABR_RAM_ADSP
/ABR_RAM_OE
Fast
/ABR_RAM_ADV
/ABR_RAM_WE
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
4.3.7 Receive Cell Buffer DRAMs
Table Receive Cell Buffer Interface Signals Pins) Signal Name RX_DRAM_ADD(8:0) Ball J26, F28, K25, G28, H26, J27, K26, J25, Type Drive/ Input Level Slew Rate Description DRAM Address Bits part 9-bit SRAM address bus. Note that TX_DRAM_ADD(8) must connected AutoPrecharge pin.If DRAM_TYPE (refer "RX_DRAM_TYPE" page 104) then connect RX_DRAM_ADD(8) DRAM autoprecharge pin, which should DRAM address Receive DRAM Data Bits part 32-bit SRAM data bus.
RX_DRAM_DATA(31:0)
B23, E21, D22, B24, B25, C23, E22, C24, D23, B26, C25, D24, B27, E24, C26, E23, D25, C27, G25, B28, E26, C28, E27, D27, D28, F25, E28, G26, F26, F29, F27,
Bidir
ma/CMOS
RX_DRAM_CLK
Fast
Receive DRAM Clock provides clock SDRAM.This signal should terminated with series resistor before connecting modules DRAM Clock Enable provides clock enable signal RX_DRAM TX_DRAM Receive DRAM Chip Select Bits enable SDRAMs. DRAM_TYPE (refer "RX_DRAM_TYPE" page 104), these RX_DRAM_ADD(9:8). Receive DRAM Bank Address defines bank which operation addressed. Receive DRAM Address Strobe active signal that writes address. Receive DRAM Column Address Strobe active signal that writes column address. Receive DRAM Write Enable active signal that enables write into synchronous DRAM.
DRAM_CKE
/RX_DRAM_CS(1:0)
H25,
RX_DRAM_BA
/RX_DRAM_RAS
/RX_DRAM_CAS
/RX_DRAM_WE
NOTE: (I/O mask enables) pins SGRAM need tied logic
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
4.3.8 Transmit Cell Buffer DRAMs
Table Transmit Cell Buffers Interface Signals Pins) Signal Name TX_DRAM_ADD(8:0) Ball AG21, AF20, AE21, AH20, AG22, AG20, AH21, AE18, AE17 Type Drive/ Input Level Slew Rate Description Transmit DRAM Address Bits part 9-bit DRAM address bus. Note that TX_DRAM_ADD(8) must connected AutoPrecharge pin. DRAM_TYPE (refer "RX_DRAM_TYPE" page 104) then connect TX_DRAM_ADD(8) DRAM autoprecharge pin, which should DRAM address bus. Transmit DRAM Data Bits part 32-bit DRAM data bus.
TX_DRAM_DATA(31:0)
AB25, AC27, AE28, AD27, AC26, AD26, AE27, AF28, AF27, AC25, AG28, AE26, AG27, AE23, AF26, AF25, AH27, AG25, AG26, AH26, AE24, AH25, AF23, AF24, AJ24, AG24, AG23, AE22, AH22, AF21, AH24, AE20 AH18
Bidir
ma/CMOS
TX_DRAM_CLK
Fast
Transmit DRAM Clock provides clock SDRAM.This signal should terminated with series resistor before connecting modules Transmit DRAM Chip Select Bits select SDRAM devices. DRAM_TYPE (refer "RX_DRAM_TYPE" page 104), then these TX_DRAM_ADD(9:8). Transmit DRAM Bank Address defines bank which operation addressed. Transmit DRAM Address Strobe active signal that writes address. Transmit DRAM Column Address Strobe active signal that writes column address.
/TX_DRAM_CS(1:0)
AH23, AF22
TX_DRAM_BA
AF17
/TX_DRAM_RAS
AG19
/TX_DRAM_CAS
AF19
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
Table Transmit Cell Buffers Interface Signals Pins) (Continued) Signal Name /TX_DRAM_WE Ball AE19 Type Drive/ Input Level Slew Rate Description Transmit DRAM Write Enable active signal that enables write into synchronous DRAM.
NOTE: (I/O mask enables) pins SGRAM SDRAM need tied logic
PM73487
PMC-980618
Issue
Mbps ATraffic Management Device
4.3.9 UTOPIA ALayer Interface Signals 4.3.9.1 Transmit UTOPIA ALayer Interface Signals
Table Transmit UTOPIA ALayer Interface Signals Pins) Signal Name ATM_CLK Ball Type Drive/Input Level CMOS Slew Rate Description UTOPIA ALayer Clock provides timing information both transmit receive UTOPIA interfaces. Transmit UTOPIA ALayer Address Bits Transmit UTOPIA ALayer Data Bits part 16-bit UTOPIA transmit data that carries data toward layer device. Transmit UTOPIA ALayer Cell Available Bits active high signals that indicate selected layer devices accept another cell. Transmit UTOPIA ALayer StartOf-Cell marks start cell. Transmit UTOPIA ALayer Write Enable enables write cell byte. Transmit UTOPIA ALayer Parity over TATM_DATA(15:0).
TATM_ADD(4:0) TATM_DATA(15:0)
AH19, AG17, AF18, AJ17, AG18 AH17, AH16, AF16, AG16, AE16, AH15, AE15, AF15, AG15, AJ13, AH13, AH14, AG13, AG14, AF13, AH12 AH11, AF14, AG12, AF12
TATM_CLAV(3:0)
TATM_SOC /TATM_WRITE_EN TATM_PARITY
AE12 AE14 AE13
4.3.9.2
Receive UTOPIA ALayer Interface Signals
Table Receive UTOPIA ALayer Interface Signals Pins)
Signal Name RATM_ADD(4:0) RATM_DATA(15:0)
Ball C19, C21, B21, E20, D15, A17, B17, C17, B18, D17, C16, B20, B19, D16, D18, C18, E18, E16, E17, C22, E19, A24,
Type
Drive/ Input Level
Slew Rate
Description Receive UTOPIA ALayer Address Bits Receive UTOPIA ALayer Data Bits part 16-bit UTOPIA receive data that carries data from layer device. Receive UTOPIA ALayer Start-OfCell marks start cell. Receive UTOPIA ALayer Cell Available Bits indicate selected layer devices have another cell.
RATM_SOC RATM_CLAV(3:0)
/RATM_READ_EN
Receive UTOPIA ALayer Read Enable causes read from FIFO layer device.
PM73487
PMC-980618 4.3.10
Issue Boundary Scan Signals
Mbps ATraffic Management Device
Table Test Signals Signal Pins) Signal Name /JTAG_RESET JTAG_TCK Ball Type Drive/Input Level CMOS CMOS Slew Rate Description JTAG Reset active low, true asynchronous reset JTAG controller. Scan Test Clock independent clock used drive internal boundary scan test logic. Connect this signal through pull-up resistor. Scan Test Data Input serial input boundary scan test data instruction bits. Connect this signal through pull-up resistor. Scan Test Data Output serial output boundary scan test data. Scan Test Mode Select controls operation boundary scan test logic. Connect this signa
Other recent searches
VPW05980 - VPW05980 VPW05980 Datasheet
TEA7540 - TEA7540 TEA7540 Datasheet
STM8S - STM8S STM8S Datasheet
PA2707GR - PA2707GR PA2707GR Datasheet
MSM7541 - MSM7541 MSM7541 Datasheet
7542 - 7542 7542 Datasheet
IDT7203 - IDT7203 IDT7203 Datasheet
IDT7204 - IDT7204 IDT7204 Datasheet
IDT7205 - IDT7205 IDT7205 Datasheet
IDT7206 - IDT7206 IDT7206 Datasheet
3210208 - 3210208 3210208 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
