PM7328 S/UNI-ATLAS-1K800 ALayer Solution Monolithic single c
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PM7328 S/UNI-ATLAS-1K800
ALayer Solution
Monolithic single chip device which handles bi-directional ALayer functions including VPI/VCI address translation, cell appending, policing (ingress only), cell counting requirements 1024 (virtual connections). Instantaneous bi-directional transfer rate Mbit/s supports bidirectional cell transfer rate 1.42x106 cell/s. Ingress input interface supports interface using direct addressing devices (Utopia Level Multi-PHY addressing devices (Utopia Level Ingress output interface supports SCI-PHY byte cell) interface (Utopia Level switch fabric. Egress input output interfaces support SCI-PHY byte cell) interface using direct addressing devices (Utopia Level Multi-PHY addressing devices (Utopia Level Compatible with PM7329 S/UNIAPEX-1K800 Traffic Manager, PMC-Sierra's VORTEX Architecture. Ingress functionality includes highly flexible search engine that covers entire PHYID/VPI/VCI address range, dual leaky bucket policing, per-VC cell counts, OAM-FM OAM-PM processing. Egress functionality includes direct address lookup, per-VC cell counts, OAM-FM OAM-PM processing. Per-PHY output buffering scheme resolves head-of-line blocking issue. Includes FIFO buffered 16-bit microprocessor interface cell insertion extraction, deterministic Table access, status monitoring configuration device. Supports access cell extraction. UTOPIA external SRAM interfaces max.
POLICING
ITU-I.371, AForum TM4.0 compliant, per-VC programmable dual leaky bucket policing with programmable action (tag, discard, count only) each bucket, each with programmable non-compliant cell counts. Per-PHY single leaky bucket policing with programmable action (tag, discard, count only).
SCI-PHY Level Level Interface (Master) RDAT[15:0] RPRTY RDRENB[1] RCA[1] RADDR[4:3]/RCA[3:2] RAVALID/RCA[4] RADDR[2:0]/RRDENB[4:2] RSOC RFCLK RPOLL
ISYSCLK
ISD[63:0] ISP[7:0] ISA[19:16] ISA[9:0] ISWRB ISOEB ISADSB
BLOCK DIAGRAM
External Synchronous SRAM
SCI-PHY Level Interface (Slave) ODAT[15:0] OPRTY OSOC OFCLK ORDENB OTSEN
Ingress Input Cell Interface
Ingress Search Engine
Ingress Cell Processor
Ingress Output Cell Interface
Ingress Backward Cell Interface
Statistics Collection
Egress Backward Cell Interface Egress Input Cell Interface IDAT[15:0] IPRTY IFCLK ISOC ICA[1] IWRENB[1] IAVALID/ICA[4] IADDR[4:3]/ICA[3:2] IADDR[2:0]/IWRENB[4:2] IPOLL
TDAT[15:0] TPRTY TWRENB[1] TCA[1] TADDR[4:3]/TCA[3:2] TAVALID/TCA[4] TADDR[2:0]/TDWRENB[4:2] TSOC TFCLK TPOLL
Egress Output Cell
Egress Cell Processor
Ingress Microprocessor Cell Interface
Egress Microprocessor Cell Interface
JTAG Interface
Microprocessor Interface ESD[31:0] ESP[3:0] ESA[19:16] ESA[9:0] ESADSB ESRWB ESOEB ESYSCLK SCI-PHY Level Level Interface (Master) SCI-PHY Level Level Interface (Slave)
External Synchronous SRAM
PMC-2010037 (r2) PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL Copyright PMC-Sierra, Inc. 2001
Release PM7328 S/UNI-ATLAS-1K800
ALayer Solution
Guaranteed Frame Rate (GFR) Policing with Minimum Cell Rate Frame Tagging.
CELL COUNTING
Per-VC counts include CLP0 cells, CLP1 cells, policing violations. Per-PHY counts include CLP0 cells, CLP1 cells, cells, errored cells, unassigned/invalid cells policing violations. Per-device counts include total cells received/transmitted, physical layer cells.
ITU-I.610 compliant both Ingress Egress directions. Complete Fault Management (AIS, RDI, processing, VP/VC, Segment/End-to-end flows VCs. Complete Performance Monitoring processing, VP/VC, Segment/Endto-end, Forward/Backward flows, Bi-directional VCs.
power 0.35 micron, 3.3V CMOS technology with 3.3V UTOPIA (SCIPHY), 3.3/5V Microprocessor interfaces 3.3V external synchronous SRAM interfaces. Packaged 432-pin ball grid array (BGA) package.
APPLICATIONS
Mini Digital Subscriber Loop Access Multiplexer (Mini-DSLAM). Subscriber Access Equipment. Digital Loop Card Traffic Aggregation.
PACKAGING
Provides standard signal P1149.1 JTAG test port boundary scan board test purposes.
TYPICAL APPLICATION
S/UNI-ATLAS-1K800 MINI-DSLAM APPLICATION
Any-PHY/ SCI-PHY line cards Utopia ports PM7351 S/UNIVORTEX
PM7350 S/UNIDUPLEX line cards
Utopia ports
PM7350 S/UNIDUPLEX
Mbit/s LVDS
PM7329 S/UNI-APEX1K800
PM7328 S/UNI-ATLAS1K800
Context SSRAM
Ingress SSRAM
Host
Packet/Cell SDRAM
Egress SSRAM Core Card
S/UNI-ATLAS-1K800 DIGITAL LOOP CARD APPLICATION
line interface Any-PHY/ SCI-PHY
PM7329 S/UNI-APEX1K800 PM7328 S/UNI-ATLAS1K800
expansion
Context SSRAM
Ingress SSRAM
Host
Packet/Cell SDRAM
Egress SSRAM Digital Loop Card
Head Office: PMC-Sierra, Inc. #105 8555 Baxter Place Burnaby, B.C. Canada Tel: 604.415.6000 Fax: 604.415.6200
order documentation, send email document@pmc-sierra.com contact head office, Attn: Document Coordinator
product documentation available site http://www.pmc-sierra.com corporate information, send email info@pmc-sierra.com
PMC-2010037 (r2) Copyright PMC-Sierra, Inc. 2001. rights reserved. August 2001 S/UNI registered trademark PMC-Sierra, Inc. Any-PHY SCI-PHY trademarks PMC-Sierra, Inc.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
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