PALCE16V8 Family CMOS 20-Pin Universal Programmable Array Logic

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PALCE16V8 Family CMOS 20-Pin Universal Programmable Array Logic

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COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25
PALCE16V8 Family
CMOS 20-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
function compatible with 20-pin devices Electrically erasable CMOS technology provides reconfigurable logic full testability High-speed CMOS technology 5-ns propagation delay "-5" version 7.5-ns propagation delay "-7" version Direct plug-in replacement PAL16R8 series most PAL10H8 series Outputs programmable registered combinatorial combination Peripheral Component Interconnect (PCI) compliant Programmable output polarity Programmable enable/disable control Preloadable output registers testability Automatic register reset power Cost-effective 20-pin plastic DIP, PLCC, SOIC packages Extensive third-party software programmer support through FusionPLD partners Fully tested 100% programming functional yields high reliability version utilizes split leadframe improved performance
GENERAL DESCRIPTION
PALCE16V8 advanced device built with low-power, high-speed, electrically-erasable CMOS technology. functionally compatible with 20-pin devices. macrocells provide universal device architecture. PALCE16V8 will directly replace PAL16R8 PAL10H8 series devices, with exception PAL16C1. PALCE16V8 utilizes familiar sum-of-products (AND/OR) architecture that allows users implement complex logic functions easily efficiently. Multiple levels combinatorial logic always reduced sum-of-products form, taking advantage very wide input gates available devices. equations programmed into device through floatinggate cells logic array that erased electrically. fixed array allows eight data product terms output logic functions. these products feeds output macrocell. Each macrocell programmed registered combinatorial with activehigh active-low output. output configuration determined global bits local controlling four multiplexers each macrocell. AMD's FusionPLD program allows PALCE16V8 designs implemented using wide variety popular industry-standard design tools. working closely with FusionPLD partners, certifies that tools provide accurate, quality support. ensuring that thirdparty tools available, costs lowered because designer does have complete tools each device. FusionPLD program also greatly reduces design time since designer tool that already installed familiar.
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Publication# 16493 Rev. Issue Date: February 1996
Amendment
BLOCK DIAGRAM
CLK/I0
Programmable Array
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
OE/I9
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7 16493D-1
CONNECTION DIAGRAMS View DIP/SOIC
CLK/I0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE/I9
PLCC/LCC
CLK/I0 I/O7
I/O6 I/O5 I/O4 I/O3 I/O2
16493D-2
OE/I9 I/O0 I/O1
16493D-3
Note: marked orientation.
DESIGNATIONS
Clock Ground Input Input/Output Output Enable Supply Voltage PALCE16V8 Family
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ORDERING INFORMATION Commercial Industrial Products
programmable logic products commercial industrial applications available with several ordering options. order number (Valid Combination) formed combination
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable NUMBER ARRAY INPUTS OUTPUT TYPE Versatile NUMBER OUTPUTS POWER Half Power ICC) Quarter Power ICC) SPEED
OPTIONAL PROCESSING Blank Standard Processing PROGRAMMING DESIGNATOR Blank Initial Algorithm First Revision Second Revision (Same Algorithm
OPERATING CONDITIONS Commercial (0°C +75°C) Industrial (-40°C +85°C) PACKAGE TYPE 20-Pin Plastic 020) 20-Pin Plastic Leaded Chip Carrier 020) 20-Pin Plastic Gull-Wing Small Outline Package 020)
Valid Combinations PALCE16V8H-5 PALCE16V8H-7 PALCE16V8H-10 PALCE16V8Q-10 PALCE16V8H-15 PALCE16V8Q-15 PALCE16V8Q-20 PALCE16V8H-25 PALCE16V8Q-25
Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Blank,
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PALCE16V8H-5/7/10/15/25, Q-10/15/25 (Com'l) H-10/15/25, Q-20/25 (Ind)
FUNCTIONAL DESCRIPTION
PALCE16V8 universal device. eight independently configurable macrocells (MC0-MC7). Each macrocell configured registered output, combinatorial output, combinatorial dedicated input. programming matrix implements programmable logic array, which drives fixed logic array. Buffers device inputs have complementary outputs provide user-programmable input signal polarity. Pins serve either array inputs clock (CLK) output enable (OE), respectively, flip-flops. Unused input pins should tied directly GND. Product terms with bits unprogrammed (disconnected) assume logical HIGH state product terms with both true complement input signal connected assume logical state. programmable functions PALCE16V8 automatically configured from user's design
specification. design specification processed development software verify design create programming file (JEDEC). This file, once downloaded programmer, configures device according user's desired function. user given design options with PALCE16V8. First, programmed standard device from PAL16R8 PAL10H8 series. programmer manufacturer will supply device codes standard device architectures used with PALCE16V8. programmer will program PALCE16V8 corresponding architecture. This allows user existing standard device JEDEC files without making changes them. Alternatively, device programmed PALCE16V8. Here user must PALCE16V8 device code. This option allows full utilization macrocell.
Adjacent Macrocell
SL1X SL0X I/OX
From Adjacent
16493D-4
macrocells MC7, replaced feedback multiplexer.
PALCE16V8 Macrocell
PALCE16V8 Family
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Configuration Options
Each macrocell configured following: registered output, combinatorial output, combinatorial I/O, dedicated input. registered output configuration, output buffer enabled pin. combinatorial configuration, buffer either controlled product term always enabled. dedicated input configuration, always disabled. With exception MC7, macrocell configured dedicated input derives input signal from adjacent I/O. derives input from (OE) from (CLK). macrocell configurations controlled configuration control word. contains global bits (SG0 SG1) local bits (SL00 through SL07 SL10 through SL17). determines whether registers will allowed. determines whether PALCE16V8 will emulate PAL16R8 family PAL10H8 family device. Within each macrocell, SL0x, conjunction with SG1, selects configuration macrocell, SL1x sets output either active active high individual macrocell. configuration bits work acting control inputs multiplexers macrocell. There four multiplexers: product term input, enable select, output select, feedback select multiplexer. SL0x control signals four multiplexers. MC7, replaces feedback multiplexer. This accommodates being adjacent adjacent MC0.
feedback path will feedback path MC0.
Combinatorial Non-Registered Device
control settings SL0x Only seven product terms available gate. eighth product term used enable output buffer. signal back array feedback multiplexer. This allows used input. Because used non-registered device, pins available inputs. will feedback path will feedback path MC0.
Combinatorial Registered Device
control settings SL0x Only seven product terms available gate. eighth product term used output enable. feedback signal corresponding signal.
Dedicated Input Configuration
control settings SL0x output buffer disabled. Except feedback signal adjacent I/O. feedback signals pins These configurations summarized Table illustrated Figure Table Macrocell Configuration
Registered Output Configuration
control settings SL0x There only registered configuration. eight product terms available inputs gate. Data polarity determined SL1x. flip-flop loaded LOW-to-HIGH transition CLK. feedback path from register. output buffer enabled
Combinatorial Configurations
PALCE16V8 three combinatorial output configurations: dedicated output non-registered device, non-registered device registered device.
SL0X Cell Configuration Devices Emulated Device Uses Registers Registered Output PAL16R8, 16R6, 16R4 Combinatorial PAL16R6, 16R4 Device Uses Registers Combinatorial PAL10H8, 12H6, Output 14H4, 16H2, 10L8, 12L6, 14L4, 16L2 Input PAL12H6, 14H4, 16H2, 12L6, 14L4, 16L2 Combinatorial PAL16L8
Programmable Output Polarity
polarity each macrocell active-high active-low, either match output signal needs reduce product terms. Programmable polarity allows Boolean expressions written their most compact form (true inverted), output still desired polarity. also save "DeMorganizing" efforts. Selection through programmable SL1x which controls exclusive-OR gate output AND/ logic. output active high SL1x active SL1x
Dedicated Output Non-Registered Device
control settings SL0x eight product terms available gate. Although macrocell dedicated output, feedback used, with exception pins Pins feedback this mode. Because used non-registered device, pins available input signals. will 2-40
PALCE16V8 Family
Registered Active
Registered Active High
Combinatorial Active
Combinatorial Active High
Note
Note
Combinatorial Output Active
Combinatorial Output Active High
Notes: Feedback available pins combinatorial output mode. This configuration available pins
Adjacent Note
Dedicated Input Figure Macrocell Configurations PALCE16V8 Family
16493D-5
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Power-Up Reset
flip-flops power logic predictable system initialization. Outputs PALCE16V8 will depend whether they selected registered combinatorial. registered selected, output will HIGH. combinatorial selected, output will function logic.
Programming Erasing
PALCE16V8 programmed standard logic programmers. also erased reset previously configured device back virgin state. Erasure automatically performed programming hardware. special erase operation required.
Quality Testability
PALCE16V8 offers very high level built-in quality. erasability device provides direct means verifying performance parameters. addition, this verifies complete programmability functionality device provide highest programming yields post-programming functional yields industry.
Register Preload
register PALCE16V8 preloaded from output pins facilitate functional testing complex state machine designs. This feature allows direct loading arbitrary states, making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery.
Technology
high-speed PALCE16V8 fabricated with AMD's advanced electrically erasable (EE) CMOS process. array connections formed with proven cells. Inputs outputs designed compatible with devices. This technology provides strong input clamp diodes, output slew-rate control, grounded substrate clean switching.
Security
security provided PALCE16V8 deterrent unauthorized copying array configuration patterns. Once programmed, this defeats readback verification programmed pattern device programmer, securing proprietary designs from competitors. only erased conjunction with array during erase cycle.
Compliance
PALCE22V10H-7/10 fully compliant with Local Specification published Special Interest Group. PALCE22V10H-7/10's predictable timing ensures compliance with specifications independent design.
Electronic Signature Word
electronic signature word provided PALCE16V8 device. consists bits programmable memory that contain user-defined data. signature data always available user independent security bit.
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PALCE16V8 Family
LOGIC DIAGRAM
CLK/I
I/O7
I/O6
SL16
I/O5
I/O4
16493D-6
PALCE16V8 Family
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LOGIC DIAGRAM (continued)
I/O1
SL00
OE/I
16493D-6 (concluded)
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PALCE16V8 Family
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Static) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT mA),
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE16V8H-5 (Com'l)
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CAPACITANCE (Note
Parameter Symbol COUT Parameter Descriptions Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tSKEWR Clock Width Maximum Frequency (Note Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output Skew Between Registered Outputs (Note HIGH External Feedback Internal Feedback (fCNT), Feedback 1/(tS+tCO) 1/(tS+tCF) (Note 1/(tWH+tWL) 142.8 (Note Unit
fMAX
tPZX tPXZ
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. Skew testing takes into account pattern switching direction differences between outputs that have equal loading. Output delay minimums tPD, tCO, tPZX, tPXZ, tEA, defined under best case conditions. Future process improvements alter these values therefore, minimum values recommended simulation purposes only. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
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PALCE16V8H-5 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating Ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Dynamic) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note (Note (Note VOUT Max, (Note VOUT (Note VOUT (Note Outputs Open, (IOUT mA), Max,
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit test should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE16V8H-7 (Com'l)
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CAPACITANCE (Note
Parameter Symbol COUT Parameter Descriptions Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tSKEWR fMAX tPZX tPXA Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Hold Time Clock Output Skew Between Registered Outputs (Note Clock Width Maximum Frequency (Note HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) Outputs Switching Output Switching (Note Unit
Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. Skew testing takes into account pattern switching direction differences between outputs that have equal loading. Output delay minimums tPD, tCO, tPZX, tPXZ, tEA, defined under best case conditions. Future process improvements alter these values therefore, minimum values recommended simulation purposes only. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
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PALCE16V8H-7 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25 Industrial Devices Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges
Parameter Symbol IOZH IOZL (Dynamic) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Commercial Supply Current Industrial Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note
Outputs Open (IOUT Max,
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE16V8H-10 (Com'l, Ind)
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CAPACITANCE (Note
Parameter Symbol COUT Parameter Descriptions Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges (Note
Parameter Symbol Clock Width Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output HIGH External Feedback fMAX Maximum Frequency (Note Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) (Note 66.7 71.4 83.3 Unit
tPZX tPXZ
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. Output delay minimums tPD, tCO, tPZX, tPXZ, tEA, defined under best case conditions. Future process improvements alter these values therefore, minimum values recommended simulation purposes only. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
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PALCE16V8H-10 (Com'l, Ind)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Dynamic) Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT Max,
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE16V8Q-10 (Com'l)
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CAPACITANCE (Note
Parameter Symbol COUT Parameter Descriptions Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Clock Width Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) (Note 66.7 71.4 83.3 Unit
fMAX
Maximum Frequency (Note Output Enable Output Disable
tPZX tPXZ
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. Output delay minimums tPD, tCO, tPZX, tPXZ, tEA, defined under best case conditions. Future process improvements alter these values therefore, minimum values recommended simulation purposes only. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
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PALCE16V8Q-10 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25 Industrial Devices Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges
Parameter Symbol IOZH IOZL (Dynamic) (Dynamic) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Commercial Supply Current Industrial Supply Current Test Conditions -3.2 -100 -100 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT Max, Outputs Open (IOUT Max,
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE16V8H-15/25, Q-15/25 (Com'l, Ind), Q-20 (Ind)
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CAPACITANCE (Note
Parameter Symbol COUT Parameter Descriptions Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges (Note
Parameter Symbol Maximum Frequency (Note Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output Clock Width HIGH External Feedback Internal Feedback (fCNT) Feedback tPZX tPXZ Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control 1/(tS tCO) 1/(tS tCO) (Note 1/(tWH tWL) 45.5 62.5 41.6 45.4 50.0 41.6 Unit
fMAX
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
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PALCE16V8H-15/25, Q-15/25 (Com'l, Ind), Q-20 (Ind)
SWITCHING WAVEFORMS
Input Feedback Combinatorial Output
16493D-7
Input Feedback
Clock Registered Output
16493D-8
Combinatorial Output
Registered Output
Input Clock
16493D-9
0.5V 0.5V
Output
16493D-10
Clock Width
Input Output Disable/Enable
tPXZ Output 0.5V 0.5V tPZX
16493D-11
Output Disable/Enable
Notes: Input pulse amplitude Input rise fall times typical.
PALCE16V8 Family
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SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
16493D-12
Commercial Specification tPD, Closed Open Closed Open Closed H-5:
Measured Output Value
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PALCE16V8 Family
TYPICAL CHARACTERISTICS 25°C
16V8H-5
16V8H-7 (mA) 16V8H-10 16V8H-15/25
16V8Q-10/15/25
16493D-13
Frequency (MHz)
Frequency
selected "typical" pattern utilized device resources. Half macrocells were programmed registered, other half were programmed combinatorial. Half available product terms were used each macrocell. vector, half outputs were switching. utilizing device, midpoint defined ICC. From this midpoint, designer scale graphs down estimate requirements particular design.
PALCE16V8 Family
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ENDURANCE CHARACTERISTICS
PALCE16V8 manufactured using AMD's advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar
Symbol Parameter Pattern Data Retention Time Reprogramming Cycles
parts. result, device erased reprogrammed-a feature which allows 100% testing factory.
Unit Years Years Cycles
Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions
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PALCE16V8 Family
ROBUSTNESS FEATURES
PALCE16V8X-X/5 devices have some unique features that make them extremely robust, especially when operating high-speed design environments. Pull-up resistors inputs pins cause unconnected pins default known state. Input clamping circuitry limits negative overshoot, eliminating possibility false
clocking caused subsequent ringing. special noise filter makes programming circuitry completely insensitive positive overshoot that pulse width less than about versions. Selected devices also being retrofitted with these robustness features. chart below device listings.
INPUT/OUTPUT EQUIVALENT SCHEMATICS VERSIONS SELECTED VERSIONS*
Protection Clamping
Programming Pins only
Programming Voltage Detection
Positive Overshoot Filter
Programming Circuitry
Typical Input
Provides Protection Clamping Preload Circuitry Feedback Input
Typical Output
16493D-14
Letter Topside Marking: Filter Only Filter Pullups CMOS PLD's marked package PALCE16V8H-10 following manner: PALCE16V8H-15 PALCEXXXX Date Code numbers) characters)- -(Rev. Letter) PALCE16V8Q-15 Letter separated spaces. PALCE16V8H-25 Device PALCE16V8Q-25
PALCE16V8 Family
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POWER-UP RESET
PALCE16V8 been designed with capability reset during system power-up. Following power-up, flip-flops will reset LOW. output state will HIGH independent logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset
Parameter Symbol Parameter Descriptions Power-Up Reset Time Input Feedback Setup Time Clock Width
wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
1000
Unit
Switching Characteristics
Power
Registered Output
Clock
16493D-15
Power-Up Reset Waveform
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PALCE16V8 Family
TYPICAL THERMAL CHARACTERISTICS Devices (PALCE16V8H-10/4)
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal Impedance, Junction Case Thermal Impedance, Junction Ambient Thermal Impedance, Junction Ambient with Flow Ifpm Ifpm Ifpm Ifpm PDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Devices (PALCE16V8H-7/5)
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal Impedance, Junction Case Thermal Impedance, Junction Ambient Thermal Impedance, Junction Ambient with Flow Ifpm Ifpm Ifpm Ifpm PDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
PALCE16V8 Family
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PALCE16V8 Family CMOS 20-Pin Universal Programmable Array Logic

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