June 1992 NSC800 High-Performance Low-Power CMOS Microprocessor
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NSC800 High-Performance Low-Power CMOS Microprocessor
June 1992
NSC800 High-Performance Low-Power CMOS Microprocessor
NSC800 8-bit CMOS microprocessor that functions central processing unit (CPU) National Semiconductor's NSC800 microcomputer family National's microCMOS technology used fabricate this device provides system designers with performance equivalent comparable NMOS products with power advantage CMOS Some many system functions incorporated device vectored priority interrupts refresh control power-save feature interrupt acknowledge NSC800 available dual-in-line surface mounted chip carrier packages system designer choose only from dedicated CMOS peripherals that allow direct interfacing NSC800 from full line National's CMOS products allow low-power system solution dedicated peripherals include NSC810A Timer NSC858 UART NSC831 devices available commercial industrial military temperature ranges along with added reliability flows first extended burn test second military class screening accordance with Method 5004 MIL-STD-883
Features
Fully compatible with instruction Powerful instructions addressing modes internal registers power Unique power-save feature Multiplexed structure Schmitt trigger input reset On-chip controller clock generator Variable power supply 4Vb6 On-chip 8-bit dynamic refresh circuitry Speed instruction cycle NSC800-4 NSC800-35 NSC800-3 NSC800-1 Capable addressing bytes memory devices Five interrupt request lines on-chip
Block Diagram
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NSC800is trademark National Semiconductor Corp TRI-STATE registered trademark National Semiconductor Corp registered trademark Zilog Corp C1995 National Semiconductor Corporation 5171 RRD-B30M105 Printed
Table Contents
ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS TIMING WAVEFORMS NSC800 HARDWARE DESCRIPTIONS Input Signals Output Signals Input Output Signals CONNECTION DIAGRAMS FUNCTIONAL DESCRIPTION Register Array Dedicated Registers Program Counter Stack Pointer Index Register Interrupt Register Refresh Register Working Alternate Register Sets Working Registers Alternate Registers Register Functions Accumulator Register Flags Carry Adds Subtract Parity Overflow Half Carry Zero Flag Sign Flag Additional General Purpose Registers Alternate Configurations Arithmetic Logic Unit (ALU) Instruction Register Decoder TIMING CONTROL Internal Clock Generator Timing Initialization Power Save Feature TIMING CONTROL Access Control Interrupt Control NSC800 SOFTWARE INTRODUCTION ADDRESSING MODES Register Implied Immediate Immediate Extended Direct Addressing Register Indirect Indexed Relative Modified Page Zero INSTRUCTION Instruction Index Alphabetical Instruction Mnemonic Notation Assembled Object Code Notation 8-Bit Loads 16-Bit Loads 8-Bit Arithmetic 16-Bit Arithmetic Reset Test Rotate Shift Exchanges Memory Block Moves Searches Input Output Control Program Control Instruction Alphabetical Order Instruction Numerical Order DATA ACQUISITION SYSTEM NSC800M 883B CLASS SCREENING BURN-IN CIRCUITS ORDERING INFORMATION RELIABILITY INFORMATION
Absolute Maximum Ratings (Note
Military Aerospace specified devices required please contact National Semiconductor Sales Office Distributors availability specifications Storage Temperature Voltage with Respect Ground Maximum Power Dissipation Lead Temp (Soldering seconds)
Operating Conditions NSC800-1
NSC800-3
NSC800-35 883C NSC800-4 NSC800-4MIL
Electrical Characteristics
Symbol VOH1 VOH2 VOL1 VOL2 COUT Parameter Logical Input Voltage Logical Input Voltage Hysteresis RESET input Logical Output Voltage Logical Output Voltage Logical Output Voltage Logical Output Voltage Input Leakage Current Output Leakage Current Active Supply Current Active Supply Current Active Supply Current Active Supply Current Quiescent Current Power-Save Current Input Capacitance Output Capacitance Power Supply Voltage (Note IOUT IOUT IOUT IOUT Conditions
unless otherwise specified
Units
IOUT f(XIN) IOUT f(XIN) IOUT f(XIN) IOUT f(XIN) IOUT f(XIN) IOUT f(XIN)
Note Absolute Maximum Ratings indicate limits beyond which permanent damage occur Continuous operation these limits intended should limited those conditions specified under Electrical Characteristics Note operation lower voltages will reduce maximum operating speed Operation voltages other than guaranteed design tested
Electrical Characteristics
Symbol tACC(OP) tACC(MR) tAFR tBABE tBABF tBACL tBRH tBRS tCAF tCAR tCRD tCRF tDAI tDAR tDAW Parameter Period XOUT Pins Period Clock Output Clock Rise Time Clock Fall Time Clock Time Clock High Time Valid Data Valid Data AD(0 Float after Falling BACK Rising Enable BACK Falling Float BACK Fall Falling BREQ Hold Time BREQ Set-Up Time Clock Falling Falling Clock Rising Rising Clock Rising Read Rising Clock Rising Refresh Falling Falling INTA Falling Falling Falling Falling Falling 2460 1340 1875 1000 NSC800-1 NSC800-3
unless otherwise specified NSC800-4 each WAIT state opcode fetch cycles Figure also each WAIT state opcode fetch cycles Measured from signal Measured from signal duty cycle square wave input duty cycle square wave input each WAIT STATE each WAIT STATE Units Notes
NSC800-35 3333 6667
3333 3333
3333 6667
1000 6667 6667
1010 1610 1360
tD(BACK)1 Falling BACK Falling tD(BACK)2 BREQ Rising BACK Rising tD(I) Falling INTR RSTA-C BREQ Inputs Valid Rising Falling Falling WAIT Input Valid
tDPA tD(WAIT)
1685
Opcode Fetch Memory Read
Electrical Characteristics
Symbol Parameter NSC800-1 TH(ADH)1 A(8-15) Hold Time During Opcode Fetch TH(ADH)2 A(8-15) Hold Time During Memory TH(ADL) TH(WD) tINH tINS tNMI tRDH tRFLF tRL(MR) tS(AD) tS(ALE) tS(WD) tW(ALE) tW(I) tW(INTA) AD(0-7) Hold Time Write Data Hold Time Interrupt Hold Time Interrupt Set-Up Time Width Input Data Hold after Read RFSH Rising Falling Rising Rising (Memory Read) AD(0-7) Set-Up Time A(8-15) Set-Up Time Write Data Set-Up Time Width WAIT Hold Time Width INTR RSTA-C BREQ INTA Strobe Width 1000 NSC800-3
unless otherwise specified (Continued) NSC800-4 states first INTA each interrupt response string each WAIT state each WAIT State Memory Read Cycles Units Notes
NSC800-35
tW(RD)
Rising Rising Read Strobe Width During Opcode Fetch Refresh Strobe Width WAIT Set-Up Time WAIT Input Width Write Strobe Width Clock Falling Clock Rising
tW(RFSH) tW(WAIT) tW(WR) tXCF tXCR
1925
each WAIT state
Note Test conditions 1000 NSC800-1 NSC800 NSC800-35 NSC800-4 Note Output timings measured with purely capacitive load
Timing Waveforms
Opcode Fetch Cycle
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Memory Read Write Cycle
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Timing Waveforms (Continued)
Interrupt Power-Save Cycle
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Note This state last state last cycle instruction Note Response INTR input Note Response input
Acknowledge Cycle
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Waveform drawn proportion only specifying test points
Testing Input Output Waveform
Testing Load Circuit
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NSC800 HARDWARE Descriptions
INPUT SIGNALS Reset Input (RESET Active Sets (8-15) TRI-STATE (high impedance) Clears contents registers disables interrupts activates reset Request (BREQ) Active Used when another device requests system NSC800 recognizes BREQ current machine cycle sets AD(0 high impedance state RFSH high during request cycle acknowledges request BACK output signal Non-Maskable Interrupt (NMI) Active non-maskable interrupt generated peripheral device(s) highest priority interrupt edge sensitive interrupt requires only pulse internal flip-flop which generates internal interrupt request flip-flop monitored same clock edge other interrupts must also meet minimum set-up time spec interrupt accepted current machine instruction When processor accepts interrupt flip-flop resets automatically Interrupt execution independent interrupt enable flip-flop execution results saving stack automatic branching restart address X'0066 memory Restart Interrupts (RSTA RSTB RSTC) Active level sensitive recognizes restarts generated peripherals current instruction their respective interrupt enable master enable bits Execution identical except interrupts vector following restart addresses Restart Name Address (X') 0066 RSTA 003C RSTB 0034 RSTC 002C INTR (Mode 0038 order priority fixed list above starts with highest priority Interrupt Request (INTR) Active level sensitive recognizes interrupt request current instruction provided that interrupt enable master interrupt enable bits INTR lowest priority interrupt Program control selects three response modes which determines method servicing INTR conjunction with INTA Interrupt Control Wait (WAIT) Active When during INTA machine cycles (during machine cycle wait must valid prior write going active) extends machine cycle increments (wait) states wait machine cycle continues until WAIT input returns high wait strobe input will accepted only during machine cycles that have INTA strobes during machine cycle immediately after interrupt been accepted later cycle strobe suppressed will still accept wait Power-Save (PS) Active sampled during last state current instruction cycle When stops executing current instruction keeps itself low-power mode Normal operation resumes when returns high (see Power Save Feature description) CRYSTAL (XIN XOUT) used external clock input crystal connected across XOUT provide source system clock OUTPUT SIGNALS Acknowledge (BACK) Active BACK indicates requesting device that control signals TRI-STATE mode requesting device then commands control signals Address Bits Active high These most significant bits memory address during memory instruction During instruction port address lower address bits gets duplicated onto During BREQ BACK cycle TRI-STATE mode Reset (RESET OUT) Active high When RESET high indicates being reset This signal normally used reset peripheral devices Input Output Memory active high output signifies that current machine cycle input output cycle active output signifies that current machine cycle memory cycle TRISTATE during BREQ BACK cycles Refresh (RFSH) Active refresh output indicates that dynamic refresh cycle progress RFSH goes during states cycles During refresh cycle AD(0 refresh address indicates interrupt vector register data RFSH high during BREQ BACK cycles Address Latch Enable (ALE) Active high active only during state cycle also state cycle high transition indicates that valid memory refresh address available AD(0 lines Read Strobe (RD) Active receives data AD(0 lines trailing edge strobe line TRI-STATE mode during BREQ BACK cycles Write Strobe (WR) Active sends data AD(0 lines while strobe line TRI-STATE mode during BREQ BACK cycles Clock (CLK) output provided system clock output square wave half input frequency Interrupt Acknowledge (INTA) Active This signal strobes interrupt response vector from interrupting peripheral devices onto AD(0 lines INTA active during cycle immediately following state where recognized INTR interrupt request three interrupt request modes INTA mode four INTA signals strobe four byte instruction onto AD(0 lines mode INTA signal strobes lower byte interrupt response vector onto mode INTA inactive response INTR same restart interrupt
Descriptions (Continued)
Status status outputs provide encoded information regarding current cycle follows Machine Cycle Opcode Fetch Memory Read Memory Write Read Write Halt Internal Operation Acknowledge Status Control INPUT OUTPUT SIGNALS Multiplexed Address Time Time Falling Edge Time Data AD(0 Active high Input data Output data from Least significant byte address during memory reference cycle 8-bit port address during reference cycle High impedance
During BREQ BACK Cycle
suppressed this cycle This cycle that occurs immediately after accepts interrupt (RSTA RSTB RSTC INTR NMI) Note During halt continues dummy opcode fetch from location following halt instruction with halt status This continue dynamic refresh Note early status provided interrupt hardware restarts
Connection Diagrams
Dual-In-Line Package Chip Carrier Package
View
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Order Number NSC800E Package E44B V44A
View
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Order Number NSC800D Package D40C N40A
Functional Description
This section reviews architecture shown below focusing functional aspects from hardware perspective including timing details illustrated Figure NSC800 8-bit parallel device major functional blocks register array interrupt control timing control logic These areas connected 8-bit internal data Detailed descriptions these blocks provided following sections
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Note Applicable pinout 40-pin dual-in-line package within parentheses
FIGURE NSC800 Functional Block Diagram
Functional Description (Continued)
REGISTER ARRAY NSC800 register array divided into parts dedicated registers working registers shown Figure Main Alternate Stack Pointer (SP) 16-bit stack pointer contains address current stack that located external system stack organized last-in first-out (LIFO) structure pointer decrements before data pushed onto stack increments after data popped from stack Various operations store retrieve data stack This along with usage subroutine calls interrupts allows simple implementation subroutine interrupt nesting well alleviating many problems data manipulation Index Register NSC800 contains index registers hold independent 16-bit base addresses used indexed addressing mode this mode index register either contains base address area memory making pointer data tables instructions employing indexed modes operation another byte acts signed two's complement displacement This addressing mode enables easy data table manipulations Interrupt Register When NSC800 provides Mode response INTR action taken indirect call memory location containing service routine address pointer address service routine formed bytes high-byte from Register low-byte from interrupting peripheral peripheral always provides even address lower byte (LSB When processor receives lower byte from peripheral concatenates following manner Register bits (16) (16) (16) (16) External byte
Accumulator Flags Accumulator Flags Interrupt Vector Memory Refresh Dedicated Registers
Working Registers
Index Register Index Register Stack Pointer Program Counter
FIGURE NSC800 Register Array DEDICATED REGISTERS There dedicated registers NSC800 8-bit four 16-bit registers (see Figure Although their contents under program control program control over their operational functions unlike working registers function each dedicated register described follows Dedicated Registers Program Counter Stack Pointer Index Register Index Register Interrupt Vector Register Memory Refresh Register
external byte must zero
FIGURE Dedicated Registers Program Counter (PC) program counter contains 16-bit address current instruction being fetched from memory increments after contents have been transferred address lines When program jump occurs receives address which overrides incrementer There many conditional unconditional jumps calls return instructions NSC800's instruction repertoire that allow easy manipulation this register controlling program execution CALL
FIGURE Interrupt Register even memory location contains low-order byte next consecutive location contains high-order byte pointer beginning address interrupt service routine Refresh Register systems that dynamic memories rather than static RAM's NSC800 provides integral 8-bit memory refresh counter contents register incremented after each opcode fetch sent lower portion address along with refresh control signal This provides totally transparent refresh cycle does slow down operation program read write register although this usually done only test purposes
Functional Description (Continued)
WORKING ALTERNATE REGISTER SETS Working Registers portion register array shown Figure represents working registers These sixteen 8-bit registers general-purpose registers because they perform multitude functions depending instruction being executed They grouped together also types instructions that them particularly alternate operations (flag) register special-purpose register because contents more result machine status rather than program data register included because interaction with register manipulations alternate register operations Alternate Registers NSC800 registers designated working registers have common feature existence duplicate register alternate register This architectural concept simplifies programming during operations such interrupt response when machine status represented contents registers must saved alternate register concept makes registers available programmer given time instructions A`F' EXX) exchange current working registers with their alternate exchange between registers their respective duplicates saves primary status information contained accumulator flag register second exchange instruction performs exchange between remaining registers their respective alternates This essentially saves contents original complement registers while providing programmer with usable alternate Main Working Register Accumulator Register Register Register REGISTER FUNCTIONS Accumulator Register) register serves source destination register data manipulation instructions addition serves accumulator results 8-bit arithmetic logic operations register also special status some types operations that certain addressing modes reserved register only although function available other registers example register loaded immediate register indirect indexed addressing modes register however also loaded additional register indirect addressing Another special feature register that produces more efficient memory coding than equivalent instruction functions directed other registers register rotated however while requires two-byte instruction normally rotate register single-byte instruction available rotating contents accumulator register) Register Flags NSC800 flag register consists status bits that contain information regarding results previous operations register read pushing contents onto stack then reading however cannot written classified register because affiliation with accumulator existence duplicate register exchange instructions with accumulator flags shown Figure only four directly tested programmer conditional jump call return instructions They Sign Zero Parity Overflow Carry flags Half Carry Subtract flags used internal operations related arithmetic
Flags Register Register Register
Alternate Working Register Accumulator Flags Register Register Register Register Register Register
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FIGURE Flag Register
FIGURE Working Alternate Registers
Functional Description (Continued)
Carry carry from highest order accumulator during instruction borrow generated during subtraction instruction sets carry flag Specific shift rotate instructions also affect this specific instructions NSC800 instruction repertoire (SCF) complement (CCF) carry flag Other operations that affect flag follows Adds Subtracts Logic Operations (always resets flag) Rotate Accumulator Rotate Shifts Decimal Adjust Negation Accumulator Other operations affect flag Adds Subtract This flag used conjunction with flag ensure that proper correction algorithm used during decimal adjust instruction (DAA) correction algorithm depends whether subtract previously done with operands operations that flag following operations affect flag according parity result operation Logic Operations Rotate Shift Rotate Digits Decimal Adjust Input Register Indirect following operations affect flag according overflow result operation
Increments Decrements Negation Accumulator flag significance immediately after following operations Block Tests block transfers compares flag indicates status register always ending reset state after auto repeat block move Other operations affect flag Half Carry This flag indicates carry borrow result from low-order four bits operation used correct results previously packed decimal subtract operation Decimal Adjust Instruction (DAA) following operations affect flag Adds (8-bit) Subtracts (8-bit) Increments Decrements Decimal Adjust Negation Accumulator Always Logic Complement Accumulator Testing Always Reset Logic OR's XOR's Rotates Shifts Carry Input Register Indirect Block Transfers Loads Registers flag significance immediately after following operations 16-bit Adds with without carry 16-Bit Subtracts with carry Complement carry Block Block Searches Other operations affect flag
Adds with carry 8-bit with without carry) Subtracts with carry 8-bit with without carry)
Block Searches Negation Accumulator operations that reset flag Adds Increments Logic Operations Rotates Complement Carry Input Register Indirect Block Transfers Load Registers Tests Other operations affect flag Parity Overflow Parity Overflow flag dual-purpose flag that indicates results logic arithmetic operations logic operations flag indicates parity result flag (high) result even reset (low) result arithmetic operations represents overflow condition when result interpreted signed two's complement arithmetic range eight-bit accumulator b128 127)
Subtractions Decrements (8-bit) Complementing Accumulator Block
Functional Description (Continued)
Zero Flag Loading zero accumulator when zero results from operation sets zero flag following operations affect zero flag Additional General-Purpose Registers other general-purpose registers registers their alternate register general-purpose registers used interchangeably addition registers perform special functions NSC800 expanded capabilities particularly block operations these functions register address ports register provides counter function when used register indirect address mode When used with special condition jump instruction (DJNZ) register again provides counter function Alternate Configurations 8-bit general purpose registers will combine form three 16-bit registers This occurs concatenating registers form register registers form register registers form register Having these 16-bit registers allows 16-bit data handling thereby expanding number 16-bit registers available memory addressing modes register typically provides pointer address register indirect addressing memory register provides second memory pointer register NSC800's powerful block transfer operations register also provides assist block transfer operations acting byte-counter these operations ARITHMETIC-LOGIC UNIT (ALU) arithmetic logic rotate instructions performed internally communicates with registers data buffer 8-bit internal data INSTRUCTION REGISTER DECODER During opcode fetch first byte instruction transferred from data buffer internal data bus) instruction register instruction register feeds instruction decoder which gated timing signals generates control signals that read write data from registers control provide required external control signals
Block (always after auto repeat block Block Searches Load Registers Tests Negation Accumulator flag signficance immediately after following operations
Adds (16-bit with carry 8-bit with without carry) Subtracts (16-bit with carry 8-bit with without carry) Logic Operations Increments Decrements Rotate Shifts Rotate Digits Decimal Adjust Input Register Indirect
Block Transfers Other operations affect zero flag Sign Flag sign flag stores state (the most-significant sign bit) accumulator following arithmetic operation This flag when dealing with signed numbers sign flag affected following operation according result
Subtracts (16-bit with carry 8-bit with without carry) Logic Operations Increments Decrements Rotate Shifts Rotate Digits Decimal Adjust Input Register Indirect Block Search Load Registers Negation Accumulator flag significance immediately after following operations Block Block Transfers Tests Other operations affect sign
Adds (16-bit with carry 8-bit with without carry)
Timing Control
INTERNAL CLOCK GENERATOR inverter oscillator contained NSC800 chip provides necessary timing signals chip operation frequency equal half frequency this oscillator oscillator frequency controlled following methods Leaving XOUT unterminated driving with externally generated clock shown Figure When driving with square wave minimum duty cycle high
f(XTAL)
(Recommended)
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FIGURE External Clock Connecting crystal with proper biasing network between XOUT shown Figure Recommended crystal parallel resonance crystal
Note crystal frequency between series resistor (470X 1500X) should connected between XOUT XTAL Additionally capacitance should increased times recommended value crystal frequencies less than higher values required Crystal parameters will also affect capacitive loading requirements
FIGURE Crystal minimum clock frequency input XIN) which results system clock speed registers internal chip static however there dynamic logic which limits minimum clock speed input clock stopped without fear losing data damaging part stop phase clock that high When restarting precautions must taken that input clock meets these minimum specification Once started will continue operation from same location which stopped During operation typical current drain will This current drain reduced placing wait state during opcode fetch cycle then stopping clock clock stop circuit Figure
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FIGURE Clock Stop Circuit
Timing Control (Continued)
TIMING NSC800 uses multiplexed data addresses 16-bit address divided into high-order 8-bit address that handles bits 8-15 address low-order 8-bit multiplexed address data that handles bits address bits data Strobe outputs from NSC800 (ALE indicate when valid address data present indicates whether ensuing cycle accesses memory During input output instruction duplicates lower half address AD(0 onto upper address eight bits address will stay entire machine cycle used chip selection directly
Figure illustrates timing relationship opcode fetch cycles with without wait state
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FIGURE Opcode Fetch Cycles without WAIT States
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FIGURE Opcode Fetch Cycles with WAIT States
Timing Control (Continued)
During opcode fetch places contents address falling edge indicates valid address AD(0-7) lines WAIT input sampled during active causes NSC800 insert wait state (tw) WAIT sampled again during that when goes inactive continues opcode fetch latching data rising edge from AD(0 lines During RFSH goes active AD(0 dynamic refresh address from register interrupt vector from register
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FIGURE Memory Read Write Cycles without WAIT States
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FIGURE Memory Read Write with WAIT States
Timing Control (Continued) Figure shows timing memory read (other than opcode fetchs) write cycles with without wait state stobe widened (half machine state) memory reads that actual latching input data occurs later
Figure shows timing input output cycles with without wait states automatically inserts wait state into each instruction allow sufficient time port decode address
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FIGURE Input Output Cycles without WAIT States
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WAIT state automatically inserted during operation
FIGURE Input Output Cycles with WAIT States
Timing Control (Continued)
INITIALIZATION RESET initializes NSC800 RESET initializes peripheral components Schmitt trigger RESET input facilitates using network reset scheme during power (see Figure ensure proper power-up conditions NSC800 following power-up initialization procedure recommended Apply power (VCC GND) RESET active (low) Allow sufficient time (approximately crystal used) oscillator internal clocks stabilize RESET must remain least state (CLK) times RESET goes high soon active RESET signal clocked into first flip-flop after on-chip Schmitt trigger RESET signal available reset peripherals RESET high RESET then goes inactive RESET signal clocked into first flip-flop after on-chip Schmitt trigger Following this initiates first opcode fetch cycle Note NSC800 initialization includes Clear X'0000 (the first opcode fetch therefore from memory location X'0000) Clear registers (Interrupt Vector Base) (Refresh Counter) X'00 Clear interrupt control register bits interrupt control maintain INS8080A Z80A compatibility (see INTERRUPTS more details) disables maskable interrupts enters INTR Mode While RESET active (low) A(8-15) AD(0-7) lines high impedance (TRI-STATE) strobes inactive state (see Figure
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FIGURE Power-On Reset
POWER-SAVE FEATURE NSC800 provides unique power-save mode means input sampled last state last cycle instruction After recognizing active (low) level NSC800 stops internal clocks thereby reducing power dissipation half operating power maintaining register values internal control status NSC800 keeps oscillator running makes signal available system When power-save strobe will stopped high address lines AD(0 will indicate next machine address When returns high opcode fetch cycle) begins normal manner Note this cycle could also interrupt acknowledge cycle NSC800 interrupted simultaneously with priority over simultaneously occurring interrupt) However interrupts accepted during power save Figure illustrates power save timing
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FIGURE NSC800 Signals During Power-On Manual Reset
Timing Control (Continued)
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FIGURE NSC800 Power-Save
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during BREQ will indicate same machine cycle during cycle when BREQ accepted time states during which control signals high impedance mode
FIGURE Acknowledge Cycle event BREQ asserted (low) instruction cycle active simultaneously following occurs NSC800 will into BACK cycle Upon completion BACK cycle still active will into power-save mode ACCESS CONTROL Figure illustrates access control NSC800 external device controller produces active BREQ signal that requests When responds with BACK then related control strobes high impedance (TRI-STATE) RFSH signal remains high should noted that BREQ sampled last state machine cycle only NSC800 will acknowledge interrupt restart requests will peform dynamic refresh functions until after BREQ input signal inactive high BREQ signal priority over interrupt request signals should BREQ interrupt request become active simultaneously Therefore interrupts latched instruction cycle will serviced after simultaneously occurring BREQ latched during active BREQ INTERRUPT CONTROL NSC800 five interrupt restart inputs four maskable (RSTA RSTB RSTC INTR) non-maskable (NMI) highest priority interrupts user cannot disable After recognizing active input stops before next instruction pushes onto stack jumps address X'0066 where user's interrupt service routine located restart memory location X'0066) intended interrupts requiring immediate attention such power-down control panel RSTA RSTB RSTC restart inputs which enabled execute restart memory location X'003C X'0034 X'002C respectively Note that response request input basically identical except restored memory location Unlike however restart request inputs must enabled
Figure illustrates interrupt machine cycles cycle will dummy opcode fetch cycle followed which stack push operations following instruction then starts from interrupts restart location
Note does during this dummy opcode fetch unique indication INTA decoded using ALEs
Timing Control (Continued)
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Note This only machine cycle that does have INTA strobe will accept wait strobe
FIGURE Non-Maskable Restart Interrupt Machine Cycle NSC800 also provides more general purpose interrupt request input INTR When enabled responds INTR three modes defined instruction modes respectively Following reset automatically enables mode Interrupt (INTR) Mode responds interrupt request providing INTA (interrupt acknowledge) strobe which used gate instruction from peripheral onto data inserts wait states during first INTA cycle allow interrupting device controller) ample time gate instruction determine external priorities (Figure This instruction from four bytes most popular instruction one-byte call (restart instruction) threebyte call (CALL instruction) three-byte call issues total three INTA strobes last (which include wait states) read
Note instruction stored doesn't require pushed onto stack then will pushed
Interrupt (INTR) Mode Similar restart interrupts except restart location X'0038 (Figure Interrupt (INTR) Mode With this mode programmer maintains table that contains 16-bit starting address every interrupt service routine This table located anywhere memory When accepts Mode interrupt (Figure forms 16-bit pointer obtain desired interrupt service routine starting address from table upper bits this pointer from contents register lower bits pointer supplied interrupting device with forced zero programmer must load interrupt vector prior interrupt occurring uses pointer adjacent bytes from interrupt service routine starting address table complete 16-bit service routine starting ad21
dress first byte each entry table least significant (low-order) portion address programmer must obviously fill this table with desired addresses before interrupts accepted Note that programmer change this table time allow peripherals serviced different service routines Once interrupting device supplies lower portion pointer automatically pushes program counter onto stack obtains starting address from table does jump this address interrupts have fixed priorities built into NSC800 0066 (Highest Priority) RSTA 003C RSTB 0034 RSTC 002C INTR 0038 (Lowest Priority) Interrupt Enable Interrupt Disable NSC800 types interrupt inputs non-maskable interrupt four software maskable interrupts non-maskable interrupt (NMI) cannot disabled programmer will accepted whenever peripheral device requests interrupt usually reserved important functions that must serviced when they occur such imminent power failure programmer selectively enable disable maskable interrupts (INT RSTA RSTB RSTC) This selectivity allows programmer disable maskable interrupts during periods when timing constraints don't allow program interruption There interrupt enable flip-flops (IFF1 IFF2) NSC800 instructions control these flip-flops Enable Interrupt (EI) Disable Interrupt (DI) state IFF1 determines enabling disabling maskable interrupts while IFF2 used temporary storage location state IFF1
Timing Control (Continued)
reset will force both IFF1 IFF2 reset state disabling maskable interrupts They enabled instruction time programmer When instruction executed pending interrupt requests will accepted until after instruction following been executed This single instruction delay necessary situations where following instruction return instruction interrupts must allowed until return been completed instruction sets both IFF1 IFF2 enable state When accepts interrupt both IFF1 IFF2 automatically reset inhibiting further interrupts until programmer wishes issue instruction Note that previous cases IFF1 IFF2 always equal function IFF2 retain status IFF1 when non-maskable interrupt occurs When non-maskable interrupt accepted IFF1 reset prevent further interrupts until reenabled programmer Thus after non-maskable interrupt been accepted maskable interrupts disabled previous state IFF1 saved IFF2
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FIGURE Interrupt Mode
Timing Control (Continued)
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generated WAIT state response interrupt request Note will only occur mode mode During stack pointer decremented Note jump appropriate address occurs here mode mode continues gathering data from interrupting peripheral mode total machine cycles mode cycles M2-M4 have only wait state
FIGURE Interrupt Acknowledge Machine Cycle
Timing Control (Continued)
that complete state just prior nonmaskable interrupt restored method restoring status IFF1 through execution Return Non-Maskable Interrupt (RETN) instruction Since this instruction indicates that non-maskable interrupt service routine completed contents IFF2 copied back into IFF1 that status IFF1 just prior acceptance non-maskable interrupt will automatically restored Operation Initialize IFF1 IFF2 Comment Interrupt Disabled
Figure depicts status flip flops during sample series interrupt instructions Interrupt Control Register interrupt control register (ICR) 4-bit write only register that provides programmer with second level maskable control over four maskable interrupt inputs internal NSC800 addressed through space address port X'BB Each register controls mask dedicated each maskable interrupt RSTA RSTB RSTC INTR interrupt request accepted these inputs corresponding mask must IFF1 IFF2 must This provides programmer with control over individual interrupt inputs rather than just system wide enable disable
INTR
Interrupt Enabled after next instruction
Interrupt Disable INTR Being Serviced
Interrupt Enabled after next instruction Interrupt Enabled
Interrupt Disabled
RETN Interrupt Enabled Interrupt Disabled
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INTR
Name
Function Interrupt Enable INTR Interrupt Enable RSTC Interrupt Enable RSTB Interrupt Enable RSTA
example order enable RSTB interrupts must enabled must reset other mask bits cleared This maintains software compatibility between NSC800 Z80A Execution block move instruction will affect state interrupt control bits only instructions that will modify this write only register
RETN
Interrupt Disabled Being Serviced
Interrupt Disabled INTR Being Serviced
Interrupt Enabled after next instruction Interrupt Enabled
FIGURE IFF1 IFF2 States Immediately after Operation been Completed
NSC800 SOFTWARE Introduction
This chapter provides reader with detailed description NSC800 software Each NSC800 instruction described terms opcode function flags affected timing addressing mode IMMEDIATE most straightforward introducing data registers immediate addressing where data contained additional byte multi-byte instructions Example Instruction Load register with constant value X'7C Mnemonic X'7C Opcode
Addressing Modes
following sections describe addressing modes supported NSC800 Note that particular addressing modes often restricted certain types instructions Examples instructions used particular addressing modes follow each mode description addressing modes instructions provide flexible powerful instruction REGISTER most basic addressing mode that which addresses data various registers these cases bits opcode select specific registers that addressed instruction Example Instruction Load register from register Mnemonic Opcode
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this instruction register addressed with register addressing while constant X'7C immediate data second byte instruction IMMEDIATE EXTENDED immediate addressing allows bits data supplied operand immediate extended addressing allows bits data supplied operand These additional bytes instruction Example Instruction Load 16-bit register with constant value X'ABCD Mnemonic X'ABCD Opcode
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this instruction both registers addressed opcode bits IMPLIED implied addressing mode extension register addressing mode this mode specific register accumulator used execution instruction particular arithmetic operations employ implied addressing since register assumed destination register result without being specifically referenced opcode Example Instruction Subtract contents register from Accumulator register) Mnemonic Opcode
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this instruction register addressing selects register while 16-bit quanity X'ABCD immediate data supplied immediate extended format
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this instruction register addressed with register addressing while register implied opcode
Addressing Modes (Continued)
DIRECT ADDRESSING Direct addressing most straightforward addressing supplies location memory space Direct addressing 16-bits memory address information bytes data part instruction memory address could either data source destination location program execution program control instructions Example Instruction Jump location X'0377 Mnemonic X'0377 Opcode Defines jump opcode Indexed addressing particularly useful dealing with lists data Example Instruction Increment data memory location X'1020 register contains X'1000 Mnemonic X'20) Opcode
Constant X'0377
This instruction loads Program Counter (PC) loaded with constant second third bytes instruction program counter contents transferred direct addressing REGISTER INDIRECT Next direct addressing register indirect addressing provides second most straightforward means addressing memory register indirect addressing specified register pair contains address desired memory location instruction references register pair register contents define memory location operand Example Instruction contents memory location X'0254 register register contains X'0254 Mnemonic (HL) Opcode
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indexed addressing mode uses contents index registers along with displacement form pointer memory RELATIVE Certain instructions allow memory locations addressed position relative register These instructions allow jumps memory locations which offsets around program counter offset together with current program location determined through displacement byte included instruction formation this displacement byte explained more fully ``Instructions Set'' section Example Instruction Jump memory location bytes beyond current location Mnemonic Opcode Defines relative jump opcode Displacement applied
This instruction uses implied addressing registers register indirect addressing access data pointed register INDEXED most flexible mode memory addressing indexed mode This similar register indirect mode addressing because index registers contains base memory address addition byte data included instruction acts displacement address index register
program will continue location seven locations past current
Addressing Modes (Continued)
MODIFIED PAGE ZERO subset NSC800 instructions (the Restart instructions) provides code-efficient single-byte instruction that allows CALLs performed eight dedicated locations page zero (locations X'0000 X'00FF) Normally CALL 3-byte instruction employing direct memory addressing Example Instruction Perform restart call location X'0028 Mnemonic X'28 Opcode Program execution continues location X'0028 after execution single-byte call employing modified page zero addressing NSC800 allows setting resetting testing individual bits registers memory data bytes Example Operation register Mnemonic Opcode
5171
5171
addressing allows selection register selected register addressing
Instruction
This section details entire NSC800 instruction terms instructions grouped order under following functional headings
Opcode Instruction Function Timing Addressing Mode
8-Bit Loads 16-Bit Loads 8-Bit Arithmetic 16-Bit Arithmetic Reset Test Rotate Shift Exchanges Memory Block Moves Searches Input Output Control Program Control
Instruction Index
Alphabetical Assembly Mnemonic CALL CALL CPDR CPIR Operation with carry memory location contents Accumulator with carry immediate data Accumulator with carry register contents Accumulator with carry register pair memory location contents Accumulator immediate data Accumulator register contents Accumulator register pair register pair register pair register pair contents register pair Logical `AND' memory contents Accumulator Logical `AND' immediate data Accumulator Logical `AND' register contents Accumulator Test location Test register Call subroutine location condition true Unconditional call subroutine location Complement carry flag Compare memory contents with Accumulator Compare immediate data with Accumulator Compare register contents with Accumulator Compare location (HL) Accumulator decrement Compare location (HL) Accumulator decrement repeat until Compare location (HL) Accumulator increment decrement Compare location (HL) Accumulator increment decrement repeat until Complement Accumulator (1's complement) Decimal adjust Accumulator Decrement data memory location Decrement register contents Decrement register pair contents Page
Instruction Index (Continued)
Alphabetical Assembly Mnemonic DJNZ (SP) A'F' Disable interrupts Decrement jump relative
Operation
Page
Enable interrupts Exchange location (SP) with register Exchange contents A'F' Exchange contents Exchange contents with contents D'E' H'L' respectively Halt (wait interrupt reset) interrupt mode interrupt mode interrupt mode Load Accumulator with input from device Load register with input from device Increment data memory location Increment register Increment contents register pair Load location (HL) with input from port decrement Load location (HL) with input from port decrement repeat until Load location (HL) with input from port increment decrement Load location (HL) with input from port increment decrement repeat until Jump location condition true Unconditional jump location Unconditional jump location (ss) Unconditional jump relative Jump relative true Load Accumulator with register contents Load Accumulator from location Load Accumulator with register contents Load register with Accumulator contents Load memory with immediate data Load memory from register Load memory from Accumulator Load memory location with register pair Load register from memory Load register with immediate data Load register from Accumulator Load destination register from source register Load register pair from memory location Load register pair with immediate data Load from register pair Load location (DE) with location (HL) decrement Load location (DE) with location (HL) decrement repeat until Load location (DE) with location (HL) increment decrement Load location (DE) with location (HL) increment decrement repeat until Negate Accumulator (2's complement) operation
HALT INDR INIR
(ss) (nn) (nn) LDDR LDIR
Instruction Index (Continued)
Alphabetical Assembly Mnemonic OTDR OTIR OUTD OUTI PUSH RETI RETN RLCA RRCA Operation Logical `OR' memory location contents accumulator Logical `OR' immediate data Accumulator Logical `OR' register Accumulator Load output port with location (HL) decrement repeat until Load output port with location (HL) increment decrement repeat until Load output port with register Load output port with Accumulator Load output port with location (HL) decrement Load output port with location (HL) increment decrement Load register pair with stack Load stack with register pair Reset memory location Reset register Unconditional return from subroutine Return from subroutine true Unconditional return from interrupt Unconditional return from non-maskable interrupt Rotate memory contents left through carry Rotate register left through carry Rotate Accumulator left through carry Rotate memory contents left circular Rotate register left circular Rotate Accumulator left circular Rotate digit left right between Accumulator memory (HL) Rotate memory contents right through carry Rotate register right through carry Rotate Accumulator right through carry Rotate memory contents right circular Rotate register right circular Rotate Accumulator right circular Rotate digit right left between Accumulator memory (HL) Restart location Subtract with carry memory contents from Accumulator Subtract with carry immediate data from Accumulator Subtract with carry register from Accumulator Subtract with carry register pair from carry flag memory location contents register Shift memory contents left arithmetic Shift register left arithmetic Shift memory contents right arithmetic Shift register right arithmetic Shift memory contents right logical Shift register right logical Subtract memory contents from Accumulator Subtract immediate data from Accumulator Subtract register from Accumulator Exclusive `OR' memory contents Accumulator Exclusive `OR' immediate data Accumulator Exclusive `OR' register Accumulator Page
Instruction (Continued)
INSTRUCTION MNEMONIC NOTATION following instruction listing notations used shown below Designates register memory location address mode uses this indicator Designates condition codes used conditional Jumps Calls Return instruction Non-Zero flag Zero flag Non-Carry flag Carry flag Parity Overflow Parity Even Overflow Positive Negative Designates 8-bit signed complement displacement Relative indexed address modes this indicator Subset condition codes used conjunction with conditional relative jumps Designates (HL) Register indirect indexed address modes this indicator Designates (BC) (DE) (nn) Register indirect direct address modes this indicator 8-bit binary number 16-bit binary number Designates restart vectors values Restart instructions employing modified page zero addressing mode this indicator Designates 16-bit register used destination operand 16-bit arithmetic operations employing register address mode Designates during operations employing register address mode Designates Register addressing modes this indicator Designates Register addressing modes this indicator Designates Register addressing modes this indicator Subscript indicates lower-order byte 16-bit register Subscript indicates high-order byte 16-bit register parentheses indicate contents considered pointer address memory location ASSEMBLED OBJECT CODE NOTATION Register Codes Register Register Register Register Register
Conditions Codes Mnemonic Mnemonic Restart Addresses X'00 X'08 X'10 X'18 X'20 X'28 X'30 X'38
True Flag Condition True Flag Condition
8-Bit Loads
REGISTER REGISTER Load register with cycles states Register Addressing Mode cycles states Register
flags affected
Timing
Timing Addressing Mode
Load Accumulator with contents register negative result zero result Reset according IFF2 (zero interrupt occurs during operation) Reset affected cycles states Register
Load Refresh register with contents Accumulator flags affected cycles states Register
Timing Addressing Mode
Load register with immediate data flags affected Timing Addressing Mode REGISTER MEMORY Load memory from reigster flags affected (HL) cycles states Source Register Destination Register Indirect r(for r(for cycles states Source Immediate Destination Register
Timing Addressing Mode
Load Interrupt vector register with contents flags affected cycles states Register
Timing Addressing Mode
Timing Addressing Mode Timing Addressing Mode
Load Accumulator with contents register negative result zero result Reset according IFF2 (zero interrupt occurs during operation) Reset affected
cycles states Source Register Destination Indexed
8-Bit Loads (Continued)
flags affected (BC) (DE) MEMORY REGISTER Load register from memory location flags affected Timing Addressing Mode cycles states Source Register (Implied) Destination Register Indirect (nn) (low-order byte) (high-order byte) Timing Addressing Mode cycles states Source Register (Implied) Destination Direct Timing Addressing Mode cycles states Source Indexed Destination Register (HL) Load memory from Accumulator
Timing Addressing Mode
cycles states Source Register Indirect Destination Register (for (for
Load memory with immediate data flags affected Timing Addressing Mode cycles states Source Immediate Destination Register Indirect n(for n(for LD(HL)
Load Accumulator from memory location flags affected (BC) (DE)
Timing Addressing Mode
cycles states Source Register Indirect Destination Register (Implied) (nn)
(low-order byte) (high-order byte) Addressing Mode Timing Addressing Mode cycles states Source Immediate Destination Indexed Timing cycles states Source Immediate Extended Destination Register (Implied)
16-Bit Loads
REGISTER REGISTER Load 16-bit register pair with immediate data flags affected REGISTER MEMORY (nn) Load memory location with contents 16-bit register (nn) flags affected (nn) (note alternate opcode below)
(low-order byte) (high-order byte) Timing Addressing Mode
(low-order byte) cycles states Source Immediate Extended Destination Register (for (for (low-order byte) (high-order byte) Timing Addressing Mode cycles states Source Immediate Extended Destination Register (low-order byte) (high-order byte) Timing Addressing Mode cycles states Source Register Destination Direct (nn) (for (nn) (for (high-order byte) Timing Addressing Mode cycles states Source Register Destination Direct (nn) (nn) (nn) (nn)
Load from 16-bit register flags affected
Timing Addressing Mode
cycles states Source Register Destination Register (Implied) (for (for cycles states Source Register Destination Register (Implied)
(low-order byte) (high-order byte) Timing Addressing Mode cycles states Source Register Destination Direct
Timing Addressing Mode
16-Bit Loads (Continued)
PUSH Push contents register pair onto memory stack flags affected PUSH PUSH PUSH PUSH Timing Addressing Mode cycles states Source Register Destination Register Indirect (Stack) PUSH (for PUSH (for cycles states Source Register Destination Register Indirect (Stack) (high-order byte) Timing Addressing Mode cycles states Source Direct Destination Register (nn) (nn) (nn) (nn)
(low-order byte) (high-order byte) Timing Addressing Mode cycles states Source Direct Destination Register (nn)(for (nn) (for
(low-order byte)
Timing Addressing Mode
MEMORY REGISTER (nn) Load 16-bit register from memory location (nn) flags affected (nn) (note alternate opcode below) (low-order byte) (high-order byte) Timing Addressing Mode cycles states Source Direct Destination Register
contents memory stack register flags affected (SP) Timing Addressing Mode cycles states Source Register Indirect (Stack) Destination Register (for (for cycles states Source Register Indirect (Stack) Destination Register
Timing Addressing Mode
8-Bit Arithmetic
REGISTER ADDRESSING ARITHMETIC Value Value Number Added Before Before After Upper Lower Digit Digit Byte (Bits 7-4) (Bits 3-0) cycles states Source Register Destination Implied
Timing Addressing Mode
Subtract contents register from Accumulator result negative AwAbr result zero borrow from result exceeds 8-bit complement range according borrow cycles states Source Register Destination Implied
Timing Addressing Mode
contents register Accumulator negative result zero result carry from according overflow condition Reset carry from cycles states Source Register Destination Implied
Timing Addressing Mode
Subtract contents register carry from Accumulator result negative result zero borrow from result exceeds 8-bit complement range according borrow cycles states Source Register Destination Implied
Timing Addressing Mode
contents register plus carry flag Accumulator negative result zero result carry from result exceeds complement range Reset carry from
Logically contents register Accumulator result negative result zero result parity even Reset Reset
8-Bit Arithmetic (Continued)
cycles cycles states Source Register Destination Register
Timing Addressing Mode
Timing Addressing Mode
states Source Register Destination Implied
Logically contents register Accumulator result negative result zero Reset result parity even Reset Reset cycles states Source Register Destination Implied
Compare contents register with Accumulator flags accordingly result negative result zero borrow from result exceeds 8-bit complement range according borrow cycles states Source Register Destination Implied register result negative result zero according borrow from only X'80 prior operation cycles states Source Register Destination Register
Timing Addressing Mode
Timing Addressing Mode Decrement contents rwrb1
Logically exclusively contents register with Accumulator result negative result zero Reset result parity even Reset Reset cycles states Source Register Destination Implied
Timing Addressing Mode Increment register rwra1
Timing Addressing Mode
result negative result zero carry from only X'7F before operation Reset
Complement Accumulator (1's complement)
8-Bit Arithmetic (Continued)
cycles states Implied Adjust Accumulator addition subtraction operations executed after data been operated upon standard binary instructions (see ``Register Addressing Arithmetic'' table) according result result zero according instructions according parity result according instructions cycles states Implied
Timing Addressing Mode
Negate Accumulator (2's complement) Aw0bA result negative result zero according borrow from only Accumulator X'80 prior operation only Accumulator X'00 prior operation cycles states Implied
Timing Addressing Mode
IMMEDIATELY ADDRESSED ARITHMETIC immediate data Accumulator AwAan result negative result zero carry from result exceeds 8-bit complement range Reset carry from Timing Addressing Mode cycles states Source Immediate Destination Implied
Timing Addressing Mode
Complement carry flag Previous carry Reset Complement previous carry cycles states Implied
Timing Addressing Mode carry flag
Reset Reset cycles states Implied
with carry immediate data Accumulator result negative result zero carry from result exceeds 8-bit complement range Reset according carry from
Timing Addressing Mode
8-Bit Arithmetic (Continued)
Timing Addressing Mode cycles states Source Immediate Destination Implied immediate data logically AND'ed Accumulator result negative result zero result parity even Reset Reset Timing Addressing Mode cycles states Source Immediate Destination Implied
Subtract immediate data from Accumulator result negative AwAbn result zero borrow from result exceeds 8-bit complement range according borrow condition Timing Addressing Mode cycles states Source Immediate Destination Implied
Subtract with carry immediate data from Accumulator result negative result zero borrow from result exceeds 8-bit complement range according borrow condition
immediate data logically OR'ed contents Accumulator result negative result zero Reset result parity even Reset Reset Timing Addressing Mode cycles states Source Immediate Destination Implied
immediate data exclusively OR'ed with Accumulator result negative result zero Reset result parity even Reset Reset
Timing Addressing Mode
cycles states Source Immediate Destination Implied
8-Bit Arithmetic (Continued)
Timing Addressing Mode cycles states Source Immediate Destination Implied Timing Addressing Mode cycles states Source Indexed Destination Implied (for (for
Compare immediate data with contents Accumulator subtraction return appropriate flags contents Accumulator affected result negative result zero borrow from result exceeds 8-bit complement range according borrow condition
contents memory location plus carry Accumulator result negative result zero carry from result exceeds 8-bit complement range Reset according carry from (HL)
Timing cycles states Immediate Addressing Mode
Timing Addressing Mode
cycles states Source Register Indirect Destination Implied (for (for
MEMORY ADDRESSED ARITHMETIC contents memory location Accumulator result negative result zero carry from result exceeds 8-bit complement range Reset according carry from (HL)
Timing Addressing Mode
cycles states Source Indexed Destination Implied
Timing Addressing Mode
cycles states Source Register Indirect Destination Implied
Subtract contents memory location from Accumulator result negative result zero borrow from result exceeds 8-bit complement range according borrow condition
8-Bit Arithmetic (Continued)
(HL) data memory location logically AND'ed Accumulator result negative result zero result parity even Reset Reset Timing Addressing Mode cycles states Source Indexed Destination Implied (HL)
Timing Addressing Mode
cycles
states Source Register Indirect Destination Implied (for (for
Timing Addressing Mode Timing Addressing Mode
Subtract with carry contents memory location from Accumulator result negative result zero carry from result exceeds 8-bit complement range according borrow condition (HL)
cycles states Source Register Indirect Destination Implied (for (for
cycles states Source Indexed Destination Implied
Timing Addressing Mode
cycles states Source Register Indirect Destination Implied (for (for
Timing Addressing Mode
data memory location logically OR'ed with Accumulator result negative result zero Reset result parity even Reset Reset (HL)
Timing Addressing Mode cycles states Source Indexed Destination Implied Timing Addressing Mode
cycles states Source Register Indexed Destination Implied (for (for
cycles states Source Indexed Destination Implied
8-Bit Arithmetic (Continued)
Timing Addressing Mode cycles states Source Indexed Implied data memory location exclusively OR'ed with data Accumulator result negative result zero Reset result parity even Reset Reset (HL)
Destination
Timing Addressing Mode Timing Addressing Mode
cycles states Source Register Indexed Destination Implied (for (for
Increment data memory location result negative result zero according carry from data X'7F before operation Reset (HL)
Timing Addressing Mode Timing Addressing Mode
cycles states Source Indexed Destination Implied
cycles states Source Register Indexed Destination Register Indexed (for (for
Compare data memory location with data Accumulator subtraction result negative result zero borrow from result exceeds 8-bit complement range according borrow condition (HL)
cycles states Source Indexed Destination Indexed
Timing Addressing Mode
cycles
Decrement data memory location result negative result zero according borrow from only X'80 before operation
states Source Register Indirect Destination Implied (for (for
8-Bit Arithmetic (Continued)
(HL)
result exceeds 16-bit complement range Reset carry cycles states Source Register Destination Register
Timing Addressing Mode
cycles states Source Register Indexed Destination Register Indexed (for (for
Timing Addressing Mode
Timing Addressing Mode
cycles states Source Indexed Destination Indexed
Subtract with carry contents 16-bit register from 16-bit register result negative result zero according borrow from result exceeds 16-bit complement range according borrow condition cycles states Source Register Destination Register
16-Bit Arithmetic
contents 16-bit register contents 16-bit register
carry from Reset carry from
Timing Addressing Mode
Timing Addressing Mode
cycles states Source Register Destination Register (for (for
Increment contents 16-bit register flags affected Timing Addressing Mode cycles states Register (for (for cycles states Register
Timing Addressing Mode
cycles states Source Register Destination Register
contents 16-bit register added with carry register result negative result zero according carry
Timing Addressing Mode
16-Bit Arithmetic (Continued)
Decrement contents 16-bit register flags affected cycles states Register (for (for cycles states Register
Timing Addressing Mode MEMORY
cycles states Register
Timing Addressing Mode
memory location flags affected cycles states Register Indirect (for (for (HL)
Timing Addressing Mode
Timing Addressing Mode Timing
Reset Test
REGISTER register cycles states Register
flags affected
Timing Addressing Mode register reset
Addressing Mode
cycles states Indexed
memory location reset flags affected cycles states Register Indirect (for (for (HL)
flags affected
Timing Addressing Mode Timing Addressing Mode
Timing Addressing Mode
cycles states Register
register tested with result flag Undefined Inverse tested Undefined Reset
cycles states Indexed
Reset Test (Continued)
memory location tested flag Undefined Inverse tested Undefined Reset (HL)
RLCA
Timing
cycles
states Addressing Mode Implied (Note RLCA does affect flags Rotate register left through carry
5171
Timing Addressing Mode
cycles states Register Indirect (for (for
result negative result zero Reset result parity even Reset according (Note alternate register below) cycles states Register
cycles states Indexed
Timing Addressing Mode
Timing Addressing Mode
Rotate Shift
REGISTER Rotate register left circular
Timing
cycles states Addressing Mode Implied (Note does affect flags Rotate register right circular
5171
result negative result zero Reset result parity even Reset according (Note alternate register below)
5171
result negative result zero Reset result parity even Reset according
Timing Addressing Mode
cycles states Register
Rotate Shift (Continued)
(Note alternate register below) cycles states Register result parity even Reset according cycles states Register
Timing Addressing Mode
Timing Addressing Mode
RRCA
cycles states Addressing Mode Implied (Note RRCA does affect flags Rotate register right through carry
Timing
Shift register right arithmetic
5171
5171-60
result negative result zero Reset result parity even Reset according cycles states Register (Note alternate register below)
result negative result zero Reset result parity even Reset according
Timing Addressing Mode Shift register right logical
cycles states Register
Timing Addressing Mode
5171
Timing
cycles
states Addressing Mode Implied (Note does affect flags Shift register left arithmetric
Reset result zero Reset result parity even Reset according
Timing
5171-61
result negative result zero Reset
Addressing Mode
cycles states Register
Rotate Shift (Continued)
MEMORY Rotate date memory location left circular cycles states Register Indirect (for (for (HL)
Timing Addressing Mode
5171
result negative result zero Reset result parity even Reset according cycles states Register indirect (for (for (HL)
cycles states Indexed
Timing Addressing Mode
Timing Addressing Mode
Rotate data memory location right circular
5171
cycles states Indexed
Timing Addressing Mode
Rotate data memory location left though carry
result negative result zero Reset result parity even Reset according (HL)
Timing
cycles states
5171
result negative result zero Reset result parity even Reset according
Addressing Mode Register Indirect (for (for Timing Addressing Mode cycles states Indexed
Rotate Shift (Continued)
(for (for Rotate data memory location right through carry Timing
5171-67
cycles states Indexed
result negative result zero Reset result parity even Reset according (HL)
Addressing Mode
Shift data memory location right arithmetic
5171
Timing Addressing Mode Timing Addressing Mode
cycles states Register Indirect (for (for
result negative result zero Reset result parity even Reset according cycles states Register Indirect (for (for (HL)
Timing cycles states Indexed Addressing Mode Timing
5171-68
Shift data memory location left arithmetic
cycles states Indexed
result negative result zero Reset result parity even Reset according (HL)
Addressing Mode
Shift right logical data memory location
5171
Timing Addressing Mode
cycles states Register Indirect
Reset result zero Reset result parity even Reset according
Rotate Shift (Continued)
cycles states Register Indirect (for (for
5171
(HL) Rotate digit right left between Accumulator memory (HL)
Timing Addressing Mode Timing Addressing Mode REGISTER MEMORY
cycles states Indexed
result negative result zero Reset result parity even Reset cycles states Implied Register Indirect
Rotate digit left right between Accumulator memory (HL)
Timing Addressing Mode
Exchanges
REGISTER REGISTER Exchange contents 16-bit register pairs flags affected cycles states Register
5171
result negative result zero Reset result parity even Reset cycles states Implied Register Indirect
Timing Addressing Mode
Timing Addressing Mode
A'F' contents Accumulator flag register exchanged with their corresponding alternate registers that exchanged with flags affected cycles states Register
Timing Addressing Mode
Exchanges (Continued)
Exchange contents registers with their corresponding alternate register B'C' flags affected D'E' H'L'
Move data from memory location (HL) memory location (DE) decrement memory pointer byte counter (DE)
(HL)
cycles states Implied
Timing Addressing Mode REGISTER MEMORY
Reset wise reset Reset
other-
Timing Addressing Mode
(SP) Exchange bytes external memory stack with 16-bit register (SP) flags affected (SP) cycles states Register Register Indirect (SP) (for (SP) (for cycles states Register Register Indirect
cycles states Register Indirect
Timing Addressing Mode Timing Addressing Mode
Compare data memory location (HL) Accumulator increment memory pointer decrement byte counter flag comparison equal (HL) result comparison subtract negative result comparison zero (HL) according borrow from otherwise reset cycles states Register Indirect
Memory Block Moves Searches
SINGLE OPERATIONS Move data from memory location (HL) memory location (DE) increment memory pointers decrement byte counter (DE) (HL)
Timing Addressing Mode
Reset wise reset Reset cycles states Register Indirect
Compare data memory location (HL) Accumulator decrement memory pointer byte counter flag comparison equal (HL) result negative (HL) result comparison zero according borrow from otherwise reset
other-
Timing Addressing Mode
Memory Block Moves Searches (Continued)
cycles states Register Indirect CPIR Compare data memory location (HL) Accumulator increment memory decrement byte counter repeat until (HL) equals (HL) sign subtraction performed comparison negaHL tive (HL) otherwise reset Repeat until according borrow from (HL) otherwise reset
Timing Addressing Mode REPEAT OPERATIONS
LDIR Move data from memory location (HL) memory location (DE) increment memory pointers decrement byte counter repeat until (DE) (HL) Repeat until Reset Reset Reset
cycles states cycles states Addressing Mode Register Indirect (Note that each repeat accomplished decrement that refresh continues each cycle LDDR Move data from memory location (HL) memory location (DE) decrement memory pointers byte counter repeat until (DE) (HL) Reset Reset Repeat until Reset
Timing
cycles states cycles states Addressing Mode Register Indirect (Note that each repeat accomplished decrement that refresh continues each cycle CPDR Compare data memory location (HL) contents Accumulator decrement memory pointer byte counter repeat until until (HL) equals Accumulator (HL) sign subtraction performed comparison negaHL tive according equality Repeat until (HL) true (HL) according borrow from otherwise reset
Timing
cycles states cycles states Addressing Mode Register Indirect (Note that each repeat accomplished decrement that refresh continues each cycle
Timing
cycles states cycles states Addressing Mode Register Indirect (Note that each repeat accomplished decrement that refresh continues each cycle
Timing
Input Output
Undefined Timing Addressing Mode cycles states Source Direct Destination Register cycles states Implied Source Register Indirect Destination Register Indirect Input data Accumulator from device address flags affected Timing Addressing Mode
Input data register from device addressed contents register only flags affected result negative result zero Reset result parity even Reset cycles states Source Register Indirect Destination Register
OUTI Output data from memory location (HL) device port address increment memory pointer decrement byte counter (HL) Undefined BwBb1 otherwise reset Undefined Undefined cycles states Implied Source Register Indirect Destination Register Indirect
Timing Addressing Mode
Timing Addressing Mode
Output register device addressed contents register flags affected cycles states Source Register Destination Register Indirect
Input data from device port address memory location (HL) decrement memory pointer byte counter (HL) Undefined BwBb1 otherwise reset Undefined Undefined cycles states Implied Source Register Indirect Destination Register Indirect
Timing Addressing Mode
Input data from device addressed contents register memory location pointed contents register pointer incremented byte counter decremented (HL) Undefined BwBb1 otherwise reset Undefined
Timing Addressing Mode
Input Output (Continued)
Output Accumulator device address Timing Addressing Mode cycles states Source Register Destination Direct flags affected
OUTD Data output from memory location (HL) device port address memory pointer byte counter decremented (HL) Undefined BwBb1 otherwise reset Undefined Undefined cycles states Implied Source Register Indirect Destination Register Indirect
cycles states cycles states Addressing Mode Implied Source Register Indirect Destination Register Indirect (Note that each data transfer cycle interrupts recognized refresh cycles will performed OTIR Data output device port address from memory location (HL) memory pointer incremented byte counter decremented cycles repeated until (Note that tested zero after decremented loading initially with zero data transfers will take place (HL) Undefined BwBb1 Repeat until Undefined Undefined
Timing
Timing Addressing Mode
INIR Data input from device port address memory location (HL) memory pointer incremented byte counter decremented cycle repeated until (Note that tested zero after decremented loading initially with zero data transfers will take place (HL) Undefined BwBb1 Repeat until Undefined Undefined
cycles states cycles states Addressing Mode Implied Source Register Indirect Destination Register Indirect (Note that each data transfer cycle interrupts recognized refresh cycles will performed
Timing
Input Output (Continued)
INDR Data input from device address memory location (HL) then memory pointer byte counter decremented cycle repeated until (Note that tested zero after decremented loading initially with zero data transfers will take place (HL) Undefined BwBb1 Repeat until Undefined Undefined
Control
performs operation flags affected cycles states
Timing Addressing Mode
HALT halts execution program Dummy op-code fetches performed from next memory location keep refresh circuits active until interrupted reset from halted state flags affected cycles states
cycles states cycles states Addressing Mode Implied Source Register Indirect Destination Register Indirect (Note that after each data transfer cycle interrupts recognized refresh cycles performed OTDR Data output from memory location (HL) device port address then memory pointer byte counter decremented cycle repeated until (Note that tested zero after decremented loading initially with zero data transfers will take place (HL) Undefined BwBb1 Repeat until Undefined Undefined
Timing
Timing Addressing Mode
Disable system level interrupts flags affected IFF1 IFF2 cycles states
Timing Addressing Mode
system level interrupts enabled During execution this instruction next maskable interrupts will disabled IFF1 flags affected IFF2 cycles states
Timing Addressing Mode
cycles states cycles states Addressing Mode Implied Source Register Indirect Destination Register Indirect (Note that after each data transfer cycle NSC800 will accept interrupts perform refresh cycles
Timing
placed interrupt mode flags affected cycles states
Timing Addressing Mode
Control (Continued)
placed interrupt mode flags affected
(IX) (for (IY) (for
Timing Addressing Mode
cycles states Register Indirect
cycles states
Timing Addressing Mode
placed interrupt mode flags affected cycles states
Conditionally jump program location based testable flag states true flags affected otherwise continue
(low-order byte) (high-order byte) Timing Addressing Mode cycles states Direct
Timing Addressing Mode
Program Control
JUMPS Unconditional jump program location flags affected
Unconditional jump program location calculated with respect program counter displacement flags affected
Timing Addressing Mode cycles states Relative
(low-order byte) (high-order byte) Timing Addressing Mode cycles states Direct
(ss) Unconditional jump program location pointed register flags affected (HL)
Conditionally jump program location calculated with respect program counter displacement based limited testable flag states true flags affected otherwise continue Timing (true) (not true) Addressing Mode cycles states cycles states Relative
Timing Addressing Mode
cycles states Register Indirect
Program Control (Continued)
DJNZ Decrement register conditionally jump program location calculated with respect program counter displacement based contents register BwBb1 flags affected continue else RETURNS Unconditional return from subroutine other return program location pointed stack (SP) flags affected
cycles states Register Indirect
Timing
Timing cycles states cycles states Relative
Addressing Mode CALLS
Addressing Mode Conditional return from subroutine other return program location pointed stack true flags affected (SP)
CALL Unconditional call subroutine location flags affected
else continue
Timing true
cycles states cycles states Register Indirect
true Addressing Mode
(low-order byte) (high-order byte) Timing Addressing Mode Cycles states Direct
RETI Unconditional return from interrupt handling subroutine Functionally identical instruction Unique opcode allows monitoring external hardware (SP) flags affected
CALL Conditional call subroutine location based testable flag stages true flags affected else continue
cycles states Register Indirect
Timing Addressing Mode
(low-order byte) (high-order byte) Timing true true Addressing Mode cycles states cycles states Direct
Program Control (Continued)
RETN Unconditional return from non-maskable interrupt handling subroutine Functionally similar instruction except interrupt enable state restored that prior non-maskable interrupt (SP) flags affected IFF1 IFF2 RESTARTS present contents pushed onto memory stack loaded with dedicated program locations determined specific restart executed flags affected Timing Addressing Mode
cycles states Register Indirect
Timing Addressing Mode
cycles states Modified Page Zero
Instruction Alphabetical Order
Data bit) Data bit)
(HL) (HL) (HL) (HL)
CBd46 CBd46
signed displacement
(HL) (HL) (HL) (HL) (HL)
CBd4E CBd4E CBd56 CBd56 CBd5E CBd5E CBd66 CBd66 CBd6E CBd6E
(nn) address memory location
Instruction Alphabetical Order (Continued)
CALL CALL CALL CALL CALL CALL CALL CALL CALL CPDR CPIR
Data bit) Data bit)
(HL) (HL) (HL)
(HL)
CBd76 CBd76 CBd7E CBd7E DCnn FCnn D4nn CDnn C4nn F4nn ECnn E4nn CCnn
signed displacement
DJNZ HALT INDR
(SP) (SP) (SP) A'F'
(HL)
ED78
(nn) Address memory location
Instruction Alphabetical Order (Continued)
INIR
Data bit) Data bit)
(HL) (IX) (IY) (BC) (DE) (HL) (HL) (HL) (HL) (HL) (HL) (HL) (HL) (nn) (nn) (nn) (nn) (nn) (nn) (nn) (BC) (DE)
DAnn FAnn D2nn C3nn C2nn F2nn EAnn E2nn CAnn 36dn 36dn 32nn 43nn 53nn 22nn 22nn 22nn 73nn
signed displacement
(HL) (nn) (HL) (nn) (HL) (HL) (nn) (HL)
3Ann 01nn 5Bnn 11nn
(nn) Address memory location
Instruction Alphabetical Order (Continued)
LDDR LDIR
Data bit) Data bit)
(HL) (nn) (nn) (nn) (HL) (nn)
(HL)
2Ann 21nn 2Ann 21nn 2Ann 21nn 7Bnn 31nn
signed displacement
OTDR OTIR OUTD OUTI PUSH PUSH PUSH PUSH PUSH PUSH
(HL) (HL) (HL)
CBd86 CBd86 CBd8E CBd8E CBd96 CBd96
(nn) Address memory location
Instruction Alphabetical Order (Continued)
Data bit) Data bit)
(HL) (HL) (HL) (HL) (HL)
CBd9E CBd9E CBdA6 CBdA6 CBdAE CBdAE CBdB6 CBdB6 CBdBE CBdBE
signed displacement
RETI RETN RLCA
(HL) (HL)
(HL) (HL)
CBd16 CBd16 CBd06 CBd06 CBd1E CBd1E CBd0E CBd0E
(nn) Address memory location
Instruction Alphabetical Order (Continued)
RRCA
Data bit) Data bit)
(HL) (HL) (HL) (HL)
CBdC6 CBdC6 CBdCE CBdCE
displacement
(HL) (HL) (HL) (HL) (HL)
CBdD6 CBdD6 CBdDE CBdDE CBdE6 CBdE6 CBdEE CBdEE CBdF6 CBdF6 CBdFE CBdFE
(nn) Address memory location
Instruction Alphabetical Order (Continued)
(HL) (HL) (HL) CBd26 CBd26 CBd2E CBd2E CBd3E CBd3E (HL) (HL)
Instruction Numerical Order
Code 01nn 10d2 11nn
Data bit) Data bit)
Mnemonic (BC) RLCA A'F' (BC) RRCA DJNZ (DE)
displacement
Code 18d2 20d2 21nn 22nn 28d2
Mnemonic (DE) (nn)
Code 2Ann 30d2 31nn 32nn 3Ann
Mnemonic (nn) (nn) (HL) (HL) (HL) (nn)
(nn) Address memory location
Instruction Numerical Order (Continued)
Code
Data bit) Data (8-bit)
Mnemonic (HL) (HL) (HL) (HL) (HL) (HL) (HL) (HL) (HL) (HL)
displacement
Code
Mnemonic (HL) (HL) HALT (HL) (HL) (HL) (HL) (HL) (HL) (HL)
Code C2nn C3nn C4nn CAnn CB00 CB01 CB02 CB03 CB04 CB05 CB06 CB07 CB08 CB09 CB0A CB0B CB0C CB0D CB0E CB0F CB10 CB11 CB12
Mnemonic (HL) (HL) (HL) CALL PUSH (HL) (HL)
(nn) Address memory location
Instruction Numerical Order (Continued)
Code CB13 CB14 CB15 CB16 CB17 CB18 CB19 CB1A CB1B CB1C CB1D CB1E CB1F CB20 CB21 CB22 CB23 CB24 CB25 CB26 CB27 CB28 CB29 CB2A CB2B CB2C CB2D CB2E CB2F CB38 CB39 CB3A CB3B CB3C CB3D CB3E CB3F CB40 CB41 CB42 CB43 CB44 CB45 CB46 CB47 CB48 CB49 CB4A CB4B CB4C CB4D CB4E
Data bit) Data (8-bit)
Mnemonic (HL) (HL) (HL) (HL) (HL) (HL) (HL)
displacement
Code CB4F CB50 CB51 CB52 CB53 CB54 CB55 CB56 CB57 CB58 CB59 CB5A CB5B CB5C CB5D CB5E CB5F CB60 CB61 CB62 CB63 CB64 CB65 CB66 CB67 CB68 CB69 CB6A CB6B CB6C CB6D CB6E CB6F CB70 CB71 CB72 CB73 CB74 CB75 CB76 CB77 CB78 CB79 CB7A CB7B CB7C CB7D CB7E CB7F CB80 CB81 CB82
Mnemonic (HL) (HL) (HL) (HL) (HL) (HL)
Code CB83 CB84 CB85 CB86 CB87 CB88 CB89 CB8A CB8B CB8C CB8D CB8E CB8F CB90 CB91 CB92 CB93 CB94 CB95 CB96 CB97 CB98 CB99 CB9A CB9B CB9C CB9D CB9E CB9F CBA0 CBA1 CBA2 CBA3 CBA4 CBA5 CBA6 CBA7 CBA8 CBA9 CBAA CBAB CBAC CBAD CBAE CBAF CBB0 CBB1 CBB2 CBB3 CBB4 CBB5 CBB6
Mnemonic (HL) (HL) (HL) (HL) (HL) (HL) (HL)
(nn) Address memory location
Instruction Numerical Order (Continued)
Code CBB7 CBB8 CBB9 CBBA CBBB CBBC CBBD CBBE CBBF CBC0 CBC1 CBC2 CBC3 CBC4 CBC5 CBC6 CBC7 CBC8 CBC9 CBCA CBCB CBCC CBCD CBCE CBCF CBD0 CBD1 CBD2 CBD3 CBD4 CBD5 CBD6 CBD7 CBD8 CBD9 CBDA CBDB CBDC CBDD CBDE CBDF CBE0 CBE1 CBE2 CBE3 CBE4 CBE5 CBE6 CBE7 CBE8 CBE9 CBEA CBEB
Data bit) Data (8-bit)
Mnemonic (HL) (HL) (HL) (HL) (HL) (HL)
displacement
Code CBEC CBED CBEE CBEF CBF0 CBF1 CBF2 CBF3 CBF4 CBF5 CBF6 CBF7 CBF8 CBF9 CBFA CBFB CBFC CBFD CBFE CBFF CCnn CDnn D2nn D4nn DAnn DCnn DD09 DD19 DD21nn DD22nn DD23 DD29 DD2Ann DD2B DD34d DD35d DD36dn DD39 DD46d DD4Ed DD56d DD5Ed
Mnemonic (HL) (HL) (HL) CALL CALL CALL PUSH CALL (nn) (nn)
Code DD66d DD6Ed DD70d DD71d DD72d DD73d DD74d DD75d DD77d DD7Ed DD86d DD8Ed DD96d DD9Ed DDA6d DDAEd DDB6d DDBEd DDCBd06 DDCBd0E DDCBd16 DDCBd1E DDCBd26 DDCBd2E DDCBd3E DDCBd46 DDCBd4E DDCBd56 DDCBd5E DDCBd66 DDCBd6E DDCBd76 DDCBd7E DDCBd86 DDCBd8E DDCBd96 DDCBd9E DDCBdA6 DDCBdAE DDCBdB6 DDCBdBE DDCBdC6 DDCBdCE DDCBdD6 DDCBdDE DDCBdE6 DDCBdEE DDCBdF6 DDCBdFE DDE1 DDE3 DDE5 DDE9
Mnemonic (SP) PUSH (IX)
(nn) Address memory location
Instruction Numerical Order (Continued)
Code DDF9 E2nn E4nn EAnn ECnn ED40 ED41 ED42 ED43nn ED44 ED45 ED46 ED47 ED48 ED49 ED4A ED4Bnn ED4D ED50 ED51 ED52 ED53nn ED56 ED57 ED58 ED59 ED5A ED5Bnn ED5E ED60 ED61 ED62 ED67 ED68 ED69 ED6A ED6F ED72 ED73nn ED78 ED79 ED7A
Data bit) Data (8-bit)
Mnemonic (SP) CALL PUSH (HL) CALL (nn) RETN (nn) RETI (nn) (nn) (nn)
displacement
Code ED7Bnn EDA0 EDA1 EDA2 EDA3 EDA8 EDA9 EDAA EDAB EDB0 EDB1 EDB2 EDB3 EDB8 EDB9 EDBA EDBB F2nn F4nn FAnn FCnn FD09 FD19 FD21nn FD22nn FD23 FD29 FD2Ann FD2B FD34d FD35d FD36dn FD39 FD46d FD4Ed FD56d FD5Ed FD66d FD6Ed FD70d FD71d FD72d
Mnemonic (nn) OUTI OUTD LDIR CPIR INIR OTIR LDDR CPDR INDR OTDR CALL PUSH CALL (nn) (nn)
Code FD73d FD74d FD75d FD77d FD7Ed FD86d FD8Ed FD96d FD9Ed FDA6d FDAEd FDB6d FDBEd FDE1 FDE3 FDE5 FDE9 FDF9 FDCBd06 FDCBd0E FDCBd16 FDCBd1E FDCBd26 FDCBd2E FDCBd3E FDCBd46 FDCBd4E FDCBd56 FDCBd5E FDCBd66 FDCBd6E FDCBd76 FDCBd7E FDCBd86 FDCBd8E FDCBd96 FDCBd9E FDCBdA6 FDCBdAE FDCBdB6 FDCBdBE FDCBdC6 FDCBdCE FDCBdD6 FDCBdDE FDCBdE6 FDCBdEE FDCBdF6 FDCBdFE
Mnemonic (SP) PUSH (IY)
(nn) Address memory location
Data Acquisition System
natural application NSC800 that requires remote operation Since power consumption system consists only CMOS components entire package conceivably operate from only battery power source application described herein only source power will from battery pack composed stacked array NiCad batteries (see Figure application that remote data acquisition system Extensive made some other CMOS components manufactured National notably ADC0816 MM58167 ADC0816 16-channel analog-todigital converter which operates from source MM58167 microprocessor-compatible real-time clock (RTC) schematic this system shown Figure necessary features system contained integrated circuits NSC800 NSC810A NSC831 HN6136P ADC0816 MM58167 Some other small scale integration CMOS components used normal interface requirements reduce component count linear selection techniques used generate chip selects NSC810A NSC831 Included also current loop communication link enable remote system transfer data collected host system order keep component count maximize effectiveness many features NSC800 family have been utilized section NSC810A used data buffer store intermediate measurements scratch memory calculations Both timers contained NSC810A used produce clocks required converter Power-Save feature NSC800 makes possible reduce system power consumption when necessary collect data analog input channels connected battery pack enable monitor voltage supply notify host that battery change needed operation NSC800 makes readings various input conditions through ADC0816 type devices connected input depends nature remote environment example duties remote system might monitor temperature variations large building this case analog inputs would connected temperature transducers system situated process control environment might monitoring fluid flow temperatures fluid levels either case operation would necessary even power failure occurred thus need battery operation least battery backup some fixed times some particular time durations system takes readings selecting analog input channels commands perform conversion reads data then formats transmission system checks readings against points transmits warning points exceeded With addition host need command remote system take these readings each time necessary NSC800 could simply interrupt previously defined time when interrupt occurs make readings resultant values could stored NSC810A later correlation example temperature monitoring building might desired know high temperatures 12-hour period After compiling information system could dump data host over communications link Note from schematic that current communication link supplied host remove constant current drain from battery supply required clocks peripheral devices generated timers NSC810A Through various divisors master clock generated NSC800 divided down produce clocks Four examples shown table following Figure crystal frequencies standard frequencies various divisors listed selected produce from master clock frequency NSC800 exact clock MM58167 clock within operating range converter MM58167 programmable real-time clock that microprocessor compatible data format allows system program interrupt register produce interrupt output either time match (which includes week date month) every month week hour minute second tenth second With this capability added system precise time measurements possible without having timekeeping interrupt output connected through port NSC810A power-save mode reenable preset time interrupt output also connected hardware restart inputs (RSTB) enable time duration measurements This power-down mode operation would possible NSC800 duties timekeep-
Data Acquisition System (Continued)
5171
FIGURE Remote Data Acquisition
Data Acquisition System (Continued)
When power-save mode system power requirements decreased about thus extending battery life Communication with peripheral devices (MM58167 ADC0816) accomplished through ports NSC810A NSC831 peripheral devices connected NSC800 they directly compatible with multiplexed structure Therefore additional components would required place them microprocessor Writing data into MM58167 performed first putting desired data Port followed selecting address internal register applying chip select through Port clear operation performed emulate pulse Port connected input MM58167 read operation same sequence operations performed except that Port input mode operation line pulsed Similar techniques used read converted data from converter When conversion desired selects channel commands ADC0816 start conversion When conversion complete converter will produce End-of-Conversion signal which connected RSTA interrupt input NSC800 When operating system shown consumes about When power-save mode power consumption decreased about likely system power-save mode most time battery life quite long depending amp-hour rating batteries incorporated into system example battery pack rated amp-hours system should able operate about 400-500 hours before battery charge change required shown schematic (refer Figure analog input connected battery source this monitor power source notify host that needs battery replacement charge Since battery source shown stacked array NiCads producing converter input connected middle that take reading three cells Since NiCad batteries have relatively constant voltage output until very nearly discharged sense that ``knee'' discharge curve been reached notify host
Typical Timer Output Frequencies Crystal Frequency 097152 276800 194304 915200 Clock Output 048576 638400 097152 457600 Timer Output divisor divisor divisor divisor Timer Output divisor divisor divisor divisor
NSC800M 883B MIL-STD-833 Class Screening
National Semiconductor offers NSC800D NSC800E with full class screening MIL-STD-883 Military Aerospace programs requiring high reliability addition this screening available NSC800 peripheral devices Electrical testing performed accordance with RESTS800X which tests guarantees electrical performance characteristics NSC800 data sheet copy current revision RETS800X available upon request
100% Screening Flow Test Internal Visual Stabilization Bake Temperature Cycling Constant Acceleration Fine Leak Gross Leak Burn-In Final Electrical MIL-STD-883 Method Condition 2010B 1008 1010 Cycles 2001 Axis 1014 1014C (using 1015 burn-in circuits shown below) RETS800X RETS800X RETS800X RETS800X 5005 2009 Requirement 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% Sample Method 5005 100%
Acceptance Quality Conformance External Visual
Burn-In Circuits
5240HR NSC800D 883B (Dual-In-Line) 5241HR NSC800E 883B (Leadless Chip Carrier)
5171-32
View
5171
resistors unless marked otherwise Note resistors unless otherwise specified Note clocks duty cycle phase with rise fall time Note Device cooled down under power after burn-in
Ordering Information
NSC800 Reliability Screening MIL-STD-883 Screening (Note Industrial Temperature (b40 Military Temperature (b55 Special Temperature (b55 Designation Commercial Temperature
Clock Clock Output Clock Output Clock Output
Ceramic Package Plastic Package Ceramic Leadless Chip Carrier (LCC) Plastic Leaded Chip Carrier (PCC)
Note specify temperature option parts screened military temperature
Reliability Information
Gate Count 2750 Transistor Count
Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package Order Number NSC800N Package Number N40A
Hermetic Dual-In-Line Package Order Number NSC800D Package Number D40C
Physical Dimensions inches (millimeters) (Continued)
Leadless Chip Carrier Package Order Number NSC800E Package Number E44A
NSC800 High-Performance Low-Power CMOS Microprocessor
Physical Dimensions inches (millimeters) (Continued)
Plastic Chip Carrier Order Number NSC800V Package Number V44A
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