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Newsletter Altera Customers
Altera Provides Complete Solution with APEX Device Family
Altera introduces APEXII device family- flexible, high-performance, high-density programmable logic devices (PLDs) that deliver performance bandwidth complex system-on-a-programmable-chip (SOPC) solutions. APEX devices build Altera's industry-leading APEX 20KE APEX 20KC devices. APEX device family features 1-gigabit second (Gbps) dedicated True-LVDScircuitry, support high-speed transfer protocols such RapidIO POSPHY Level 624-megabit second (Mbps) Flexible-LVDScircuitry, phase-locked loops (PLLs), high-density embedded system blocks (ESBs), enhanced all-layer-copper interconnects. Figure lists features APEX devices offer.
Complete Solution
look-up-table (LUT)-based APEX devices manufactured state-of-the-art 0.15-µm all-layer-copper interconnect technology address increasing performance bandwidth requirements communication applications. These devices offer industry-leading versatility flexibility high-performance SOPC applications. APEX device densities range from 16,640 89,280 logic elements (LEs) (1.9 million maximum gates). Based SRAM process technology, APEX devices support wide range high-speed differential single-ended standards such LVDS, PCML, LVPECL, HyperTransport, HSTL,
continued page
Figure APEX Features
Host Processor Interface
True-LVDS Solution
Gbps channel LVDS, LVPECL, PCML,
Processor
RapidIO HyperTransport PCI-X
HyperTransport input output channels
Clock-Data Synchronization
Memory Interface
ZBT, DDR, SRAM SDR, SDRAM Fast-cycle (FCRAM)
Memory
Flexible-LVDS Solution
Mbps channel LVDS, LVPECL Hyper-
Inside This Issue:
PHY-Link Layer Interface
UTOPIA
Transport
input output
channels
ASSP
Switch Fabric Interface
CSIX
Altera Ships ARM-Based Excalibur Devices, Using EPC16 Devices General-Purpose Memory, APEX
POS-PHY Flexbus
M-NV-Q201-01
Altera Corporation
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Contents
Contributed Article Master: POS-PHY UTOPIA Testing from Innocor Amplify Enables Advanced Programmable Design Altera Publications Current Software Versions Technical Articles Using Mercury Devices High-Speed Communications Implementing Drivers Devices 7000B: Only Product-Term Device that Interfaces with Altera News Altera's System Solutions Site: Gateway Networking, Wireless Telecom Communications Altera Enhances Design Services Strategy Adding Certified Design Center Program Discontinued Devices Update Every Issue Questions Answers APEX Frequently Asked Questions Altera Device Selection Guide Contact Altera.
Features Altera Provides Complete Solution with APEX Device Family Altera Ships ARM-Based Excalibur Devices Devices Tools Ethernet Linux Solutions Available Nios Embedded Processor Nios Development µClinux Nios Ethernet Development Mercury Devices Shipping Mercury Intellectual Property APEX 20KC Devices Shipping Product Notifications APEX Devices Industrial-Grade APEX Devices ACEX Industrial-Grade Availability Industrial-Temperature 7000B Devices Available High-Density Configuration Devices Quartus Software Version Service Pack Available Quartus Version Solaris Available MAX+PLUS Version 10.1 Available Operating System Update Download Latest Synthesis Simulation Tools Design Tips Using EPC16 Devices General-Purpose Memory Customer Applications NextNet Chooses APEX 20KE Signal Processing Develop First Non-LOS Broadband Wireless Access System
Altera, ACAP, ACCESS, ACEX, ACEX AMPP, APEX, APEX 20K, APEX 20KC, APEX 20KE, APEX BitBlaster, ByteBlaster, ByteBlasterMV, Classic, ClockBoost, ClockLock, ClockShift, CoreSyn, E+MAX, Excalibur, FastLUT, FastTrack, FineLine BGA, FLEX, FLEX 10K, FLEX 10KE, FLEX 10KA, FLEX 8000, FLEX 6000, FLEX 6000A, Flexible-LVDS, MegaStore, Jam, LogicLock, MasterBlaster, MAX, 9000, 9000A, 7000, 7000E, 7000S, 7000A, 7000AE, 7000B, 3000, 3000A, MAX+PLUS, MAX+PLUS MegaCore, MegaLAB, MegaStore, MegaWizard, Mercury, MultiCore, MultiVolt, NativeLink, Nios, nSTEP, OpenCore, OptiFLEX, PowerFit, PowerGauge, Quartus, Quartus RapidLAB, SignalTap, SignalTap Plus, SoftMode, True-LVDS, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: Adobe Acrobat registered trademarks Adobe Systems Incorporated. AMBA, ARM, ARM922T, ARM9TDMI, ARMulator, CodeWarrior, Thumb, Powered logo registered trademarks Limited. Cadant registered trademark trademark Cadant, Inc. DOCSIS registered trademark CableLabs. Data UniSite registered trademarks Data Corporation. Expedient trademark NextNet Wireless. HP-UX trademark Hewlett-Packard Company. Mentor Graphics registered trademark LeonardoSpectrum ModelSim trademarks Mentor Graphics Corporation. Microsoft, Windows, Windows Windows registered trademarks Microsoft Corporation. R4000, 4Kc, MIPS32, MIPS-based, MIPS Technologies logo trademarks MIPS Technologies, Inc. Rochester Electronics registered trademark Rochester Electronics, Inc. registered trademark Solaris trademark Microsystems, Inc. Synplicity registered trademark Amplify Physical Optimizer trademarks Synplicity, Inc. Synopsys registered trademark FPGA Express trademark Synopsys, Inc. System General registered trademark System General. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. actual availability Altera's products features could differ from those projected this publication provided solely estimate reader. Copyright 2001 Altera Corporation. rights reserved. Printed recycled paper.
John Panattoni, Publisher Greg Steinke, Technical Editor Innovation Drive Jose, 95134 Tel: (408) 544-7000 Fax: (408) 544-7809 n_v@altera.com
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Features Altera Provides Complete Solution with APEX Device Family, continued from page SSTL. This support enables high-speed data transfers with other PLDs, application-specific integrated circuits (ASICs), applicationspecific standard products (ASSPs). With TrueLVDS circuitry, APEX devices achieve data transfer rates Gbps channel with full channel-to-channel synchronization support. APEX devices also feature four general-purpose PLLs that drive eight different global clock nets flexible clock management synthesis needs. Table describes some highlights APEX devices. Table shows wide range APEX features packages available. LVCMOS also supported APEX devices. These standards allow APEX devices interact with other on-board highspeed devices high-bandwidth applications. APEX devices also feature MultiVoltI/O interface, allowing them work with devices using different voltage levels, including
Clock-Data Synchronization
Distributing high-speed clock signals among different devices organized manner become more difficult challenging task system designers. Variations trace lengths, capacitive loading, threshold voltages, transmission-line terminations cause clock signals arrive early late, resulting incorrect data transmission. These system variations introduce different delays between clock data, resulting skew. This skew have significant impact system performance. clock-to-data synchronization solution reduces effect skew maintain high chip-to-chip performance enhance system flexibility.
Standard Support High-Bandwidth Applications
APEX devices support cutting-edge highspeed differential standards such LVPECL, PCML, HyperTransport, LVDS with performance Gbps channel. Single-ended standards such HSTL, SSTL, CTT, GTL+, PCI-X, AGP, LVTTL,
Table APEX Highlights Feature
1-Gbps True-LVDS solution
Benefit
Provides input output high-speed channels high-performance applications. Supports LVDS, LVPECL, PCML, HyperTransport.
624-Mbps Flexible-LVDS solution
input output channels high-bandwidth needs. Supports LVDS, LVPECL, HyperTransport.
Clock-data synchronization (CDS)
Allows independent high-speed data channels interface with APEX device. Corrects amount board skew.
registers element (IOE)
Provides support high-speed external memory interfaces such ZBT-, DDR-, QDR-based memory devices. Supports ClockLockTM, ClockBoostTM, ClockShiftcircuitry flexible clock synthesis clock management with eight output taps off-chip outputs.
Enhanced PLLs
Advanced embedded system blocks (ESBs) Implements dual-port with bidirectional read/write ports, first-in first-out (FIFO) buffers, ROM, content-addressable memory (CAM). Four Kbits memory ESB. Peripheral component interconnect (PCI) PCI-X compliance SignalTap® logic analysis Density 89,280 MultiVolt operation FineLine BGApackaging Vertical migration Improves verification chip functionality. Addresses system-level needs high-density device. Ideal mixed-voltage systems. Area-optimized, 1.0-mm ball pitch provides high count. Addresses changing device density without need re-spin board. Meets 64-bit, 66-MHz PCI-X specifications.
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Features
Figure Internal Synchronization
Internally Synchronizes Individual Data Streams System Clock
Channel Transmitter
Skew Receiver
Channel
Transmitter
offers system designers superior flexibility synchronizing highspeed differential data from different sources using system clock.
Clock
APEX devices offer compensate fixed clock-to-data skew (see Figure offers system designers superior flexibility synchronizing high-speed differential data from different sources using system clock. APEX devices automatically adjusts receivers compensate varying chip delays trace lengths. APEX implementation compensate much full-bit period skew single-bit mode
Table APEX Device Overview Feature EP2A15
Maximum gates Typical gates Logic elements ESBs General-purpose PLLs Maximum bits True-LVDS channels (transmit/receive) Flexible-LVDS channels (transmit/receive) Maximum user pins Available packages 724-pin 672-pin FineLine 56/56 1,900,000 600,000 16,640 425,984 36/36
unlimited skew multi-bit mode. Synchronizing clock data channels each high-speed True-LVDS channel independently simplifies board design helps designers fully utilize high-speed capabilities APEX devices. APEX supports multiple standards, such LVDS, LVPECL, PCML, HyperTransport. continued page
Device EP2A25
2,750,000 900,000 24,320 622,592 36/36
EP2A40
3,000,000 1,500,000 38,400 655,360 36/36
EP2A70
5,250,000 3,000,000 67,200 1,146,880 36/36
EP2A90
7,000,000 4,000,000 89,280 1,523,712 36/36
56/56
88/88
88/88
88/88
724-pin 672-pin FineLine
724-pin 672-pin FineLine
1,060 724-pin
1,140 724-pin
1,508-pin FineLine 1,508-pin FineLine
1,020-pin FineLine 1,020-pin FineLine
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Features Altera Provides Complete Solution with APEX Device Family, continued from page
Advanced Phase-Locked Loops
APEX devices include four embedded general-purpose PLLs with enhanced ClockLock, ClockBoost, ClockShift circuitry, four dedicated LVDS PLLs synthesizing high-speed clocks that used dedicated True-LVDS circuitry. ClockLock circuitry reduces clock delay skew within device. ClockBoost circuitry provides clock frequency multiplication division, minimizing number external clocks needed design. ClockShift circuitry provides programmable clock delay phase shift capability aligning clock edges. Each four general-purpose PLLs output taps total eight output taps device that independently feed eight global clock lines internal device. Each APEX device also external clock output pins that directly from separate PLLs.
High-Speed External Memory Interfaces
Each True-LVDS channel supports data transfer rates Gbps. APEX devices enables emerging high-speed memory interfaces such zero-bus turnaround (ZBT), double-data rate (DDR), quad-data rate (QDR) SRAMs, single-data rate (SDR), SDRAMs, fast-cycle (FCRAM) SDRAMs. Each consists input registers, output registers, output-enable registers input latch, dedicated timing circuitry. addition APEX IOE, Altera also provides APEX II-optimized intellectual property (IP) MegaCore® functions implement memory controllers that direct data access from external memory devices. Refer MegaStoreweb site list available controllers different types memory devices.
Figure 1-Gbps True-LVDS Waveform
High-Performance Differential Support
APEX devices support multiple high-speed differential standards including LVDS, LVPECL, PCML, HyperTransport. Differential signaling techniques facilitate high data transfer rates, reduce electromagnetic interference, simplify printed circuit board design. True-LVDS Solution True-LVDS solution uses dedicated circuitry perform high-speed data serialization/deserialization (SERDES). Each True-LVDS channel supports data transfer rates Gbps. Figure shows oscilloscope output True-LVDS channel running Gbps. APEX devices feature receiver channels transmitter channels, well independent LVDS clock domains driven dedicated PLLs. Each channel supports LVPECL, PCML, HyperTransport well independent clock multiplication feature. True-LVDS correct fixed multi-bit-period skew between different LVDS receiver channels, synchronizing them single-system clock.
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Features
Figure Packet Processing
Host Processor (CPU)
RapidIO HyperTransport
Packet Processing LVDS/ LVPECL Layer Framer/ Parser Control Plane Functions Modification/ Forwarding Queuing
CSIX Switch Fabric
Classification
Encryption/ Compression
SRAM
SDRAM
Flexible-LVDS Solution Flexible-LVDS solution capable data transfers Mbps channel, using general-purpose logic SERDES functions. APEX devices support receiver transmitter channels. Flexible-LVDS channels support LVDS, HyperTransport I/O, LVPECL inputs, LVDS HyperTransport outputs.
APEX devices also feature support interfaces host processors (PCI-X, HyperTransport, RapidIO), Switch fabric (CSIX), PHY-layers (POS-PHY Level Flexbus Level APEX devices support industry-leading differential standards such LVDS, LVPECL, PCML. APEX devices provide interface external SRAM (using ZBT, QDR, DDR) SDRAM (using SDR).
High-density, featurerich APEX devices ideal SOPC solutions. such SOPC application packet processor.
Packet Processing Applications
High-density, feature-rich APEX devices ideal SOPC solutions. such SOPC application packet processor. Packet processors require functions such framer/ parser, modification/forwarding, queuing, classification. Altera offers many standard functions required packet processing applications, shown Figure These functions optimized APEX architecture available through MegaStore site. Using Altera APEX devices, designers significantly decrease time-to-market.
Enhanced Embedded System Blocks
APEX devices feature ESBs total Mbits memory. Each accommodates Kbits memory that configured various data widths: 1,024 2,048 4,096 bit. 4-Kbit ESBs split into 2-Kbit blocks, effectively doubling number ESBs. APEX ESBs support bidirectional read write ports based independent clocks, synchronous asynchronous operation, high-speed FIFO buffers. ESBs also configured high-performance used high-speed search applications. Multiple ESBs combined create deeper, wider CAM. continued page
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Features Altera Provides Complete Solution with APEX Device Family, continued from page SRAM controller Interface zerobus turnaround latency) SRAM memory devices SRAM controller Interface quad data rate SRAM memory devices MHz/667 Mbps PCI-X 64-bit PCI-X initiator/target function
Breakthrough Performance with All-LayerCopper Interconnect
APEX devices built state-of-the-art alllayer-copper interconnect technology. Copper lower resistance better electromigration characteristics than aluminum, translating significant performance improvements. Additionally, copper more scalable than aluminum, resulting smaller sizes.
Signal Processing Correlator Finite impulse response (FIR) filter compiler Reed-Solomon encoder/decoder Turbo encoder/decoder Parallel high-speed Viterbi decoder
Simplifies Design
release APEX device family, featuring unparalleled logic density silicon support advanced standards, brings increased need Altera design flow. shortens design time, lowers development cost, gives designers access technology that outside their core competency. With increased device capacity, Altera expects increase usage multiple functions single device. With device density over 89,000 Mbits on-chip RAM, typical APEX design contain four eight functions addition custom logic. total functions available SOPC development high-density, high-performance APEX device family. These functions come from both Altera's portfolio MegaCore functions well from independent Altera Megafunction Partners Program (AMPPSM) partners. Some functions that form critical component APEX solution listed below: Interfaces Peripherals HyperTransport (formerly LDT) advanced communications interface SDRAM controller Interface SDRAM memory devices SDRAM controller Interface SDRAM memory devices MHz/334 Mbps
Communications RapidIO processor backplane interface 10/100 Ethernet media access controller (MAC) POS-PHY Level (formerly SPI-4 Phase UTOPIA Level master UTOPIA Level slave Flexbus Level optical networking protocol (AMCC)
APEX devices built state-of-theart all-layer-copper interconnect technology. Copper lower resistance better electromigration characteristics than aluminum.
Quartus Development Tool
Quartus® software version adds full compilation, simulation, programming support APEX EP2A15 device advanced support APEX EP2A25, EP2A40, EP2A70 devices. Quartus software version will support APEX architecture features. Support architecture features version include: 4-Kbit deep mixed-width dual-port RAM, enhanced PLLs, (DDIO), 1-Gbps LVDS channels, 624-Mbps Flexible-LVDS circuitry, external memory interfaces such QDR, other differential single-ended standards. Quartus design software offers LogicLockincremental design methodology includes parts: creation LogicLock constraints, integration LogicLock constraints into larger design. This methodology allows designer create placement constraints around function block logic, verify functionality performance, then control placement.
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Features LogicLock constraints used with custom blocks logic pre-verified from Altera AMPP partners. LogicLock constraints guarantee repeatable placement when implementing block logic current project exporting block another project, making design reuse reality. LogicLock constraints lock down logic fixed location device floating location. Floating locations allow Quartus software determine best relative placement core meet design requirements.
Conclusion
APEX device family provides ideal solution your SOPC design needs. Visit Altera® site learn more about APEX device family complete solution http://www.altera.com.
Altera Ships ARM-Based Excalibur Devices
Altera shipping sample units first member ARM®-based Excaliburproduct family, EPXA10 device. This device integrates 200-MHz ARM922Tembedded processor core, on-chip single- dual-port memory, peripherals, from 4,160 38,400 logic elements (LEs) programmable logic. Altera will ship EPXA10 devices 2001, EPXA4 EPXA1 devices will available second half 2001. ARM-based Excalibur devices used broad range applications such network processors, digital TVs, basestations, frame relay switch port cards, embedded routers, network interface cards, other applications that benefit from customization integration. These devices support prototyping well volume production requirements. Excalibur solutions-consisting Niossoft core processor, ARM-based hard core devices, MIPS-basedhard core devices-enable development complex system-on-a-programmable-chip (SOPC) designs with flexibility substantial timeto-market benefits programmable logic. licensing fees per-unit royalties apply Excalibur solutions, Nios development kits currently available shipping. Excalibur solutions will available through Altera® distributors worldwide.
Second Quarter 2001 News Views
Altera also offers broad range blocks through MegaCore® program well third-party Altera Megafunction Partners Program (AMPPSM) partnerships both which implemented within ARM-based Excalibur devices. ARM922T embedded processor based ARM9TDMI32-bit core, includes Kbytes each instruction data caches, memory management unit (MMU), embedded trace module (ETM) capability. addition processor, ARM-based Excalibur family devices integrate both single- dual-port SRAM within processor stripe, with Kbytes single-port SRAM Kbytes dual-port SRAM available EPXA10 device (see Figure page 10). addition internal memories, embedded processor stripe provides interfaces external memory. device includes interfaces: SDRAM controller expansion interface (EBI). SDRAM controller supports Mbytes 32-bitwide SDRAM both single-data rate (SDR) double-data rate (DDR) SDRAMs Mbps, respectively. SDRAM controller also independent continued page
Altera Corporation
Features Altera Ships ARM-Based Excalibur Devices, continued from page addition memories memory interfaces, EPXA10 devices have several hard peripherals built into embedded processor stripe, including universal asynchronous receiver/transmitter (UART) serial communication, timer support real-time applications, watchdog timer system checks, interrupt controller. interrupt controller replaced augmented within programmable logic device (PLD). device memory on-chip memories user-configurable. processor stripe EPXA10 device implements AMBAhigh-performance architecture, which runs allow full processor speed operation. processor core, PLD, SDRAM controller have PLLs their individual clock domains they operate their maximum frequencies higher system-level performance. ARM-based Excalibur embedded processor PLDs supported Altera Quartus® software, Development Suite (ADS) Lite software embedded processor development, MegaWizard® flow configure core peripherals. Lite tool comes with C/C++ compiler assembler Thumb® code, debugger, full documentation. Lite tool ARM92xT-processor-core specific. full version software available from Limited, adds CodeWarriorgraphical user interface (GUI) ARMulator® instruction simulator. ARM-based Excalibur devices also supported WindRiver Systems VxWorks real-time operating system. ARM-based Excalibur development board, including utilities, reference design examples, full board support package, GNUPro software tool chain support will soon available.
Figure Excalibur EPXA10 Device
Dual-Port Single-Port ARM922T RISC Processor Combined with Complete Peripheral
Programmable Logic
phase-locked loop (PLL) SDRAM clock support external memories different clock frequencies. second interface, EBI, designed interface flash memory, SRAM, memory-mapped peripherals. access four devices, each Mbytes. This allows user-configurable memory EPXA10 device independently access boot flash memory, user SRAM, peripheral devices.
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Devices
Tools MERCURY 10-Mbps Ethernet port their Nios systems. following hardware software components included kit: Ethernet daughter card 5-foot cable crossover connector Hardware reference design Complete TCP/IP stack software (with source code) server application software (with source code) Documentation, including Internet Core Protocols reference book O'Reilly Associates, Inc.) Excalibur development µClinux introduces flexible Nios processor embedded Linux developers.
EXCALIBUR
Ethernet Linux Solutions Available Nios Embedded Processor
July 2001, Altera scheduled begin shipping Excaliburdevelopment kits featuring Niosembedded processor. These kits will add-on components existing Nios development board, allowing addition Linux operating system Ethernet peripheral support Nios soft core embedded processor.
Excalibur Development µClinux
Developed with Microtronix Datacom Ltd., provider Linux-based solutions, Excalibur development µClinux introduces flexible Nios processor embedded Linux developers. following hardware software components included designed work with Excalibur development µClinux: µClinux source code SDRAM/flash memory module SDRAM controller core (with source code) Ethernet daughter card Host adapter board (with real-time clock mass storage interface) Hardware reference design server application software (with source code)
Nios Ethernet development scheduled begin shipping July 2001, will cost only $495. same license agreement applies Excalibur development kit.
MERCURY
Mercury Devices Shipping
Mercuryproduct family continues roll out, with samples EP1M120 device shipping, Quartus® software version support available entire Mercury family. These devices feature eight channels clock-data recovery (CDR), 120,000 typical gates, 4,800 logic elements (LEs), Kbits RAM, maximum user pins 484-pin FineLine BGApackage. Sample EP1M350 devices scheduled begin shipping July 2001 will feature full channels support. These high-speed serial links make Mercury devices ideal serial backplane applications.
Excalibur development µClinux will cost $2,495 scheduled ship July 2001. Designers purchase this development will receive free, perpetual license included SDRAM controller.
Mercury Intellectual Property
Mercury Gigabit Transceiver MegaCore® function available from MegaStoreon Altera® site. This MegaCore function incorporates 8B/10B encoding decoding functionality, byte alignment, comma detection, rate-matching
Nios Ethernet Development
Nios Ethernet development add-on component Excalibur development kit, featuring Nios embedded processor. Nios developers requiring network connectivity
continued page
Second Quarter 2001 News Views Altera Corporation
Devices Tools Devices Tools, continued from page first-in first-out (FIFO) buffers perform lowlevel functions commonly required applications.
Industrial-Grade APEX Devices
Over different industrial-grade APEX devices available various package offerings. Tables
Table APEX 20KC Devices Quartus Software Support Availability Device Package Software Support Availability
APEX
APEX 20KC Devices Shipping
first three APEX20KC devices (EP20K400C, EP20K600C, EP20K1000C) shipping. high-performance APEX 20KC devices address high-bandwidth needs system-on-a-programmable-chip (SOPC) applications. These devices combine state-of-the-art features found APEX 20KE devices with industry-leading, 0.15-µm alllayer-copper interconnect technology, providing performance improvements over 0.18-µm-based devices. Table shows availability schedule APEX 20KC devices. APEX 20KC devices supported Quartus software version shown Table
Table APEX 20KC Device Availability Device
EP20K200C EP20K400C EP20K600C EP20K1000C EP20K1500C
EP20K200C
208-pin PQFP 240-pin PQFP 356-pin 484-pin FineLine 652-pin 672-pin FineLine
EP20K400C
652-pin 672-pin FineLine
EP20K600C
652-pin 672-pin FineLine 1,020-pin FineLine
EP20K1000C 652-pin 672-pin FineLine 1,020-pin FineLine EP20K1500C 652-pin 1,020-pin FineLine
Note Table Plastic quad flat pack: PQFP; ball-grid array: BGA.
Availability
2001 2001
Table APEX Device Industrial Offering Device
EP20K100
Package
208-pin PQFP 240-pin PQFP
Speed Grade
Product Notifications APEX Devices
Altera will discontinue selected devices from APEX family. Refer more details. Additionally, Altera will switching from 8-inch wafers 12-inch wafers EP20K400E devices beginning July 2001. Refer more information. Product notifications found Altera site http://www.altera.com.
EP20K200
240-pin PQFP 484-pin FineLine
EP20K400
652-pin 672-pin FineLine
Note Table denotes 5.0-V tolerant I/O.
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Devices Tools Full software support ACEX devices available from MAX+PLUS® software version 10.1. addition, wide range ACEX-optimized intellectual property (IP) functions found Altera MegaStore site.
Table APEX 20KE Device Industrial Offering Device
EP20K30E EP20K60E EP20K100E
Package
144-pin FineLine 208-pin PQFP 144-pin FineLine 324-pin FineLine
Speed Grade
EP20K160E EP20K200E
484-pin FineLine 240-pin PQFP 484-pin FineLine
Industrial-Temperature 7000B Devices Available
past, industrial-temperature devices were primarily used only industrial applications. Now, however, they used wide range communications networking products. industrial-temperature range guarantees device fully functional junction temperatures -40°C +105°C. These devices through extensive product characterization reliability stresses that they able withstand extreme temperature variations. MAX® 7000B devices provide broad range industrial-grade 2.5-V devices averaging densities from macrocells. Altera shipping 7000B industrial-temperature-grade devices shown Table
Table 7000B Industrial-Temperature Device Availability Device
EPM7032B EPM7064B
EP20K300E EP20K400E
672-pin FineLine 652-pin 672-pin FineLine
EP20K600E
652-pin 672-pin FineLine
EP20K1000E
652-pin 672-pin FineLine
Note Table denotes phase-locked loop (PLL) LVDS support.
ACEX
ACEX Industrial-Grade Availability
Altera currently offers ACEX1K devices industrial grades. Table shows which packages available industrial grades. Contact your local Altera sales representative availability lead times specific packages.
Package
44-pin TQFP 44-pin PLCC 44-pin TQFP 100-pin TQFP
Speed Grade
Table ACEX Industrial-Temperature Device Availability Device
EP1K10
Package
100-pin TQFP 144-pin TQFP 256-pin FineLine
Speed Grade
EPM7128B
100-pin FineLine 100-pin TQFP 144-pin TQFP 256-pin FineLine
EP1K30
144-pin TQFP 256-pin FineLine
EPM7256B
100-pin TQFP 144-pin TQFP 208-pin PQFP 256-pin FineLine
EP1K50
256-pin FineLine 484-pin FineLine
EP1K100
208-pin PQFP 256-pin FineLine 484-pin FineLine
EPM7512B
256-pin FineLine 256-pin
Note Table denotes support.
continued page
Second Quarter 2001 News Views Altera Corporation
Devices Tools Devices Tools, continued from page
TOOLS
Quartus Software Version Service Pack Available
download Quartus software version Service Pack (SP2) This service pack adds Programmer Object File (.pof) generation Mercury EP1M120 devices aluminum FineLine packages APEX EP20K600C devices 652-pin packages. Additionally, enhances support Mercury LVDS features. mySupport download page Altera site more information. Quartus software version download page also includes link download simulation models. also update ModelSim®-Altera version 5.4e software with latest simulation models used Quartus software version SP2. ModelSim SE/PE other simulation tools require updates.
CONFIGURATION
High-Density Configuration Devices
Altera EPC16 devices with megabits flash memory programmable logic industry's largest configuration device. Utilizing patented data compression technology, EPC16 device configure APEX EP20K1500E devices APEX EP20K600E device, other combination over million system gates programmable logic. EPC16 device offers in-system programmability (ISP) through built-in IEEE Std. 1532 boundary-scan-based in-system configuration (ISC) standard programmable devices. inclusion reprogramming capability provides significant advantage over one-time-programmable solutions introducing flexibility reusability configuration process. EPC16 device also introduces numerous features specialized configuration needs. These features include: parallel configuration capability accelerate configuration times, page mode that allows users store multiple configurations, block protection partial reprogramming support, full clocking flexibility through programmable clock external clock features. Unused portions EPC16 flash memory used general-purpose memory built-in processor access feature. This advanced feature enhances overall design experience while improving manufacturability high-volume environment. more information EPC16 devices, "Using EPC16 Devices General-Purpose Memory" page
Quartus software version MAX+PLUS software version 10.1 both support Solaris operating system.
Quartus Version Solaris Available
Quartus software version Solaris shipped customers with active FLOATNET subscriptions. This version gone through more installation graphical user interface (GUI) testing than previous version Quartus software Solaris, resulting better performance, easier installation, better stability. PowerFittechnology place-and-route algorithms (available Quartus software version included Quartus software version Solaris, providing improved fMAX performance industry's fastest compile times. Quartus software version Solaris first version support Solaris operating system. Table shows complete list operating systems supported Quartus software version 1.0. Quartus software version includes enhancements updates included Quartus software version including generation
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Devices Tools Mercury EP1M120 devices (aluminum) 484-pin FineLine package APEX EP20K600C devices 652-pin package. Altera focuses operating system support efforts latest most widely-used operating systems. example, based customer demand, Quartus software support version Linux operating system planned upcoming release. decreased usage, Altera will discontinue support Solaris 2.6, HP-UX 10.2, Windows operating systems versions Quartus MAX+PLUS software released after June 2002. Quartus software version adds generation devices packages shown Table
Table Device Support Quartus Software Version Service Pack Device
EP20K600C EP1M120 (aluminum)
MAX+PLUS Version 10.1 Available
MAX+PLUS® software version 10.1 available from your local sales office will ship users with active subscription (with next version Quartus software). This first version that introduces support Solaris HP-UX 11.0 operating systems. Version 10.1 also adds programming support EPC16 configuration device. list current operating systems supported MAX+PLUS software version 10.1, Table
Table Operating Systems Supported Quartus MAX+PLUS Software Software
Quartus software version
Package
652-pin 484-pin FineLine
Operating System
Microsoft Windows 2000 Windows version higher Microsoft Windows Solaris 2.6, 2.7, HP-UX 10.2x 11.0
Download Latest Synthesis Simulation Tools
customers with active subscriptions licensed latest versions synthesis simulation tools Altera includes with software subscriptions. These versions include support APEX 20KC, Mercury, Excalibur device families. Table shows versions available.
Table Synthesis Simulation Tools Tool
Synopsys® FPGA Express3.5.1 2001.1a Exemplar Logic®
MAX+PLUS software version 10.1
Microsoft Windows 2000 Windows version higher Microsoft Windows Solaris 2.6, 2.7, HP-UX 10.2x 11.0
Version
Operating System Update
Quartus software version MAX+PLUS software version 10.1 both support Solaris operating system. MAX+PLUS software version 10.1 also adds support HP-UX 11.0 operating system. Table shows latest operating systems supported Quartus software MAX+PLUS software.
LeonardoSpectrum-Altera Model TechnologyModelSim-Altera 5.4e
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Using EPC16 Devices General-Purpose Memory
Altera's EPC16 configuration devices used memory storage programmable logic device (PLD) processor. main components EPC16 device standard flash memory controller, shown Figure Flash memory used store configuration data that controller accesses configure more PLDs. Unused portions flash memory available processor external flash memory interface.
Figure EPC16 Device Block Diagram
driven processor access flash memory when interface available (i.e., when controller accessing flash memory). address control lines flash memory have weak internal pull-up resistors that always active. other hand, flash data lines bus-hold. When controller accessing flash memory (while configuring in-system programming EPC16 device) processor must tri-state flash interface pins avoid contention. When controller accessing flash memory, tristates memory interface, allowing processor access flash memory. Table lists EPC16 passive serial interface signals that should monitored processor determine flash memory interface available. Flash access available after successful configuration PLD, indicated high level CONF_DONE, nSTATUS, nCONFIG pins. most other cases, flash memory interface used controller processor should tri-state flash memory interface pins. When nCONFIG nSTATUS high CONF_DONE low, states possible: being configured, EPC16 device blank. During configuration, EPC16
address, data, control ports flash memory connected controller internally external pins EPC16 package.
JTAG/ISP Interface
Flash Memory
Controller
Flash Memory Interface
EPC16 flash memory interface tri-state implementation. address, data, control ports flash memory connected controller internally external pins EPC16 package. These external pins
Table EPC16 Device Passive Serial Interface Signals
nINIT_CONF/nCONFIG OE/nSTATUS nCS/CONF_DONE
External Flash Interface
State
available EPC16 power-on reset (POR); nCONFIG asserted processor external source) private Joint Test Action Group (JTAG) initiate configuration instruction
available EPC16 failed configuration
(DCLK active)
available Configuration process when DCLK toggling
(DCLK inactive)
Available Available
Blank EPC16 when DCLK toggling PLDs configured
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Figure Board-Level Connections
Being Configured DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
EPC16 Configuration Device C-WE# C-RP# DCLK DATA0 nINIT_CONF PORSEL PGM[2.0] EXCLK VCCW F-WE# F-RP#
Microprocessor A[20.0] DQ[15.0] RY/BY#
A[20.0] DQ[15.0] RY/BY#
Tri-state interface. These signals (displayed dotted lines) should driven when flash interface available (see Table page 16).
Notes Figure pull-up resistors except APEX20KE APEX 20KC devices; APEX 20KE APEX 20KC devices' pull-up resistors nCS, nINIT_CONF pins EPC16 configuration devices have internal pull-up resistors. internal pull-up resistor nINIT_CONF always active. However, pins, user option turning these resistors through software. Designers must either internal external pull-up resistors, both. nSTATUS should have external pull-up resistor ACEXor FLEX® devices. nINIT_CONF available used, nCONFIG must pulled either directly through resistor. should tied GND. leave this floating, since controller does drive PORSEL should tied 2-ms 100-ms POR, respectively. EXCLK only input pin. Quartus® software, user select EXCLK internal oscillator clock source. test pins should connected follows user mode: connected connected VCC.
device will toggle DCLK DATA. Conversely, when EPC16 device blank, DCLK DATA toggling. Checking activity DCLK enables designer determine processor access flash memory. designer cannot force EPC16 controller relinquish flash access processor. processor wait until configuration complete (CONF_DONE goes high) before accessing flash memory. Auto-Restart Configuration option enabled corrupt programming data flash memory, EPC16 device will continuously attempt configure PLD. this situation, external processor cannot access flash memory until valid programming file downloaded EPC16 device. external processor cause configuration process restart releasing control interface then toggling nCONFIG.
Board-Level Connections
EPC16 device used general-purpose memory, connect EPC16 external flash pins processor. processor should tri-state these pins when flash access available. Alternatively, when design does external flash memory interface, leave flash pins unconnected board (see Figure internal pull-up resistors prevents these signals from floating. Connecting these flash pins causes contention during controller access cycles.
Conclusion
EPC16 configuration devices industry's largest devices that support in-system programmability (ISP). EPC16 device's external flash memory interface allows designers access unused flash memory save board space combining flash memory configuration functions into single, versatile device.
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Application
Altera's system-on-a-programmable-chip (SOPC) product solutions boosted NextNet's development Expediencesystem, designed provide multichannel multipoint distribution system (MMDS) service providers with rapid, low-cost deployment high-speed, two-way data, voice other broadband services over last mile communications network. This latest joint effort between Altera NextNet further proof Altera's success wireless communications market. "Altera's PLDs signal processing provided necessary development aids take NextNet's unique non-line-of-sight wireless technology from concept product timely cost-effective manner," said Merv Grindahl, NextNet vice president chief architect. needed technology caliber Altera's APEXdevice family order development this complexity face today's time-to-market challenges. received excellent support from entire Altera team day-to-day basis." creating Expedience system, NextNet required cost-effective hardware solution that would also allow them their complex development system full speed. Altera's signal processing along with APEX 20KE PLDs allowed NextNet achieve operating speeds that they required. pleased provide NextNet Wireless with right signal processing customer support their Expedience broadband fixed wireless product," said Justin Cowling, Altera senior marketing manager. "Altera's highperformance signal processing portfolio other SOPC products factor providing flexibility rapid time-tomarket that companies like NextNet need." NextNet shipping Expedience system beta quantities, with full production scheduled summer 2001.
NextNet Chooses APEX 20KE Devices Signal Processing Develop First Non-LOS Broadband Wireless Access System
About NextNet Wireless
NextNet Wireless privately held start-up company focused building MMDS non-lineof-sight broadband wireless access systems rapid deployment high-speed, two-way voice data services over "last mile" communications network. Company's endto-end Expedience system enables MMDS service providers deliver low-cost, converged services small office/home office residential subscribers over single multiservice network. This technology will initially applied MMDS band (2.5 2.686 GHz), later leveraged other frequency bands applications. More information NextNet Wireless available http://www.nextnetwireless.com.
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(INL03991-02), which integrated into programmable logic device (PLD) each pod. Each interface comprised power regulator block, APEXEP20K400E device, MAX® EPM7128AE device, Mbytes SDRAM, Kbytes SRAM, Mbytes flash memory. Each hold four images, which stored flash memory. ability dynamically reprogram support different standards (i.e., UTOPIA POSPHY) major advantage this EP20K400E device-based architecture. Design reprogrammability enables level customization ability adapt quickly emerging standards, which would otherwise impossible with applicationspecific integrated circuit (ASIC) implementation. primary function EPM7128AE device program EP20K400E device with appropriate image selected controller. heart each interface APEX EP20K400E device. EP20K400E device selected this application because integrated phase-locked loops (PLLs), high logic density, embedded RAM, unparalleled in-system performance. continued page
Figure POS-PHY UTOPIA Tester
Master: POS-PHY UTOPIA Testing from Innocor
part Altera Megafunction Partners Program (AMPPSM) partnership, Innocor presents physical layer (PHY) tester (PHY Master), which industry leader physical layer testing applications. These applications have power meet highperformance physical layer test development requirements. Innocor's Master unique innovative approach development testing variety physical implementations Packet over SONET (POS)-PHY Universal Test Operations Interface A(UTOPIA). Master emulates link layer side Alayer UTOPIA interface. master compact suitable desktop testing. separate transmit receive pods easily connected user's system under test. Both UTOPIA POS-PHY interfaces support maximum devices. master consists controller interface pods (see Figure Figure shows master architecture. transmit interface receive interface. controller comprised Motorola quad integrated communications controller (QUICC) processor (68EN360), Mbytes DRAM plus Mbytes flash memory, well serial interfaces that connect pods controller. controller responsible housing embedded server software required provide control indication interface pods. receive transmit pods each connect controller custom serial control cable. serial cable provides power communications between pods controller. communication between controller each provided bitoriented high-level data link control (HDLC) over serial cable. controller, this serial communications link provided embedded serial communications controller QUICC. pods, bit-HDLC function provided Innocor's bit-HDLC system-on-a-programmable-chip (SOPC) core
APEX EP20K400E device selected Innocor's application because device integrated phase-locked loops (PLLs), high logic density, embedded RAM, unparalleled in-system performance.
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Contributed Article Master: POS-PHY UTOPIA Testing from Innocor, continued from page
Figure Master Architecture
POS-PHY UTOPIA Interface Master Transmit System under Test Receive Control Cable Operator Access Control Cable Controller Remote Access
EP20K400E device provides POS-PHY UTOPIA interfaces, traffic generation monitoring Innocor's error rate testing (BERT) SOPC core (INL08991-01), well communications from controller Innocor's bit-HDLC SOPC core (INL03991-02). support both 5.0-V 3.3-V interfaces without concern power sequencing, EP20K400E device shielded from interface switches. integrated termination scheme each ensures signal integrity across high-speed UTOPIA POS-PHY buses.
POS-PHY Saturn-compatible interfaces. Master provides ability error rate (BER) pseudo random sequences (PRBS), including 2e15-1, 2e20-1, 2e23-1, user data into variable length POSPHY packets Kbytes. Master also inserts detects data errors (single errors, 10e-3 10e-6 errors) POS-PHY packet errors. While operating POS-PHY mode, Master supports internallygenerated transfer clock rates MHz. Each also accepts external clock input operation between MHz.
Hardware Interoperability Testing
Using Altera's high-performance programmable logic off-the-shelf intellectual property (IP), system architects design engineers quickly efficiently implement high-speed, standardized telecom interfaces such POSPHY UTOPIA. Innocor Master allows designers verify hardware software functionality interoperability between Altera's MegaCore® communications functions, well designer's proprietary logic through emulation real network traffic into layer.
UTOPIA Testing
UTOPIA interface supports UTOPIA 8and 16-bit parallel interfaces (Level Level Master allows user insert monitor PRBS user-defined traffic Acells with full bandwidth control. addition PRBS stream fully-specified virtual circuit, Master UTOPIA interface delivers extensive virtual circuit saturation across providing user ability define traffic across entire virtual circuit range. Master reports extensive performance statistics (e.g., cell counts, errors, UTOPIA errors). While operating UTOPIA mode, Master supports internally-generated transfer clock rates MHz; also accepts external clock inputs operation between MHz.
POS-PHY Testing
POS-PHY interface POS-PHY Level that supports 16-bit data width. also supports 8-bit POS-PHY Level interface. Master implements link layer
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Connecting Master
operator choice controlling monitoring test process workstation that directly connected Master controller, remotely connection. Master supports command-line interface that accessed Telnet session RS-232 serial console. simple syntax command-line interface especially suited automation test procedures using scripts. addition command-line interface, master intuitive, Java-based graphical user interface (GUI) that accessible session from standard browser. Figure shows user interface POS-PHY mode operation. Figure shows user interface UTOPIA mode operation.
Figure POS-PHY Graphical User Interface
Figure UTOPIA Graphical User Interface
Master Solutions
Master allows POS-PHY UTOPIA ASIC developers test framer devices well demonstrate their implementations running real traffic across their systems. network equipment developer, Master replaces link layer functions allow insertion BERT user traffic into layer. master member Innocor's TestPoint product line high-performance testing systems manufacturing, research development, field support applications telecommunications industry. more information about Master, visit Innocor site http://www.innocor.com e-mail info@innocor.com.
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Amplify Enables Advanced Programmable Design
Advances process technology have significantly increased number applications that programmable logic. These advances have given rise design challenges. Densities multi-million gates, speeds approaching MHz, short design cycles present difficult problems designers. advanced programmable devices, physical interconnections between logic elements rather than logic itself, dominate design performance equation. Interconnects account much overall circuit delay process geometries descend below 0.15 Amplify industry's only physical synthesis optimization technology devised specifically programmable logic. Advanced techniques employed Amplify enable programmable logic designers reach their performance goals systematically. Amplify works seamlessly with Quartus® software enable advanced programmable design. Performance optimization conventional synthesis environment physical interconnect information. This lack up-front physical information cause performance problems later design process. synthesis process must comprehend physical effects. Back-annotation timing after place-and-route with resynthesis help slightly, does have ability restructure logic greater performance gain converge required timing performance quickly physical synthesis. Physical synthesis refers utilization physical placement information during synthesis process. Amplify allows users specify timing constraints register transfer level (RTL) physical constraints front uses these constraints perform unique optimizations. circuit synthesized Amplify optimized logic well physical effects. output includes physically optimized netlist critical placement
Amplify combines innovative physical optimization technology with production-proven logic synthesis algorithms Synplify.
information that will used place-androute tools. Physical synthesis represents major technology leap design high performance programmable devices. characterized simultaneous placement optimization. Unique optimizations enhance results synthesis process using physical design characteristics that affect actual topology circuit. This technology makes possible communicate physical constraint information such placement regional interconnect delay synthesis process. design then physically optimized prior placement routing stages. Amplify combines innovative physical optimization technology with productionproven logic synthesis algorithms Synplify. core logic synthesis algorithms have been perfected over years specifically programmable logic synthesis. Amplify's hierarchical optimization engine leverages topology placement knowledge produce significantly improved netlist results after physical synthesis. Amplify provides intuitive flexible graphical interface creating physical constraints opposed gate level). also translates physical constraints forward annotation place route tools. Amplify also provides powerful netlist restructuring capabilities such zippering slicing easily partitioning design without modifying hardware description language (HDL) code. Amplify powerful users that either trying meet high design performance goal reduce design cost using slower speed grade.
Floorplanning Improves Timing Estimates Optimizations
Typically designers more comfortable with description their design knowledge this description level create better physical constraints. Designers optimize their design create physical
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Contributed Article regions assign proper logic them. Amplify uses knowledge device architecture estimate timing within these defined physical regions (rows FLEX® devices, MegaLABstructures APEXdevices) more accurately. then uses timing estimates localized physical regions, produce better optimized circuit.
Figure Amplify Front Panel APEX Devices
Floorplanning: Better Manage Design Performance
Amplify provides easy optimize control physical placement design level. Throughout process, designer maintains high level control flexibility. Amplify allows designer change physical hierarchy, allowing creation regions, without having actually change source code. resulting physical hierarchy, which different from logic hierarchy, optimized performance. Unlike gate-level floorplanning, Amplify operates design level creates netlist better than created with logic synthesis.
Facilitates Team Design
large design project typically divided into sub-circuits very early design stages, before physical effects fully understood. Design modules most frequently delineated according logical hierarchy with little consideration physical effects. After placeand-route, critical paths cross boundaries several modules. Amplify provides unique solution this problem enabling teams divide design responsibilities without advance knowledge design's critical path. Multiple team members work parallel integrate different logical blocks using Amplify's floorplanning interface. Amplify create physical hierarchy that different from original logic partitioning meets timing performance.
presents data right level abstraction easy physical constraint creation. Using this intuitive interface, designers enter physical constraints dragging dropping critical path elements from view physical view. physical regions available APEX devices single MegaLAB structure, custom regions (multiple MegaLAB structures single column), half column, full column. FLEX devices, rows used available physical regions. Users manually replicate logic without making changes code. They also easily estimate utilization physical region after assigning logic
Advanced Optimization Techniques
Amplify features many highly advanced optimization techniques ensure best possible performance given design. These techniques include critical path restructuring, logic tunneling, feed-through optimization, constant propagation, logic replication, replication, state machine optimizations, pipelining, logic retiming, interconnect delay retiming. Some Amplify's optimization techniques that include tunneling time budgeting discussed following paragraphs. continued page
Unleashes Productivity
Amplify built state-of-the-art graphical user interface (GUI). provides several features that facilitate rapid coding, support team design, provide designers with high degree control over floorplanning process (see Figure Amplify's
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Contributed Article Amplify Enables Advanced Programmable Design, continued from page Logic Replication Applying automatic replication during optimization traditionally effective means manage high fan-out during synthesis. Amplify takes replication concept step further performing automatic replication based fan-out timing, also providing flexibility manually replicating design instances through GUI. Powerful Amplify algorithms allow designer-controlled module, register, gate-level replication. Such replication minimizes critical path delay, even when critical logic spread across device. Tunneling Automatic tunneling uses boundary optimization techniques resolve detailed timing issues. Region assignments Amplify considered soft when negative slack present circuit logic migrate across region boundaries (tunneling) improve timing along given path. Such migration reduce interconnect delay improve speed. Tunneling employed when positive slack determined along given path design. Therefore, tunneling performed needed improve timing. Time Budgeting Automatic time budgeting across hierarchical design blocks eliminates need physically constrain entire design. ability create physical constraints only part design saves time focuses physical optimization most critical path. same time, remaining logic regionally grouped with critical path. This allows place-and-route create most direct routes minimize delay. most cases, provide benefit netlist synthesized specifically timing physical constraints. Some these options described below: Overestimating physical effects producing overly conservative design obviously more costly fails take full advantage device resources. Employing ASIC synthesis tools programmable designs does work because they lack sufficient knowledge programmable device architectures. Programmable devices have substantially different interconnect architectures from their ASIC counterparts, making ASIC synthesis ASIC interconnect models inadequate designing with advanced programmable devices. Back-annotation flow does create placement information drive placeand-route process; lack this placement information results reduced improvements design performance.
Performance Improvement
Actual customer results show that designs through Amplify exhibit which significant performance improvement over netlists synthesized with traditional logic synthesis. These results clearly demonstrate that benefits Amplify simply result forward annotating placement constraints. Amplify netlist differs significantly structure from that traditional synthesis alone optimizations that become possible when physical constraints present. Within first year introduction, more than companies have benefited from Amplify's unique technology. Table shows customer design data APEX devices.
Limitations Alternatives Amplify Physical Synthesis
Alternative approaches that occasionally considered place Amplify's physical synthesis unproductive ineffective
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Table Amplify Customer Design Data APEX Devices Device
EP20K400C-7 EP20K200E-1 EP20K200E-1 EP20K200E-1
Device Utilization
10.0 82.0 50.0 82.0
fMAX Improvement
11.0 30.0
Amplify Version
2.2.0 2.2.0 2.2.0 2.2.0
Altera Version
Quartus Quartus Quartus Quartus
Altera Publications
publications available from Altera Literature Services lit_req@altera.com. When ordering, please specify part number shown parentheses. On-line documents available Altera site http://www.altera.com. Altera Digital Library CD-Rom, Version (P-CD-ADL2001-02) APEX Devices Brochure (M-GB-APEXII-01) APEX Programmable Logic Device Family Data Sheet (A-DS-APEXII-01) Nios Getting Started User Guide (A-UG-NIOSKIT-01) Constellation Mapper/Demapper MegaCore Function User Guide (A-UG-IPMAPPER-01) Color Space Converter User Guide (A-UG-CSCONVERT-01) Copper Interconnects Altera Devices White Paper (M-WP-COPPER-01) Implementing OFDM with Altera Intellectual Property White Paper (M-WP-IPOFDM-01) 8b10b Encoder/Decoder MegaCore Function Data Sheet (ED8B10B) Mercury Gigabit Transceiver MegaCore Function Data Sheet (M1GXCVR) 119: Implementing High-Speed Applications with Altera (A-AN-119-01) 120: Using LVDS APEX 20KE Devices (A-AN-120-01) 125: Evaluating AMPP MegaCore Functions (A-AN-125-01) 138: LVDS Signaling Using APEX Device Pins (A-AN-138-01) 7000B Devices: Industry's Only Product-Term Device Support 1.8-V Interfaces (M-TB-075-01)
Introduction
have been data standard speeds, higher low-volta clock used formance increasin standard High-per pace with These keep devices. introduc backplan low-volta microprocessors, rates, these with memory, want highto interface Designer nary need flexible, devices. revolutio mable logic peripher buffers. Altera'shighest with program ndard standard density, nce, multi-sta offer highest necessary performa with 20KE devices solution industrie APEX mable logic compute program ication performa commun leader term standard lthe productmacrocel devices only MAX® 7000B (GTL+), devices Altera logic plus 7000B transceiv SSTL-3. support: Gunning standard 3.3-V support (SSTL-2) based devices logic terminat stub series supporte standard mable single device program With 7000B devices, standards, well buses multiple APEX 20KE eously support low-voltage memory different simultan low-volta with high-spe include 622.08 million interface standard data rates These simplify supports backplan standard into mable (LVDS), which signaling (Mbps). Program like LVDS integrate reducing space, circuitry bits second Dedicate saving board board design. logic devices (PLDs), nce. mable performa program improvin with usage, designin following guideline covers note provides devices This applicati standards Altera selectabl topics: ions Applicat Standard Standard Overview 7000B APEX 20KE Conditio Operatin Using LVDS Schemes Board Terminat
Current Software Versions
Quartus® version software latest release, available following operating systems: Microsoft Windows 2000 Microsoft Windows Microsoft Windows version higher Solaris version 2.6, 2.7, HP-UX version 10.2x 11.0 MAX+PLUS® software version 10.1 available following operating systems: Microsoft Windows 2000 Microsoft Windows Microsoft Windows version higher Solaris version 2.6, 2.7, HP-UX version 10.2x 11.0
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Using Mercury Devices High-Speed Communications
rapidly expanding telecommunications market produced wide variety possibilities programmable logic devices (PLDs). need fast network infrastructures increase, performance devices used this equipment must improve. bottleneck such systems data rates between devices, boards, boxes. Clock-data recovery (CDR), feature Mercurydevices, provides technology support these higher data rates. system. Traditionally, designs parallel architectures such peripheral component interconnect (PCI) backplane communications. However, data rates increase, these architectures cannot keep result, need higher performance created shift toward high-speed serial communications, differential standards such LVDS, LVPECL, PCML. Differential serial links enable faster data rates, require less routing space, exhibit higher noise immunity, consume less power. Mercury devices well-suited serial backplane applications. dedicated highspeed differential interface (HSDI) circuitry provides support differential standards LVDS, LVPECL, PCML. full flexibility designs, Mercury supports multiple data rates, enabling these devices communicate data rate from megabits second (Mbps) 1.25 gigabits second (Gbps) full coverage proprietary designs. addition, performance-optimized programmable logic provides option implement functions required complete design. combination these features Mercury devices allows them meet backplane specification, while their flexibility allows them effectively communicate with other Mercury devices with third-party ASSPs (see Figure
Mercury devices provide functionality 1.25 Gbps with performanceoptimized logic array, enabling designers address backplane line-side applications.
important metrics box's communications performance include: Line-side communications that allow talk with other boxes Backplane communications that allow different boards talk each other Device-to-device communications that allow different devices talk each other
Altera offers solution these challenges with Mercury device family. Mercury devices provide functionality 1.25 gigabits second (Gbps) with performance-optimized logic array, enabling designers address backplane applications line-side applications that comply with Gigabit Ethernet, synchronous optical network (SONET), Fibre Channel, myriad other standards. This feature allows Mercury devices address system solutions through both Mercury-to-Mercury communication effective interaction with common industry application-specific standard products (ASSPs). This article focuses backplane communications well Gigabit Ethernet SONET applications illustrates Mercury devices complete these systems.
Gigabit Ethernet Applications
accelerating growth local-area network (LAN) traffic generating continued demand higher-speed network technologies. Ethernet Fast Ethernet have been most widely used transport protocols network connections. However, today's cutting-edge systems have progressed towards even higher data rates, making Gigabit Ethernet ideal solution. Gigabit Ethernet backbone interconnect technology used between switches routers that employs same frame size
Communication across Backplane
Communication speed across backplane critical factor overall performance
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Technical Articles frame format predecessors (Ethernet Fast Ethernet), making easy transition, while providing gigabit bandwidth 1.25 Gbps data rates. standard data flow Gigabit Ethernet shown Figure This data flow requires several discrete steps. First, serializer/deserializer (SERDES) functions required accurately receive data reduce more manageable data rate. This process followed 8B/10B encoding/decoding functions ensure that clock transitions necessary incorporated into data stream. Additionally, another step required implement media access control (MAC) layer function Gigabit Ethernet. Altera introduces system-on-a-programmablechip (SOPC) solution this challenge with Mercury devices. Mercury devices provide SERDES functionality dedicated HSDI circuitry with CDR-enabled transceivers. Mercury Gigabit Transceiver MegaCore® function delivers byte alignment 8B/10B encoding/decoding functionality. Mercury devices also provide performanceoptimized programmable logic needed perform additional desired data processing. example, designer easily incorporate Gigabit Ethernet core from Altera's extensive intellectual property (IP) portfolio drop that into design, completing lowerlayer Gigabit Ethernet functions.
Figure Backplane Communications
Board Additional Logic Data Board Mercury Device
Additional Logic Data Board
Mercury Device
Backplane
Additional Logic Data
ASSP
multitude optical carrier (OC) levels each with associated speed, including: OC-3 Mbps, OC-12 Mbps, OC-48 Gbps. Altera's Mercury device family offers solution appropriate interpreting data some SONET/SDH applications. While dedicated HSDI circuitry provides required high-performance SERDES functionality, programmable nature Mercury devices allow designer interpret data level, whether OC-3, OC-12, OC-48, even OC-192 Gbps). With programmable core logic that built bandwidth, Mercury devices efficiently implement other necessary SONET/SDH continued page
SONET/SDH Applications
SONET/SDH standard optical telecommunications transport wide-area networks (WANs) metropolitan-area networks (MANs). SONET/SDH defines
Figure Gigabit Ethernet: Mercury Implementation
Mercury Device Fiber/ Copper SERDES Byte Alignment 8B/10B Encoder/ Decoder Upper Layer Functions
GMII
Notes Figure Physical media dependent: PMD. Gigabit media independent interface (GMII) optional.
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Technical Articles Using Mercury Devices High-Speed Communications, continued from page
Figure 3.SONET/SDH: Mercury Implementation
Mercury Device OC-N SERDES Frame Alignment Mulltiplexer/ Demultiplexer (Interleaver) Higher Layer Functions
Mapper
multiple data rate capability Mercury devices allows system designed Fast Ethernet today, transitioned Gigabit Ethernet future simply downloading programming file.
functions, level, within same device. Designers choose SONET/ Framer MegaCore function (which includes framer functions frame alignment), multiplexer demultiplexer, their proprietary design. Mappers also available Acell packet processing. Figure shows Mercury devices address these SONET/SDH requirements provide SOPC solution. Contact your local sales representative more details Mercury's applicability SONET/SDH system.
Mercury devices also offer limitless variety available only with programmable logic. Traditional implementations have constrained functionality forced designers lock specifications early design process. Mercury devices, meanwhile, allow designers change specifications anytime during design process, even updating design after completion. example, multiple data rate capability Mercury devices allows system designed Fast Ethernet today, transitioned Gigabit Ethernet future simply downloading programming file.
Implementing Programmable
Mercury devices provide seamless integration CDR-transceiver functionality with bandwidth-optimized programmable core logic. This high level integration saves valuable board space dramatically reduces board trace issues complexity. addition, Mercury devices provide channels CDR, giving designers ability combine multiple channels functionality into single Mercury device.
Conclusion
Whether application Gigabit Ethernet, SONET, proprietary backplane, Mercury devices address situation interface seamlessly with common industrystandard ASSPs. High-performance transceivers programmable logic core built bandwidth make Mercury devices ideal solution needs. Incorporating unmatched flexibility integration, Mercury devices SOPC solution high-speed communications.
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Implementing Drivers Devices
Discrete light-emitting diode (LED) driver devices common many system boards. design engineers integrate their discrete drivers into product-term based programmable logic devices (PLDs), such Altera's MAX® 7000AE, 7000B, 7000S, 3000A devices. choosing device with sufficient register capabilities, designers integrate single multiple driver devices along with required user logic into single device. common-anode LEDs. anode these types LEDs connected cathodes each connected output current-sinking driver device that sinks current required drive display. Current-regulating circuits implemented inside driver devices. turned when driver device's output pins pulled low. Many device manufacturers such Texas Instruments, National Semiconductor, Toshiba manufacture current-sinking driver devices. Table lists some common driver devices. More information about specific driver device found data sheets provided respective manufacturers.
Commercial Driver Devices
Current-sinking drivers more common than current-sourcing drivers. Many LEDs (particularly seven-segment display)
Table Common Current-Sinking Driver Devices Driver Device
TLC5905 driver with shift registers, data latch constant current circuitry TLC5910 driver with shift registers, data latch, on-chip phase-locked loop (PLL) gray scale generation constant current TLC5911 driver with shift registers, data latch, on-chip gray scale generation constant current TLC5921 driver with shift register, data latch current-sink constant current circuitry National DS8874 National DS8863 National DS8963 Toshiba TB62701AN Toshiba TB62705 Toshiba TB62706 Toshiba TB62707 16-bit constant current driver with shift register latch functions 8-bit constant current driver with shift register latch functions 16-bit constant current driver with shift register latch functions 8-bit constant current driver with latch functions MOS-to-LED 8-digit driver MOS-to-LED 8-digit driver 9-digit shift input driver
Implementing Drivers Devices
When device used driver device, current-limiting resistor must placed between cathode side LED's diode device. tied VCC, turned when device pulled low. most important element driver device amount current sink. Many applications call current sink specification 7000S, 7000A, 3000A devices sink current pin; 7000B devices sink pin. Table
Table Maximum Sink Current Devices Device
7000S 7000A 7000B 3000A
Package
Current (mA)
continued page
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Technical Articles Implementing Drivers Devices, continued from page
Figure TB62701AN Block Diagram
Out0 Out1 Out15
with enough register capabilities replace functionality entire driver device. emulate functioning TB62701AN device (see Figure need registers latches flipflops, input pins (clock, serial input, latch), output pins (the serial output outputs) total pins. extra input extra registers gates required implementing enable function.
R-Ext
I-Reg
Enable
Latch
Serial-In
Serial-Out
Clock
Even though single sink current, every simultaneously sink 7000B devices, each IOGND group concurrently sink current support multiple banks advanced standards. more information IOGND groupings, 7000B Programmable Logic Device Data Sheet.
integrate entire circuit just device, choose device that least pins registers. smallest 7000A device that satisfy requirements EPM7032AE device, with registers (macrocells) maximum user pins. However, necessary implement enable function, smallest 7000A device required would EPM7064AE device with registers (macrocells) maximum pins. external resistor current-regulating circuit have replaced with individual current-limiting resistors placed between cathode side LED's diodes pins device. Figure shows implementation driver using device. right-hand side Figure shows connection between discrete LEDs pins device, while left-hand side shows connection between seven-segment device. output pins device connected LEDs pulled turn LEDs.
Example
example, consider circuit containing TB62701AN device-Toshiba's 16-bit constant current driver with shift registers latch functions. implement driver device into device, important choose
Figure Using Device Implement Current-Sinking Driver
+3.3 Resistor Array +3.3 +3.3
Seven Segment Display
Device
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Conclusion
major advantage integrating drivers devices incorporate user logic into same device, eliminating device-to-device delays, saving valuable board space, reducing system cost. Figure
Figure Integration Both Logic User Logic
Device
User Logic
Driver
7000B: Only Product-Term Device that Interfaces with
More more systems processors memory functions, well programmable logic (e.g., APEX20KE devices) running these systems, product-term devices used control decode logic must capable interfacing with these 1.8-V devices. MAX® 7000B devices only product-term devices that capable supporting 1.8-V interfaces. Each bank 7000B device separate VCCIO than (see Figure When VCCIO pins within that bank interface with 1.8-V signals. Table shows 7000B devices provide support multiple-voltage levels. With VCCIO powered 7000B pins interface with 1.8-V signals, making only product-term device that interface with 1.8-V signals without voltage translation.
Figure 7000B Banks with Independent VCCIO
Programmable Banks with Individual VCCIO Individual Power Buses
Table 7000B MultiVolt Support VCCIO
Input Voltage
Output Voltage
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Altera's System Solutions Site: Gateway Networking, Wireless Telecom Solutions
Designers find solutions communications industry Altera® site. system solutions section provides specific system-level information that will designers developing their networking, wireless, telecom systems. Additionally, site includes: Clickable system block diagrams Block descriptions Intellectual property (IP) cores Design advantages Links related information example, wireless section site maps solution wideband-code division multiple access (W-CDMA) systems. this page, designers find clickable system block diagram W-CDMA transmitter (see Figure receiver. Other systems that
Figure W-CDMA Block Diagram
discussed systems solutions site include SONET/SDH, wireless networks, voice over Internet protocol (VoIP), multiprotocol label switching (MPLS) systems. Altera strives provide customers with most complete system-on-a-programmablechip (SOPC) solutions. Altera's SOPC solutions provide high-performance devices, software development tools, sophisticated intellectual property cores. Altera's SOPC solutions revolutionizing communications industry enabling Internet technology advances. Visit Altera site http://www.altera.com click System Solutions more information.
Embedded Processor Application Programmable Logic Application OVSF Code Generator Encoder Convolutional Encoder
FIlter
Interpolation
Data
Block Interleaver
Baseband Transmit Filter
Turbo Encoder Scrambling Code Cyclic redundancy code Digital analog convertor Numerically controlled oscillator OVSF Orthogonal variable spreading factor Root raised cosine FIlter Interpolation
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Altera Enhances Design Services Strategy Adding Certified Design Center Program
Altera recently revealed third component design services strategy launching Altera® Certified Design Center (CDC) partnership program. program brings world-leading system-on-a-chip (SOC) designers customers seeking integrate Altera's Excaliburembedded processor solutions, intellectual property (IP), their customized logic into single programmable platform. offering system-on-a-programmable-chip (SOPC) design services, program complements Northwest Logic, wholly-owned subsidiary Altera, that offers system-level design services with team Altera experts. Additional services provided with existing Altera Consultants Alliance Program (ACAP®), through which partners offer focused technical expertise. Figure Partners Altera program include Tality (the largest global provider product development outsourcing), Zaiq Technologies (based North America), Barco Silex, Camino GmbH, Excel Consultants, Plextek, Reflex Consulting, Sci-worx (based Europe). Altera chose partners based their ability serve customers throughout North America Europe, their strong track records SOC, multi-million gate designs, their expertise areas embedded software processor cores. example, Tality, BarcoSilex, Sci-worx members Approved Design Center program. This focus enables Altera partners support SOPC designers seamlessly deploy Altera's Excalibur embedded processor solutions, which combine logic, memory, NiosTM, ARM®-based, MIPS-basedprocessor core. ensure success program, Altera provides partners with in-depth training entire product line. Altera also granting partners right resell integrated
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Figure SOPC Design Services Solutions
Independent Consultants
ASIC Expertise (Altera Certified Design Center) Bringing Expertise World SOPC
Wholly Owned Altera Subsidiary
System-Level Expertise (Northwest Logic) SOPC Altera Technology Experts
Local Specialists (ACAP) Focused Technical Expertise
customers part design services offered. This benefit creates single point contact SOPC design, including integration Excalibur-based designs, shown Figure
Figure Customer Integration
Customer
Altera Packet Processing Certified Design Center
Intellectual Property
Excalibur Solutions
Custom Logic
more information, contact your local sales representative e-mail: cdc@altera.com.
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Discontinued Devices Update
increase operational efficiency manufacturing flow, Altera will discontinuing several products (see Table details). ensure that customers make lifetime buys, Altera will maintain shipments many these devices through 2003; Table shows last order last shipment dates discontinued devices. detailed list discontinued ordering codes, refer Altera® document listed reference column.
Table Discontinued Device Update Product Family
ClassicMAX® 7000 9000
Continued support Altera devices beyond phase period available through Rochester Electronics, extended after-market supplier. Please contact Rochester Electronics (508) 462-9332 more information. additional information discontinued devices, contact your local Altera representative.
Altera will maintain shipments many discontinued devices through 2003.
Device
Last Order Date
08/31/01 08/31/01 08/31/01 02/28/02 02/28/02 02/28/03 02/28/02 02/28/03
Last Shipment Date
02/28/02 02/28/02 02/28/02 08/31/02 08/31/02 08/31/03 08/31/02 08/31/03
Reference
Selected devices with pack option Selected devices with pack option Selected devices with carrier option Selected devices
0102 0103 0106
FLEX® 8000
Selected FLEX 8000 pin-grade array (PGA) packages Selected devices
0107
FLEX
Selected FLEX packages Selected FLEX ball-grid array (BGA) packages
0107 0107
FLEX 10KA FLEX 10KE APEX20K
Selected FLEX 10KA packages Selected FLEX 10KE packages Selected APEX packages
02/28/03 02/28/03 02/28/03
08/31/03 08/31/03 08/31/03
0107 0107 0107
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Answers more information ARM922T core, refer ARM922T Technical Reference Manual site http://www.arm.com.
Does EPC16 configuration device support fast passive parallel (8-bit parallel) configuration single APEXII, APEX, ACEXTM, FLEX® device? EPC16 devices support fast passive parallel programming exclusively APEX devices. This parallel programming mode sends bits parallel data APEX device clock cycle, thereby shortening configuration time. EPC16 device cannot configure APEX, ACEX, FLEX devices fast passive parallel mode. However, does support parallel programming multiple devices serial mode. example, eight DATA bits from EPC16 device connected each programmable logic device (PLD).
calculate power usage APEX 20KE general-purpose PLLs?
following equation used calculate current consumption single general-purpose mode: lcc_pll 0.176 (maximum output frequency) (mA) What benefit independent clock multiplication serializer/deserializer (SERDES) factors? True-LVDSimplementation, three frequencies need managed: clock frequency, SERDES first-in firstout (FIFO) frequency, logic array frequency. APEX 20KE devices, clock multiplication factor SERDES factors must same, since this factor used generate required SERDES FIFO logic array frequencies from LVDS input clock. This factor limits APEX 20KE input LVDS clock frequency single, specific frequency. With independent clock multiplication APEX Mercury devices, SERDES factor independent LVDS multiplication factor. Since clock multiplication factor independent SERDES factor, design simplified limiting designer single clock frequency. example, 622-Mbps data received with 311-MHz clock driven into logic array 8-bit, 77.75MHz bus. Independent clock multiplication also enables high-speed interfaces such RapidIO POS-PHY Level
utility called nios-elf-size available that will measure size SREC File. BASH, type: nios-elf-size *.srec display size file. Nios embedded soft core processor solution compatible with Altera's Mercurydevice family?
determine size Nios embedded processor SREC File (.srec)?
Yes. target Mercury device family with Nios embedded processor, version higher.
Altera's ARM®-based Excaliburembedded processor solutions, ARM922Tcore fully static? Yes. ARM922T core fully static. Therefore, stop clocks running within core indefinite period time without losing state processor. However, driving stripe with ARM-based Excalibur phase-locked loop (PLL), required lock time specified (Using Clocklock Clockboost feature APEX devices).
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APEX Frequently Asked Questions
response APEXII customer interest, Altera compiled list questions answers dedicated entirely APEX devices.
What APEX device family?
What densities will available what packages?
APEX devices range density from 16,640 89,280 logic elements (LEs). "Altera Device Selection Guide" page What speed grades will available APEX devices?
APEX device family nextgeneration APEX system-on-aprogrammable-chip (SOPC) solution from Altera. APEX look-up table (LUT)-based programmable logic devices (PLDs) include enhanced features that provide unmatched flexibility performance, enabling cuttingedge SOPC applications. Building successful APEX architecture, APEX device family marks breakthrough capability system performance that will, first time, place programmable logic directly data path high-performance communication applications.
APEX devices will available speed grades, with being fastest. naming convention APEX devices different than other Altera® LUT-based families? APEX nomenclature based rather than system gates. PLDs become more more complex, becomes increasingly difficult represent logic density, features, memory using single unit measure. LE-based nomenclature more accurately communicates logic capacity programmable logic devices, instead using gate counts that follow defined, industry standard. Disproportionate growth embedded memory logic elements leads unbalanced weighting gate enumeration ultimately misleading density representations. LE-based nomenclature will facilitate better device selection avoid confusion that could result from using gate-based nomenclature.
Where APEX devices?
coupling huge advancements made performance flexibility with fast, high-density core, APEX devices directly data path, offering short time-to-market customization benefits typically associated with PLDs. Historically, PLDs have been restricted control signal paths performance-intensive, high-bandwidth applications. inability receive, process, transmit large amounts high-speed data prevented PLDs from implementing functions that involved direct interaction processing high-speed data. high-speed APEX device core features place this device center highperformance networking communications technologies combine multiple functions onto single device, partition complex functions into multiple devices, complement application-specific standard products (ASSPs).
What process technology will used APEX devices?
APEX devices will manufactured 1.5-V, 0.15-µm, 8-layer-metal, all-layercopper process technology.
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much embedded memory available?
Each embedded system block (ESB) accommodates 4-Kbits memory, capable implementing first-in first-out (FIFO) functions, RAM, contentaddressable memory (CAM). With ESBs device, designers have over Mbits available storing anything from incoming high-speed data instruction codes soft processor cores. Each partitioned into equivalent blocks, effectively doubling number ESBs device, they seamlessly stitched together form larger, aggregate structures-all without degradation performance. APEX devices interface with highspeed external memory devices?
channel-to-channel clock-to-channel skew resolved, allowing single APEX device driven individual, highspeed sources. reduces printed circuit board design complexity eliminating need match trace delays between highspeed sources receiving APEX device. These delays attributed internal device characteristics such varying output timing characteristics external factors such varying trace lengths.
What physical layer transfer protocols will APEX devices support?
APEX devices include extensive support most popular physical layer transfer protocols: Host Processor Interfaces: RapidIO, HyperTransport, PCI-X PHY-Link Layer Interfaces: POS-PHY Level UTOPIA Flexbus Switch Fabric Interfaces: CSIX What functions will APEX devices support?
memory-intensive functions that require more than provided ESBs, APEX devices communicate with latest SRAM SDRAM technologies. 200-MHz ZBT, 334-Mbps DDR, 667-Mbps SRAMs supported interfaces, well 334-Mbps SDRAMs. This capability possible dedicated circuitry registers each element. many PLLs available APEX devices?
APEX devices have eight onboard PLLs. Four general-purpose PLLs available clock synthesis, each featuring taps that directly drive individual global clock net. These four general-purpose PLLs also drive external pins external system clock management. four True-LVDSPLLs each APEX device. pair PLLs drives LVDS receiver clock domains other pair drives LVDS transmit clock domains. LVDS transmit PLLs feature individual off-chip outputs.
Intellectual property (IP) function support APEX devices will extensive ranging from external memory device interfacing such zero-bus turnaround synchronous random access memory (ZBT SRAM) controllers advanced high-speed physical layer standards such RapidIO POS-PHY Level Additionally, existing MegaCore® Altera® Megafunction Partners Program (AMPPSM) megafunctions will fully supported APEX devices.
When will first APEX engineering samples available?
EP2A15 device scheduled available 672-pin FineLine BGApackage 2001.
What Clock-Data Synchronization (CDS) circuitry?
circuitry individually synchronizes each True-LVDS channel with single system clock. Unlimited amounts fixed,
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Altera Device Selection Guide
Current information Altera® ExcaliburTM, MercuryTM, APEXII, APEX 20K, ACEX1K, FLEX® 10K, FLEX 6000, MAX® 9000, 7000, 3000, configuration devices listed here. Information other Altera products located Altera Component Selector Guide. most up-todate information, Altera site http://www.altera.com. Some devices listed available. Contact Altera your local sales office latest device availability.
Excalibur Devices
DEVICE
EPXA1 EPXM1 EPXA4 EPXM4 EPXA10 EPXM10
GATES
100,000 100,000 400,000 400,000 1,000,000 1,000,000
PIN/PACKAGE OPTIONS
484-Pin BGA2, 672-Pin BGA2, 612-Pin 484-Pin BGA2, 672-Pin BGA2, 612-Pin
PINS
173, 178, 173, 178, 275, 360, 215, 275, 360, 215, 521, 521,
SUPPLY VOLTAGE
LOGIC ELEMENTS
4,160 4,160 16,640 16,640 38,400 38,400
BITS
53,248 53,248 212,992 212,992 327,680 327,680
EMBEDDED PROCESSOR
ARM922T 32-bit MIPS32 ARM922T 32-bit MIPS32 ARM922T 32-bit MIPS32
672-Pin BGA2, 1,020-Pin BGA2, 612-Pin BGA, 864-Pin 672-Pin BGA2, 1,020-Pin BGA2, 612-Pin BGA, 864-Pin
1,020-Pin BGA2, 864-Pin 1,020-Pin BGA2, 864-Pin
Mercury Devices
DEVICE
EP1M120 EP1M350
GATES
120,000 350,000
PIN/PACKAGE OPTIONS
484-Pin BGA1 780-Pin BGA1
PINS
SUPPLY VOLTAGE
CHANNELS
LOGIC ELEMENTS
4,800 14,400
BITS
49,152 114,688
APEX Devices
DEVICE
EP2A15 EP2A25 EP2A40 EP2A70 EP2A90
GATES
600,000 900.000 1,500,000 3,000,000 4,000,000
PIN/PACKAGE OPTIONS
724-Pin BGA, 672-Pin BGA2 724-Pin BGA, 672-Pin BGA2, 1,020-Pin BGA2 724-Pin BGA, 672-Pin BGA2, 1,020-Pin BGA2 724-Pin BGA, 1,508-Pin BGA2
PINS
1,060 1,140
SUPPLY VOLTAGE
LOGIC ELEMENTS
16,640 24,320 38,400 62,200 89,280
BITS
425,984 622,592 655,360 1,146,880 1,523,712
724-Pin BGA, 1,508-Pin BGA2
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APEX Devices
DEVICE
EP20K30E EP20K60E
GATES
30,000 60,000
PIN/PACKAGE OPTIONS
144-Pin TQFP, 144-Pin BGA2, 208-Pin PQFP, 324-Pin BGA2 144-Pin TQFP, 144-Pin BGA2, 208-Pin PQFP, 240-Pin PQFP,
PINS
128, 148, 151, 196, 101, 159, 189, 252, 151, 183, 246, 143, 175, 271, 144, 174, 277, 136, 168, 271, 376, 376, 136, 168, 271, 376, 376, 152, 408, 502, 488, 488, 488, 508,
SUPPLY VOLTAGE
LOGIC ELEMENTS
1,200 2,560
BITS
24,576 32,768
324-Pin BGA2, 356-Pin EP20K100 100,000 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 324-Pin BGA2, 356-Pin EP20K100E 100,000 144-Pin TQFP, 144-Pin BGA2, 208-Pin PQFP, 240-Pin PQFP, 324-Pin BGA2, 356-Pin EP20K160E 160,000 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA2 EP20K200 EP20K200E 200,000 200,000 208-Pin RQFP, 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA2 208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA2, 652-Pin BGA, 672-Pin BGA2 EP20K200C 200,000 208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA2, 652-Pin BGA, 672-Pin BGA2 EP20K300E EP20K400 EP20K400E EP20K400C EP20K600E EP20K600C EP20K1000E EP20K1000C EP20K1500E EP20K1500C 300,000 400,000 400,000 400,000 600,000 600,000 1,000,000 1,000,000 1,500,000 1,500,000 240-Pin RQFP, 652-Pin BGA, 672-Pin BGA2 652-Pin BGA, 672-Pin BGA2 652-Pin BGA, 672-Pin BGA2 652-Pin BGA, 672-Pin BGA2 652-Pin BGA, 672-Pin BGA2, 1,020-Pin BGA2 652-Pin BGA, 672-Pin BGA2, 1,020-Pin BGA2 652-Pin BGA, 672-Pin BGA2, 1,020-Pin BGA2 652-Pin BGA, 672-Pin BGA2, 1,020-Pin BGA2 652-Pin BGA, 1,020-Pin BGA2
4,160
53,248
4,160
53,248
6,400
81,920
8,320 8,320
106,496 106,496
8,320
106,496
11,520 16,640 16,640 16,640 24,320 24,320 38,400 38,400 51,840 51,840
147,456 212,992 212,992 212,992 311,296 311,296 327,680 327,680 442,368 442,368
488, 508,
488,
652-Pin BGA, 1,020-Pin BGA2
Configuration Devices APEX FLEX Devices
DEVICE
EPC1064 EPC1064V EPC1213 EPC14413 EPC13 EPC23 EPC44 EPC16
PIN/PACKAGE OPTIONS
8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC 8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC 20-Pin PLCC, 32-Pin TQFP 44-Pin PLCC, 44-Pin TQFP, 144-Pin BGA2 88-Pin BGA5
SUPPLY VOLTAGE
3.3/5.0 3.3/5.0 3.3/5.0 1.8/2.5
DESCRIPTION
64-Kbit serial configuration device designed configure FLEX 8000 devices 64-Kbit serial configuration device designed configure FLEX 8000 devices 213-Kbit serial configuration device designed configure FLEX 8000 devices 440-Kbit serial configuration device designed configure FLEX devices 1-Mbit serial configuration device designed configure APEX FLEX devices 1.6-Mbit serial configuration device designed configure SRAM-based devices 4-Mbit serial/parallel configuration device designed configure SRAM-based devices 16-Mbit serial/parallel configuration device designed configure SRAM-based devices
continued page
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ACEX Devices
DEVICE
EP1K10 EP1K30 EP1K50 EP1K100
GATES
10,000 30,000 50,000 100,000
PIN/PACKAGE OPTIONS
100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1, 484-Pin BGA2 208-Pin PQFP, 256-Pin BGA2, BGA2
PINS
120, 102, 147, 102, 147, 186, 147, 186,
SUPPLY VOLTAGE
LOGIC ELEMENTS
1,728 2,880 4,992
BITS
12,288 24,576 40,960 49,152
FLEX Devices
DEVICE
EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K30E EPF10K40 EPF10K50 EPF10K50V EPF10K50E EPF10K50S
GATES
10,000 10,000 20,000 30,000 30,000 30,000 40,000 50,000 50,000 50,000 50,000
PIN/PACKAGE OPTIONS
84-Pin PLCC, 144-Pin TQFP, 208-Pin PQFP 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2 144-Pin TQFP, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2, 356-Pin BGA, 484-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2, 484-Pin BGA2 208-Pin RQFP, 240-Pin RQFP 240-Pin RQFP, 356-Pin BGA, 403-Pin 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2, 484-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2, 356-Pin BGA, 484-Pin BGA2
PINS
102, 102, 134, 102, 147, 147, 189, 102, 147, 189, 191, 246, 102, 147, 176, 147, 189, 274, 189, 274, 102, 147, 189, 191, 102, 147, 189, 191, 220, 189, 189, 274, 369, 147, 189, 147, 189, 191, 274, 470, 186, 274, 369, 424, 470, 470, 182, 274, 369, 470, 470,
SUPPLY VOLTAGE
SPEED GRADE
LOGIC ELEMENTS
1,152 1,728 1,728 1,728 2,304 2,880 2,880 2,880 2,880
BITS
6,144 6,144 12,288 12,288 12,288 24,576 16,384 20,480 20,480 40,960 40,960
EPF10K70 EPF10K100 EPF10K100A EPF10K100B EPF10K100E
70,000 100,000 100,000 100,000 100,000
240-Pin RQFP, 503-Pin 503-Pin 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA2, 600-Pin 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2, 356-Pin BGA, 484-Pin BGA2
3,744 4,992 4,992 4,992 4,992
18,432 24,576 24,576 24,576 49,152
EPF10K130V EPF10K130E
130,000 130,000
599-Pin PGA, 600-Pin 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA2, 600-Pin 672-Pin BGA2 599-Pin PGA, 600-Pin BGA, 672-Pin BGA2 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA2, 600-Pin BGA, 672-Pin BGA2
6,656 6,656
32,768 65,536
EPF10K200E EPF10K200S
200,000 200,000
9,984 9,984
98,304 98,304
EPF10K250A
250,000
599-Pin PGA, 600-Pin
12,160
40,960
FLEX 6000 Devices
DEVICE
EPF6010A EPF6016 EPF6016A
GATES
10,000 16,000 16,000
PIN/PACKAGE OPTIONS
100-Pin TQFP, 144-Pin TQFP 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin 100-Pin TQFP, 100-Pin BGA2, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2
PINS
117, 171, 199, 117, 171, 117, 171, 199, 218,
SUPPLY VOLTAGE
SPEED GRADE
FLIPFLOPS
1,320 1,320
LOGIC ELEMENTS
1,320 1,320
EPF6024A
24,000
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA, 256-Pin BGA2
1,960
1,960
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7000 Devices
DEVICE
EPM7032S EPM7032AE EPM7032B EPM7064S EPM7064AE EPM7064B EPM7128S EPM7128AE
MACROCELLS
44-Pin PLCC/TQFP 44-Pin PLCC/TQFP
PIN/PACKAGE OPTIONS
PINS
SUPPLY VOLTAGE
SPEED GRADE
-10, -5,-7,-10
44-Pin PLCC/TQFP, 49-Pin BGA2 44-Pin PLCC/TQFP, 84-Pin PLCC, 100-Pin TQFP 44-Pin PLCC/TQFP, 49-Pin BGA2, 100-Pin TQFP, 100-Pin BGA1 44-Pin PLCC/TQFP, 49-Pin BGA2, 100-Pin TQFP, 100-Pin BGA1
100, 100, 100, 100, 120, 164, 120, 140, 164, 120, 176, 212, 120, 140, 176, 212,
84-Pin PLCC, 100-Pin PQFP/TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 100-Pin BGA1, 144-Pin TQFP, 169-Pin BGA2, 256-Pin BGA1 49-Pin BGA2, 100-Pin TQFP, 100-Pin BGA1, 144-Pin TQFP, 169-Pin BGA2, 256-Pin BGA1
EPM7128B
EPM7160S EPM7192S EPM7256S EPM7256AE EPM7256B EPM7512AE EPM7512B
84-Pin PLCC, 100-Pin TQFP, 160-Pin PQFP 160-Pin PQFP 208-Pin PQFP 100-Pin TQFP, 100-Pin BGA1, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1 100-Pin TQFP, 144-Pin TQFP, 169-Pin BGA2, 208-Pin PQFP, 256-Pin BGA1 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1, 256-Pin
-10, -10, -10,
144-Pin TQFP, 169-Pin BGA2, 208-Pin PQFP, 256-Pin BGA1, 256-Pin
3000 Devices
DEVICE
EPM3032A EPM3064A EPM3128A EPM3256A
MACROCELLS
44-Pin PLCC/TQFP
PIN/PACKAGE OPTIONS
PINS
116,
SUPPLY VOLTAGE
SPEED GRADE
44-Pin PLCC/TQFP, 100-Pin TQFP 100-Pin TQFP, 144-Pin TQFP 144-Pin TQFP, 208-Pin PQFP
9000 Devices
DEVICE
EPM9320A EPM9320 EPM9400 EPM9480 EPM9560A EPM9560
MACROCELLS
PIN/PACKAGE OPTIONS
84-Pin PLCC, 208-Pin RQFP, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 280-Pin PGA, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP, 356-Pin
PINS
132, 132, 139, 146, 153, 191, 153, 191,
SUPPLY VOLTAGE
SPEED GRADE
-15, -15, -15, -15,
Notes Tables: Preliminary. Contact Altera latest information. This package space-saving FineLine package. This device programmed user operate either This device programmed user operate either This package space-saving Ultra FineLine package, Altera's 0.8-mm pitch package.
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