2-Bank 524,288 Word SYNCHRONOUS DYNAMIC This version Sep.1999

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2-Bank 524,288 Word SYNCHRONOUS DYNAMIC This version Sep.1999

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MSM56V16160F
2-Bank 524,288 Word SYNCHRONOUS DYNAMIC
This version Sep.1999
DESCRIPTION
MSM56V16160F 2-Bank 524,288-word Synchronous dynamic RAM, fabricated OKI's CMOS silicon-gate process technology. device operates 3.3V. inputs outputs LVTTL compatible.
FEATURES
Silicon gate quadruple polysilicon CMOS 1-transistor memory cell 2-bank 524,288-word 16bit configuration 3.3V power supply 0.3V tolerance Input Output Refresh LVTTL compatible LVTTL compatible 4096 cycles/64
Programmable data transfer mode Latency (1,2,3) Burst Length (1,2,4,8,Full page) Data scramble (sequential interleave)
auto-refresh, Self-refresh capability Package: 50-pin 400mil plastic TSOP (Type (TSOPII50-P-400-0.80-K) (Product MSM56V16160F-xxTS-K) indicates speed rank.
PRODUCT FAMILY
Family MSM56V16160F-8 MSM56V16160F-10 Max. Frequency 125MHz 100MHz Access Time (Max.) tAC2 tAC3
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MSM56V16160F
CONFIGRATION (TOP VIEW)
VSSQ DQ16 DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 VCCQ UDQM
VCCQ VSSQ VCCQ LDQM
50-Pin Plastic TSOP (II) Type)
Name A0-A10
Function System Clock Chip Select Clock Enable Address Bank Select Address Address Strobe Column Address Strobe Write Enable
Name UDQM, LDQM VCCQ VSSQ
Function Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground (0V) Data Output Power Supply (3.3V) Data Output Ground (0V) Connection
Note:
same power supply voltage must provided every VCCQ pin. same voltage level must provided every VSSQ pin.
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MSM56V16160F
DESCRIPTION
Fetches inputs edge. Disables enables device operation asserting deactivating inputs except CLK, CKE, UDQM LDQM. Masks system clock deactivate subsequent operation. deactivated, system clock will masked that subsequent operation deactivated. should asserted least cycle prior command. column multiplexed. address RA10 Column Address Slects bank activated during address latch time selects bank precharge read/write during column address latch time. A11="L" Bank A11="H" Bank Functionality depends combination. details, function truth table. Masks read data clocks later when UDQM LDQM edge clock signal. Masks write data same clock when UDQM LDQM edge clock signal. UDQM controls upper byte LDQM controls lower byte. Data inputs/outputs multiplexed same pin.
Address
UDQM, LDQM
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MSM56V16160F
BLOCK DIAGRAM
UDQM LDQM
Latency Burst Controller Controller
Timing Register
Programing Register
Bank Controller
Internal Col. Address Counter
Input Data Register Column Address Buffers Column Decoders
Input Buffers
Sense Amplifiers Internal Address Counter
Read Data Register
Output Buffers
DQ16
Decoders
Word Drivers
Memory Cells
Address Buffers
Decoders
Word Drivers
Memory Cells
Sense Amplifiers
Column Decoders
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MSM56V16160F
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Voltages referenced VSS)
Parameter Voltage Relative Supply Voltage Storage Temperature Power Dissipation Short Circuit Current Operating Temperature Symbol VIN, VOUT VCC, VCCQ Tstg Topr 25°C Rating -0.5 -0.5 Unit
Recommended Operating Conditions
(Voltages referenced
Parameter Power Supply Voltage Input High Voltage Input Voltage Symbol VCC, VCCQ Min. -0.3 Typ. Max. Unit
Capacitance
(VBIAS 1.4V, 25°C, 1MHz)
Parameter Input Capacitance (CLK) Input Capacitance (RAS, CAS, CKE, UDQM, LDQM, A0-A11) Input/Output Capacitance (DQ1-DQ16) Symbol CCLK COUT Min. Max. Unit
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MSM56V16160F
Characteristics
Condition Parameter Output High Voltage Output Voltage Input Leakage Current Input Leakage Current Symbol Bank Bank Active Others -2.0mA 2.0mA MSM56V16160 F-10 Unit Note
ICC1 Average power supply current (Operating)
tCC=min. tRC=min. Burst
ICC1D
tCC=min. =min. Both Banks Active tRRD=min. Burst Both Banks tCC=min. Precharge Both Banks tCC=min. Active Bank Active
Power supply current (Standby) Average power supply current (Clock Suspension) Average power supply current (Active Standby Power supply current (Burst) Power supply current (Auto-Refresh) Average power supply current (Self-Refresh) Average power supply current (Power Down)
ICC2
ICC3S
ICC3
tCC=min.
ICC4
Both Banks tCC=min. Active Bank Active tCC=min. tRC=min.
ICC5
ICC6
Both Banks tCC=min. Precharge Both Banks tCC=min. Precharge
ICC7
Notes:
Measured with outputs open. address data changed once left unchanged during cycle. address data changed once left unchanged during cycles.
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MSM56V16160F
Mode Address Keys
Latency Reserved Reserved Reserved Reserved Reserved Burst Type Sequential Interleave Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Notes: should stay during mode cycle. POWER SEQUENCE With inputs state, turn power supply start system clock. After voltage reached specified level, pause 200ms more with input kept state. Issue precharge bank command. Apply auto-refresh eight more times. Enter mode register setting command.
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MSM56V16160F
Characteristic (1/2)
Note
MSM56V16160 Parameter Symbol Min. Clock Cycles Time Access Time from Clock Clock High Pulse Time Clock Pulse Time Input Setup Time Input Hold Time Output Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock Cycle Time Precharge Time Active Time Delay Time Write Recovery Time Bank Active Delay Time Refresh Time Power-down Exit setup Time Input Level Transition Time Delay Time(Min.) Clock Disable Time from Data Output High Impedance Time from UDQM, LDQM Data Input Mask Time from UDQM, LDQM Data Input Mask Time from Write Command tOLZ tOHZ tRAS tRCD tRRD tREF tPDE lCCD lCKE lDOZ lDOD lDWD tSI+1CLK Max.
F-10 Min. tSI+1CLK
Unit Max. Cycle Cycle Cycle Cycle Cycle
Note
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MSM56V16160F
Characteristic (2/2)
Note
MSM56V16160 Parameter Symbol Min. Data Output High Impedance Time from Precharge Command Active Command Input Time from Mode Register Command Input (Min.) Write Command Input Time from Output lROH lMRD lOWD Max. Min. F-10 Max. Cycle Cycle Unit Note
Cycle
Notes:
measurements assume that 1ns. reference level timing input signals 1.4V. Output load.
Z=50W Output 50pF (External Load)
access time defined 1.5V. longer than 1ns, then reference level timing input signals VIL.
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MSM56V16160F
TIMING WAVEFORM
Read Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4
tRCD
ADDR
UDQM, LDQM
Active Read Command
tOHZ
Precharge Command
Active Write Command
Precharge Command
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MSM56V16160F
Single Read-Write-Read Cycle (Same Page) @CAS Latency=2, Burst Length=4
High
ICCD
ADDR
tOHZ
tOLZ lOWD
UDQM, LDQM
Active Read Command Write Command Precharge Command Read Command
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MSM56V16160F
*Notes When "High" clock transition from "Low" "High", inputs except CKE, UDQM LDQM invalid. When issuing active, read write command, bank selected A11. Active, read write Bank Bank
auto precharge function enabled disabled input when read write command issued. Operation After burst, bank holds idle status. After burst, bank precharged automatically. After burst, bank holds idle status. After burst, bank precharged automatically.
When issuing precharge command, bank precharged selected inputs. Operation Bank precharged. Bank precharged. Both banks precharged.
input data write command latched same clock (Write latency output forced high impedance (1CLK+tOHZ) after UDQM, LDQM entry.
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MSM56V16160F
Page Read Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4
High
Bank Active
ICCD
ADDR
lOWD
UDQM, LDQM
Read Command Read Command
*Note
*Note
Write Command Precharge Command Write Command
*Notes:
write data before burst read ends, UDQM LDQM should asserted three cycles prior write command avoid contention. assert precharge before burst write ends, wait after last write data input. Input data during precharge input cycle will masked internally.
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MSM56V16160F
Read Write Cycle with Auto Precharge Burst Length=4
High
tRRD
ADDR
Latency=1 UDQM, LDQM Latency=2 UDQM, LDQM Latency=3 UDQM, LDQM
Active (A-Bank) Active (B-Bank) Bank Read with Auto Precharge
A-Bank Precharge Start
A-Bank Precharge Start
A-Bank Precharge Start
Bank Write with Auto Precharge
Bank Precharge Start Point
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MSM56V16160F
Bank Interleave Random Read Cycle @CAS Latency Burst Length
High
tRRD
ADDR
UDQM, LDQM
Active (A-Bank) Read Command (A-Bank) Active (B-Bank) Read Command (B-Bank) Active (A-Bank) Read Command (A-Bank)
Precharge Command (A-Bank)
Precharge Command (B-Bank)
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MSM56V16160F
Bank Interleave Random Write Cycle @CAS Latency Burst Length
High
ADDR
UDQM, LDQM
Active (A-Bank) Active (B-Bank) Write Command (A-Bank) Precharge Command Write Command (A-Bank) (B-Bank) Active (A-Bank) Write Command (A-Bank) Precharge Command (A-Bank)
Precharge Command (B-Bank)
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MSM56V16160F
Bank Interleave Page Read Cycle @CAS Latency Burst Length
*Note
High
ADDR
IROH
UDQM, LDQM
Active (A-Bank) Read Command (A-Bank) Active (B-Bank) Read Command (B-Bank) Read Command (B-Bank) Read Command (A-Bank) Read Command (A-Bank) Precharge Command (A-Bank)
*Note:
ignored when RAS, high same cycle.
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MSM56V16160F
Bank Interleave Page Write Cycle @CAS Latency Burst Length=4
High
ADDR
UDQM, LDQM
Active Active (A-Bank) Write Command (B-Bank) Write Command (B-Bank) (A-Bank) Write Command Write Command (B-Bank) Precharge Command (A-Bank) (Both Bank)
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MSM56V16160F
Bank Interleave Random Read/Write Cycle @CAS Latency Burst Length
High
ADDR
UDQM, LDQM
Active (A-Bank) Read Command (A-Bank) Active (B-Bank) Precharge Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) Active (A-Bank)
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MSM56V16160F
Bank Interleave Page Read/Write Cycle @CAS Latency Burst Length
High
ADDR
UDQM, LDQM
Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank)
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MSM56V16160F
Clock Suspension Operation Cycle @CAS Latency Burst Length
*Note *Note
ADDR
DQ0-7
*Note
*Note
tOHZ
*Note
tOHZ
DQ8-15
UDQM
*Note
LDQM
Active Read CLOCK Suspension Read Read Command Read Write CLOCK Suspension Write
Read Command
Write Command
*Notes:
When Clock Suspension asserted, next clock cycle ignored. When LDQM UDQM asserted, read data after clock cycles masked. When LDQM UDQM asserted, write data same clock cycle masked. When LDQM High, input/output data DQ0-7 masked. When UDQM High, input/output data DQ8-15 masked.
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MSM56V16160F
Read Write Cycle (Same Bank) @CAS Latency Burst Length
*Note
tRCD
ADDR
UDQM, LDQM
Active Read Command Write Command Precharge Command
*Note:
Case latency READ interrupted WRITE. minimum command interval [burst length cycles. UDQM LDQM must high least clocks prior write command.
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MSM56V16160F
Read Interruption Precharge Command @Burst Length
High
ADDR
Latency=1 UDQM, LDQM Latency=2 UDQM, LDQM Latency=3 UDQM, LDQM
Active Read Command Precharge Command
*Note
lROH
*Note
lROH
*Note
lROH
*Notes:
When latency precharge asserted before burst read ends, then read data will output after next clock cycle precharge command. When latency precharge asserted before burst read ends, then read data will output after second clock cycle precharge command. When latency precharge asserted before burst read ends, then read data will output after second clock cycle precharge command.
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MSM56V16160F
Burst Stop Command @Burst Length
High
ADDR
Latency=1 UDQM, LDQM Latency=2 UDQM, LDQM Latency=3 UDQM, LDQM
Read Command Burst Stop Command Write Command Burst Stop Command
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MSM56V16160F
Power Down Mode @CAS Latency Burst Length
tPDE *Note
*Note
tREF (min.)
ADDR
UDQM, LDQM
Power-down Entry Power-down Exit Active Clock Suspension Entry
Read Command Clock Suspension Exit Precharge Command
*Notes:
When both banks precharge state, low, then MSM56V16160F enters power-down mode maintains mode while low. release circuit from power-down mode, high longer than (tSI 1CLK).
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MSM56V16160F
Self Refresh Cycle
ADDR
UDQM, LDQM
Self Refresh Entry
Self Refresh Exit
Active
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MSM56V16160F
Mode Register Cycle
Auto Refresh Cycle
High
High
lMRD
ADDR
UDQM, LDQM
Command Auto Refresh Auto Refresh
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MSM56V16160F
FUNCTION TRUTH TABLE (Table (1/2)
Current State Idle
ADDR Code ILLEGAL ILLEGAL Active
Action
Auto-Refresh Self-Refresh Mode Register Write Read Write ILLEGAL Precharge ILLEGAL (Continue Active after Burst ends) (Continue Active after Burst ends) Term Burst Active Term Burst, start Burst Read Term Burst, start Burst Write ILLEGAL Term Burst, execute Precharge ILLEGAL (Continue Active after Burst ends) (Continue Active after Burst ends) Term Burst Active Term Burst, start Burst Read Term Burst, start Burst Write ILLEGAL Term Burst, execute Precharge ILLEGAL (Continue Burst enter Precharge) (Continue Burst enter Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Continue Burst enter Precharge) (Continue Burst enter Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Active
Read
Write
Read with Auto Precharge
Write with Auto Precharge
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MSM56V16160F
FUNCTION TRUTH TABLE (Table (2/2)
Current State Precharge
ADDR Idle after Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Action
Write Recovery
Active
Active after tRCD Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Refresh
Mode Register Access
ABBREVIATIONS Address Column Address
Bank Address Auto Precharge
OPeration command
*Notes inputs enabled when high least cycle prior inputs. Illegal bank specified state, legal some cases depending state bank selection. Satisfy timing lCCD prevent contention. bank precharging idle state. Precharges activated bank A10. Illegal bank idle.
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MSM56V16160F
FUNCTION TRUTH TABLE (Table
Current State Self Refresh CKEn-1 Power Down Banks Idle (ABI) State Other than Listed Above CKEn ADDR INVALID Exit Self Refresh Exit Self Refresh ILLEGAL ILLEGAL ILLEGAL (Maintain Self Refresh) INVALID Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL (Continue power down mode) Refer Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL Refer Operations Table Begin Clock Suspend Next Cycle Enable Clock Next Cycle Continue Clock Suspension Action
*Notes Power-down self-refresh entered only when banks idle state.
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NOTICE
information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit assembly designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited to:traffic control, automotive, safety, aerospace, nuclear power control, medical, including lift support maintenance. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents contained herein reprinted reproduced without prior permission.
Copyright 1997 ELECTRIC INDUSTRY CO.,LTD.

2-Bank 524,288 Word SYNCHRONOUS DYNAMIC This version Sep.1999

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