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Semiconductor MSC1212-01 48-Bit Grid/Anode Driver This versi


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E2C0021-27-Y3 Semiconductor
Semiconductor MSC1212-01
48-Bit Grid/Anode Driver
This version: Nov. 1997 MSC1212-01 Previous version: Jul. 1996
GENERAL DESCRIPTION
MSC1212-01 driver implemented BiCMOS technology. circuit consists 48-bit shift register 48-bit latch; they control display data, which output from display drivers. Since 64-pin plastic package used, display unit size reduced.
FEATURES
Logic supply voltage (VCC) Driver supply voltage (VDISP) Operating temperature range Driver output current +105°C IO2-1 (for only driver state) IO2-2 (total current drivers state) IO2-3
Built-in 48-bit output Driver (with latch) Built-in 48-bit shift register Clock frequency Package: 64-pin plastic (QFP64-P-1414-0.80-BK) (Product name: MSC1212-01GS-BK)
1/11
Semiconductor
MSC1212-01
BLOCK DIAGRAM
VDISP
48-BIT LATCH HVO48 DOUT 48-BIT L-GND D-GND PO48
2/11
Semiconductor
CONFIGURATION (TOP VIEW)
MSC1212-01
HVO1 VDISP D-GND L-GND DOUT D-GND VDISP
No-connection 64-Pin Plastic
3/11
Semiconductor
MSC1212-01
INPUT OUTPUT CONFIGURATION
Schematic Diagrams Logic Portion Input Circuit
VDISP
INPUT
Schematic Diagrams Logic Portion Input Schematic Diagrams Logic Portion Input Circuit (Pull-down) Circuit (Pull-up)
VDISP
VDISP
INPUT
INPUT
Schematic Diagrams Logic Portion Output Schematic Diagrams Driver Output Circuit Circuit
VDISP VDISP
OUTPUT
OUTPUT
4/11
Semiconductor
MSC1212-01
DESCRIPTION
Function Driver Output Driver Power Supply Logic Power Supply Driver Logic Data Input Symbol HVO1 HVO48 VDISP D-GND L-GND Power supply pins driver circuit. Both should connected externally. Power supply logic. pins driver circuit. Both should connected externally. logic circuit. Input without pull-up pull-down resistor. Input shift register. Display data input synchronized with clock signal. (positive logic) Input without pull-up pull-down resistor. Clock Input Data shift register shifted from stage next application each clock rising edge. Input without pull-up pull-down resistor. Latch Strobe Input When level, latch shunted shift register output becomes lacth output. When level, lacth holds shift register output just bafore goes level. Clear input with pull-up resistor. Normally Clear Input level. this condition, driver output changes according latch output level. When "H", driver output pins fixed "L". Test input with pull-down resistor. Normally level, here, CL="H", then driver output changes Test Input according latch output level. when level, driver output fixed test. Data Output DOUT Serial output shift register. Description Driver output pins, applicable each shift register.
5/11
Semiconductor
MSC1212-01
ABSOLUTE MAXIMUM RATINGS
Parameter Logic Supply Voltage Input Voltage Data Output Voltage Power Dissipation Thermal Resistance Storage Temperature Driver Supply Voltage Symbol VDISP Rj-a TSTG Condition Applicable input pins Applicable data output Applicable driver output 25°C Rating -0.3 +6.5 -0.3 -0.3 +0.3 -0.3 +0.3 -0.3 VDISP +0.3 +150 Unit °C/W
Driver Output Voltage
Maximum supply voltage with respect L-GND D-GND Catastrophic breakdown occur applied voltage more than rating. Thermal resistance package (between junction atmosphere) junction temperature (Tj) given following formula should exceed 150°C. Rj-a maximum power dissipation)
6/11
Semiconductor
MSC1212-01
RECOMMENDED OPERATING CONDITIONS
Parameter Logic Supply Voltage Driver Supply Voltage High Level Input Voltage Level Input Voltage Logic Output Current Driver High Level Output Current Driver High Level Output Current Driver Level Output Current Frequency Data Setup Time Data Hold Time Pulse Width Pulse Width Pulse Width Pulse Width CLK-LS Delay Time LS-CLK Delay Time LS-CHG Delay Time LS-CL Delay Time Operating Temperature Symbol VDISP IO2-1 IO2-2 IO2-3 fCLK tWLS tWCHG tWCL tWCLK tDCLK-LS tWLS-CLK tWLS-CHG tWLS-CL Condition
Applicable logic supply voltage Applicable driver supply voltage
Min. -0.1
Max.
Unit
Applicable input pins Applicable input pins Applicable DOUT Only driver state Total current driver outputs state Applicable driver output pins Timing Diagram Timing Diagram Timing Diagram Timing Diagram Timing Diagram Timing Diagram Timing Diagram Timing Diagram Timing Diagram Timing Diagram Timing Diagram
7/11
Semiconductor
MSC1212-01
ELECTRICAL CHARACTERISTICS
Characteristics
(VCC VDISP +105°C) Parameter Logic Power Supply Current Driver Power Supply Current High Level Input Threshold Voltage Level Input Threshold Voltage Hysteresis Voltage High Level Input Current Level Input Current High Level Data Output Current Level Data Output Current Driver High Level Output Current Driver Level Output Current Voltage Difference Between Pins IOL1 IOH2 IOL2 VGND Symbol ICC1 ICC2 IDISP IIH1 IIH2 IIL1 IIL2 IOH1 Load Load input pins input pins input pins Input pins except Input pins except Condition fCLK fCLK Min. -600 -0.1 -0.1 Typ. 2.75 3.25 1.75 2.25 Max. -100 Unit
VCC-VOH1 VOL1 Only driver state VDISP-VOH2 VOL2 Voltage difference between D-GND L-GND
D-GND L-GND connected internally. Therefore, voltage between D-GND L-GND same level connecting both pins externally. Characteristics
(VCC VDISP +105°C) Parameter CLK-Dout Delay Time Delay Time High Transit Time High Delay Time High Transit Time High Symbol tDLH tTLH tDHL tTHL Condition Timing Diagram Timing Diagram Timing Diagram Timing Diagram Timing Diagram Min. Typ. Max. Unit
8/11
tWCLK 1/fCLK
T1/2
T3/4
T47/48
T1/2
T3/4
TIMING DIAGRAM
Semiconductor
DOUT tDCLK-LS tDLS-CLK
tWLS tDLS-CHG tWCHG tWCHG
tDLS-CL tWCL tWCL
tDLH tDLH tDHL tDHL
(Others) tTLH tTLH tTHL tTHL
MSC1212-01
9/11
Semiconductor
MSC1212-01
FUNCTIONAL DESCRIPTION
Function Table
CLOCK PO46 PO47 PO48 DOUT
PO1k PO2k PO1k PO2k
PO3k PO45k PO46k PO47k PO47k PO3k PO45k PO47k PO47k PO47k HVOn
Level, High Level, Don't Care, Change
10/11
Semiconductor
MSC1212-01
PACKAGE DIMENSIONS
(Unit
QFP64-P-1414-0.80-BK
Mirror finish
Package material Lead frame material treatment Solder plate thickness Package weight
Epoxy resin alloy Solder plating more 0.87 TYP.
Notes Mounting Surface Mount Type Package SOP, QFP, TSOP, SOJ, (PLCC), surface mount type packages, which very susceptible heat reflow mounting humidity absorbed storage. Therefore, before perform reflow mounting, contact Oki's responsible sales person product name, package name, number, package code desired mounting conditions (reflow method, temperature times).
11/11

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