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Semiconductor ML9060 DUTY, 160-OUTPUT STATIC DRIVER This ver


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E2B0051-19-22 Semiconductor
Semiconductor ML9060
DUTY, 160-OUTPUT STATIC DRIVER
This version: Feb. 1999 ML9060
GENERAL DESCRIPTION
ML9060 consists 320-bit shift register, 320-bit data latch, sets drivers, common signal generator circuit. display data input serially shift register from DATA synchronization with CLOCK signal, stored data latch LOAD signal. display data stored data latch output drivers. maximum segments driven static display mode maximum segments driven directly duty display mode. possible select mode using internal oscillator circuit mode using external clock common signal generator circuit. ML9060 also outputs sync signal during duty display mode.
FEATURES
Logic power supply 5.5V Driving voltage Maximum number segments that driven: Static display mode segments Duty display mode segments Serial transfer clock max. microcontroller interface consists three signals DATA CLOCK LOAD oscillator circuit built which either external resistor internal resistor. Cascade connection several possible. Built-in common signal generator circuit. Built-in common output mid-level voltage generator circuit. Input turning segments available (SEG-TEST IN). Input turning segments available (BLANK IN). Gold bump chip Product name: ML9060DVWA
1/17
Semiconductor
ML9060
BLOCK DIAGRAM
SEG1 SEG2 VLCD
SEG160
Segment Drivers
1/2VLCD Generator Common Drivers SEG-TEST BLANK
SEG-TEST BLANK
DS01 DS02 DS0160 DSI1b DSI160b
Data Selector
DSI1a DSI160a
L01a
L0160a
L01b
L0160b
Data Latch
LI1a LI160a
Data Latch
LI1b LI160b
LOAD DATA
P01a P0160a P01b P0160b
LOAD
Shift Register CLOCK
Shift Register
DATA
CLOCK Timing Generator
OSC1 OSCR OSC2 SYNC SYNC 1/64 1/128
2/17
Semiconductor
ML9060
ABSOLUTE MAXIMUM RATINGS
Parameter Logic power supply voltage Driving voltage Input voltage Storage temperature Symbol Condition 25°C 25°C 25°C Rating -0.3 +6.5 GND-0.3 +0.3 +150 Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Logic power supply voltage Driving voltage Operating temperature Symbol Condition Range Unit
with VLCD Note: Never place short between output another output between output other pins (input pins, pins, power supply pins).
3/17
Semiconductor
ML9060
ELECTRICAL CHARACTERISTICS
Characteristics
(VDD 5.5V, VLCD 16V, +85°C) Parameter Input voltage Symbol VIH1 VIH2 VIL1 VIL2 Condition Min. 0.7VDD 0.8VDD Typ. Max. 0.3VDD 0.2VDD ±1.0 Unit Applicable DATA CLOCK LOAD SEG-TEST BLANK M/S, OSC1, SYNC SEG1 SEG160 DATA CLOCK Output voltage Logic LOAD VOHL1 -100mA 0.9VDD SEG-TEST BLANK SYNC VOHL2 Output voltage Common Segment Common -200mA 0.9VDD 1/2VLCD -0.15 1/2VLCD 1/2VLCD +0.15 OSC2 SEG1 SEG160 DATA CLOCK Output voltage Logic LOAD VOLL1 100mA 0.1VDD SEG-TEST BLANK SYNC VOLL2 Output resistance Segment Common RSEG RCOM 200mA 0.1VDD OSC2 SEG1 SEG160
Input voltage Input leakage current
Input leakage current Segment Common
VOHS VOHC
-30mA -150mA
VLCD-0.2 VLCD-0.2
VOMC ±150mA VOLS VOLC 30mA 150mA
"M": Middle level
4/17
Semiconductor
ML9060
Parameter
Symbol
Condition (Static) other input levels either Oscillator stopped load (1/2duty) other input levels either Oscillator stopped load (Static) other input levels either Oscillator stopped load (1/2duty) other input levels either Oscillator stopped load 5.5V (Static) OSC1 Open OSC2 connected OSCR Other inputs load 5.5V (1/2duty) OSC1 Open OSC2 connected OSCR Other inputs load 5.5V (Static) OSC1 Open OSC2 connected OSCR Other inputs load 5.5V (1/2duty) OSC1 Open OSC2 connected OSCR Other inputs load
Min.
Typ.
Max.
Unit
Applicable
IDDS1
IDDS2 Static supply current
ILCDS1
VLCD
ILCDS2
VLCD
IDD1
IDD2
Dynamic supply current
ILCD1
VLCD
ILCD2
VLCD
Applicable DATA LOAD SEG-TEST M/S, D/S, pins. Applicable CLOCK OSC1, BLANK pins. Applicable voltage drop when current flows into pin. power supply current consumption will determined finally sample evaluations. display data input alternately. 5/17
Semiconductor Switching Characteristics
ML9060
(VDD 5.5V, VLCD 16V, +85°C) Parameter Clock frequency (external input) Clock pulse width (external input) External clock frequency (internal oscillations) Internal clock frequency (with built-in oscillator) Data clock frequency Data clock pulse width Data setup time Data hold time CLOCK LOAD Period LOAD CLOCK Period LOAD Pulse width CLOCK DATA delay time fOSC1 Symbol fCP1 tWCP1 Condition clock input OSC1 pin. pins OSC2 OSCR left open. 120k connected between OSC1 OSC2. OSCR left open. OSC1 open. OSC2 fOSC2 OSCR shorted. tied level. fCP2 tWCP2 tWLD tPLH tPHL CL=15pF 12.8 20.5 OSC1, OSCR, OSC2 12.8 20.5 OSC1, OSC2 Min. Typ. Max. Unit Applicable
25.6 OSC1 OSC1
CLOCK CLOCK DATA CLOCK CLOCK LOAD LOAD CLOCK DATA CLOCK IN/OUT LOAD IN/OUT SEG-TEST IN/OUT BLANK IN/OUT SYNC inputs other than OSCR input
delay time
tDIO
load
SYNC delay time Input signal rise time Input signal fall time
tDCS
CL=15pF
specifications internal clock frequency external clock frequency will determined finally sample evaluations.
6/17
Semiconductor
ML9060
TIMING DIAGRAM
1/fCP1 tWCP1 OSC1 (External clock) tWCP1
DATA
tWCP2
tWCP2 tWLD
CLOCK
1/fCP2
LOAD
tPLH tPHL
DATA
CLOCK LOAD SEG-TEST BLANK CLOCK LOAD SEG-TEST BLANK input signals
tDIO tDIO
1/2VDD tDCS
1/2VDD tDCS 1/2VDD 1/2VDD
SYNC
7/17
Semiconductor
ML9060
FUNCTIONAL DESCRIPTION
ML9060 driver with internal shift register internal data latches capable driving displays segments either static mode duty mode. display data read into shift register serially from DATA rising edge CLOCK input signal. display data transferred internally data latches High level LOAD input signal output segments segment drivers this display data shift register output DATA synchronization with falling edge CLOCK input signal. display data should input sequence SEG160, SEG159, SEG2, SEG1 proper display data. Description Functions This input selecting either Master mode Slave mode. This goes into master mode when this High enters Slave mode when this Low. This input selecting either dynamic display mode duty mode input) static display mode mode input). Note that internal bias resistor made dynamic mode turned static mode (S). This input selecting whether external clock input mode, internal oscillation mode external oscillation mode. When this tied level, internal oscillation mode external oscillation used. When this tied level, external clock input used operation LSI. slave mode operation this LSI, input this will ignored. Hence, this slave mode. OSC1, OSCR, OSC2 These pins oscillator generating common signal. Master mode (M/S "H"): possible select from among three modes internal oscillation mode, external oscillation mode, external clock input mode. During static display operation mode, common signal with 1/128th frequency clock oscillator output pin. During duty dynamic display operation mode, common signal with 1/64th frequency clock oscillator output pin. Internal oscillation mode: "H", short pins OSCR OSC2, leave OSC1 open. External oscillation mode: "L", connect external resistor between pins OSC1 OSC2, leave OSCR open. External clock input mode: "L", leave open pins OSCR OSC2, input external clock signal OSC1.
8/17
Semiconductor
ML9060
Slave mode (M/S "L"): Leave open pins OSCR OSC2 connect OSC1 ML9060 which been master mode. common signal that input OSC1 will used internal common signal also output buffer from pin. This common signal output pin. Connect this OSC1 ML9060 that slave mode. During operation master mode (M/S "H") static display, common signal with 1/128th frequency oscillator output. During operation master mode (M/S "H") duty dynamic display, common signal with 1/64th frequency oscillator output. During operation slave mode (M/S "L"), common signal that input OSC1 output from this buffer. SYNC This common signal synchronization. This becomes synchronization signal output during operation master mode (M/S "H") duty dynamic display. This becomes synchronization signal input during operation slave mode "H") duty dynamic display. cascade operation duty display mode, connect SYNC pins ML9060 used together. During operation static display mode, this tied level inside Connect this either leave open. DATA This display data input pin. Input display data sequence SEG160, SEG159, SEG2, SEG1. segment turned when display data when "L". DATA This display data output pin. During static display mode operation, data 160th stage shift register output from this pin. During duty dynamic display mode, data 320th stage shift register output from this pin. CLOCK This input shift clock display data. display data that input DATA input serially shift register rising edge CLOCK signal. Also, display data shift register output from DATA falling edge CLOCK signal. CLOCK This output shift clock display data. shift clock signal that input CLOCK output buffer from this pin. LOAD This input display data load signal. display data shift register output such segment driver when this signal level. When this signal made "L", shift register isolated from segment drivers, display data shift register just before this goes retained data latches transfered segment drivers. 9/17
Semiconductor
ML9060
LOAD This output display data load signal. load signal that input LOAD output from this buffer. SEG-TEST This input making segments When this "H", segment outputs (SEG1 SEG160) become irrespective display data Blank signal. When this made "L", each segment outputs (SEG1 SEG160) become according display data. SEG-TEST This output making segments segment signal that input SEG-TEST output buffer. BLANK This input making segments OFF. When this "H", segment outputs (SEG1 SEG160) become irrespective display data. When this made "L", each segment outputs (SEG1 SEG160) becomes according display data. BLANK valid when segment signal "L". BLANK This output making segments OFF. segment signal that input BLANK output buffer. SEG1 SEG160 These signal outputs driving segments connected corresponding segment pins panel. During Static mode operation: SEGn output corresponds display data data latch display data data latch becomes invalid. segment condition, signal with phase opposite that signal output from these pins. segment condition, signal with phase identical that signal output from these pins. During duty dynamic display mode operation: SEGn output corresponds display data data latch when been selected display data data latch when been selected. segment display condition, signal opposite phase that selected output output from these pins. segment display condition, signal identical phase that selected output output from these pins. These outputs display connected common pins panel. During Static mode operation: both output signal with same phase that signal.
10/17
Semiconductor
ML9060
During duty dynamic display mode operation: change their states every cycle signal repeat selected non-selected modes always opposing each other phase. signal with same phase that signal output selected mode. voltage equal 1/2VLCD output non-selected mode. When selected mode (that non-selected mode), segment outputs (SEG1 SEG160) output signals corresponding display data data latch When selected mode (that non-selected mode), segment outputs (SEG1 SEG160) output signals corresponding display data data latch This power supply input logic circuits. VLCD This power supply input drivers. This ground circuits.
11/17
Semiconductor Segment Output Common Output Waveforms During duty display operation mode:
ML9060
SYNC Selected Selected Selected Selected
VLCD 1/2VLCD VLCD
1/2VLCD VLCD VLCD VLCD VLCD
SEGn
Data latch
Data latch
Data latch
Data latch
During static display operation mode:
VLCD
VLCD VLCD VLCD
SEGn
12/17
Semiconductor
ML9060
APPLICATION CIRCUIT EXAMPLES
When single ML9060 used Static display mode (internal oscillation mode)
Panel segments, static display
SEG1 SEG-TEST BLANK From controller LOAD DATA CLOCK OSC1 open OSC2
SEG160 open open
ML9060
SYNC
OSCR
When single ML9060 used duty dynamic display mode (external oscillation mode)
Panel segments, Duty dynamic display
SEG1 SEG-TEST BLANK From controller LOAD DATA CLOCK OSC1 OSC2
SEG160
ML9060
SYNC
open
OSCR open
13/17
Semiconductor Cascade Connection Static display mode (external clock input mode)
ML9060
Panel (160 segments)
SEG-TEST BLANK LOAD DATA CLOCK SYNC Static SEG-TEST BLANK LOAD DATA CLOCK SYNC open open
open SEG-TEST BLANK LOAD DATA CLOCK
From controller
SEG-TEST BLANK LOAD DATA CLOCK
ML9060
ML9060
open
OSC1 OSC2 OSCR open open
OSC1 OSC2 OSCR open open
External clock
Note: Take care about resistance capacitance wiring cascade connection.
Cascade Connection duty dynamic display mode (internal oscillation mode)
Panel (320 segments)
SEG-TEST BLANK LOAD DATA CLOCK SEG-TEST BLANK LOAD DATA CLOCK SYNC SEG-TEST BLANK LOAD DATA CLOCK duty dynamic display SEG-TEST BLANK LOAD DATA CLOCK SYNC open open
From controller
ML9060
ML9060
open
OSC1 OSC2 OSCR open
OSC1 OSC2 OSCR open open
Note: Take care about resistance capacitance wiring cascade connection.
14/17
Semiconductor
ML9060
CONFIGURATION
layout (Pattern side) Chip size Chip thickness Minimum bump pitch Bump size Bump height Bump height inside chip Bump hardness
14.50 1.48mm 625mm 30mm 80mm 80µm 15mm max. min. max. (HV: LOAD)
substrate chip should either connected level left open. Coordinates
name SYNC COMOUT VLCD VLCD VLCD
X-coordinate Y-coordinate
(mm) -6680 -6146 -5611 -5077 -4542 -4008 -3474 -2939 -2405 -1870 -1336 -802 -267 1336 1870 2405 2939 3474
(mm) -561 -561 -561 -561 -561 -561 -561 -561 -561 -561 -561 -561 -561 -561 -561 -561 -561 -561 -561 -561
name OSC2 OSCR OSC1 DATA CLOCK LOAD SEG-TEST BLANK COMA
X-coordinate Y-coordinate
(mm) 4008 4542 5077 5611 6146 6680 7121 7121 7121 7121 7121 7121 7121 7121 7121 7121 6680 6600 6520 6440
(mm) -561 -561 -561 -561 -561 -561 -360 -280 -200 -120
Connection 15/17
Semiconductor
ML9060
name SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44
X-coordinate Y-coordinate
(mm) 6360 6280 6200 6120 6040 5960 5880 5800 5720 5640 5560 5480 5400 5320 5240 5160 5080 5000 4920 4840 4760 4680 4600 4520 4440 4360 4280 4200 4120 4040 3960 3880 3800 3720 3640 3560 3480 3400 3320 3240 3160 3080 3000 2920 2840
(mm)
name SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89
X-coordinate Y-coordinate
(mm) 2760 2680 2600 2520 2440 2360 2280 2200 2120 2040 1960 1880 1800 1720 1640 1560 1480 1400 1320 1240 1160 1080 1000 -120 -200 -280 -360 -440 -520 -600 -680 -760
(mm)
16/17
Semiconductor
ML9060
name SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133 SEG134
X-coordinate Y-coordinate
(mm) -840 -920 -1000 -1080 -1160 -1240 -1320 -1400 -1480 -1560 -1640 -1720 -1800 -1880 -1960 -2040 -2120 -2200 -2280 -2360 -2440 -2520 -2600 -2680 -2760 -2840 -2920 -3000 -3080 -3160 -3240 -3320 -3400 -3480 -3560 -3640 -3720 -3800 -3880 -3960 -4040 -4120 -4200 -4280 -4360
(mm)
name SEG135 SEG136 SEG137 SEG138 SEG139 SEG140 SEG141 SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 SEG160 BLANKOUT SEG-TESTOUT LOADOUT CLOCKOUT DATAOUT
X-coordinate Y-coordinate
(mm) -4440 -4520 -4600 -4680 -4760 -4840 -4920 -5000 -5080 -5160 -5240 -5320 -5400 -5480 -5560 -5640 -5720 -5800 -5880 -5960 -6040 -6120 -6200 -6280 -6360 -6440 -6520 -6600 -6680 -7121 -7121 -7121 -7121 -7121 -7121 -7121 -7121 -7121 -7121
(mm) -120 -200 -280 -360
17/17
E2Y0002-29-11
NOTICE
information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents cotained herein reprinted reproduced without prior permission. MS-DOS registered trademark Microsoft Corporation.
Copyright 1999 Electric Industry Co., Ltd.
Printed Japan

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