Embedded Processor Data Sheet Publication 22529 Issue Date: 2000
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AMD-K6
Embedded Processor Data Sheet
Publication 22529 Issue Date: 2000
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2000 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, logo, AMD-K6, 3DNow!, combinations thereof, K86, Super7, trademarks; RISC86 registered trademark; Fusion service mark Advanced Micro Devices, Inc. trademark Pentium registered trademark Intel Corporation. Microsoft, Windows, Windows registered trademarks Microsoft Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
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AMD-K6TM-2E Processor Data Sheet
HAVE QUESTIONS, WE'RE HERE HELP YOU. customer service network includes U.S. offices, international offices, customer training center. Expert technical assistance available from worldwide staff field application engineers factory support staff answer E86family hardware software development questions. Frequently accessed numbers listed below. Additional contact information listed back this manual. AMD's site lists latest phone numbers. Technical Support Answers technical questions available online, through e-mail, telephone. AMD's home page www.amd.com follow Support link latest technical support phone numbers, software, Frequently Asked Questions. technical support questions products, send e-mail epd.support@amd.com Canada) euro.tech@amd.com Europe UK). also call Corporate Applications Hotline (800) 222-9323 44-(0) 1276-803-299 Support specific information products, access home page www.amd.com follow Embedded Processors link. These pages provide information upcoming product releases, overviews existing products, information product support tools, list technical documentation. Support tools include online benchmarking tools CodeKit software-tested source code example applications. Many technical documents available online form. Questions, requests, input concerning AMD's pages sent e-mail web.feedback@amd.com. Documentation Literature Support Data books, user's manuals, data sheets, application notes, product free with simple phone call. Internationally, contact your local sales office product literature. Toll-free U.S. Canada U.K. Europe hotline
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order literature: Web: U.S. Canada: (800) 222-9323 Third-Party Support FusionE86SM partners provide array products designed meet critical time-tomarket needs. Products solutions available include chipsets, emulators, hardware software debuggers, board-level products, software development tools, among others. site E86Family Products Development Tools order #21058, describe these solutions. addition, mature development tools applications platform widely available general marketplace.
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AMD-K6TM-2E Processor Data Sheet
Contents
Revision History. About this Data Sheet.xvii
Overview xvii
AMD-K6TM-2E Processor
AMD-K6TM-2E Embedded Processor Features Process Technology. Super7Platform Initiative AMD-K6TM-2E Processor Microarchitecture Overview Cache, Instruction Prefetch, Predecode Bits. Instruction Fetch Decode Centralized Scheduler Execution Units. Branch-Prediction Logic. Registers Model-Specific Registers (MSR) Memory Management Registers. Paging. Descriptors Gates Exceptions Interrupts Instructions Supported AMD-K6TM-2E Processor
Internal Architecture
Software Environment
Logic Symbol Diagram Signal Descriptions
5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 Signal Terminology. A20M# (Address Mask) A[31:3] (Address Bus). ADS# (Address Strobe) ADSC# (Address Strobe Copy) AHOLD (Address Hold) (Address Parity). APCHK# (Address Parity Check). BE[7:0]# (Byte Enables) BF[2:0] (Bus Frequency) BOFF# (Backoff) BRDY# (Burst Ready). BRDYC# (Burst Ready Copy) BREQ (Bus Request). CACHE# (Cacheable Access) (Clock) D/C# (Data/Code) D[63:0] (Data Bus). DP[7:0] (Data Parity). EADS# (External Address Strobe).
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5.21 5.22 5.23 5.24 5.25 5.26 5.27 5.28 5.29 5.30 5.31 5.32 5.33 5.34 5.35 5.36 5.37 5.38 5.39 5.40 5.41 5.42 5.43 5.44 5.45 5.46 5.47 5.48 5.49 5.50 5.51 5.52 5.53 5.54 5.55 5.56
EWBE# (External Write Buffer Empty) FERR# (Floating-Point Error) FLUSH# (Cache Flush) HIT# (Inquire Cycle Hit). HITM# (Inquire Cycle Modified Line). HLDA (Hold Acknowledge) HOLD (Bus Hold Request). IGNNE# (Ignore Numeric Exception). INIT (Initialization) INTR (Maskable Interrupt). (Invalidation Request) KEN# (Cache Enable). LOCK# (Bus Lock) M/IO# (Memory I/O) (Next Address). (Non-Maskable Interrupt) (Page Cache Disable). PCHK# (Parity Check) (Page Writethrough) RESET (Reset) RSVD (Reserved). SCYC (Split Cycle). SMI# (System Management Interrupt). SMIACT# (System Management Interrupt Active). STPCLK# (Stop Clock) (Test Clock). (Test Data Input) (Test Data Output). (Test Mode Select) TRST# (Test Reset). VCC2DET (VCC2 Detect) VCC2H/L# (VCC2 High/Low). W/R# (Write/Read) WB/WT# (Writeback Writethrough). Tables Type Cycle Definitions Timing Diagrams. States. Memory Reads Writes. Read Write Inquire Arbitration Cycles Special Cycles
Cycles
Power-On Configuration Initialization
Signals Sampled During Falling Transition RESET RESET Requirements State Processor After RESET.
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State Processor After INIT MESI States Data Cache Predecode Bits. Cache Operation Cache Disabling Flushing Cache-Line Fills Cache-Line Replacements. Write Allocate Prefetching Cache States Cache Coherency Writethrough Writeback Coherency States. A20M# Masking Cache Accesses EWBE# Control Memory Type Range Registers Memory-Range Restrictions Examples.
Cache Organization
8.10 8.11 8.12
Write Merge Buffer
Floating-Point Multimedia Execution Units
10.1 10.2 10.3 Floating-Point Execution Unit. Multimedia 3DNow!Execution Units Floating-Point MMXTM/3DNow!Instruction Compatibility. Operating Mode Default Register Values. State-Save Area. Revision Identifier. Base Address Halt Restart Slot Trap Doubleword Trap Restart Slot Exceptions, Interrupts, Debug SMM. Built-In Self-Test (BIST) Three-State Test Mode Boundary-Scan Test Access Port (TAP). Cache Inhibit. Debug Clock Control States Halt State. Stop Grant State. Stop Grant Inquire State. Stop Clock State.
System Management Mode (SMM)
11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8
Test Debug
12.1 12.2 12.3 12.4 12.5
Clock Control
13.1 13.2 13.3 13.4 13.5
Electrical Data
14.1 Operating Ranges
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14.2 14.3 14.4 14.5 14.6 14.7
Absolute Ratings. Characteristics Power Dissipation Power Derating Based Lower Frequencies Power Grounding. Buffer Characteristics
Signal Switching Characteristics
15.1 15.2 Switching Characteristics. Clock Switching Characteristics 100-MHz Operation. 15.3 Clock Switching Characteristics 66-MHz Operation. 15.4 Valid Delay, Float, Setup, Hold Timings 15.5 Output Delay Timings 100-MHz Operation. 15.6 Input Setup Hold Timings 100-MHz Operation. 15.7 Output Delay Timings 66-MHz Operation. 15.8 Input Setup Hold Timings 66-MHz Operation. 15.9 RESET Test Signal Timing 15.10 Timing Diagrams.
Thermal Design
16.1 16.2 16.3 16.4 Package Thermal Specifications Measuring Case Temperature Sample Heatsink Measured Data. Layout Airflow Considerations
Designation Diagrams
17.1 18.1 Designations Functional Grouping 321-Pin Staggered CPGA Package Specification.
Package Specifications Ordering Information Index.
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List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure AMD-K6TM-2E Processor Block Diagram.9 Cache Sector Organization Instruction Buffer AMD-K6TM-2E Processor Decode Logic AMD-K6TM-2E Processor Scheduler.18 Register Functional Units Register with 16-Bit 8-Bit Name Components Integer Data Registers.25 Segment Register Segment Usage Floating-Point Register.28 Status Word Register Control Word Register Word Register.29 Packed Decimal Data Register Precision Real Data Registers MMXTM/3DNow!Registers MMXData Types 3DNow!Data Types EFLAGS Register Control Register (CR4) Control Register (CR3) Control Register (CR2) Control Register (CR1) Control Register (CR0) Debug Register Debug Register Debug Registers DR4.38 Debug Registers DR3, DR2, DR1, DR0.39 Machine-Check Address Register (MCAR) Machine-Check Type Register (MCTR) Test Register (TR12).42 Time Stamp Counter (TSC) Extended Feature Enable Register (EFER).43 SYSCALL/SYSRET Target Address Register (STAR) Write Handling Control Register (WHCR).44 UC/WC Cacheability Control Register (UWCCR) Processor State Observability Register (PSOR) Page Flush/Invalidate Register (PFIR).46 Memory Management Registers Task State Segment (TSS) 4-Kbyte Paging Mechanism 4-Mbyte Paging Mechanism
List Figures
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Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Page Directory Entry 4-Kbyte Page Table (PDE) Page Directory Entry 4-Mbyte Page Table (PDE) Page Table Entry (PTE).52 Application Segment Descriptor System Segment Descriptor Gate Descriptor Waveform Definitions.134 State Machine Diagram .135 Non-Pipelined Single-Transfer Memory Read/Write Write Delayed EWBE# .139 Misaligned Single-Transfer Memory Read Write.141 Burst Reads Pipelined Burst Reads .143 Burst Writeback Cache-Line Replacement.145 Basic Read Write .146 Misaligned Transfer.147 Basic HOLD/HLDA Operation .149 HOLD-Initiated Inquire Shared Exclusive Line.151 HOLD-Initiated Inquire Modified Line.153 AHOLD-Initiated Inquire Miss .155 AHOLD-Initiated Inquire Shared Exclusive Line.157 AHOLD-Initiated Inquire Modified Line.159 AHOLD Restriction.161 BOFF# Timing.163 Basic Locked Operation.165 Locked Operation with BOFF# Intervention.167 Interrupt Acknowledge Operation .169 Basic Special Cycle (Halt Cycle) .171 Shutdown Cycle .172 Stop Grant Stop Clock Modes, Part .174 Stop Grant Stop Clock Modes, Part .175 INIT-Initiated Transition from Protected Mode Real Mode.177 Cache Organization .185 Cache Sector Organization .186 Write Handling Control Register (WHCR).194 Write Allocate Logic Mechanisms Conditions .195 Page Flush/Invalidate Register (PFIR).200 UC/WC Cacheability Control Register (UWCCR) .208 External Logic Supporting Floating-Point Exceptions.215 Memory.218 State Diagram .237 Debug Register .241 Debug Register .242
List Figures
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Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. Figure 110. Figure 111. Figure 112. Figure 113. Figure 114. Figure 115.
Debug Registers DR4.242 Debug Registers DR3, DR2, DR1, DR0.243 Clock Control State Transitions.248 Suggested Component Placement .263 Waveform .269 Timing Diagrams .281 Output Valid Delay Timing .281 Maximum Float Delay Timing .282 Input Setup Hold Timing .282 Reset Configuration Timing .283 Timing.284 TRST# Timing.284 Test Signal Timing .284 Thermal Model .286 Power Consumption Thermal Resistance .287 Processor Heat Dissipation Path .288 Measuring Case Temperature.289 Heatsink height) .290 Heatsink height).290 Heatsink height) .290 Measured Thermal Resistance Airflow (Socketed 321-Pin CPGA Package) .291 Measured Maximum Ambient Temperature (Socketed 321-Pin CPGA Package) .292 Measured Thermal Resistance Airflow (Soldered 321-Pin CPGA Package).293 Measured Maximum Ambient Temperature (Soldered, 321-Pin CPGA Package).294 Voltage Regulator Placement .295 Airflow Heatsink with .296 Airflow Path Dual-Fan System .296 Airflow Path Form-Factor System .297 AMD-K6TM-2E Processor Connection Diagram (Top-Side View CPGA) .299 AMD-K6TM-2E Processor Connection Diagram (Bottom-Side View CPGA).300 321-Pin Staggered CPGA Package Specification .303
List Figures
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List Figures
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AMD-K6TM-2E Processor Data Sheet
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Execution Latency Throughput Execution Units General-Purpose Registers General-Purpose Register Doubleword, Word, Byte Names.25 Segment Registers AMD-K6TM-2E Processor Model 8/[F:8] Model-Specific Registers.40 Extended Feature Enable Register (EFER)Definition SYSCALL/SYSRET Target Address Register (STAR) Definition Memory Management Registers.47 Application Segment Types System Segment Gate Types Summary Exceptions Interrupts.55 Integer Instructions Floating-Point Instructions MMXInstructions.78 3DNow!Instructions.81 Processor-to-Bus Clock Ratios Output Float Conditions .127 Input Types .130 Output Float Conditions .131 Input/Output Float Conditions .131 Test Pins.131 Cycle Definition .132 Special Cycles.132 Bus-Cycle Order During Misaligned Memory Transfers A[4:3] Address-Generation Sequence During Bursts .142 Bus-Cycle Order During Misaligned Transfers .147 Interrupt Acknowledge Operation Definition .168 Encodings Special Cycles.170 Output Signal State After RESET.180 Register State After RESET .181 Signal Generation .188 Signal Generation .189 CACHE# Signal Generation.189 Data Cache States Read Write Accesses.198 Cache States Inquire Cycles, Snoops, Flushes, Invalidation .202 Snoop Action .203 EWBEC Settings.207 WC/UC Memory Type .209 Valid Masks Range Sizes .210 Initial State Registers System Management Mode State-Save Area .219
List Tables
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Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Revision Identifier .222 Trap Doubleword Configuration .224 Trap Restart Slot .225 Boundary Scan Definitions .233 Device Identification Register .234 Supported Test Access Port (TAP) Instructions .235 Definitions .245 Operating Ranges .254 Absolute Ratings.255 Characteristics .256 Typical Maximum Power Dissipation Suffix (Low-Power Devices) .258 Typical Maximum Power Dissipation Suffix (Standard-Power Devices) .259 Power Derating Specification Standard-Power Devices (AMD-K6-2E/233AFR 266AFR) .260 Power Derating Specification Low-Power Devices (AMD-K6-2E/233AMZ 266AMZ) .261 Switching Characteristics 100-MHz Operation .268 Switching Characteristics 66-MHz Operation .268 Output Delay Timings 100-MHz Operation .270 Input Setup Hold Timings 100-MHz Operation .272 Output Delay Timings 66-MHz Operation .274 Input Setup Hold Timings 66-MHz Operation RESET Configuration Signals 100-MHz Operation.278 RESET Configuration Signals 66-MHz Operation .279 Waveform TRST# Timing .280 Test Signal Timing MHz.280 Package Thermal Specification Suffix (Low-Power Devices) .285 Package Thermal Specification Suffix (Standard-Power Devices) .285 Passive Heatsink Samples.289 Socketed CPGA Package: Measured Thermal Resistance (°C/W) .291 Socketed CPGA Package: Measured Maximum Ambient Temperature (°C) .292 Soldered CPGA Package: Measured Thermal Resistance (°C/W) .293 Soldered CPGA Package: Measured Maximum Ambient Temperature (°C) .294 Valid Ordering Part Number Combinations .306
List Tables
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Revision History
Date June 1999 2000 2000 2000 Description Initial published release. Replaced Figure "AMD-K6TM-2E Processor Decode Logic," page with updated figure. Replaced Table page with revised boundary scan definitions. Changed Vcc2 maximum specification from Table "Absolute Ratings," page OPNs with exception 233AFR, 233AMZ, 266AFR, 266AMZ, AFR, provided that processor marked with following date code. 300AMZ, 333AMZ, 350AMZ ordering part numbers, added characteristics Table page 256, added power dissipation specifications Table page 258, added package thermal specifications Table page 285, added ordering information beginning page 305. 333AFR, 350AFR, 400AFR ordering part numbers, added characteristics Table page 256, added power dissipation specifications Table page 259, added package thermal specifications Table page 285, added ordering information beginning page 305. Added power derating specifications beginning page 260. Added sample measured heat sink data beginning page 289.
2000
2000 2000 2000
Revision History
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Revision History
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AMD-K6TM-2E Processor Data Sheet
About this Data Sheet
AMD-K6TM-2E Processor Data Sheet complete specification AMD-K6-2E embedded processor.
Overview
This data sheet organized into following sections: Chapter "AMD-K6TM-2E Processor" page provides list AMD-K6-2E processor's distinguishing characteristics, description features, discussion about Super7platform initiative. Chapter "Internal Architecture" page describes functional elements advanced design techniques, known RISC86® microarchitecture, implemented AMD-K6-2E processor. Chapter "Software Environment" page provides general overview AMD-K6-2E processor's software environment briefly describes data types, registers, operating modes, interrupts, instructions supported AMD-K6-2E processor's architecture design implementation. Chapter "Logic Symbol Diagram" page contains AMD-K6-2E processor logic symbol diagram. Chapter "Signal Descriptions" page lists signals their descriptions alphabetically function. Chapter "Bus Cycles" page 133, describes illustrates timing relationship signals during various types cycles. Chapter "Power-On Configuration Initialization" page 179, describes system logic resets AMD-K6-2E processor using RESET signal. Chapter "Cache Organization" page 185, describes basic architecture resources AMD-K6-2E processor's internal caches. Chapter "Write Merge Buffer" page 205, describes 8-byte write merge buffer merging multiple write cycles into single write cycle ultimately increases overall system performance. Chapter "Floating-Point Multimedia Execution Units" page 213, describes AMD-K6-2E processor's IEEE 754-compatible 854-compatible floating point About this Data Sheet xvii
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execution unit, multimedia 3DNow!technology execution units, floating-point MMX/3DNow! technology instruction compatibility. Chapter "System Management Mode (SMM)" page 217, describes SMM, state-save area, entry into exit from SMM, exceptions interrupts SMM, memory allocation addressing SMM, SMI# SMIACT# signals. Chapter "Test Debug" page 227, describes various test debug modes that enable functional manufacturing testing systems boards that AMD-K6-2E processor that allow designers debug instruction execution software components. Chapter "Clock Control" page 247, describes five modes clock control supported AMD-K6-2E processor. Chapter "Electrical Data" page 253, includes operating ranges, absolute ratings, characteristics, power dissipation data, power grounding information, decoupling recommendations, buffer characteristics. Chapter "Signal Switching Characteristics" page 267, provides tables listing valid delay, float, setup, hold timing specifications AMD-K6-2E processor signals. Chapter "Thermal Design" page 285, lists package thermal specifications, discusses measure case temperature, provides sample heat sink measurement data, along with layout airflow considerations. Chapter "Pin Designation Diagrams" page 299, lists AMD-K6-2E processor's designations functional grouping. Chapter "Package Specifications" page 303, provides table diagram containing 321-pin CPGA package specifications. Chapter "Ordering Information" page 305, provides ordering part number (OPN) valid combinations.
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AMD-K6TM-2E Processor
Advanced 6-Issue RISC86® Superscalar Microarchitecture parallel specialized execution units Multiple sophisticated x86-to-RISC86 instruction decoders Advanced two-level branch prediction Speculative execution Out-of-order execution Register renaming data forwarding RISC86 instructions clock Large on-chip split 64-Kbyte level-one (L1) cache 32-Kbyte instruction cache with additional Kbytes predecode cache 32-Kbyte writeback dual-ported data cache Two-way associative MESI protocol support 3DNow!technology Additional instructions improve graphics multimedia performance Separate multiplier superscalar instruction execution 321-pin ceramic grid array (CPGA) package Socket platform compatible, 66-MHz frontside Super7platform compatible, 100-MHz frontside supported 300-MHz, 350-MHz, 400-MHz versions AMD-K6-2E processor High-performance industry-standard MMXinstructions Dual integer superscalar execution High-performance IEEE 754-compatible 854-compatible floating-point unit Industry-standard system management mode (SMM) IEEE 1149.1 boundary scan binary software compatibility Low-power 0.25-micron process technology Split-plane power with support full Available with low-power 1.9-V core voltage extended temperature rating with standard-power 2.2-V core voltage standard temperature rating
following features AMD-K6TM-2E processor:
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AMD-K6TM-2E Processor
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AMD-K6TM-2E Embedded Processor Features
AMD-K6-2E processor with 3DNow!technology functionally compatible embedded version sixth generation, Microsoft® Windows® compatible AMD-K6-2 processor. AMD-K6-2E embedded processor delivers same high performance incorporates same leading-edge features, including innovative efficient RISC86® microarchitecture, large 64-Kbyte level-one cache (32-Kbyte dual-ported data cache, 32-Kbyte instruction cache with predecode data), powerful IEEE 754-compatible 854-compatible floating-point execution unit. AMD-K6-2E embedded processor also supports features incorporated into AMD-K6-2 processor. These features include superscalar MMXinstruction execution support, support Super7100-MHz frontside bus, AMD's innovative 3DNow!technology high-performance multimedia graphics operation based high-performance single instruction multiple data (SIMD) execution resources. AMD-K6-2E embedded processor includes several features that very beneficial embedded market. AMD-K6-2E processor offers leading-edge performance embedded systems requiring compatibility with extensive installed base software. AMD-K6-2E processor's Socket Super7 platform-compatible, 321-pin ceramic grid array (CPGA) package allows product designer reduce time-to-market leveraging today's cost-effective industry-standard infrastructure deliver superior-performing embedded solution. AMD-K6-2E embedded processor available versions.
low-power version 1.9-V core voltage extended temperature rating. standard-power version 2.2-V core voltage embedded equivalent industry-standard desktop version AMD-K6-2 processor.
System Management Mode Power Management Features AMD-K6-2E processor includes complete industry-standard system management mode (SMM), which critical system resource power management. (See "System Management Mode (SMM)" page more detailed information about this feature.) AMD-K6-2E processor also features industry-standard Stop-Clock (STPCLK#) control circuitry Halt instruction, both required implementing ACPI power management specification. ("Clock Control" page provides more information these power management features.)
AMD-K6TM-2E Processor
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Microarchitecture decode/execution superscalar design that implements state-of-the-art design techniques achieve leading-edge performance. Advanced design techniques implemented AMD-K6-2E processor include multiple instruction decode, single-clock internal RISC operations, execution units that support superscalar operation, out-of-order execution, data forwarding, speculative execution, register renaming. addition, processor supports advanced branch prediction logic implementing 8192-entry branch history table, branch target cache, return address stack, which combine deliver better than prediction rate. These design techniques enable AMD-K6-2E issue, execute, retire multiple instructions clock, resulting excellent scalable performance. microarchitecture AMD-K6-2E processor more completely described "Internal Architecture" page 3DNow!Technology AMD's 3DNow! technology instruction-set extension x86, which includes instructions accelerate graphics other single-precision floating-point compute intensive operations. Improvements include fast frame rates high-resolution graphics applications, superior modeling real-world environments physics, life-like images, graphics, audio. already shipped millions processors with 3DNow! technology desktop notebook PCs, revolutionizing experience with four times peak floating-point performance previous sixth generation solutions. bringing this advanced capability embedded systems. taken leadership role developing these instructions that enable exciting levels performance realism. 3DNow! technology defined implemented collaboration with Microsoft, application developers, graphics vendors, received enthusiastic reception. compatible with today's existing software, supported industry-standard APIs, requires operating system support, thereby enabling broad class applications benefit from 3DNow! technology. Industry-Standard Architecture AMD-K6-2E processor binary code compatible. AMD's extensive experience through generations processors been carefully integrated into processor enable compatibility with Windows®-based operating systems, including Windows Windows Windows Windows NT®, Windows NTE. Chapter AMD-K6TM-2E Processor
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AMD-K6-2E processor also compatible with DOS, OS/2, UNIX, other leading operating systems, including real-time operating systems (RTOS) commonly used embedded applications such pSOS, QNX, RTXC, VxWorks. AMD-K6-2E processor compatible with more than 60,000 software applications, including latest software optimized 3DNow! technologies. shipped more than million microprocessors, including more than million Windows-compatible processors. AMD-K6-2E processor among long line Microsoft Windows compatible processors from AMD. combination state-of-the-art features, leading-edge performance, high-performance multimedia engine, compatibility, low-cost infrastructure enable decreased development costs improved time-to-market, making AMD-K6-2E processor superior choice embedded systems.
Process Technology
AMD-K6-2E processor implemented using advanced CMOS 0.25-micron process technology that utilizes split core voltage supply, which allows core processor operate voltage while portion operates industry-standard This technology enables high performance while reducing power consumption operating core voltage limiting power requirements acceptable levels today's embedded systems.
Super7Platform Initiative
AMD-K6-2E processors remain compatible with existing Socket solutions; however, maximum system performance, 300-MHz, 350-MHz, 400-MHz versions processor work optimally Super7 designs that incorporate advanced features such support 100-MHz frontside graphics. industry partners investing future Socket with Super7 platform initiative. goal initiative maintain competitive vitality Socket infrastructure through series enhancements, including development industry-standard 100-MHz processor protocol. addition 100-MHz processor protocol, Super7 initiative includes introduction chipsets that support specification support backside cache frontside cache.
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Super7Platform Enhancements 100-MHz processor bus-The AMD-K6-2E processor supports 100-MHz, Mbyte/second frontside provide high-speed interface Super7 platform-based chipsets. 100-MHz interface frontside Level (L2) cache main system memory speeds access frontside cache main memory percent over 66-MHz Socket interface, resulting significant increase overall system performance.
Accelerated graphics port support -AGP improves performance video graphics systems that have small amounts video memory graphics card. industry-standard specification enables 133-MHz graphics interface will scale even higher levels performance. Support backside frontside cache-The Super7 platform `headroom' support higher-performance AMD-K6 processors with clock speeds scaling beyond. Super7 platform also supports AMD-K6-III processor, which features full-speed, internal backside 256-Kbyte cache designed deliver levels system performance desktop notebook systems. AMD-K6-III processor also supports optional 100-MHz frontside cache even higher-performance system configurations.
Super7Platform Advantages Super7 platform following advantages:
Delivers performance features competitive with alternate platforms same clock speed, significantly lower cost Takes advantage existing system designs superior value Enables OEMs resellers take advantage mature, high-volume infrastructure supported multiple BIOS, chipset, graphics, motherboard suppliers Reduces inventory design costs with motherboard wide range products Builds huge installed base more than million motherboards Provides easy upgrade path future embedded applications, well bridge legacy applications
taking advantage low-cost, mature Socket infrastructure, Super7 platform will continue provide superior value leading-edge performance embedded systems.
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Internal Architecture
AMD-K6-2E processor implements advanced design techniques known RISC86 microarchitecture. RISC86 microarchitecture decoupled decode/execution design approach that yields superior sixth-generation performance x86-based software. This chapter describes techniques used functional elements RISC86 microarchitecture.
AMD-K6TM-2E Processor Microarchitecture Overview
When discussing processor design, important understand implementation.
Architecture refers instruction features processor that visible software programs running processor. architecture determines which software processor run. architecture AMD-K6-2E processor industry-standard instruction set. Microarchitecture refers design techniques used processor reach target cost, performance, functionality goals. AMD-K6-2E processor based sophisticated RISC core known Enhanced RISC86 microarchitecture. Enhanced RISC86 microarchitecture advanced, second-order decoupled decode/execution design approach that enables industry-leading performance x86-based software. Design implementation refers actual logic circuit designs from which processor created according microarchitecture specifications.
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Enhanced RISC86® Microarchitecture
anced RISC86 croarchi tecture characteristics AMD-K6-2E processor. innovative RISC86 microarchitecture approach implements instruction internally translating instructions into RISC86 operations. These RISC86 operations were specially designed include direct support instruction while observing RISC performance principles fixed length encoding, regularized instruction fields, large register set. arch nabl performance promotes straightforward extensibility future designs. Instead directly executing complex instruct ions, which have lengths bytes, AMD-K6-2E processor executes simpler easier fixed-length RISC86 opcodes, while maintaining instruction coding efficiencies found programs. AMD-K6-2E processor contains parallel decoders, centralized RISC86 operation scheduler, execution units that support superscalar operation-multiple decode, execution, retirement-of instructions. These elements packed into aggressive highly efficient six-stage pipeline.
AMD-K6TM-2E Processor Block Diagram
shown Figure page high-performance, out-of-order execution engine AMD-K6-2E processor mated split level-one 64-Kbyte writeback cache with Kbytes instruction cache Kbytes data cache. instruction cache feeds decoders and, turn, decoders feed scheduler. Instruction Control Unit (ICU) issues retires RISC86 operations contained scheduler. system interface industry-standard 64-bit Super7 Socket demultiplexed bus. AMD-K6-2E processor combines latest processor microarchitecture provide highest performance today's computational systems. AMD-K6-2E offers true sixth-generation performance binary software compatibility.
Internal Architecture
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Predecode Logic
32-KByte Level-One Instruction Cache 64-Entry ITLB 20-KByte Predecode Cache
16-Byte Fetch
Level-One Cache Controller
Branch Logic Multiple Instruction Decoders
RISC86 Four RISC86 Decode (8192-Entry BHT) (16-Entry BTC) (16-Entry RAS)
Super7 Interface
Out-of-Order Execution Engine RISC86 Operation Issue
Scheduler Buffer
RISC86)
Instruction Control Unit
Load Unit
Store Unit
Register Functional Units Integer/ Multimedia/3DNow!
Register Functional Units Integer/ Multimedia /3DNow!
Branch Unit
Store Queue
32-KByte Level-One Dual-Port Data Cache
128-Entry DTLB
Figure AMD-K6TM-2E Processor Block Diagram Decoders Decoding instructions begins when on-chip instruction cache filled. Predecode logic determines length instruction byte-by-byte basis. This instructions, instruction cache, used later decoders. decoders translate on-the-fly, with additional latency, instructions clock into RISC86 operations. Note: this chapter, "clock" refers processor clock. AMD-K6-2E processor categorizes instructions into three types decodes-short, long, vector. decoders process either short, long, vector decode time.
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three types decodes have following characteristics:
Short decodes-x86 instructions that less than equal seven bytes long Long decodes-x86 instructions less than equal bytes long Vector decodes-complex instructions
Short long decodes processed completely within decoders. Vector decodes started decoders then completed fetched sequences from on-chip ROM. After decoding, RISC86 operations delivered scheduler dispatching execution units. Scheduler/Instruction Control Unit centralized scheduler buffer managed ICU. buffers manages RISC86 operations time. This equals from instructions. This buffer size (24) perfectly matched processor's six-stage RISC86 pipeline, four RISC86-operations decode rate, parallel execution units. scheduler accepts many four RISC86 operations time from decoders retires four RISC86 simultaneously issuing RISC86 operations time execution units. This consists following types operations:
Memory load operation Memory store operation Complex integer, MMX, 3DNOW! register operation Simple integer register operation Floating-point register operation Branch condition evaluation
Registers
When managing RISC86 operations, uses microarchitecture.
Forty-eight physical registers located general register file. Twenty-four these rename registers. other twenty-four committed architectural registers, consisting scratch registers registers Internal Architecture Chapter
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that correspond general-purpose registers- EAX, EBX, ECX, EDX, EBP, ESP, ESI, EDI. analogous registers available specifically 3DNow! operations. Twelve these MMX/3DNow! rename registers. Nine MMX/3DNow! committed architectural registers, consisting scratch register eight registers that correspond registers (mm0- mm7). more detailed information, 3DNow!Technology Manual, order #21928.
Branch Logic
sophisticated dynamic branch logic consisting following:
Branch history/Prediction table Branch target cache Return address stack
AMD-K6-2E processor implements two-level branch prediction scheme based 8192-entry branch history table. branch history table stores prediction information that used predicting conditional branches. Because branch history table does store predicted target addresses, special address ALUs calculate target addresses on-the-fly during instruction decode. performance avoiding clock cache-fetch penalty. This specialized target cache does this supplying first bytes target instructions decoders when branches predicted. return address stack unique device specifically designed optimizing CALL RETURN pairs. summary, AMD-K6-2E processor uses dynamic branch logic minimize delays branch instructions that common software. 3DNow!Technology taken lead role improving multimedia capabilities processor family with introduction 3DNow! technology, which uses packed, single-precision, floating-point data format Single Instruction Multiple Data (SIMD) operations also found technology model.
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Cache, Instruction Prefetch, Predecode Bits
writeback level-one cache AMD-K6-2E processor organized separate 32-Kbyte instruction cache 32-Kbyte data cache with two-way associativity. cache line size bytes lines prefetched from main memory using efficient pipelined burst transaction. instruction cache filled, each instruction byte analyzed instruction boundaries using predecoding logic. Predecoding annotates each instruction byte with information bits byte) that later enables decoders efficiently decode multiple instructions simultaneously.
Cache
processor cache design takes advantage sectored organization (see Figure Each sector consists bytes configured 32-byte cache lines. cache lines sector share common have separate pairs MESI (Modified, Exclusive, Shared, Invalid) bits that track state each cache line.
Cache Line Byte Predecode Bits Byte Predecode Bits Byte Predecode Bits MESI Bits Cache Line Byte Predecode Bits Byte Predecode Bits Byte Predecode Bits MESI Bits
Address
Figure Cache Sector Organization forms cache misses associated cache fills take place-a tag-miss cache fill tag-hit cache fill.
Tag-miss cache fill-The miss mismatch, which case required cache line filled from external memory, cache line within sector that required marked invalid. Tag-hit cache fill-The address matches tag, requested cache line marked invalid. required cache line filled from external memory, cache line within sector that required remains same cache state.
Prefetching
AMD-K6-2E processor conditionally performs cache prefetching which results filling required cache line first, prefetch second cache line making other half sector. From perspective external bus, cache-line fills typically appear 32-byte Internal Architecture Chapter
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burst read cycles occurring back-to-back allowed, pipelined cycles. 3DNow! technology includes instruction named PREFETCH that allows cache line prefetched into data cache. PREFETCH instruction format defined Table "3DNow!Instructions," page more detailed information, 3DNow!Technology Manual, order #21928. Predecode Bits Decoding instructions particularly difficult because instructions variable length bytes). Predecode logic supplies five predecode bits associated with each instruction byte. predecode bits indicate number bytes start next instruction. predecode bits stored extended instruction cache alongside each instruction byte, shown Figure page predecode bits passed with instruction bytes decoders where they assist with parallel instruction decoding.
Instruction Fetch Decode
processor fetch bytes clock instruction cache branch target cache. fetched information placed into 16-byte instruction buffer that feeds directly into decoders (see Figure page 14). Fetching occur along single execution stream with seven outstanding branches taken. instruction fetch logic capable retrieving contiguous bytes information within 32-byte boundary. There additional penalty when bytes instructions across cache line boundary. instruction bytes loaded into instruction buffer they consumed decoders. Although instructions consumed with byte granularity, instruction buffer managed memory-aligned word (two bytes) organization. Therefore, instructions loaded replaced with word granularity. When control transfer occurs such instruction entire instruction buffer flushed reloaded with instruction bytes.
Instruction Fetch
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Bytes 32-Kbyte Level-One Instruction Cache Bytes
Branch-Target Cache Bytes
Branch Target Address Adders Return Address Stack Bytes Fetch Unit Instruction Bytes plus Sets Predecode Bits
Instruction Buffer
Figure Instruction Buffer Instruction Decode AMD-K6-2E processor decode logic designed decode multiple instructions clock (see Figure page 15). decode logic accepts instruction bytes their predecode bits from instruction buffer, locates actual instruction boundaries, generates RISC86 operations from these instructions. RISC86 operations fixed-format internal instructions. Most RISC86 operations execute single clock. RISC86 operations combined perform every function instruction set. Some instructions decoded into zero RISC86 opcodes, instance NOP, RISC86 operation, register-to-register add. More complex instructions decoded into several RISC86 operations.
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Instruction Buffer
Short Decoder Short Decoder
Long Decoder On-Chip
Vector Decoder
RISC86® Sequencer
Vector Address
RISC86 Operations
Figure AMD-K6TM-2E Processor Decode Logic AMD-K6-2E processor uses combination decoders convert instructions into RISC86 operations. hardware consists three sets decoders-two parallel short decoders, long decoder, vector decoder. Parallel Short Decoders. parallel short decoders translate most commonly-used instructions moves, shifts, branches, ALU, FPU) extensions instruction (MMX 3DNow! technology) into zero, one, RISC86 operations each. short decoders only operate instructions that seven bytes long. addition, decoders designed decode instructions clock.
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Long Decoder. commonly-used instructions that greater than seven bytes more than bytes long, instructions that slightly less common seven bytes long handled long decoder. long decoder only performs decode clock generates four RISC86 operations. Vector Decoder. other translations (complex instructions, serializing conditions, interrupts exceptions, etc.) handled combination vector decoder RISC86 operation sequences fetched from on-chip ROM. complex operations, vector decoder logic provides first RISC86 operations vector (initial address) sequence further RISC86 operations. same types RISC86 operations fetched from those that generated hardware decoders. Note: Although three sets decoders simultaneously copy instruction buffer contents, only three types decoders used during decode clock. Grouped Operations. decoders RISC86 sequencer always generate group four RISC86 operations. decodes that cannot fill entire group with four RISC86 operations, RISC86 operations placed empty locations grouping. example, long-decoded instruction that converts only three RISC86 operations padded with single RISC86 operation then passed scheduler. groups, RISC86 operations, placed scheduler time. Floating Point Instructions. common, uncommon, floating-point instructions (also known instructions) hardware decoded short decodes. This decode generates RISC86 floating-point operation and, optionally, associated floating-point load store operation. Floating-point instruction decode only allowed first short decoder, non-ESC instructions, excluding instructions, decoded simultaneously second short decoder along with instruction decode first short decoder. 3DNow!Instructions. instructions, with exception EMMS, FEMMS, PREFETCH instructions, hardware decoded short Internal Architecture Chapter
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decodes. instruction decode generates RISC86 operation and, optionally, associated load store operation. 3DNow! instruction decode generates RISC86 3DNow! operation and, optionally, associated load store operation. 3DNow! instructions decoded either both short decoders.
Centralized Scheduler
scheduler heart AMD-K6-2E processor (see Figure page 18). scheduler contains logic necessary manage out-of-order execution, data forwarding, register renaming, simultaneous issue retirement multiple RISC86 operations, speculative execution. scheduler's buffer hold RISC86 operations. This equates maximum instructions. When possible, scheduler simultaneously issue RISC86 operation available execution unit (store, load, branch, integer, integer/multimedia, floating-point). total, scheduler issue retire four RISC86 operations clock. main advantage scheduler operation buffer ability examine instruction window equal instructions time. This advantage fact that scheduler operates RISC86 operations parallel allows AMD-K6-2E processor perform dynamic on-the-fly instruction code scheduling optimized execution. Although scheduler issue RISC86 operations out-of-order execution, always retires instructions order.
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From Decode Logic RISC86 RISC86 RISC86 RISC86
Centralized RISC86® Operation Scheduler
RISC86 Issue Buses
RISC86 Operation Buffer
Figure AMD-K6TM-2E Processor Scheduler
Execution Units
AMD-K6-2E processor contains parallel execution units-store, load, integer ALU, integer ALU, (X), (Y), MMX/3DNow! multiplier, 3DNow! ALU, floating-point, branch condition. Each unit independent capable handling RISC86 operations. Table page details execution units, functions performed within these units, operation latency, operation throughput. store load execution units two-stage pipelined designs.
store unit performs data writes register calculation LEA/PUSH. Data memory register writes from stores available after clock. Store operations held store queue prior execution. From there, they execute order. load unit performs data memory reads. Data available from load unit after clocks. Internal Architecture Chapter
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executio unit operat operations, multiplies, divides (signed unsigned), shifts, rotates. Integer execution unit operate basic word doubleword operations ADD, AND, CMP, SUB, XOR, zero-extend, sign-extend operands. Table Execution Latency Throughput Execution Units
Functional Unit
Store Load Integer
Function
LEA/PUSH, Address (Pipelined) Memory Store (Pipelined) Memory Loads (Pipelined) Integer Integer Multiply Integer Shift Shifts, Packs, Unpack Multiply Basic (16-bit 32-bit operands) Resolves Branch Conditions FADD, FSUB, FMUL 3DNow! 3DNow! Multiply 3DNow! Convert
Latency
Throughput
Multimedia (processes instructions) Integer Branch 3DNow!
functional units that execut 3DNow! instructions share pipeline control with Integer Integer units. Register Pipelines register functional units attached issue register execution pipeline issue register execution pipeline both. Each register pipeline dedicated resources that consist integer execution unit execution unit, therefore allowing superscalar operation integer instructions. addition, both issue buses connected 3DNow! ALU, MMX/3DNow! multiplier, shifter, which allows appropriate RISC86 operation issued through either bus. Figure page shows details register pipelines.
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Scheduler Buffer RISC86® Operations) Issue Register Execution Pipeline Issue Register Execution Pipeline
Integer
MMX/ Multiplier
Shifter
3DNow!
Integer
Figure Register Functional Units branch condition unit separate from branch prediction logic that resolves conditional branches such LOOP after branch condition been evaluated.
Branch-Prediction Logic
Sophisticated branch logic that minimize hide impact changes program flow designed into AMD-K6-2E processor. Branches code into categories:
Unconditional branches always change program flow (that branches always taken) Conditional branches divert program flow (that branches taken not-taken). When conditional branch taken, processor simply continues decoding executing next instructions memory.
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Typical applications have unconditional branches another conditional branches. AMD-K6-2E processor branch logic been designed handle this type program behavior negative effects instruction execution, such stalls delayed instruction fetching draining processor pipeline. branch logic contains 8192-entry branch history table, 16-entry 16-byte branch target cache, 16-entry return address stack, branch execution unit. Branch History Table AMD-K6-2E processor handles unconditional branches without penalty redirecting instruction fetching target address unconditional branch. However, branch-prediction mechanism built into AMD-K6-2E processor. two-level adaptive history algorithm implemented 8192-entry branch history table. This table stores executed branch information, predicts individual branches, predicts behavior groups branches. accommodate large branch history table, AMD-K6-2E processor does store predicted target addresses. Instead, branch target addresses calculated on-the-fly using ALUs during decode stage. adders calculate possible target addresses before instructions fully decoded, processor chooses which addresses valid. Branch Target Cache avoid clock cache-fetch penalty when branch predicted taken, built-in branch target cache supplies first bytes instructions directly instruction buffer (assuming target address hits this cache). (See Figure page 14.) branch target cache organized entries bytes. total, branch prediction logic achieves branch prediction rates greater than 95%. Return Address Stack return address stack special device designed optimize CALL pairs. Software typically compiled with subroutines that frequently called from various places program. This usually done save space.
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Entry into subroutine occurs with execution CALL instruction. that time, processor pushes address next instruction memory following CALL instruction onto stack (allocated space memory). When processor encounters instruction (within subroutine), branch logic pops address from stack begins fetching from that location. avoid latency main memory accesses during CALL operations, return address stack caches pushed addresses. Branch Execution Unit branch execution unit enables efficient speculative execution. This unit gives processor ability execute instructions beyond conditional branches before knowing whether branch prediction correct. AMD-K6-2E processor does permanently update registers memory locations until speculatively executed conditional branch instructions resolved. When prediction incorrect, processor backs point mispredicted branch instruction restores registers. AMD-K6-2E processor support seven outstanding branches.
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Software Environment
This chapter provides general overview AMD-K6-2E processor's software environment briefly describes data types, registers, operating modes, interrupts, instructions supported AMD-K6-2E architecture design implementation. tepping Model versi proces determines implementation format ModelSpecific Registers (MSRs). AMD-K6-2E processor supports Model steppings [F:8] eight possible model/steppings-Models 8/8, 8/9, 8/A, 8/B, 8/C, 8/D, 8/E, 8/F. Note that name AMD-K6-2E processor itself refers steppings Model 8/[F:8] version.
Registers
AMD-K6-2E processor contains registers defined architecture, including general-purpose, segment, floating-point, MMX/3DNow!, EFLAGS, control, task, debug, test, descriptor/memory-management registers. addition information about these registers, this chapter provides information AMD-K6-2E processor MSRs. Note: Areas register designated Reserved should modified software.
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General-Purpose Registers
eight 32-bit general-purpose registers used hold integer data memory pointers used instructions. Table contains list general-purpose registers functions which they used. Table General-Purpose Registers
Register Function
Commonly used accumulator Commonly used pointer Commonly used counting loop operations Commonly used hold information pass parameters Commonly used destination pointer segment Commonly used source pointer segment Used point stack segment Used point data within stack segment
support byte word operations, EAX, EBX, ECX, also used 8-bit 16-bit registers. shorter registers overlaid longer ones. example, name 16-bit version (low bits EAX) 8-bit names (high order bits) (low order bits). same naming convention applies EBX, ECX, EDX. EDI, ESI, ESP, used smaller 16-bit registers called respectively, these registers have 8-bit versions. Figure shows register with name components, Table page lists doubleword (32-bit) general-purpose registers their corresponding word (16-bit) byte (8-bit) versions.
Figure Register with 16-Bit 8-Bit Name Components
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Table General-Purpose Register Doubleword, Word, Byte Names
32-Bit Name (Doubleword)
16-Bit Name (Word)
8-Bit Name 8-Bit Name (High-order Bits) (Low-order Bits)
Integer Data Types
Four types data used general-purpose registers-byte, word, doubleword, quadword integers. Figure shows format integer data registers.
Precision Bits
Byte Integer
Word Integer
Precision Bits
Doubleword Integer
Precision Bits
Quadword Integer
Precision Bits
Figure Integer Data Registers Chapter Software Environment
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Segment Registers
16-bit segment registers used pointers areas (segments) memory. Table lists segment registers their functions. Figure shows format segment registers. Table Segment Registers
Segment Segment Register Function Register
Code segment, where instructions located Data segment, where data located Data segment, where data located Data segment, where data located Data segment, where data located Stack segment
Figure Segment Register Segment Usage operating system determines type memory model that implemented. segment register usage determined operating system's memory model. real mode memory model, segment register points base address memory. protected mode memory model, segment register called selector selects segment descriptor descriptor table. This descriptor contains pointer base segment, limit segment, various protection attributes. more information descriptor formats, "Descriptors Gates" page Figure page shows segment usage real mode protected mode memory models.
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Physical Memory
Segment Base Segment Register Real Mode Memory Model Descriptor Table Physical Memory
Base Base
Limit Limit
Base
Segment Selector
Segment Base
Protected Mode Memory Model
Figure Segment Usage Instruction Pointer instruction pointer (EIP used conjunction with code segment register (CS). instruction pointer either 32-bit register (EIP) 16-bit register (IP) that keeps track where next instruction resides within memory. This register cannot directly manipulated, altered modifying return pointers when CALL instruction used. floating-point execution unit AMD-K6-2E processor designed perform mathematical operations non-integer numbers. This floating-point unit conforms IEEE standards uses several registers meet these standards eight numeric floating-point registers, status word register, control word register, word register.
Floating-Point Registers
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eight floating-point registers physically bits wide labeled FPR0-FPR7. Figure shows format these floating-point registers. "Floating-Point Register Data Types" page information allowable floating-point data types.
Sign Exponent Significand
Figure Floating-Point Register 16-bit status word register contains information about state floating-point unit. Figure shows format status word register.
TOSP
Symbol TOSP
Description Bits Busy Condition Code Stack Pointer 13-11 Condition Code Condition Code Condition Code Error Summary Status Stack Fault Exception Flags Precision Error Underflow Error Overflow Error Zero Divide Error Denormalized Operation Error Invalid Operation Error TOSP Information FPR0 FPR7
Figure Status Word Register
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control word register allows programmer manage processing options. Figure shows format control word register.
Reserved Symbol Description Infinity (80287 compatibility) Rounding Control Precision Control Exception Masks Precision Underflow Overflow Zero Divide Denormalized Operation Invalid Operation Bits 11-10 Precision Control Information bits Single Precision Real Reserved bits Double Precision Real bits Extended Precision Real
Rounding Control Information Round nearest even number Round down toward negative infinity Round toward positive infinity Truncate toward zero
Figure Control Word Register word register contains information about registers register stack. Figure shows format word register.
(FPR4) (FPR3) (FPR2) (FPR1) (FPR0)
(FPR7)
(FPR6)
(FPR5)
Values Valid Zero Special Empty
Figure Word Register
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Floating-Point Register Data Types
Floating-point registers four different types data packed decimal, single-precision real, double-precision real, extended-precision real. Figures show formats these registers.
Ignore Zero
Precision Digits, Bits Used, 4-Bits/Digit
Description Bits Ignored Load, Zeros Store 78-72 Sign
Figure Packed Decimal Data Register
Single-Precision Real
Significand
Biased Exponent
Sign
Double-Precision Real
Biased Exponent
Significand
Sign
Extended-Precision Real
Biased Exponent Significand
Sign
Integer
Figure Precision Real Data Registers
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MMXTM/3DNow!Registers
MMX/3DNow! registers multimedia software. These registers mapped floating-point register stack. 3DNow! instructions refer these registers mm7. Figure shows format these registers. more information, AMD-K6® Processor Multimedia Technology Manual, order #20726 3DNow! Technology Manual, order #21928.
Figure MMXTM/3DNow!Registers
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MMXData Types
instructions, registers three types data packed 8-byte integer, packed quadword integer, packed dual doubleword integer. Figure shows format data types.
Packed Bytes Integer
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Packed Words Integer
Word Word Word Word
Packed Doubleword Integer
Doubleword Doubleword
Figure MMXData Types
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3DNow!Data Types
3DNow! instructions, MMX/3DNow! registers packed single-precision real data. Figure shows format 3DNow! data type.
Packed Single Precision Floating Point
Significand Significand
Biased Exponent Sign
Biased Exponent Sign
Figure 3DNow!Data Types
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EFLAGS Register
EFLAGS register provides three different types flags system, control, status. system flags provide operating system controls, control flag provides directional information string operations, status flags provide information resulting from logical arithmetic operations. Figure shows format EFLAGS register.
Reserved Symbol IOPL Description Bits Flag Virtual Interrupt Pending Virtual Interrupt Flag Alignment Check Virtual-8086 Mode Resume Flag Nested Task Privilege Level 13-12 Overflow Flag Direction Flag Interrupt Flag Trap Flag Sign Flag Zero Flag Auxiliary Flag Parity Flag Carry Flag
Figure EFLAGS Register
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Control Registers
five control registers contain system control bits pointers. Figures through show formats control registers.
Reserved Symbol Description Machine Check Enable Page Size Extensions Debugging Extensions Time Stamp Disable Protected Virtual Interrupts Virtual-8086 Mode Extensions
Figure Control Register (CR4)
Page Directory Base
Reserved Symbol Description Page Cache Disable Page Writethrough
Figure Control Register (CR3)
Page Fault Linear Address
Figure Control Register (CR2)
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Reserved
Figure Control Register (CR1)
Symbol Description Paging Cache Disable Writethrough
Reserved Symbol Description Alignment Mask Write Protect Numeric Error Extension Type Task Switched Emulation Monitor Co-processor Protection Enabled
Figure Control Register (CR0)
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Debug Registers
Figures through show 32-bit debug registers supported processor. These registers further described "Debug" page 240.
Symbol Description Length Breakpoint Type Transaction(s) Trap Length Breakpoint Type Transaction(s) Trap Length Breakpoint Type Transaction(s) Trap Length Breakpoint Type Transaction(s) Trap Bits 31-30 29-28 27-26 25-24 23-22 21-20 19-18 17-16
Reserved Symbol Description General Detect Enabled Global Exact Breakpoint Enabled Local Exact Breakpoint Enabled Global Exact Breakpoint Enabled Local Exact Breakpoint Enabled Global Exact Breakpoint Enabled Local Exact Breakpoint Enabled Global Exact Breakpoint Enabled Local Exact Breakpoint Enabled Global Exact Breakpoint Enabled Local Exact Breakpoint Enabled
Figure Debug Register
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Reserved Symbol Description Breakpoint Task Switch Breakpoint Single Step Breakpoint Debug Access Detected Breakpoint Condition Detected Breakpoint Condition Detected Breakpoint Condition Detected Breakpoint Condition Detected
Figure Debug Register
Reserved
Reserved
Figure Debug Registers
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Breakpoint 32-bit Linear Address
Breakpoint 32-bit Linear Address
Breakpoint 32-bit Linear Address
Breakpoint 32-bit Linear Address
Figure Debug Registers DR3, DR2, DR1,
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Model-Specific Registers (MSR)
AMD-K6-2E processor based functionally identical AMD-K6-2 processor Model 8/[F:8], which provides model-specific registers (MSRs).
value register selects addressed RDMSR WRMSR instructions. values used inputs outputs RDMSR WRMSR instructions.
Table lists MSRs corresponding value register. Figures through show formats. Table AMD-K6TM-2E Processor Model 8/[F:8] Model-Specific Registers
Model-Specific Register
Machine-Check Address Register (MCAR) Machine-Check Type Register (MCTR) Test Register (TR12) Time Stamp Counter (TSC) Extended Feature Enable Register (EFER) SYSCALL/SYSRET Target Address Register (STAR) Write Handling Control Register (WHCR) UC/WC Cacheability Control Register (UWCCR) Processor State Observability Register (PSOR) Page Flush/Invalidate Register (PFIR)
Value
C000_0080h C000_0081h C000_0082h C000_0085h C000_0087h C000_0088h
more information about MSRs, AMD-K6® Processor BIOS Design Application Note, order #21329. info WRMSR instructions, K86Family BIOS Software Tools Development Guide, order #21062.
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MCAR MCTR
AMD-K6-2E processor does support generation machine-check exception. However, processor does provide 64-bit machine-check address register (MCAR), 64-bit machine-check type register (MCTR), machine check enable (MCE) CR4. Because processor does support machine check exceptions, contents MCAR MCTR registers only affected WRMSR instruction RESET being sampled asserted (where bits each register reset formats machine-check address register machine-check type register shown Figure Figure respectively.
MCAR
Figure Machine-Check Address Register (MCAR)
MCTR
Reserved
Figure Machine-Check Type Register (MCTR)
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Test Register (TR12)
Test register provides method disabling caches. Figure shows format TR12 register.
Symbol Description Cache Inhibit
Reserved
Figure Test Register (TR12)
Time Stamp Counter
With each processor clock cycle, processor increments 64-bit time stamp counter (TSC) MSR. Figure shows format register.
Figure Time Stamp Counter (TSC)
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Extended Feature Enable Register (EFER)
extended feature enable register (EFER) contains contro bits that enable extended features AMD-K6-2E processor. Figure shows format EFER register, Table defines function each EFER register.
EWBEC
Reserved Symbol EWBEC Description EWBE# Control Data Prefetch Enable System Call Extension
Figure Extended Feature Enable Register (EFER) Table Extended Feature Enable Register (EFER)Definition
63-4
Description
Reserved EWBE# Control (EWBEC) Data Prefetch Enable (DPE)
Function
Writing reserved causes general protection fault occur. reserved bits always read This 2-bit field controls behavior processor with respect ordering write cycles EWBE# signal. EFER[3] EFER[2] Global EWBE# Disable (GEWBED) Speculative EWBE# Disable (SEWBED), respectively. must enable data prefetching (this default setting following reset). enabled, cache misses initiated memory read within 32-byte cache line conditionally followed cache-line fetches other line 64-byte sector. must enable usage SYSCALL SYSRET instructions.
System Call Extension (SCE)
more information about EWBEC bits, "EWBE# Control" page 205.
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SYSCALL/SYSRET Target Address Register (STAR)
SYSCALL/SYSRET target address register (STAR) contains target address used SYSCALL instruction 16-bit code stack segment selector bases used SYSCALL SYSRET instructions. Figure shows format STAR register, Table defines function each STAR register. more information, SYSCALL SYSRET Instruction Specification Application Note, order #21086.
Target Address
SYSRET Selector Selector Base
SYSCALL Selector Selector Base
Figure SYSCALL/SYSRET Target Address Register (STAR) Table SYSCALL/SYSRET Target Address Register (STAR) Definition
63-48 47-32 31-0
Description
SYSRET Selector Base SYSCALL Selector Base Target Address
Write Handling Control Register (WHCR)
write handling control register (WHCR) that contains fields-the write allocate enable limit (WAELIM) field, write allocate enable 15-to-16-Mbyte (WAE15M) bit. Figure shows format WHCR register. "Write Allocate" page more information.
WAELIM
Reserved Symbol WAELIM WAE15M Description Bits Write Allocate Enable Limit 31-22 Write Allocate Enable 15-to-16-Mbyte
Note: Hardware RESET initializes this zeros.
Figure Write Handling Control Register (WHCR) Software Environment Chapter
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UC/WC Cacheability Control Register (UWCCR)
AMD-K6-2E processor provides variable-range Memory Type Range Registers (MTRRs)-MTRR0 MTRR1-that each specify range memory. Each range defined uncacheable (UC) write-combining (WC) memory. Figure shows format UWCCR register. more detailed information about MTRR0, MTRR1, UWCCR registers, "Memory Type Range Registers" page 207.
Bits Physical Base Address Symbol Description Uncacheable Memory Type Write-Combining Memory Type Bits
Symbol
Description Uncacheable Memory Type Write-Combining Memory Type
Physical Base Address
Physical Address Mask
Physical Address Mask
MTRR1
MTRR0
Figure UC/WC Cacheability Control Register (UWCCR)
Processor State Observability Register (PSOR)
AMD-K6-2E processor provides processor state observability register (PSOR) (see Figure 38).
STEP
Reserved Symbol NOL2 STEP Description Functionality Processor Stepping Frequency Divisor
Figure Processor State Observability Register (PSOR)
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Page Flush/Invalidate Register (PFIR)
AMD-K6-2E processor contains Page Flush/Invalidate Register (PFIR) (see Figure that allows cache invalidation optional flushing specific 4-Kbyte page from linear address space. Using this register result much lower cycle count flushing particular pages versus flushing entire cache. When PFIR written (using WRMSR instruction), invalidation and, optionally, flushing begins.
LINPAGE
Reserved Symbol LINPAGE Description 20-bit Linear Page Address Page Fault Occurred Flush/Invalidate Command 31-12
Figure Page Flush/Invalidate Register (PFIR)
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Memory Management Registers
AMD-K6-2E processor controls segmented memory management with registers listed Table Figure shows formats memory management registers.
Table Memory Management Registers
Register Name
Global Descriptor Table Register Interrupt Descriptor Table Register Local Descriptor Table Register Task Register
Function
Contains pointer base global descriptor table Contains pointer base interrupt descriptor table Contains pointer local descriptor table current task Contains pointer task state segment current task
Global Interrupt Descriptor Table Registers
32-Bit Linear Base Address 16-Bit Limit
Local Descriptor Table Register Task Register
Selector
32-Bit Linear Base Address
32-Bit Limit
Attributes
Figure Memory Management Registers
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Task State Segment
Figure shows format task state segment (TSS).
Permission Bitmap (IOPB) Kbytes) Limit from
Interrupt Redirection Bitmap (IRB) (eight 32-bit locations)
Operating System Data Structure
Base Address IOPB 0000h 0000h 0000h 0000h 0000h 0000h 0000h EFLAGS 0000h ESP2 0000h ESP1 0000h ESP0 0000h
0000h Selector
Link (Prior Selector)
Figure Task State Segment (TSS)
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Paging
AMD-K6-2E processor physically address four Gbytes memory. This memory segmented into pages. size these pages determined operating system design values page directory entries (PDE) page table entries (PTE). processor access both 4-Kbyte pages 4-Mbyte pages, page sizes intermixed within page directory. When page size extension (PSE) set, processor translates linear addresses using either 4-Kbyte translation lookaside buffer (TLB) 4-Mbyte TLB, depending state page size (PS) page directory entry. Figures show 4-Kbyte 4-Mbyte page translations work.
4-Kbyte Page Frame
Page Directory
Page Table
Physical Address
Page Directory Offset
Page Table Offset
Page Offset
Linear Address
Figure 4-Kbyte Paging Mechanism
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4-Mbyte Page Frame
Page Directory
Physical Address
Page Directory Offset
Page Offset
Linear Address
Figure 4-Mbyte Paging Mechanism Figures through show formats PTE. These entries contain information regarding location pages their status.
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Page Table Base Address
Symbol
Description Available Software Reserved Page Size Reserved Accessed Page Cache Disable Page Writethrough User/Supervisor Write/Read Present (valid)
Bits 11-9
Figure Page Directory Entry 4-Kbyte Page Table (PDE)
Physical Page Base Address
Reserved
Symbol
Description Available Software Reserved Page Size Reserved Accessed Page Cache Disable Page Writethrough User/Supervisor Write/Read Present (valid)
Bits 11-9
Figure Page Directory Entry 4-Mbyte Page Table (PDE)
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Physical Page Base Address
Symbol
Description Available Software Reserved Dirty Accessed Page Cache Disable Page Writethrough User/Supervisor Write/Read Present (valid)
Bits 11-9
Figure Page Table Entry (PTE)
Descriptors Gates
There various types structures registers architecture that define, protect, isolate code segments, data segments, task state segments, gates. These structures called descriptors.
application segment descriptor used point either data code segment. Figure page shows application segment descriptor format. Table contains information describing memory segment type which descriptor points. system segment descriptor used point task state segment, call gate, local descriptor table. Figure page shows system segment descriptor format. Table contains information describing type segment gate which descriptor points. AMD-K6-2E processor uses gates transfer control between executable segments with different privilege levels. Figure page shows format gate descriptor types. Table contains information describing type segment gate which descriptor points.
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Reserved
Symbol Type
Description Granularity 32-Bit/16-Bit Available Software Present/Valid Descriptor Privilege Level Descriptor Type Table
Bits 14-13 11-8
Base Address 31-24 Segment Limit Type
Base Address 23-16
Base Address 15-0
Segment Limit 15-0
Figure Application Segment Descriptor
Table Application Segment Types
Type Data/Code Description
Code Data Read-Only Read-Only-Accessed Read/Write Read/Write-Accessed Read-Only-Expand-down Read-Only-Expand-down, Accessed Read/Write-Expand-down Read/Write-Expand-down, Accessed Execute-Only Execute-Only-Accessed Execute/Read Execute/Read-Accessed Execute-Only-Conforming Execute-Only-Conforming, Accessed Execute/Read-Only-Conforming Execute/Read-Only-Conforming, Accessed
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Reserved
Symbol Type
Description Granularity Needed Availability Software Present/Valid Descriptor Privilege Level Descriptor Type Table
Bits 14-13 11-8
Base Address 31-24 Segment Limit Type
Base Address 23-16
Base Address 15-0
Segment Limit 15-0
Figure System Segment Descriptor
Table System Segment Gate Types
Type Description
Reserved Available 16-bit Busy 16-bit 16-bit Call Gate Task Gate 16-bit Interrupt Gate 16-bit Trap Gate Reserved Available 32-bit Reserved Busy 32-bit 32-bit Call Gate Reserved 32-bit Interrupt Gate 32-bit Trap Gate
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Reserved
Symbol Type
Description Present/Valid Descriptor Privilege Level Descriptor Type Table
Bits 14-13 11-8
Offset 31-16 Type
Segment Selector
Offset 15-0
Figure Gate Descriptor
Exceptions Interrupts
Table summarizes exceptions interrupts.
Table Summary Exceptions Interrupts
Interrupt Interrupt Type Number
0-255 Divide Zero Error Debug Non-Maskable Interrupt Breakpoint Overflow Bounds Check Invalid Opcode Device Available Double Fault Reserved Interrupt Invalid Segment Present Stack Segment General Protection Page Fault Floating-Point Error Alignment Check Software Interrupt
Cause
DIV, IDIV Debug trap fault signal sampled asserted INTO BOUND Invalid instruction WAIT Fault occurs while handling fault Task switch invalid segment Instruction loads segment present (invalid segment) Stack operation causes limit violation present Segment related miscellaneous invalid actions Page protection violation reference missing page Arithmetic error generated floating-point instruction Data reference unaligned operand. (The flag
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Instructions Supported AMD-K6TM-2E Processor
This section documents instructions supported AMD-K6TM-2E processor. Tables through define integer, floating-point, MMX, 3DNow! instructions AMD-K6-2E processor, respectively. Each table shows instruction mnemonic, opcode, modR/M instruction.
Instruction Mnemonic Operand Types
first column each table indicates instruction mnemonic operand types, with following notations:
disp16/32-16-bit 32-bit displacement value disp32/48-doubleword 48-bit displacement value disp8-8-bit displacement value eXX-register width depending operand size imm16/32-16-bit 32-bit immediate value imm8-8-bit immediate value mem16/32-word doubleword integer value memory mem32/48-doubleword 48-bit integer value memory mem32real-32-bit floating-point value memory mem48-48-bit integer value memory mem64-64-bit value memory mem64real-64-bit floating-point value memory mem8-byte integer value memory mem80real-80-bit floating-point value memory mmreg-MMX/3DNow! register mmreg1-MMX/3DNow! register defined bits modR/M byte mmreg2-MMX/3DNow! register defined bits modR/M byte mreg16/32-word doubleword integer register, word doubleword integer value memory defined modR/M byte mreg8-byte integer register byte integer value memory defined modR/M byte reg8-byte integer register defined instruction byte(s) bits modR/M byte Software Environment Chapter
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reg16/32-word doubleword integer register defined instruction byte(s) bits modR/M byte
Opcode Bytes ModR/M Byte
second third columns list applicable opcode bytes. fourth column lists modR/M byte when used instruction. modR/M byte defines instruction register memory form. modR/M bits documented (memory form), only 10b, 00b. fifth column lists type instruction decode short, long, vector. AMD-K6-2E processor decode logic process short, long, vector decode clock. sixth column lists type RISC86 operation(s) required instruction. operation types corresponding execution units follows:
Decode Type
RISC86 Operation
alu-either integer execution units alux-integer execution unit only branch-branch condition unit float-floating-point execution unit limm-load immediate, instruction control unit load, fload, mload-load unit meu-Multimedia execution units 3DNow! instructions store, fstore, mstore-store unit
Table Integer Instructions
Instruction Mnemonic
mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8
First Byte
Second Byte
ModR/M Byte
Decode RISC86 Type Operations
vector vector vector vector
11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
vector vector vector vector vector vector
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Table Integer Instructions (continued)
Instruction Mnemonic
reg16/32, mreg16/32 reg16/32, mem16/32 imm8 EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8 EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8
First Byte
Second Byte
ModR/M Byte
11-xxx-xxx mm-xxx-xxx
Decode RISC86 Type Operations
vector vector vector vector
11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
vector vector vector vector vector vector short long short long short short short short short short alux load, alux, store load, alu, store alux load, alux load, alux alux load, alux, store load, alu, store alux load, alux, store alux load, alux, store load, alu, store alux load, alux load, alux
11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
short long short long short long short long short long short short short short short
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Table Integer Instructions (continued)
Instruction Mnemonic
EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) ARPL mreg16, reg16 ARPL mem16, reg16 BOUND reg16/32, mreg16/32 reg16/32, mem16/32 reg16/32, mreg16/32 reg16/32, mem16/32 BSWAP BSWAP BSWAP BSWAP BSWAP BSWAP BSWAP BSWAP mreg16/32, reg16/32 mem16/32, reg16/32 mreg16/32, imm8 mem16/32, imm8 mreg16/32, reg16/32 mem16/32, reg16/32 mreg16/32, imm8 mem16/32, imm8 mreg16/32, reg16/32 mem16/32, reg16/32 mreg16/32, imm8 mem16/32, imm8 mreg16/32, reg16/32
First Byte
Second Byte
ModR/M Byte
11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-xxx-xxx mm-xxx-xxx
Decode RISC86 Type Operations
short short long short long short long vector vector vector vector vector vector vector long long long long long long long long alux load, alux, store load, alu, store alux load, alux, store
11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
11-xxx-xxx mm-xxx-xxx 11-100-xxx mm-100-xxx 11-xxx-xxx mm-xxx-xxx 11-111-xxx mm-111-xxx 11-xxx-xxx mm-xxx-xxx 11-110-xxx mm-110-xxx 11-xxx-xxx
vector vector vector vector vector vector vector vector vector vector vector vector vector
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Table Integer Instructions (continued)
Instruction Mnemonic
mem16/32, reg16/32 mreg16/32, imm8 mem16/32, imm8 CALL full pointer CALL near imm16/32 CALL mem16:16/32 CALL near mreg32 (indirect) CALL near mem32 (indirect) CBW/CWDE CLTS mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8 EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) CMPSB mem8, mem8 CMPSW mem16, mem32 CMPSD mem32, mem32 CMPXCHG mreg8, reg8 CMPXCHG mem8, reg8
First Byte
Second Byte
ModR/M Byte
mm-xxx-xxx 11-101-xxx mm-101-xxx
Decode RISC86 Type Operations
vector vector vector vector short store
11-011-xxx 11-010-xxx mm-010-xxx
vector vector vector vector vector vector vector
11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
vector vector short short short short short short short short short short 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx short short short short long long vector vector vector alux load, alux load, alux load, alux load, alux alux load, alux load, load, load,
11-xxx-xxx mm-xxx-xxx
vector vector
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Table Integer Instructions (continued)
Instruction Mnemonic
CMPXCHG mreg16/32, reg16/32 CMPXCHG mem16/32, reg16/32 CMPXCHG8B EDX:EAX CMPXCHG8B mem64 CPUID CWD/CDQ EDX, mreg8 mem8 mreg16/32 mem16/32 mreg8 mem8 EAX, mreg16/32 EAX, mem16/32 IDIV mreg8 IDIV mem8 IDIV EAX, mreg16/32 IDIV EAX, mem16/32 IMUL reg16/32, imm16/32 IMUL reg16/32, mreg16/32, imm16/32 IMUL reg16/32, mem16/32, imm16/32 IMUL reg16/32, imm8 (sign extended) IMUL reg16/32, mreg16/32, imm8 (signed) IMUL reg16/32, mem16/32, imm8 (signed) IMUL mreg8
First Byte
Second Byte
ModR/M Byte
11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
Decode RISC86 Type Operations
vector vector vector vector vector vector vector vector short short short short short short short short load, alux, store load, alu, store
11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-110-xxx mm-110-xxx 11-110-xxx mm-110-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-101-xxx
vector long vector long vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector
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Table Integer Instructions (continued)
Instruction Mnemonic
IMUL mem8 IMUL EDX:EAX, EAX, mreg16/32 IMUL EDX:EAX, EAX, mem16/32 IMUL reg16/32, mreg16/32 IMUL reg16/32, mem16/32 imm8 imm8 EAX, imm8 EAX, mreg8 mem8 mreg16/32 mem16/32 INVD INVLPG short disp8 JB/JNAE short disp8 short disp8 JNB/JAE short disp8 JZ/JE short disp8 JNZ/JNE short disp8 JBE/JNA short disp8 JNBE/JA short disp8 short disp8 short disp8
First Byte
Second Byte
ModR/M Byte
mm-101-xxx 11-101-xxx mm-101-xxx
Decode RISC86 Type Operations
vector vector vector vector vector vector vector vector vector vector vector short short short short short short short short load, alux, store load, alu, store
11-xxx-xxx mm-xxx-xxx
11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx mm-111-xxx
vector long vector long vector vector short short short short short short short short short short branch branch branch branch branch branch branch branch branch branch
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Table Integer Instructions (continued)
Instruction Mnemonic
JP/JPE short disp8 JNP/JPO short disp8 JL/JNGE short disp8 JNL/JGE short disp8 JLE/JNG short disp8 JNLE/JG short disp8 JCXZ/JEC short disp8 near disp16/32 near disp16/32 JB/JNAE near disp16/32 JNB/JAE near disp16/32 JZ/JE near disp16/32 JNZ/JNE near disp16/32 JBE/JNA near disp16/32 JNBE/JA near disp16/32 near disp16/32 near disp16/32 JP/JPE near disp16/32 JNP/JPO near disp16/32 JL/JNGE near disp16/32 JNL/JGE near disp16/32 JLE/JNG near disp16/32 JNLE/JG near disp16/32 near disp16/32 (direct) disp32/48 (direct) disp8 (short) mreg32 (indirect) mem32 (indirect) near mreg16/32 (indirect) near mem16/32 (indirect) LAHF reg16/32, mreg16/32 reg16/32, mem16/32 reg16/32, mem32/48 reg16/32, mem16/32
First Byte
Second Byte
ModR/M Byte
Decode RISC86 Type Operations
short short short short short short vector branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch
short short short short short short short short short short short short short short short short short vector short 11-101-xxx mm-101-xxx 11-100-xxx mm-100-xxx vector vector vector vector vector vector vector vector short
11-xxx-xxx mm-xxx-xxx mm-xxx-xxx mm-xxx-xxx
load,
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Table Integer Instructions (continued)
Instruction Mnemonic
LEAVE reg16/32, mem32/48 reg16/32, mem32/48 LGDT mem48 reg16/32, mem32/48 LIDT mem48 LLDT mreg16 LLDT mem16 LMSW mreg16 LMSW mem16 LODSB mem8 LODSW mem16 LODSD EAX, mem32 LOOP disp8 LOOPE/LOOPZ disp8 LOOPNE/LOOPNZ disp8 reg16/32, mreg16/32 reg16/32, mem16/32 reg16/32, mem32/48 mreg16 mem16 mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 mreg16, segment mem16, segment segment reg, mreg16 segment reg, mem16 mem8 EAX, mem16/32
First Byte
Second Byte
ModR/M Byte
mm-xxx-xxx
Decode RISC86 Type Operations
long vector vector vector vector vector vector vector vector vector long long long short vector vector load, load, load, alu, branch load, alu,
mm-011-xxx 11-010-xxx mm-010-xxx 11-100-xxx mm-100-xxx mm-010-xxx
11-xxx-xxx mm-xxx-xxx mm-xxx-xxx 11-011-xxx mm-011-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
vector vector vector vector vector short short short short short short short short long vector vector vector short short load load alux store store alux load load load
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Table Integer Instructions (continued)
Instruction Mnemonic
mem8, mem16/32, imm8 imm8 imm8 imm8 imm8 imm8 imm8 imm8 EAX, imm16/32 ECX, imm16/32 EDX, imm16/32 EBX, imm16/32 ESP, imm16/32 EBP, imm16/32 ESI, imm16/32 EDI, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 MOVSB mem8,mem8 MOVSD mem16, mem16 MOVSW mem32, mem32 MOVSX reg16/32, mreg8 MOVSX reg16/32, mem8 MOVSX reg32, mreg16 MOVSX reg32, mem16 MOVZX reg16/32, mreg8 MOVZX reg16/32, mem8 MOVZX reg32, mreg16 MOVZX reg32, mem16 mreg8 mem8
First Byte
Second Byte
ModR/M Byte
Decode RISC86 Type Operations
short short short short short short short short short short short short short short short short short short store store limm limm limm limm limm limm limm limm limm limm limm limm limm limm limm limm limm store limm store load, store, alux, alux load, store, alu, load, store, alu, load, load, load, load,
11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx
short long short long long long long
11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-100-xxx mm-100-xxx
short short short short short short short short vector vector
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Table Integer Instructions (continued)
Instruction Mnemonic
EAX, mreg16/32 EAX, mem16/32 mreg8 mem8 mreg16/32 mem16/32 (XCHG EAX, EAX) mreg8 mem8 mreg16/32 mem16/32 mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8 EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) imm8, imm8, imm8,
First Byte
Second Byte
ModR/M Byte
11-100-xxx mm-100-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
Decode RISC86 Type Operations
vector vector short vector short vector short short vector short vector short long short long short short short short short short alux load, alux, store load, alu, store alux load, alux load, alux alux load, alux, store load, alu, store alux load, alux, store limm alux alux
11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx
short long short long short long vector vector vector vector vector vector vector vector
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Table Integer Instructions (continued)
Instruction Mnemonic
mreg 16/32 16/32 POPA/POPAD POPF/POPFD PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH imm8 PUSH imm16/32 PUSH mreg16/32 PUSH mem16/32 PUSHA/PUSHAD PUSHF/PUSHFD
First Byte
Second Byte
ModR/M Byte
Decode RISC86 Type Operations
vector vector vector short short short short short short short short load, load, load, load, load, load, load, load, load, load, store,
11-000-xxx mm-000-xxx
short long vector vector long vector
load, store
vector vector vector long short short short short short short short short long long 11-110-xxx mm-110-xxx vector long vector vector load, store load, store store store store store store store store store store store
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Table Integer Instructions (continued)
Instruction Mnemonic
mreg8, imm8 mem8, imm8 mreg16/32, imm8 mem16/32, imm8 mreg8, mem8, mreg16/32, mem16/32, mreg8, mem8, mreg16/32, mem16/32, mreg8, imm8 mem8, imm8 mreg16/32, imm8 mem16/32, imm8 mreg8, mem8, mreg16/32, mem16/32, mreg8, mem8, mreg16/32, mem16/32, near imm16 near imm16 mreg8, imm8 mem8, imm8 mreg16/32, imm8 mem16/32, imm8 mreg8, mem8, mreg16/32,
First Byte
Second Byte
ModR/M Byte
11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx
Decode RISC86 Type Operations
vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector
11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx
vector vector vector vector vector vector vector
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Table Integer Instructions (continued)
Instruction Mnemonic
mem16/32, mreg8, mem8, mreg16/32, mem16/32, mreg8, imm8 mem8, imm8 mreg16/32, imm8 mem16/32, imm8 mreg8, mem8, mreg16/32, mem16/32, mreg8, mem8, mreg16/32, mem16/32, SAHF mreg8, imm8 mem8, imm8 mreg16/32, imm8 mem16/32, imm8 mreg8, mem8, mreg16/32, mem16/32, mreg8, mem8, mreg16/32, mem16/32, mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8
First Byte
Second Byte
ModR/M Byte
mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx
Decode RISC86 Type Operations
vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector short vector short vector short vector short vector short vector short vector vector vector vector vector vector alux alux alux
Chapter
Software Environment
Preliminary Information AMD-K6TM-2E Processor Data Sheet
22529B/0-January 2000
Table Integer Instructions (continued)
Instruction Mnemonic
reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8 EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) SCASB mem8 SCASW mem16 SCASD EAX, mem32 SETO mreg8 SETO mem8 SETNO mreg8 SETNO mem8 SETB/SETNAE mreg8 SETB/SETNAE mem8 SETNB/SETAE mreg8 SETNB/SETAE mem8 SETZ/SETE mreg8 SETZ/SETE mem8 SETNZ/SETNE mreg8 SETNZ/SETNE mem8 SETBE/SETNA mreg8 SETBE/SETNA mem8 SETNBE/SETA mreg8 SETNBE/SETA mem8 SETS mreg8 SETS mem8 SETNS mreg8 SETNS mem8 SETP/SETPE mreg8
First Byte
Second Byte
ModR/M Byte
mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
Decode RISC86 Type Operations
vector vector vector vector vector
11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx
vector vector vector vector vector vector vector vector vector
11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx
vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector
Software Environment
Chapter
22529B/0-January 2000
AMD-K6TM-2E Processor Data Sheet
Table Integer Instructions (continued)
Instruction Mnemonic
SETP/SETPE mem8 SETNP/SETPO mreg8 SETNP/SETPO mem8 SETL/SETNGE mreg8 SETL/SETNGE mem8 SETNL/SETGE mreg8 SETNL/SETGE mem8 SETLE/SETNG mreg8 SETLE/SETNG mem8 SETNLE/SETG mreg8 SETNLE/SETG mem8 SGDT mem48 SIDT mem48 SHL/SAL mreg8, imm8 SHL/SAL mem8, imm8 SHL/SAL mreg16/32, imm8 SHL/SAL mem16/32, imm8 SHL/SAL mreg8, SHL/SAL mem8, SHL/SAL mreg16/32, SHL/SAL mem16/32, SHL/SAL mreg8, SHL/SAL mem8, SHL/SAL mreg16/32, SHL/SAL mem16/32, mreg8, imm8 mem8, imm8 mreg16/32, imm8 mem16/32, imm8 mreg8, mem8, mreg16/32, mem16/32, mreg8, mem8,
First Byte
Second Byte
ModR/M Byte
mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx mm-000-xxx mm-001-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx
Decode RISC86 Type Operations
vector vector vector vector vector vector vector vector vector vector vector vector vector short vector short vector short vector short vector short vector short vector short vector short vector short vector short vector short vector alux alux alux alux alux alux
Chapter
Software Environment
Preliminary Information AMD-K6TM-2E Processor Data Sheet
22529B/0-January 2000
Table Integer Instructions (continued)
Instruction Mnemonic
mreg16/32, mem16/32, SHLD mreg16/32, reg16/32, imm8 SHLD mem16/32, reg16/32, imm8 SHLD mreg16/32, reg16/32, SHLD mem16/32, reg16/32, SHRD mreg16/32, reg16/32, imm8 SHRD mem16/32, reg16/32, imm8 SHRD mreg16/32, reg16/32, SHRD mem16/32, reg16/32, SLDT mreg16 SLDT mem16 SMSW mreg16 SMSW mem16 STOSB mem8, STOSW mem16, STOSD mem32, mreg16 mem16 mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8 EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32
First Byte
Second Byte
ModR/M Byte
11-101-xxx mm-101-xxx
Decode RISC86 Type Operations
short vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector long long long store, alux store, alux store, alux
11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-000-xxx mm-000-xxx 11-100-xxx mm-100-xxx
11-001-xxx mm-001-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
vector vector short long short long short short short short short short alux load, alux, store load, alu, store alux load, alux load, alux alux load, alux, store
11-101-xxx mm-101-xxx 11-101-xxx
short long short
Software Environment
Chapter
22529B/0-January 2000
AMD-K6TM-2E Processor Data Sheet
Table Integer Instructions (continued)
Instruction Mnemonic
mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) SYSCALL SYSRET TEST mreg8, reg8 TEST mem8, reg8 TEST mreg16/32, reg16/32 TEST mem16/32, reg16/32 TEST imm8 TEST EAX, imm16/32 TEST mreg8, imm8 TEST mem8, imm8 TEST mreg16/32, imm16/32 TEST mem16/32, imm16/32 VERR mreg16 VERR mem16 VERW mreg16 VERW mem16 WAIT WBINVD XADD mreg8, reg8 XADD mem8, reg8 XADD mreg16/32, reg16/32 XADD mem16/32, reg16/32 XCHG reg8, mreg8 XCHG reg8, mem8 XCHG reg16/32, mreg16/32 XCHG reg16/32, mem16/32 XCHG EAX, XCHG EAX, XCHG EAX, XCHG EAX, XCHG EAX, XCHG EAX,
First Byte
Second Byte
ModR/M Byte
mm-101-xxx 11-101-xxx mm-101-xxx
Decode RISC86 Type Operations
long short long vector vector load, alu, store alux load, alux, store
11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
short vector short vector long long
alux alux alux load, alux load,
11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-100-xxx mm-100-xxx 11-101-xxx mm-101-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-100-xxx mm-100-xxx 11-101-xxx mm-101-xxx
long long long long vector vector vector vector vector vector vector vector vector vector vector vector vector vector short long long long long long
limm alu, alu, alu, alu, alu, alu, alu, alu, alu, alu,
Chapter
Software Environment
Preliminary Information AMD-K6TM-2E Processor Data Sheet
22529B/0-January 2000
Table Integer Instructions (continued)
Instruction Mnemonic
XCHG EAX, XCHG EAX, XLAT mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8 EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.)
First Byte
Second Byte
ModR/M Byte
Decode RISC86 Type Operations
long long vector alu, alu, alu, alu, alux load, alux, store load, alu, store alux load, alux load, alux alux load, alux, store load, alu, store alux load, alux, store
11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
short long short long short short short short short short
11-110-xxx mm-110-xxx 11-110-xxx mm-110-xxx 11-110-xxx mm-110-xxx
short long short long short long
Table Floating-Point Instructions
Instruction Mnemonic
F2XM1 FABS FADD ST(0), ST(i)1 FADD ST(0), mem32real FADD ST(i), ST(0)
First Byte
Second Byte
ModR/M Byte
Decode RISC86 Type Operations
short short float float float fload, float float fload, float float
11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-100-xxx mm-110-xxx
short short short short short vector vector short vector
FADD ST(0), mem64real FADDP ST(i), ST(0) FBLD FBSTP FCHS FCLEX
float
Software Environment
Chapter
22529B/0-January 2000
AMD-K6TM-2E Processor Data Sheet
Table Floating-Point Instructions (continued)
Instruction Mnemonic
FCOM ST(0), ST(i)1 FCOM ST(0), mem32real FCOM ST(0), mem64real FCOMP ST(0), ST(i)1 FCOMP ST(0), mem32real FCOMP ST(0), mem64real FCOMPP FCOS FDECSTP FDIV ST(0), ST(i) (single precision)
First Byte
Second Byte
ModR/M Byte
11-010-xxx mm-010-xxx mm-010-xxx 11-011-xxx mm-011-xxx mm-011-xxx
Decode RISC86 Type Operations
short short short short short short short short short float fload, float fload, float float fload, float fload, float float float float float float float float float float fload, float fload, float float float float fload, float fload, float float float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float
11-011-001
11-110-xxx 11-110-xxx 11-110-xxx 11-111-xxx 11-111-xxx 11-111-xxx mm-110-xxx mm-110-xxx 11-111-xxx 11-110-xxx 11-111-xxx mm-111-xxx mm-111-xxx 11-110-xxx 11-000-xxx mm-000-xxx mm-000-xxx mm-010-xxx mm-010-xxx mm-011-xxx mm-011-xxx mm-110-xxx mm-110-xxx mm-111-xxx
short short short short short short short short short short short short short short short short short short short short short short short short
FDIV ST(0), ST(i) (double precision)1 FDIV ST(0), ST(i) (extended precision)1 FDIV ST(i), ST(0) (single precision)1 FDIV ST(i), ST(0) (double precision)1 FDIV ST(i), ST(0) (extended precision)1 FDIV ST(0), mem32real FDIV ST(0), mem64real FDIVP ST(0), ST(i)
FDIVR ST(0), ST(i)1 FDIVR ST(i), ST(0)1 FDIVR ST(0), mem32real FDIVR ST(0), mem64real FDIVRP ST(i), ST(0) FFREE ST(i)1 FIADD ST(0), mem32int FIADD ST(0), mem16int FICOM ST(0), mem32int FICOM ST(0), mem16int FICOMP ST(0), mem32int FICOMP ST(0), mem16int FIDIV ST(0), mem32int FIDIV ST(0), mem16int FIDIVR ST(0), mem32int
Chapter
Software Environment
Preliminary Information AMD-K6TM-2E Processor Data Sheet
22529B/0-January 2000
Table Floating-Point Instructions (continued)
Instruction Mnemonic
FIDIVR ST(0), mem16int FILD mem16int FILD mem32int FILD mem64int FIMUL ST(0), mem32
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