VCXO-Based Frame Clock Frequency Translator MK2059-01 VCXO (Volta

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VCXO-Based Frame Clock Frequency Translator MK2059-01 VCXO (Volta

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MK2059-01
VCXO-Based Frame Clock Frequency Translator
MK2059-01 VCXO (Voltage Controlled Crystal Oscillator) based clock generator that produces common telecommunications reference frequencies. output clock phase locked 8kHz (frame rate) input reference clock. MK2059-01 also provides jitter attenuation. Included selection output frequencies these common system clocks: 1.544 (T1) 19.44 (OC-3) 2.048 (E1) 16.384
Features
Generates OC-3 other common telecom
clock frequencies from 8kHz frame clock Configurable jitter attenuation characterisitics, excellent Stratum source de-jitter circuit Input input reference clocks VCXO-based clock generation offers very jitter phase noise generation Output clock phase frequency locked selected input reference clock Fixed input output phase relationship +115ppm minimum crystal frequency pullability range, using recommended crystal Industrial temperature range power CMOS technology SOIC package Single 3.3V power supply
This monolithic combined with external inexpensive quartz crystal, used replace more costly hybrid VCXO retiming module. Through selection external loop filter components, loop bandwidth damping factor tailored meet input clock jitter attenuation requirements. loop bandwidth down range possible.
Block Diagram
ullable
etecto harg
ivid
eedb ivid
CHGP
2059-01
Revision 071001
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
Assignment
Output Clock Selection Table
Input SEL2 SEL1 SEL0 Output Clock (MHz) 1.544 2.048 16.384 17.664 18.528 20.00 25.00 25.92 19.44 20.48 24.704 24.576 Crystal Used (MHz) 24.704 24.576 16.384 17.664 18.528 20.00 25.00 25.92 19.44 20.48 24.704 24.576
SOIC
Note: input programming: GND, VDD, Floating
Descriptions
Number
Name
CHGP ISET SEL2 SEL1 SEL0 ICLK2 ICLK1 ISEL
Type
Power Power Power Input Power Power Power Output Input Input Input Output Input Input Input Input Power
Crystal Input. Connect this specified crystal. Power Supply. Connect +3.3V. Power Supply. Connect +3.3V. Power Supply. Connect +3.3V. VCXO Control Voltage Input. Connect this CHGP external loop filter shown this data sheet. Connect ground Connect ground Connect ground Charge Pump Output. Connect this external loop filter VIN. Charge pump current setting node, connection setting resistor. Output Frequency Selection Determines output frequency table above. Internally biased VDD/2. Output Frequency Selection Determines output frequency table above. Internal pull-up. Internal Connection. Clock Output Output Frequency Selection Determines output frequency table above. Internal pull-up. Input Clock Connection Connect input reference clock this pin. unused, connect ground. Input Clock Connection Connect input reference clock this pin. unused, connect ground. Input Selection. Used select which reference input clock active. input level selects ICLK1, high input level selects ICLK2. Internal pull-up. Connect ground. Crystal Output. Connect this specified crystal.
2059-01
Revision 071001
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
Functional MK2059-01 clock generator that generates output clock directly from internal VCXO circuit which works conjunction with external quartz crystal. VCXO controlled internal (Phase Locked Loop) circuit, enabling device perform clock regeneration from input reference clock. MK2059-01 configured provide communications reference clock output from 8kHz input clock. There selectable output frequencies. Please refer Output Clock Selection Table Page Most typical clock devices internal (Voltage Controlled Oscillator) output clock generation. using VCXO with external crystal, MK2059-01 able generate jitter, phase-noise output clock within bandwidth PLL. This serves provide input clock jitter attenuation enables stable operation with frequency reference clock. VCXO circuit requires external pullable crystal operation. External loop filter components enable configuration with loop bandwidth.
Quartz Crystal
important that correct type quartz crystal used with MK2059-01. Failure result reduced frequency pullability range, inability loop lock, excessive output phase jitter. MK2059-01 operates phase-locking VCXO circuit input signal selected ICLK input. VCXO consists external crystal integrated VCXO oscillator circuit. achieve best performance reliability, crystal device with recommended parameters (shown below) must used, layout guidelines discussed Layout Recommendations section must followed. frequency oscillation quartz crystal determined external load capacitance. MK2059-01 incorporates variable load capacitors on-chip which "pull", change, frequency crystal. crystals specified with MK2059-01 designed have zero frequency error when total on-chip stray capacitance 14pF. achieve this, layout should short traces between MK2059-01 crystal. complete description recommended crystal parameters shown below.
Application Information
Output Frequency Configuration
MK2059-01 configured generate output frequencies from 8kHz input clock. Please refer Output Clock Selection Table Page Input bits SEL2:0 according this table, external crystal frequency. Please refer Quartz Crystal section this page regarding external crystal requirements.
Recommended Crystal Parameters: Operating Temperature Range Commercial Applications Industrial Applications Initial Accuracy 25°C Temperature Stability Aging Load Capacitance Shunt Capacitance, C0/C1 Ratio Equivalent Series Resistance 70°C 85°C Note
Input
Input serves select between alternate input reference clocks. Upon reselection input clock, clock glitches output clock will generated "fly-wheel" effect VCXO (the quartz crystal high-Q tuned circuit). When input clocks phase aligned, phase output clock will change reflect phase newly selected input controlled phase slope (rate phase change) influenced loop characteristics.
Note crystal frequencies between 13.5MHz 27MHz nominal crystal load capacitance specification should 14pF. Contact MicroClock applications (408) 297-1201 regarding crystal below 13.5MHz. obtain list qualified crystal devices that meet these requirements, please contact MicroClock applications department.
2059-01
Revision 071001
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
Loop Filter Components
analog circuits loop filter establish operating stability. MK2059-01 uses external loop filter components following reasons: Larger loop filter capacitor values used, allowing lower loop bandwidth. This enables lower input clock reference frequencies also input clock jitter attenuation capabilities. Larger loop filter capacitors also allow higher loop damping factors when less passband peaking desired. loop filter values user selected optimize loop response characteristics given application. Referencing External Component Schematic this page, external loop filter made components RSET establishes charge pump current therefore influences loop filter characteristics.
External Component Schematic
tuff efer ptional stal uning section)
Xtal
Recommended Loop Filter Values Output Frequency Range Selection
Crystal
SEL2 SEL1 SEL0 Multiplier
RSET
Loop Bandwidth
(-3dB point)
Damping Factor
3088 3072 2048 2208 2316 2500 3125 3240 2430 2560 3088 3072
Note: input programming: GND, VDD, Floating
2059-01
Revision 071001
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
"normalized" loop bandwidth calculated follows: "normalized" bandwidth equation above does take into account effects damping factor second pole. However, does provide useful approximation filter performance. loop damping factor calculated follows: Damping Factor Where: Value resistor loop filter (Ohms) Charge pump current (amps) (refer Charge Pump Current Table, below) Crystal multiplier shown above table Value capacitor loop filter (Farads) general rule, following relationship should maintained between components loop filter:
loop capacitors should low-leakage type avoid leakage-induced phase noise. this reason, type polarized electrolytic capacitors. Microphonics (mechanical board vibration) also induce output phase noise, especially when loop bandwidth less than 1kHz. this reason, ceramic capacitors should have dielectric. Avoid high-K dielectrics like X7R. These some other ceramics have piezoelectric properties that convert mechanical vibration into voltage noise that interferes with VCXO operation. larger loop capacitor values such film types made Panasonic, metal poly types made Murata Cornell Dubilier recommended. questions changes regarding loop filter characteristics, please contact your sales area FAE, MicroClock Applications.
Series Termination Resistor
Clock output traces over inch should series termination. series terminate trace commonly used trace impedance), place resistor series with clock line, close clock output possible. nominal impedance clock output (The optional series termination resistor shown External Component Schematic.)
Decoupling Capacitors
with high performance mixed-signal MK2059-01 must isolated from system power supply noise perform optimally. Decoupling capacitors 0.01µF must connected between each ground plane. further guard against interfering system supply noise, MK2059-01 should common connection power plane shown diagram next page. ferrite bead bulk capacitor help reduce lower frequency noise supply that lead output clock phase modulation.
Charge Pump Current Table
RSET Charge Pump Current (ICP)
Special considerations must made choosing loop components
2059-01
Revision 071001
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
Recommended Power Supply Connection Optimal Device Performance
onnection 3.3V lane Ferrite
should trace ground via. Distance ferrite bead bulk decoupling from device less critical. loop filter components must also placed close CHGP pins. should closest device. Coupling noise from other system signal traces should minimized keeping traces short away from active signal traces. vias should avoided. external crystal should mounted just next device with short traces. traces should routed next each other with minimum spaces, instead they should separated away from other traces. minimize series termination resistor, needed, should placed close clock output. optimum layout with components same side board, minimizing vias through other signal layers (the ferrite bead bulk decoupling capacitor mounted back). Other signal traces should routed away from MK2059-01. This includes signal traces just underneath device, layers adjacent ground plane layer used device. Applications Note MAN05 also referenced additional suggestions layout crystal section.
ecoupling apacitor (such Tantalum
0.01 ecoupling apacitors
Crystal Load Capacitors
device crystal connections should include pads small capacitors from ground from ground, shown External Component Schematic. These capacitors used adjust stray capacitance board match nominally required crystal load capacitance. Because load capacitance only increased this trimming process, important keep stray capacitance minimum using very short traces (and via's) been crystal device. most cases load capacitors will required. They should stuffed prototype evaluation board indiscriminate these trim capacitors will typically cause more crystal centering error than their absence. need load capacitors later determined, values will fall within range. need for, value these trim capacitors only determined prototype evaluation. Please refer Optimization Crystal Load Capacitors section more information.
Optimization Crystal Load Capacitors
concept behind optional crystal load capacitors introduced previously this data sheet (see Crystal Load Capacitor section Page determine need value these capacitors, will need your final layout, frequency counter capable less than resolution accuracy, power supplies, some samples crystals which plan production, along with measured initial accuracy each crystal specified crystal load capacitance, determine value crystal capacitors: Connect 3.3V. Connect second power supply. Adjust voltage Measure record frequency output.
Layout Recommendations
optimum device performance lowest output phase noise, following guidelines should observed. Please also refer Recommended Layout drawing Page Each 0.01µF decoupling capacitor should mounted component side board close possible. via's should used between decoupling capacitor pin. trace should kept short possible,
2059-01
Revision 071001
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
Adjust voltage 3.3V. Measure record frequency same output. calculate centering error:
3.0V Error error xtal
much stray capacitance will need redone with layout reduce stray capacitance. Alternately, crystal re-specified higher lower load capacitance. Contact MicroClock details. centering error more than positive, identical fixed centering capacitors from each crystal ground. value each these caps given External Capacitor (centering error)/(trim sensitivity) Trim sensitivity parameter which supplied your crystal vendor. know value, assume ppm/pF. After changes, repeat measurement verify that remaining error acceptably (less than ±15ppm).
Where: ftarget nominal crystal frequency errorxtal =actual initial accuracy ppm) crystal being measured centering error less than ppm, adjustment needed most applications. centering error more than negative,
Recommended Layout
clock jitte ithin this tire othe traces from
clock jitte evice ctio bulk ling evice (see xt).
ectio
2059-01
Revision 071001
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
Absolute Maximum Ratings
Stresses above ratings listed below cause permanent damage MK2059-01. These ratings, which standard values commercially rated parts, stress ratings only. Functional operation device these other conditions above those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability. Electrical parameters guaranteed only over recommended operating temperature range.
Item
Supply Voltage, Inputs Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature
Rating
-0.5V VDD+0.5V +85°C +150°C 175°C 260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured respect GND)
Min.
+3.15
Typ.
+3.3
Max.
+3.45
Units
Electrical Characteristics
Unless stated otherwise, 3.3V ±5%, Ambient Temperature +85°C
Parameter
Operating Voltage Supply Current Input High Voltage, SEL2 Input Voltage, SEL2 Input High Voltage, ISEL, SEL1:0 Input Voltage, ISEL, SEL1:0 Input High Voltage, ICLK1, Input Voltage, ICLK1, Input High Current Input Current Input Capacitance, except
Symbol
Conditions
Clock outputs unloaded, 3.3V
Min.
3.15
Typ.
Max.
3.45
VDD/2-1
Units
VDD-0.5
VDD/2+1
2059-01
Revision 071001
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
Parameter
Output High Voltage (CMOS Level) Output High Voltage Output Voltage Short Circuit Current VIN, VCXO Control Voltage Nominal Output Impedance
Symbol
ZOUT
Conditions
Min.
VDD-0.4
Typ.
Max.
Units
Electrical Characteristics
Unless stated otherwise, 3.3V ±5%, Ambient Temperature +85°
Parameter
VCXO Crystal Pull Range VCXO Crystal Nominal Frequency Input Jitter Tolerance Input pulse width Output Frequency Error Output Duty Cycle high time) Output Rise Time Output Fall Time Skew, Input Output Clock Cycle Jitter (short term jitter) Timing Jitter, Filtered 500Hz-1.3MHz (OC-3) Timing Jitter, Filtered 65kHz-1.3MHz (OC-3)
Symbol
FOUT
Conditions
Using Recommended Crystal
Min.
-115 13.5
Typ.
Max. Units
+115
reference input clock period ICLK error Measured VDD/2, CL=15pF 2.0V, CL=15pF 0.8V, CL=15pF Rising edges, CL=15pF Referenced Mitel/Zarlink MT9045, Note Referenced Mitel/Zarlink MT9045, Note
Note Minimum high time input clock. Note Input reference output from Mitel/Zarlink MT9045 device freerun mode (SEL2:0 100, 19.44 external crystal).
2059-01
Revision 071001
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com
MK2059-01 VCXO-Based Frame Clock Frequency Translator
Package Outline Package Dimensions SOIC, Mil. Wide Body)
Package dimensions kept current with JEDEC Publication
Millimeters Symbol Inches
Index
-2.65 1.10 -2.05 2.55 0.33 0.51 0.18 0.32 12.60 13.00 7.40 7.60 1.27 Basic 10.00 10.65 0.25 0.75 0.40 1.27
-0.104 0.0040 -0.081 0.100 0.013 0.020 0.007 0.013 0.496 0.512 0.291 0.299 0.050 Basic 0.394 0.419 0.010 0.029 0.016 0.050
Ordering Information
Part Order Number
MK2059-01SI MK2059-01SITR
Marking
MK2059-01SI MK2059-01SI
Shipping packaging
Tubes Tape Reel
Package
SOIC SOIC
Temperature
+85° +85°
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments.
2059-01
Revision 071001
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 295-9800 www.icst.com

VCXO-Based Frame Clock Frequency Translator MK2059-01 VCXO (Volta

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