Communications Edition 2001-04-06 Published Infineon Technologies

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Communications Edition 2001-04-06 Published Infineon Technologies

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Reconfigurable IPAC-X 21150, ISAC-SX 3086, ISAC-SX 3186 SBCX-X 3081
Communications
Edition 2001-04-06 Published Infineon Technologies St.-Martin-Strasse D-81541 Germany
Infineon Technologies 2001.
Rights Reserved. Attention please! information herein given describe certain components shall considered warranted characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Infineon Technologies approved CECC manufacturer. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office Germany Infineon Technologies Representatives worldwide (see address list). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
Reconfigurable IPAC-X 21150, ISAC-SX 3086, ISAC-SX 3186 SBCX-X 3081
Communications
Revision History: Previous Version: Page
2001-04-06 01.96
Subjects (major changes since last revision)
questions technology, delivery prices please contact Infineon Technologies Offices Germany Infineon Technologies Companies Representatives worldwide: webpage http://www.infineon.com
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Table Contents 1.8.1 1.8.2 1.10 1.11 2.4.1 Page
Non-Reconfigureable ISDN Modes IOM-2 Clock Generation with Reference Clock Hand-Over Determining Parameter Adaptive IOM-2 Interface IOM-2 Connected Interface D-Channel HDLC controller output Host Interface Selection Register Access Initialization Monitor Channel Normal Interchip Connection Inverse Interchip Connection Safe Input/Outputs Transceiver State Machine Status C/I0 Handler Commands Disabling Reconfigureable Avoiding External DU/DD Multiplexers Time Slot Alignment Register setting Re-configurable Reconfigurable with Monitor Channel Control Register setting Reconfigurable PBX, Controlled Monitor Handler
Application Note
2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Non-Reconfigureable
Non-Reconfigureable
This type (private branch exchange) very common. This contains S/Tinterfaces switching D-channel controller unit. This unit contains often complex functions there conference calls switching with minimum constant delay. D-channel controller central D-channel control. typical structure this type shown Figure
External Lines (Upstream) Counter SCLK
SBCX-X LT-T
SBCX-X LT-T
Switching Unit D-Channel PCM_output Controllers
PCM_input
SBCX-X LT-S
SBCX-X LT-S
SBCX-X LT-S
Internal Lines (Downstream)
SBCX-X (Serial Controlled Interface)
MicroController
SBCX-X PBX.EMF
Figure
Block diagram non-reconfigurable
Every S-transceiver pinstrapped LT-S LT-T mode (hardwired configuration). lines hardwired connected way, that pure input/output lines characteristic switching HDLC unit met.
ISDN Modes IOM-2 Clock Generation with
SBCX-X work LT-T mode serve upstream lines (external S0-interfaces). Three SBCX-X LT-S mode operate downstream terminals (internal S0interfaces). SBCX-X pinstrapped into appropriated ISDN mode (hardwired M0/M1 inputs). Every SBCX-X works different IOM-2 channel. avoid collisions IOM2 IOM-2 channel hardwired selected (AUX0.2). Therefore every SBCX-X four time slots within IOM-channel.
Application Note 2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Non-Reconfigureable Only SBCX-X LT-T mode generates reference clock whole PBX. This reference clock (SCLK) selected mutliplexer goes through frequency multiplier PLL. This generates 4096 clock SBCX-X (also SBCX-X LT-T mode). With 4096 clock eight IOM-2 channels used. always necessary, that IOM-2 synchronous S-interface. S-interface connected activated), SCLK derived from quartz crystal directly. possible save components, buffered crystal clock output C768 used SBCX-X's XTAL1 inputs. whole work with single crystal then. Please refer Figure
IPAC 21150
SCLK XTAL1
LT-T mode
IPAC 21150
SCLK XTAL1
LT-T mode
4096kHz
(without PLL)
Counter (:192)
1536kHz
Counter (:512)
IPAC 21150
SCLK
LT-T mode
C768
IOM-2 7.68 S-Transceiver LT-S mode
Figure
reference clock (SCLK) selected IOM-2 interface
frequency multiplier used, should derived from output derived from SCLK signal directly. Otherwise edge would synchronous PLL-generated frequency, settled. sampled with falling edge DCL/BCL clock inside SBCX-X could affect S-bus timing SBCX-X LT-S/T mode.
Application Note
2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Non-Reconfigureable
Reference Clock Hand-Over
Every SBCX-X LT-T mode generates SCLK. SCLK absolutely synchronous S-interface S-line activated). phase between these SCLK's common (rising edge) different each SBCX-X, because S0-line length central office (CO) different (refer Figure generated dividing 1536 SCLK frequency external frequency multiplier used.
SR1-SR2 (S-Bus, LT-T No.1)
SCKL1 (IOM-2 Bus)
SR1-SR2 (S-Bus, LT-T No.2)
Phase Shift
SCKL2 (IOM-2 Bus)
Figure
Each SBCX-X LT-T mode operate with different phase shift.
example (Figure Figure both LT-T S-lines activated. SCLK signal LT-T no.1 clock reference whole PBX. Assuming, that line LT-T no.1 must deactivated, because on-hook now. SCLK multiplexer select LT-T no.2, this external S0-interface just activated. microcontroller detect this situation select alternative SCLK reference clock whole (No. here). changing SCLK source phase shift given (maximum phase shift 180°, that's 1536 kHz) expect, that will take some time until adjusted phase SCLK source (one frame might provide 125.325 124.675 therefore).
Application Note 2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Non-Reconfigureable
Determining Parameter
external must provide clock clock with specific quality. output frequency must range average over long time interval about second (because rate test, TBR3 chapter 9.2.1). Note, that frequency used generate S0-frames SBCX-X LT-S mode. code practice very accurate clock generators flywheel mode. jitter should less than +/-25 cycle (DCL input duty cycle: 25%.75%). number clocks frame constant. Often pure SCLK multiplexer cannot used, because could generate spikes drop outs PLL. over sweep exceed limits. Therefore first reference clock switched afterwards SCLK source switched input synchronously. This avoids such critical spikes drop outs. side effect that external running fly-wheel mode (free running) during this hand-over. Because frequency normally equal reference clock from central office side, PBX-internal clocks start wander (the reference always master clock central office side). Therefore Stransceivers LT-T mode needs have 'maximum allowed wander'. Stransceiver must able read/write from/to IOM-2 bus, even there wander. Condition after power-on after 'SLIP' detected allowed Wander area -62,5 .+187,5 -187,5 µs.+62,5 -125 .+125
maximum allowed wander between S-interface IOM-2 125µs. phase shift exceeds this allowed wander limit 'SLIP' generated transceiver (CI0-Indication '0011'). Data lost 'SLIP' occured. After 'SLIP' detected, internal wander buffers re-aligned (refer table above).
Application Note
2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Non-Reconfigureable
Adaptive IOM-2 Interface
IOM-2 interface S-transceiver adaptive. S-transceiver counts always number clock cycles within frame. Derived from this number counts number time slots bit) choosen automatically stored internally. difference between expected number counts number measured counts more than cycles adapts number time slots automatically. consecutive frames with same number cycles must measured before number time slots adapted. With every rising edge time slot adaption going valid. Table Clock input frequencies LT-S, LT-T mode clock input 1024 1536 2048 2560 3072 3584 4096 clock input 1024 1280 1536 1792 2048
frequency multiple kHz. clock used clock frequency multiple kHz. clock input pin, IOM_CR.CLKM must set.
Application Note
2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Non-Reconfigureable
IOM-2 Connected Interface
Figure shows hardwired configuration. LT-S mode line outputs B1+B2+D channel data, whereas LT-T mode line input transceiver data. Therefore line SBCX-X LT-S mode connected directly input switching unit (inclusive D-channel controllers). output connected line SBCX-X LT-T mode. Figure internal structure SBCX-X shown. C/I0 handler outputs command DD-line LT-S mode only). This command addresses state machine transceiver, this command also visible channel IOM-2 interface. transceiver outputs indication line LT-S, mode). This means C/I0 time slot both, output.
SBCX-X
Monitor Handler Transceiver output Handler Transceiver Mon0 outp. MON0 outp. C/I0 Mon0
LT-S
Transceiver input down down
Mon0 outp.
inp. C/I0 outp
down
Mon0 outp.
MON0
C/I0
C/I0 Handler
IOM-
SBCX-X
Monitor Handler Transceiver input Mon0 MON0
Mon0 outp.
inp. outp. down
C/I0 C/I0 outp. C/I0
Mon0
Handler
Transceiver output
Mon0 outp.
TE/LT-T
Transceiver
down
down
MON0
IOM-
C/I0 Handler
SBCX outp2.emf
Figure
Bidirectional IOM-2 Interface
avoid collisions C/I0 time slots IOM-2 interface must switched transparently B1+B2+D time slots only. This possible with SDS_CONF.DIOM_SDS SDSx_CR registers. With SDSx_CR time slots selected bit; TS+1, TS+3) with DIOM_SDS IOM2 interface made transparently selected time slots only.
Application Note 2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Non-Reconfigureable
SBCX-X
Monitor Handler Transceiver output Handler Transceiver LT-S Mon0 outp. MON0
Mon0 outp.
outp. C/I0
Mon0
Transceiver input down down
inp. C/I0 outp
down
Mon0 outp.
MON0
C/I0
IOM-
C/I0 Handler
SDS_CONF 0x04 SDS1_CR 0xE0
Transceiver output
MON0
outp.
C/I0
Transceiver input down down
inp.
down
C/I0
MON0
Pure PCM.emf
Figure Table
Every SBCX-X transparent Channel only Example: SBCX-X LT-S mode, SDS_CONF=0x04 SDS1_CR 0xEE
SBCX-X LT-T mode, SDS_CONF=0x04 SDS1_CR 0xE0
Application Note
2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Non-Reconfigureable
D-Channel HDLC controller output
Every SBCX-X LT-T mode provides also (Stop/Go) output. output default cycles) pulse going active D-channel time slot transceiver IOM-2 interface valid. polarity output inverted with TR_CONF2.SGP bit. length output pulse increased cycle length (125 setting TR_CONF2.SGD ISAC-SX used: this effect internal D-HDLC controller). Generally output block appropriate D-HDLC controller. This means, that D-HDLC controller already transmit command from software, DHDLC controller waits until goes "GO". This necessary, because upstream S-Bus D-channel occupied terminal connected parallel (bus configuration, point-to-point configuration). Therefore evaluation must enabled with TR_MODE2.DIM2.0 bits SBCX-X used: MODED.DIM2.0).
Host Interface Selection
SBCX-X controlled serial microcontroller interface (SCI). During reset host interface selected following way: 'low' (permanently) 'high' (permanently) Note: This setting taken over with rising edge. Alternatively possible Siemens/Intel multiplexed mode. this case, host interface selected following way: Levels during hardware reset: 'toggling' (all combinations allowed, '0') 'high' (permanently) 'edge' (any transition 'high low' 'low high')
Note: ALE-edge happen also reset pulse inactive already. host interface selected Siemens/Intel Non-Multiplexed (ALE low) Motorola (ALE high) until single edge detected. ALE-edge detected this host interface selection remains stored.
Application Note
2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Non-Reconfigureable
1.8.1
Register Access Initialization Monitor Channel Normal Interchip Connection
monitor channel used save wiring. necessary rout whole parallel microcontroller interface S-transceivers. example below (Figure shows minimum configuration. SBCX-X LT-S mode monitor master, second S-transceiver pinstrapped stand-alone mode. Both chips pinstrapped into different IOM-channels order avoid collisions D-and CI-channels. Automatically with IOM-Channel selection (AUX0.2 pinstrapping) MON_CR.CH2.0 bits loaded with '000' '001'. Also monitor handler output direction identically both chips. Therefore necessary register MON_CR 0x81 (DPS IOMChannel monitor master).
IOM-2 Interface
Internal S-Bus
SBCX-X LT-S
SBCX-X TE/LT-T
Monitor Handler
Monitor Handler Stand-alone
External S-Bus
Parallel Serial interface
MON_CR.DPS
pinstrapped
Controller
Memory (Flash)
B1.1 B2.1 Mon0
B1.2 B2.2 Mon1
B1.3
B2.3
Mon2
Monitor Channel Variante1.emf
LT-S
B1.1 B2.1 Mon0
LT-T
B1.2 B2.2 Mon1
B1.3 B2.3
Mon2
Figure
Terminal Adapter: left Monitor Master, right Monitor Slave
third S-transceiver connected same way, monitor master monitor channel third S-transceiver (MON_CR 0x8n)
Application Note 2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Non-Reconfigureable
1.8.2
Inverse Interchip Connection
with switching unit HDLC controllers some S-transceivers lines connected line other S-transceivers. Therefore monitor handler monitor master programmed each S-transceiver individually.
External Lines (Upstream) SBCX-X LT-T No.5
Counter
SCLK
stand-alone
stand-alone
SBCX-X LT-T No.4
Switching Unit D-Channel Controllers
PCM_input PCM_output
pinstrapped
stand-alone
SBCX-X LT-S No.3
SBCX-X LT-S No.2
stand-alone
SBCX-X LT-S No.1
Internal Lines (Downstream)
MicroController
MON_CR.DPS No.2, No.3 MON_CR.DPS No.4, No.5
B1.1 B2.1 Mon0
B1.2 B2.2 Mon1
B1.3
B2.3
Mon2
Monitor Channel Variante2.emf
B1.1 B2.1 Mon0
B1.2 B2.2 Mon1
B1.3
B2.3
Mon2
Figure
PBX: Monitor Master, four monitor slaves
monitor control register programmed following way: Table Example mixed interchip connection Pinstrapped IOM-Channel MON_CR.DPS MON_CR Monitor Monitor Slave Master (No.1) (default) (default) (default) (default) 0x81 0x82 0x83 0x84
S-transceiver
Application Note
2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Non-Reconfigureable
Safe Input/Outputs
spite S-transceivers manufactured technique, inputs safe. This means maximum input voltage must exceed additional pullup resistors between environment necessary, because input output levels S-transceivers compatible.
3,3V
C161
IPAC-X ISAC-SX ISAC-SX SBCX-X
Pull resistors necessary
safe inputs.emf
safe inputs levels levels
Figure
Direct connection environment
1.10
Transceiver State Machine Status
There exist ways indications from transceiver state machine, CIR0 register (CI-Indications), other reading TR_STA register. TR_STA register shows, whether transceiver synchronous (FSYN what info-message currently detected (RINF). This information also available CI-Indications, together with TR_STA might easier write control software. Also TR_CMD register read order information, what infomessage transceiver actually transmits. Note: default possible overwrite TR_CMD.XINF values. This would only make sense, internal hardwired state machine disabled with TR_CONF0.L1SW (not necessary normal operation). With L1SW transceiver sends '1111' CI-Indication always.
Application Note 2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Non-Reconfigureable
1.11
C/I0 Handler Commands Disabling
LT-S/T mode necessary disable bus, because used mode only block chip-internal D-HDLC controller. important MODED.DIM1 Table (disabled TIC) (disabled TIC) MODED.DIM1 necessary IOM_CR.DIS_TIC (default) (default) (disabled TIC) (disabled TIC) D-HDLC transmission possible possible Need CIX0 setting CODX0.1110 CODX0.xxxx CODX0.1110 CODX0.xxxx
MODED.DIM1
Note: Table valid ISAC-SX, ISAC-SX IPAC-X C/I0 handler time slot automatically aligned with IOM-2 channel selection (pinstrapping with AUX0.2). Please attention fact, that commands given first internal IOM-bus (can monitored IOM-2 interface pins) then transceiver state machine (please refer Figure Both handler transceiver follow 'double-last-look' criteria, meaning command/indication only accepted command/indication remains least IOM-2 frames (250µs) valid. Please attention fact, that external IOM-2 connected device could overdrive commands/indications could disturb activation process. IOM_CR.DIS_TIC frequency 1536 frequency kHz, only independent ISDN mode). internal IOM-handler detect this frequency time slots) enables TS11 automatically. TS11 should used general purpose time slot, necessary DIS_TIC '1'. Note: D-channel driven external device, '1's used bits, which collide with indications/commands.
Application Note
2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Reconfigureable
Reconfigureable
also possible build free configurable PBX. This means, every SBCX-X configurated LT-S LT-T software. structure this type quite similar non-reconfigurable PBX, needs additionally DU/DD line multiplexer each SBCX-X. This multiplexers necessary, because D-channel S-transceiver cannot change data port selection (output DD).
Switching Unit (DSP, ASIC, D-HDLC Controller
LT-S mode
LT-S mode
LT-S mode
LT-T mode
S-Transceiver LT-T Mode
S-Transceiver
LT-S Mode
S-Transceiver
LT-S Mode
S-Transceiver
LT-S Mode
PCMin_out.emf
Figure
Reconfigurable with DU/DD-MUX (only DU/DD shown)
With SBCX-X DU/DD multiplexers omitted, because DU/DD swapping internally done every SBCX-X Please compare IOM-2 wiring non-reconfigurable (Figure with IOM-2 wiring reconfigurable Figure
Application Note
2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Reconfigureable
Avoiding External DU/DD Multiplexers
Herewith shown avoid DU/DD multiplexers (SW1.SW4). principle this solution shown Figure
(CH2) (CH2) TS11 (D-Channel switched
LT-T
Stop/Go output
PCM_output PCM_input
Switching Unit (ASIC, DSP) D-HDLC Controller
LT-S
(CH1) (CH1) (internal TS7)
IOM-Interface transparent only (TS0,1) (TS2) (CH0) (CH0) (internal TS3)
LT-S
Transceiver D-channel
CDA-Handler
Transceiver
Prinzip.emf
Figure
Reconfigurable
After power-on, every SBCX-X configured LT-T mode AUX0.2 pinstrapping IOM-2 channel selected automatically. Every SBCX-X, that should work LT-S mode, programmed above shown way. transceiver input/output data easy swap from Dchannel transceiver input/output cannot swapped transceiver itself. Therefore necessary handler switching D-channel data into another time slot whereby DU/DD swapped. IOM-2 interface switched transparently switched D-channel time slot only. This avoids conflicts with interface allows also push/pull driver IOM-2 interface.
Application Note 2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Reconfigureable
Time Slot Alignment
Time slot (TS3) contains usually D-Channel time slot (from/to transceiver) 4bit time slot CI0-handler line. line transceiver outputs 4bit CI-indications. D-channel time slot switched from (into Monitor0 channel), CI-indication transceiver also switched from (always bits switched). Also would overwrite commands transceiver, handler shifted next free IOM-2 channel. Therefore TRC_CR DCI_CR registers used avoid such problems.
IOM_CR 0x28, TRC_CR 0x01 (Transceiver Indication)
CDA_TSDP10 0x02 CDA_TSDP11 0x03 CDA1_CR 0x1F
IOM-2 Interface transparent
(CI0 Commands) IOM_CR 0x08, DCI_CR 0x81
Shifted D-Channel.emf
Figure
Internal DU/DD swapping SBCX-X LT-S mode
Every SBCX-X LT-S mode must reprogrammed similar way. D-channel from/to terminal side delayed IOM-frame (125 because Dchannel switching. Note: external D-HDLC controller output data, like 'DDxx.xxxx'. necessary, that bits beside D-channel must filled with '111111'. Note: DCI_CR TRC_CR registers used, necessary fill DHDLC controller output data with 'DD11.1111'.
Application Note 2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Reconfigureable
Register setting Re-configurable
-Internal DU/DD swapping time slots Example IOM-2-Channel Select LT-S mode (all SBCX-X after reset LT-T mode) TR_MODE 0x03; Select LT-S mode CI0-Handler automatically CI-transceiver-indication Transceiver input output Swap (Transceiver output TR_TSDP_BC1 0x00; TR_TSDP_BC2 0x01; Disable Monitor Handler empty MON_CR 0x00; Monitor Channel used, disabled
Shift Handler into next free IOM-2-Channel IOM_CR 0x18; DCI_CR 0x81; CI_CS disabled. C/I0 handler output input programmed Shift Tranceiver-CI-Output next free IOM-2-Channel TR_CR 0xF8; IOM_CR 0x38; TRC_CR 0x01; Transceiver-D-channel programmed CI_CS (TS7 occupied) C/I0 indications transceiver from (TS7) Switch CDA_TSDP10 0x02; this register CDA_TSDP11 0x03; this register CDA1_CR 0x1F; Switch
Application Note
2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Reconfigureable
IOM-2-Interface transparent only SDS_CONF 0x40; SDS1_CR 0xC0; SDS2_CR 0x12; Activate SDS-data strobe DU/DD TS0, transparent transparent.
Application Note
2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Reconfigureable
Reconfigurable with Monitor Channel Control
this case D-channel cannot switched into monitor channel, because monitor time slot used register access. Therefore D-channel must switched into other time slot, e.g. from TS(x+4). This TS(x+4) D-channel time slot next IOM-2 channel. second SBCX-X LT-S mode pinstrapped IOM2 channel appropriated D-Channel (TS7) switched into TS11. This possible, because every SBCX-X transparent appropriated IOM-2 channel only.
IOM_CR.CI_CS TR_CR 0xF9
Trans. Input
Trans. Output
Mon0
Mon1
Mon2
TR_TSDP_BC1 0x00 TR_TSDP_BC2 0x01
CDA_TSDP10 0x03 CDA_TSDP11 0x07 CDA1_CR 0x1F
IOM_CR.CI_CS TRC_CR 0x02
Trans. Output Trans. Input
Mon0
Mon1
Mon2
IOM-2 Interface transparent only here SDS1_CR 0xC0, SDS2_CR 0xC2, SDS_CONF 0x04
IOM_CR.CI_CS DCI_CR 0xA2
pinstrapped (hardwired into CH0)
Transceiver input down down
Mon0 inp. MON0
Mon0 outp. down
Mon0
function
outp.
1111
Mon0 outp.
Transceiver output
MON0
function
Figure
IOM-2/PCM time slot alignment Monitor Channel Control: principle time slot structure after re-programming
2001-04-06
Application Note
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Reconfigureable register programming each IOM-2 channel (SBCX-X) works steps: Step Step Swap output direction transceiver Shift D-channel input/output transceiver CIindication (output) transceiver into CHpinstrapped+1. This done with IOM_CR.CI_CS TR_CR '1111.1xxx' (xxx CHpinstrapped+1). Shift CI-indication transceiver into IOM-2 channel, CHpinstrapped CHpinstrapped+1. example CHpinstrapped+2. (CI_CS TRC_CR 0x02) This step necessary avoid handler access conflicts. Shift commands CHpinstrapped IOM-2 channel where CI-indications transceiver located. example also (CI_CS DCI_CR 0xA2) Switch D-channel time slots. Make IOM-2 interface transparent CHpinstrapped only.
Step
Step
Step Step
Note: TS3/DU filled with '111111' beside D-channel information. This avoids overwriting monitor information does affect MR/MX control. IOM-2 interface programmed push/pull left open-drain mode (with external pull-up resistors).
Application Note
2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Reconfigureable
2.4.1
Register setting Reconfigurable PBX, Controlled Monitor Handler
-Internal DU/DD swapping time slots Example IOM-Channel ATTENTION: External D-HDLC Controller have fill 8-bit time slot with '1's avoid conflicts with commands MR/MX monitor handling. Select LT-S mode (all SBCX-X after reset LT-T mode) TR_MODE 0x03; Select LT-S mode CI0-Handler automatically CI-transceiver-indication Transceiver input output Swap (Transceiver output input TR_TSDP_BC1 0x00; TR_TSDP_BC2 0x01; Shift D/CI-Channel Transceiver into IOM_CR 0x08; TR_CR 0xF9; CI_CS enabled D-Transceiver CI-Transceiver
Shift CI-Channel Transceiver (indications) into IOM_CR 0x28; TRC_CR 0x02; CI_CS D-Channel Transceiver into only
Shift CI-Handler (commands) into IOM_CR 0x08; DCI_CR 0xA2; CI_CS C/I-Handler
Switch CDA_TSDP10 0x03; this register
Application Note 2001-04-06
IPAC-X, ISAC-SX, ISAC-SX SBCX-X
Reconfigureable
CDA_TSDP11 0x07; this register CDA1_CR 0x1F; Switch
IOM-Interface transparent time slots) only SDS_CONF 0x40; SDS1_CR 0xC0; SDS2_CR 0xC2; Activate SDS-data strobe DU/DD TS0, transparent (both B-Channels) TS3, transparent.
Application Note
2001-04-06
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Communications Edition 2001-04-06 Published Infineon Technologies

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