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Quartus Version 2000.09 Dramatically Improves fMAX Compile Times
Quartussoftware version 2000.09 includes PowerFitfitter that delivers average faster fMAX faster compile times designs targeting APEXEP20K400E larger devices. This PowerFit fitter technology optimizes designs based user's timing specifications meets design requirements with only minimal user effort. Figure shows design performance enhancements compile time reductions achieved with PowerFit technology. charts Figure demonstrate these improvements over design compiled using random assignments Quartus software versions 2000.05 Service Pack 2000.09. With each release, Quartus software consistently improved compile times. Figure page highlights compile time improvements designs targeting high-density devices. continued page
Figure Median Design Performance Relative Compile Time Improvement Device
Quartus Software Versions 2000.05 2000.09
Normalized
EP20K400E EP20K600E EP20K1000E
Inside This Issue:
APEX 20KC Devices with AllLayer Copper Interconnect Enhance Internal Performance 35%, ARM- MIPS-Based Excalibur Products Provide IndustyLeading Performance Flexibility,
Normalized Compile Times
EP20K100E EP20K300E EP20K400E Altera Corporation
Fourth Quarter 2000 M-NV-Q400-01
EP20K200E News Views
EP20K600E EP20KE1000E
Table
Contents
APEX 20KE Production Devices 5.0-V Tolerant APEX APEX 20KE Devices APEX Product Transition ACEX Devices Shipping Now. Broad Range FineLine Packages Available Devices 7000B Industrial-Grade Availability 7000AE Devices Migrate Advanced Process High-Density Configuration Devices Coming Soon Quartus Version 2000.09 MAX+PLUS Version 10.0 Available Operating System Update Quartus Roadmap MAX+PLUS BASELINE, E+MAX ASAP2 Version 10.0 Available Download Latest Synthesis Simulation Tools Technical Articles Designing Switches Routers with APEX LVDS Timing Analysis Questions Answers Every Issue Altera Publications Current Software Versions Altera Programming Support Contact Altera. Altera Device Selection Guide
Features Quartus Version 2000.09 Dramatically Improves fMAX Compile Times APEX 20KC Devices with All-Layer Copper Interconnect Enhance Internal Performance ARM- MIPS-Based Excalibur Products Provide Industry-Leading Performance Flexibility Design Tips: Designing Memory-Mapped Peripherals Nios Embedded Processor. Customer Application: OMEGA-TECHNOLOGIES S.A.: APEX Device Doubles Processing Power Signal Processing Application Contributed Article: Multi-Channel, Full-Duplex ADPCM Solutions from APEX, ACEX FLEX Devices Altera News 7000B: Standards High-Speed Applications 7000B Devices Outperform Competition EPM7128 Celebrates Million Units. Devices Tools Discontinued Devices Update Introducing APEX 20KC Devices APEX 20KE Devices Shipping LVDS Support Available IndustrialSpeed-Grade Devices
Altera, ACCESS, ACEX, ACEX AMPP, APEX, APEX 20K, APEX 20KC, APEX 20KE, Atlas, BitBlaster, ByteBlaster, ByteBlasterMV, Classic, ClockBoost, ClockLock, ClockShift, CoreSyn, E+MAX, Excalibur, FastTrack, FineLine BGA, FLEX, FLEX 10K, FLEX 10KE, FLEX 10KA, FLEX 8000, FLEX 6000, FLEX 6000A, MegaStore, Jam, MasterBlaster, MAX, 9000, 9000A, 7000, 7000E, 7000S, 7000A, 7000AE, 7000B, 3000, 3000A, MAX+PLUS, MAX+PLUS MegaCore, MegaLAB, MegaStore, MegaWizard, MultiCore, MultiVolt, NativeLink, Nios, nSTEP, OpenCore, OptiFLEX, PowerFit, Quartus, SignalTap, SignalTap Plus, True-LVDS, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: Adobe Acrobat registered trademarks Adobe Systems Incorporated. AMBA, ARM, Powered logo registered trademarkes Limited. Microsystems registered trademark Microsystems. Data UniSite registered trademarks Data Corporation. HP-UX trademark Hewlett-Packard Company. Mentor Graphics registered trademark LeonardoSpectrum ModelSim trademarks Mentor Graphics. Microsoft, Windows, Windows Windows registered trademarks Microsoft Corporation. R4000, 4Kc, MIPS32, MIPS-based, MIPS Technologies logo trademarks MIPS Technologies, Inc. Rochester Electronics registered trademark Rochester Electronics, Inc. registered trademark Solaris trademark Microsystems, Inc. Synplicity registered trademark Amplify Physical Optimizer trademarks Synplicity, Inc. Synopsys registered trademark FPGA Express trademark Synopsys, Inc. System General registered trademark System General. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. actual availability Altera's products features could differ from those projected this publication provided solely estimate reader. Copyright 2000 Altera Corporation. rights reserved.
Rhonda Scott, Publisher Greg Steinke, Technical Editor Innovation Drive Jose, 95134 Tel: (408) 544-7000 Fax: (408) 544-7809 n_v@altera.com
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Features Quartus Version 2000.09 Dramatically Improves fMAX Compile Times, continued from page With previous versions Quartus software, high-density designs took longer compile Solaris platforms. Quartus software version 2000.09 eliminates this problem through Solaris compiler optimization. Quartus software version 2000.09 Solaris offers compile times over faster than version 2000.02. Compile times Quartus software version 2000.09 Solaris only longer than compile times (SPECint normalized account performance differences UNIX-based processor architectures).
2000.02 2000.05 2000.09
Figure EP20K600E EP20K1000E Device Compile Times
Normalized Compile Times
Quartus Software Releases
Reduced Memory Requirements
minimum physical required compile high-density APEX devices drops significantly with Quartus software version 2000.09. Quartus software version 2000.05 required 1,331 Mbytes compile large EP20K1000E EP20K1500E devices. Quartus software version 2000.09 enables mainstream using Windows compile designs largest APEX 20KE devices without this high memory requirement. Table lists memory requirements Quartus software version 2000.09.
Table Quartus 2000.09 Memory Requirements Device
EP20K30E EP20K60E EP20K100E EP20K160E EP20K200E
PowerFit Technology Improves Device Fitting
PowerFit technology dramatically enhances stability fitter well device fitting, particularly highest density APEX 20KE devices. This enhancement allows designers larger designs into given APEX device.
UNIX Installation Compile Time Improvements
addition PowerFit technology improvements, Quartus software version 2000.09 includes database technology developed Altera. This database technology simplifies installation UNIX environments reduces UNIX-specific compile time bottlenecks. Figure shows UNIX compile time improvements.
Figure UNIX Compile Time Improvement
Minimum Physical
Mbytes
EP20K300E EP20K400E EP20K600E EP20K1000E
Mbytes
Normalized Compile Times
1,024 Mbytes
EP20K1500E
UNIX
2000.02 2000.05 2000.09
HP-UX 11.0 Support Available
Quartus development tool available both HP-UX 11.0 10.2 operating systems. HP-UX versions software included Altera's standard software shipments. have active FLOATNET subscription would like receive
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Quartus Software Releases
Features Quartus development tool HP-UX, fill on-line request form Altera site http://www.altera.com/hpux, software will sent you.
Third-Party Integration Enhancements
Top-level block design schematic files converted VHDL Verilog design files using Quartus software version 2000.09. VHDL Verilog output files processed third-party synthesis simulation tools. Quartus software version 2000.09 also facilitates encrypted Altera intellectual property (IP) MegaCore® functions through third-party synthesis tools produce optimal results. more information these features, visit Altera site http://www.altera.com.
Timing Analysis Enhancements
Quartus software version 2000.09 includes timing analysis enhancements that make easier analyze circuits with complex clocking structures well specify multicycle path relationships. Quartus software version 2000.09 optimizes support thirdparty simulation timing analysis tools creating distinct VHDL Verilog verification netlists Standard Delay Format Files (.sdo) targeted specific third-party tools.
APEX 20KC Devices with All-Layer Copper Interconnect Enhance Internal Performance
APEX20KC devices first programmable logic devices (PLDs) with alllayer copper metal interconnect, providing performance advantage over 0.18-µm-based devices using aluminum interconnect (see Figure
Figure Relative Interconnect Delay
APEX 20KC devices provide feature comparable APEX 20KE devices, including content-addressable memory (CAM), True-LVDScircuitry, advanced clock management. These features make APEX 20KC devices industry-leading, high-density device high-end system-on-a-programmable-chip (SOPC) solutions.
0.15-µm all-layer copper interconnectbased APEX 20KC devices offer performance improvement over 0.18-µm-based devices.
All-Layer Copper Interconnect
Breakthroughs semiconductor performance have been primarily transistor fabrication. However, advanced processes, large portion chip delays routing structure delays, transistors. Therefore, significant performance enhancements achieved replacing aluminum-which traditionally used routing structures-with superior conductor electricity that significantly decreases routing delays increases overall system performance. continued page
Normalized Interconnect Delay
0.18-µm Aluminum Interconnect
0.15-µm Copper Interconnect
Because relatively small routing delays with copper, APEX 20KC devices support high-bandwidth needs advanced networking standards that exist communication marketplace.
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Features APEX 20KC Devices with All-Layer Copper Interconnect Enhance Internal Performance 35%, continued from page primary benefit using copper interconnect layers improved internal performance. example, APEX 20KC devices with all-layer copper interconnect technology provide performance advantage over aluminum interconnects found APEX 20KE devices (see Figure faster interconnect increases operating frequencies designs. layers power planes, while bottom layers performance-critical interconnect layers. Figure shows crosssection these interconnect layers. Copper layer only does offer significant performance increase because these power layers have major impact performance. fact, using copper layers will create silicon/copper design challenges without providing significant performance benefits. Only all-layer copper interconnect, including performance-critical bottom layers, will lead significant performance advantage.
largest APEX 20KC device will have million system gates more than user pins.
All-Layer Copper Interconnect Partial Copper Interconnect
All-layer copper interconnect technology uses copper metal layers. Partial copper interconnect copper layers only.
Figure APEX 20KC Device Performance Advantage
APEX 20KC Process Technology
APEX 20KC devices will fabricated state-of-the-art 0.15-µm, 8-layer metal process with copper interconnect. This more advanced process technology all-layer copper interconnect will provide significant performance advantages over APEX 20KE devices.
Normalized
APEX 20KC Device Offering Features
APEX 20KE Devices APEX 20KC Devices
APEX 20KC devices will continue Altera's leadership density user pins.
Figure Cross-Section Interconnect Layers
Power Planes
Performance-Critical Interconnects
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Features largest APEX 20KC device will have million system gates more than user pins. Table outlines APEX 20KC device features. APEX 20KC devices will have many same features APEX 20KE devices, including True-LVDS circuitry, CAM, phase-locked loops (PLLs), advanced standards. True-LVDS Support APEX 20KC devices will support True-LVDS circuitry megabits second (Mbps), which make them ideal advanced network protocols that require high data transfer rates. Content Addressable Memory APEX 20KC devices will support applications embedded system blocks (ESBs). copper interconnect APEX 20KC devices will further reduce access times make highspeed applications possible Altera devices without external chips. Advanced feature support, high density, fast performance make APEX 20KC devices ideal SOPC applications. APEX 20KC devices will support True-LVDS circuitry, CAM, PLLs, advanced standards. Phase-Locked Loops APEX 20KC PLLs will offer higher operating frequency ranges than APEX 20KE PLLs. Advanced Standards APEX 20KC devices will support APEX 20KE advanced standards, including HSTL, GTL+, SSTL.
Software Support Device Availability
APEX 20KC devices will supported Altera's industry-leading Quartussoftware 2000. Devices will available first half 2001.
Table APEX 20KC Device Overview Device
EP20K100C EP20K200C EP20K400C EP20K600C EP20K1000C EP20K1500C
Maximum System Gates
263,000 526,000 1,052,000 1,537,000 1,772,000 2,392,000
Logic Elements (LEs)
4,160 8,320 16,640 24,320 38,400 51,840
Maximum Bits
53,248 106,496 212,992 311,296 327,680 442,368
PLLs
Speed Grades
Note: speed grade fastest speed grade.
Discontinued Devices Update
Altera distributes advisories (ADVs) product discontinuance notices (PDNs) that provide information discontinued devices. obtain copy specific PDN, contact your local Altera® sales representative. Selected ADVs, PDNs, complete listing discontinued devices also available Altera's site http://www.altera.com. Rochester Electronics, after-market supplier, offers many discontinued Altera products. Contact Rochester Electronics (978) 462-9332 their site http://www.rocelec.com.
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Features
ARM- MIPS-Based Excalibur Products Provide Industry-Leading Performance Flexibility
Altera's Excaliburembedded microprocessorbased products first industry combine design flexibility programmable logic with high-performance embedded processors, large on-chip SRAM memory arrays, peripherals that essential systemlevel design. Altera licensed both MIPS324Kcprocessor core from MIPS® Technologies ARM922 core from ARM® Ltd., most widely used instruction architectures embedded systems market. These cores eliminate customer processor licensing per-unit royalties; Altera takes care these business issues offers standard products that customers immediately design faster time-to-market. Altera's ARM-based Excalibur products will available 2001, followed MIPSbased products 2001. Both Excalibur products have hardmacro processor implementations maximum performance will operate 200-MHz processor clock frequencies. Both ARM- MIPS-based Excalibur products include on-chip single port memory Kbytes), dual-port memory Kbytes), external flash memory support Mbytes), SDRAM controller capable supporting Mbytes 133-MHz (PC133) external memory Mbytes 266-MHz (PC266) double data rate (DDR) external memory.
Table ARM- MIPS-Based Excalibur Device Features Feature
Maximum system gates Typical gates Logic elements (LEs) ESBs Maximum bits Maximum macrocells Maximum user pins Single-port SRAM Dual-port SRAM
On-chip peripherals include interrupt controllers, universal asynchronous receiver transmitters (UARTs), general purpose timers, watchdog timers, ETM9 embedded trace module, JTAG support ARM922based products well EJTAG support MIPS 4Kc-based products. Altera's highperformance APEX20KE architecture implemented Excalibur products. Table shows three different Excalibur ARM- MIPS-based product features. advantages both Excalibur hard core products that on-chip processor system buses operate full processor clock frequencies MHz) maximum system bandwidth performance. This enables superior system-level performance. Other conventional, discrete processor-based solutions limited processor system buses that operate half clock frequency system controller chip sets that only offer SDRAM controller support. advanced Excalibur hard core embedded processor products that feature on-chip peripherals support, large on-chip memory arrays, APEX embedded system blocks (ESBs) memory bits, design flexibility time-to-market advantages integrated programmable logic structures makes Excalibur products ideal system-level design.
EPXA1/EPXM1
263,000 100,000 4,160 53,248 Kbytes Kbytes
EPXA4/EPXM4
1,052,000 400,000 16,640 212,992 1,664 Kbytes Kbytes
EPXA10/EPXM10
1,772,000 1,000,000 38,400 327,680 2,560 Kbytes Kbytes
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Figure Excalibur Logic Architecture
Embedded Logic
AHB2 Configuration Logic Configuration
Programmable Logic Device (PLD)
Reset/Mode Controller Clock Generators Processor Cache Trace AHB1 Timer Bridge Interrupt Controller Single Port Watchdog Timer Dual Port AHB2-PLD Bridge Slave(s) PLD-AHB2 Bridge Master(s)
UART SDRAM Controller
Application Interfaces
Expansion (EBI)
Masters Bridges External Devices SDRAM SRAM Memory-Mapped Peripherals Flash
Both Excalibur ARM- MIPS-based products implement advanced microcontroller architecture (AMBATM) high-performance (AHB). This industry-standard architecture capable multiple masters, slave modules, locked transfers, split transactions, frequencies MHz. AMBA used interface between processor stripe, masters, slave modules implemented programmable logic architecture (see Figure processor master simultaneously access different blocks onchip single-port memory on-chip dual-port memory. addition, different system functions (e.g., processor on-chip memory, SDRAM controller peripherals, structure) decoupled from each other through
localized structures driven phaselocked loops (PLLs) different clock domains. AMBA interface used interface with Altera® MegaCore® intellectual property (IP) functions thirdparty Altera Megafunction Partners Program (AMPPSM) partner blocks. Both Excalibur ARM- MIPS-based products fully supported industry-standard realtime operating systems (RTOSs) embedded software tool chains (e.g., compilers, debuggers, assemblers, linkers, loaders). Quartusdevelopment tool used design entry, simulation, synthesis through thirdparty tools, optimized place route designs implemented programmable logic structure.
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Devices
Tools APEX
Introducing APEX 20KC Devices
high-performance APEX20KC devices address high-bandwidth needs system-on-a-programmable-chip (SOPC) applications. These devices combine stateof-the-art features found APEX 20KE devices with industry-leading, 0.15-µm all-layer copper interconnect technology provide performance improvements over 0.18-µm-based devices. more information these APEX devices, "APEX 20KC Devices with All-Layer Copper Interconnect Enhance Performance 35%" page
Table LVDS Support APEX 20KE Devices Device Maximum Data Transfer Rate True-LVDS Channel (Mbps) Commercial Commercial
EP20K300E EP20K400E EP20K600E EP20K1000E EP20K1500E
Industrial
Table Support APEX 20KE Devices Speed Grade
Commercial Commercial Industrial
Maximum Internal Output Frequency from (MHz)
APEX 20KE Devices Shipping
APEX EP20K30E device, smallest APEX 20KE device, shipping. With 30,000 typical gates (113,000 maximum system gates), 1,200 logic elements (LEs), Kbits maximum user pins, this device addresses low-density application needs. APEX 20KE devices shipping: EP20K30E, EP20K60E, EP20K100E, EP20K160E, EP20K200E, EP20K300E, EP20K400E, EP20K600E, EP20K1000E, EP20K1500E. These devices available multiple packages, including advanced Fineline BGApackage.
PLLs offer flexible frequency synthesis zero clock skew capability high-performance design needs. APEX 20KE devices also support LVPECL standard that used highperformance clocking schemes, backplanes, optical transceivers, high-speed networking, high-end video applications.
APEX 20KE Production Devices
APEX 20KE -XES engineering sample devices have changed production speed grade devices. These productionready devices available today packages replace engineering sample devices.
LVDS Support Available Industrial-Speed-Grade Devices
addition offering data transfer rates megabits second (Mbps) commercial temperature grade devices, APEX 20KE devices support LVDS industrial-speed-grade devices. APEX 20KE industrial-grade devices also feature phase-locked loops (PLLs). Table summarizes LVDS support APEX 20KE devices. Table summarizes support APEX 20KE devices. True-LVDSsolution, with data transfer rates high Mbps channel, ideal high-speed telecommunication, data communication, computing applications.
5.0-V Tolerant APEX APEX 20KE Devices
APEX device family been enhanced provide 5.0-V tolerant buffer, providing full compliance with 5.0-V specification. 5.0-V tolerant devices shipping have suffix ordering code (e.g., EP20K400BC652-1V). APEX 20KE devices used with additional external resistor make them 5.0-V
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Devices Tools tolerant provide flexibility system design. details this improvement, 5.0-V Tolerance APEX 20KE Devices White Paper Altera® site (http://www.altera.com).
Table APEX 20KE Device Quartus Software Support Availability Device Package Software Support Availability
APEX Product Transition
Altera migrating 2.5-V EP20K400 device from 0.25-µm process 0.22-µm process. Information regarding this device migration found process change notification (PCN) 0005, available Altera site http://www.altera.com.
ACEX
ACEX Devices Shipping
ACEX1K devices shipping packages 10,000-, 30,000-, 50,000-, 100,000-gate densities (see Table These costoptimized devices especially suited lowcost, high-volume applications used attain lowest cost highvolume designs.
Table ACEX Device Offerings Device
EP1K10
EP20K30E
144-pin TQFP 144-pin FineLine 208-pin PQFP 324-pin FineLine
EP20K60E
144-pin TQFP 144-pin FineLine 208-pin PQFP 240-pin PQFP 324-pin FineLine 356-pin
EP20K100E
144-pin TQFP 144-pin FineLine 208-pin PQFP 240-pin PQFP 324-pin FineLine 356-pin
ACEX devices shipping packages 10,000, 30,000, 50,000, 100.000 gate densities.
Package
100-pin TQFP 144-pin TQFP 208-pin PQFP
Availability
EP20K160E
144-pin TQFP 208-pin PQFP 240-pin PQFP 356-pin 484-pin FineLine
256-pin FineLine EP1K30 144-pin TQFP 208-pin PQFP 256-pin FineLine EP1K50 144-pin TQFP 208-pin PQFP 256-pin FineLine 484-pin FineLine EP1K100 208-pin PQFP 256-pin FineLine 484-pin FineLine
EP20K200E
208-pin PQFP 240-pin PQFP 356-pin 484-pin FineLine 652-pin 672-pin FineLine
EP20K300E
240-pin PQFP 652-pin 672-pin FineLine
EP20K400E
652-pin 672-pin FineLine
EP20K600E
652-pin 672-pin FineLine 1,020-pin FineLine
EP20K1000E 652-pin 672-pin FineLine 1,020-pin FineLine EP20K1500E 652-pin 1,020-pin FineLine
ACEX devices provide full capability ClockLockand ClockBoostfeatures, such embedded dual-port full 64-bit, 66-MHz compliance every speed grade device. Developed costoptimized 0.22-µm/0.18-µm hybrid process, featuring 2.5-V core operating voltage, ACEX devices offer ideal combination cost, performance, features.
Note: TQFP: thin quad flat pack, PQFP: plastic quad flat pack, BGA: ball-grid array.
continued page
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Devices Tools Devices Tools, continued from page Full software support ACEX devices available from MAX+PLUS® software version 10.0. addition, wide range ACEX-optimized intellectual property (IP) functions found Altera MegaStoreon-line store.
Figure Ultra FineLine Package
144-pin TQFP
169-pin Ultra FineLine
Broad Range FineLine Packages Available Devices
MAX® devices available wide range FineLine BGApackaging, including both 1.0-mm pitch (FineLine BGA) 0.8-mm pitch (Ultra FineLine BGA) packages. Table shows FineLine Ultra FineLine packaging options 7000B devices.
Table FineLine Packages Available Devices Device 100-Pin 256-Pin 49-Pin 169-Pin Ultra FineLine FineLine Ultra FineLine FineLine
This variety packages counts offers flexibility choosing device that right your specific application.
7000B Industrial-Grade Availability
Altera offers popular 2.5-V 7000B devices industrial-grades. Table shows which packages available industrial grade. Contact your local Altera sales representative availability lead times specific packages.
Table 7000B Industrial-Temperature Devices Device
EPM7032B EPM7064B
Package
44-pin TQFP 44-pin PLCC 44-pin TQFP 100-pin TQFP
Speed Grade
FineLine packages occupy smaller footprint than traditional TQFP packages offer more pins designer.
EPM7032B EPM7064B EPM7128B EPM7256B EPM7512B EPM7064AE EPM7128AE EPM7256AE EPM7512AE
EPM7128B
100-pin TQFP 100-pin FineLine 144-pin TQFP 256-pin FineLine
EPM7256B
100-pin TQFP 144-pin TQFP 208-pin PQFP 256-pin FineLine
EPM7512B
256-pin 256-pin FineLine
FineLine packages occupy smaller footprint than traditional TQFP packages offer more pins designer. example, Figure shows 169-pin Ultra FineLine package that occupies less than half board space occupied 144-pin TQFP package. EPM7512B device 169-pin FineLine package offers pins compared pins offered 144-pin TQFP package.
7000AE Devices Migrate Advanced Process
7000AE devices will migrate 0.30-µm quad-layer-metal process. This process linear shrink existing 0.35-µm quadlayer-metal process that uses same equipment process flow. These devices will pin-, function-, timing-, programming file-compatible with existing 0.35-µm versions 7000AE devices.
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Devices Tools This transition will begin March 2001. After this date, receive devices from either 0.35-µm 0.30-µm quad-layer-metal processes. additional information regarding this transition, contact your local Altera sales representative. Initial qualification characterization data will available December 2000. Contact Altera's Customer Quality Engineering Manager (408) 544-7563 more details. Table lists devices supported Quartus software version 2000.09.
Table Devices Supported Quartus Software Version 2000.09 Support
Full Compilation, Simulation, EP20K100E
Device
EP20K60E
Package
144-pin FineLine BGA, 324-pin FIneLine BGA, 356-pin 144-pin FineLine 144-pin TQFP, 208-pin RQFP, 240-pin PQFP, 356-pin BGA, 484-pin FineLine
Programming EP20K160E Support
CONFIGURATION
EP20K600E EP20K1500E
1,020-pin FineLine 652-pin BGA, 1,020-pin FineLine
High-Density Configuration Devices Coming Soon
4-Mbit EPC4 16-Mbit EPC16 configuration devices scheduled release January 2001. These devices will include features such faster configuration times reprogrammability. Additionally, single device configure several APEXor FLEX® devices parallel further speed configuration save board space. single EPC16 device will configure 1.5-million-gate EP20K1500E devices using data compression features.
Compilation Simulation Support
EP20K30E
144-pin TQFP, 144-pin FineLine BGA, 208-pin RQFP, 324-pin FineLine BGA, 356-pin
MAX+PLUS software version 10.0 adds support latest 7000B device package combinations adds programming support ACEX EP1K10 devices. Table lists devices supported MAX+PLUS software version 10.0.
Table Devices with Full Support from MAX+PLUS Software Version 10.0
TOOLS
Quartus Version 2000.09 MAX+PLUS Version 10.0 Available
Version 2000.09 Quartusdevelopment tool brings dramatic performance improvements Altera customers. PowerFitfitting technology improves customer design performance decreases compile times depending device density design. more details Quartus software version 2000.09 "Quartus Version 2000.09 Dramatically Improves fMAX Compile Times" feature article page visit Altera site http://www.altera.com.
Device
EPM7032B 44-pin TQFP
Package
49-pin Ultra FineLine
EPM7064B
49-pin Ultra FineLine 100-pin FineLine
EPM7064AE EPM7128B EPM7256B EPM7512B
49-pin Ultra FineLine 49-pin Ultra FineLine 169-pin Ultra FineLine 144-pin TQFP 256-pin 256-pin FineLine 169-pin Ultra FineLine
EP1K10
100-pin TQFP 144-pin TQFP 208-pin PQFP 256-pin
continued page
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Devices Tools Devices Tools, continued from page ASAP2 programmer software version 10.0 available download from Altera site http://www.altera.com. These software programs provide support latest 7000B devices. MAX+PLUS BASELINE software version 10.0 also adds support latest ACEX EP1K10 devices. MAX+PLUS BASELINE E+MAX software customers download license world-class Synopsys FPGA Express software and/or Exemplar Logic LeonardoSpectrumAltera software from Altera site (http://www.altera.com) support synthesis. MAX+PLUS BASELINE MAX+PLUS BASELINE software features seamless development flow that allows designers enter, compile, perform timing analysis designs program wide range Altera PLDs-including ACEX family FLEX 6000, 7000, 3000 devices. MAX+PLUS BASELINE software download file 45,822,459 bytes. E+MAX E+MAX software subset MAX+PLUS BASELINE software targeted industry's most popular product-term architectures-the 7000 3000 devices. E+MAX software longer includes Altera's native VHDL Verilog synthesis, provides access world-class synthesis tools from Exemplar Logic Synopsys Altera site (http://www.altera.com). E+MAX software download file 20,025,630 bytes. ASAP2 ASAP2 software subset MAX+PLUS software that only supports device programming. ASAP2 software download file 13,907,408 bytes. Download files available from Altera site http://www.altera.com.
Operating System Update
Quartus software version 2000.09 MAX+PLUS software version 10.0 both support Windows 2000 operating system. Quartus software version 2000.09 also adds support HP-UX 11.0 operating system. Table shows Quartus MAX+PLUS operating system support.
Table Quartus MAX+PLUS Operating System Support Software
Quartus version 2000.09
Operating System Support
Windows 2000, Windows Windows version higher, Solaris 2.7, HP-UX 10.2x 11.0
next release Quartus software will include software mode allow designers co-design software hardware within Quartus environment.
MAX+PLUS version 10.0
Windows 2000, Windows Windows Windows version higher, Solaris 2.6, HP-UX 10.2x, version higher
Note: Support Solaris will added initial releases 2001.
Quartus Roadmap
next major release Quartus software scheduled 2001. This release will support Altera Excaliburhard core embedded processor solutions include major enhancements that help designers with system-level design issues. addition compilation simulation modes, next release Quartus software will include software mode allow designers co-design software hardware within Quartus environment. This mode will provide capability configure ARM, MIPS, Nios embedded processors their integration with C/C++ compiler tools.
MAX+PLUS BASELINE, E+MAX ASAP2 Version 10.0 Available
MAX+PLUS BASELINE development software, E+MAXdevelopment software,
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Download Latest Synthesis Simulation Tools
customers with active subscription download latest versions synthesis simulation tools Altera includes with software subscriptions. These tools downloaded from Altera site http://www.altera.com. versions include support latest APEX 20KE, ACEX 7000B devices include enhancements improve design flows. LeonardoSpectrum-Altera ModelSimAltera also include support Microsoft
Windows 2000 operating system. Table shows versions available.
Table Synthesis Simulation Tools Tool
Synopsys FPGA Express Exemplar Logic LeonardoSpectrumAltera Model Technology ModelSim-Altera 3.4c 2000.1b
Version
Availability
Design
Tips
Designing Memory-Mapped Peripherals Nios Embedded Processor
Nios embedded processor interfaces memory-mapped peripherals using following signals: irq_from_the_peripheral data_to_cpu_from_the_peripheral address_to_the_peripheral cpu_be_n_to_the_peripheral cpu_read_n_to_the_peripheral cpu_write_n_to_the_peripheral data_from_cpu_to_the_peripheral select_to_the_peripheral Nios embedded processor supplies write enable, read enable, byte enable, chip select, data, address lines peripheral. These signals used read write from register bank within peripheral. register shown Figure page describes example operation each register within register bank. Figure page illustrates register timer peripheral included Excalibur Development Kit. continued page
Niosembedded processor provides high levels integration allowing microprocessor, memory, peripherals, programmable logic reside same device. ExcaliburDevelopment Kit, featuring Nios embedded processor, contains number peripherals, including timer, universal asynchronous receiver/ transmitter (UART), parallel input/ output (PIO). Other peripherals designed interface with Nios embedded processor using memory-mapped techniques. Memory-mapped peripherals provide straightforward interface Nios embedded processor.
Memory-Mapped Peripherals
peripherals that connect Nios embedded processor should designed memory-mapped peripherals. Memorymapped peripherals occupy specific range address space Nios embedded processor. memory-mapped peripheral accessed either reading writing addresses within peripherals' address range.
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Design Tips Designing Memory-Mapped Peripherals Nios Embedded Processor, continued from page
Figure Timer Peripheral Register
A2.A0 Register Name Status Control Period Period Snap Snap Timeout Period (bits 15:0) Timeout Period (bits 31:16) Timeout Counter Snapshot (bits 15:0) Timeout Counter Snapshot (bits 31:16)
Stop Start Cont
Write-event register write operation this address causes event device.) Host-written control value that read back time Read-only value
timer contains registers register map. Registers memory-mapped peripheral read-only read- write-capable. timer controlled writing register Writing register starts timer, writing register stops timer. Values pre-loaded into timer writing upper half 32-bit word register lower half 32bit word register Additional information timer operation available with Excalibur Development Kit.
Determine FIFO Peripheral Design Requirements FIFO this example designed allow Nios embedded processor interface with fast source. FIFO requires that fast source writes FIFO, Nios processor reads from FIFO. FIFO needs assert interrupt request signal whenever FIFO full. Therefore, FIFO buffer would have characteristics shown Table
Table Example FIFO Buffer Characteristics Description Criteria
bits words clock, reset, write, read, data data, empty_flag, full_flag, word_count, interrupt_request
Creating Custom Memory-Mapped Peripheral
Custom memory-mapped peripherals designed Nios embedded processor following these three steps: Determine design requirements peripheral. Create peripheral register. Code peripheral using hardware description language (HDL).
Width Depth FIFO input signals FIFO output signals
following example demonstrates these three steps creating custom memorymapped first-in first-out (FIFO) peripheral.
source will directly drive data input port FIFO. Nios embedded processor outputs cpu_write_n_to_the_peripheral cpu_be_n_to_the_peripheral signals each peripheral which interfaces. However, example Table FIFO cannot written Nios embedded processor only written source), cpu_be_n_to_the_peripheral
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Figure FIFO Peripheral Register
Register Name Read Data Status Full Empty 29.7
Data read from FIFO (bits 31:0) Usedw (bits 6:0)
Read-only value Host-written control value. read back time
cpu_write_n_to_the_peripheral signals will used. FIFO Peripheral Register layout FIFO's register determined many input output signals connected (see Figure FIFO control signal inputs (write read) data input (data). source directly writes FIFO, write registers required FIFO memory map. register consists readable registers: Read Data Status. Read Data register contains 32-bit output FIFO, Status register indicates current state FIFO. full, empty, word count
(usedw) signals placed same 32-bit register conserve address space. However, address space consideration, each output signal placed separate register register map. This FIFO peripheral implemented using block diagram shown Figure source writes FIFO directly using FIFO's data, wrreq, wrclock signals. FIFO will update Read Data register writing Register whenever Nios embedded processor sets address_to_the_peripheral signal when asserts select_to_the_peripheral cpu_read_n_to_the_peripheral continued page
Figure FIFO Peripheral Block Diagram
Address Decoder address_to_the_peripheral select_to_the_peripheral cpu_read_n_to_the_peripheral Select
LPM_FIFO_DC write_data_from_IO_source wrreq_from_IO_source data wrreq aclr wrclock rdusedw rdempty rdfull rdreq IO_clock rdclock Register data_to_cpu_from_the_peripheral Register
reset_n
irq_from_the_FIFO Address Decoder address_to_the_peripheral Read select_to_the_peripheral cpu_read_n_to_the_peripheral
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Design Tips Designing Memory-Mapped Peripherals Nios Embedded Processor, continued from page signals. Status register (Register updated FIFO whenever reads writes performed. contents Status register read setting address_to_the_peripheral signal asserting select_to_the_peripheral cpu_read_n_to_the_peripheral signals. data_to_cpu_from_peripheral outputs values through Status register read time setting address_to_the_peripheral signal asserting select_to_the_peripheral cpu_read_n_to_the_peripheral signals. Status register value output data_to_cpu_from_peripheral time data_to_cpu_from_peripheral reads value time indicating that words remain FIFO. Memory-mapped peripherals create simple interface between peripheral Nios embedded processor. When using memory-mapping, Nios embedded processor communicates peripherals reading writing system memory space. optimize register memory-mapped peripheral designing with knowledge which input output signals Nios embedded processor important your application. register central creating efficient interface between Nios embedded processor your peripheral. design should create small register map, this will conserve address space some instances increase maximum speed peripheral.
Simulation Example
Figure depicts simulation example custom FIFO. values through written FIFO asserting IO_wrreq signal applying values through FIFO's data_in_from_IO bus. After IO_clock cycles, IO_wrreq line deasserted. Nios embedded processor begins reading from FIFO asserting select_to_the_peripheral cpu_read_n_to_the_peripheral lines address holds value from which causes FIFO update data_to_cpu_from_peripheral with current output FIFO. These results verified waveform because
Figure FIFO Peripheral Simulation Example
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Application
These drawbacks natural conclusion that next generation systems would need different approach.
OMEGA-TECHNOLOGIES S.A.: APEX Device Doubles Processing Power Signal Processing Application
Hybrid radio frequency (RF) simulation widely used radar, electronic warfare (EW), laboratory communication equipment tests. This laboratory-based simulation reproduces "real life" electromagnetic environments seen receivers such handsets complex radar systems. Because simulation involves generation millions pulses signals, consumes much real-time computing power control synthesizers charge microwave generation. This real-time data processing traditionally dedicated digital signal processing (DSP) equipment, while high-level software workstations multiprocessor-networked PCs. OMEGA-TECHNOLOGIES S.A., subsidiary Thomson-CSF Massy Cedex, France, introducing CARIBOU real-time simulation engine, which replaces 200-MHz TMS320C6201 device with single Altera® APEXdevice. This APEX device offers 100% increase computing power.
Using APEX Device: CARIBOU Project
first phase replacing DSP-based system transfer core algorithms pulse processing into VHDL. Simulation Quartussoftware helps define system architecture. During each 100-ms time slice, CARIBOU architecture performs following tasks: Downloads Kbytes data from interface memory bank Extracts from other bank emitter parameters from same amount data Computes 50,000 pulse descriptors Generates channel control words (amplitude phase) each descriptor Emits output data proprietary bits wide)
Implementing APEX device increased CARIBOU simulation engine's computing power 100%.
Typical
DSP-based simulations, system architecture based real-time unit (RTU) with interface plugged into multiprocessor (Windows NT). first DSP-based multiprocessor 320C40 board (see Figure which evolved into single 320C6 board. Nevertheless, drawbacks sets following system-wide limitations: High price DSPs associated circuits Need very detailed code optimization (assembly level) full performance parallel computing (Software written portability, optimization difficult.) Speed limitation memory architecture
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CARIBOU system simple: main board with APEX device, interface chip, SRAM banks daughter boards. continued page
Figure Former Multiprocessor Board
Customer Application OMEGA-TECHNOLOGIES S.A.: APEX Device Doubles Processing Power Signal Processing Application, continued from page Table shows CARIBOU system features. Figure shows CARIBOU printed circuit board (PCB). Using VHDL core simulation Quartus software provides programming flexibility simplifies system implementation. Using VHDL core simulation provides programming flexibility, system implementation greatly simplified: boot ROMs, loader codes, power-greedy digital signal processors. CARIBOU system shows that using APEX device high-end signal processing faster much more flexible than classical DSP-based simulation.
Conclusion
Implementing Altera APEX device only allows OMEGA-TECHNOLOGIES S.A. double processing power their CARIBOU system, also reduces production costs 40%.
About OMEGA-TECHNOLOGIES S.A.
OMEGA-TECHNOLOGIES S.A. whollyowned subsidiary THOMSON-CSF located high-tech area Massy from Paris). Company developing innovative products frequency synthesis field major player simulator business. Products range from microwave modules digital synthesizers radar communications simulators, mainly range. OMEGA-TECHNOLOGIES S.A. Avenue Carnot 91349 Massey Cedex, FRANCE Tel: 69934134 Fax: 69934138 email eric.duriez@omega-tech.com http://www.omega-tech.com
Table CARIBOU System Feature
APEX devices
Description
EP20K400E EP20K600E EP20K1000E
APEX device usage Clocks SRAMs Memory Power supplies
(PLL) Mbytes bank Mbytes @1.2
Notes: basic CARIBOU system includes EP20K400EFC672-1X device 672-pin ballgrid array (BGA) package. PLL: phase-locked loop.
Figure CARIBOU System
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systems that used dominated digital signal processing (DSP) processors. used number selectable variables implement ADPCM megafunctions provide customers with range solutions that matched their specific needs. megafunctions used applications such voice-over-DSL, voice-over-Asystems, cordless telephony. megafunctions fully support ADPCM standards G.726, G.726a, G.727, G.727a facilitate individual channel reset control major requirement most voice systems. addition, functions support burst mode operation. megafunctions require clock cycles sample direction (CSC4110AA, CSC4120AA, CSC4125AA) clock cycles sample direction (CSC4130AA CSC4190AA). more information these megafunctions, contact visiting their site http://www.issdsp.com.
Multi-Channel, Full-Duplex ADPCM Solutions from APEX, ACEX FLEX Devices
Integrated Silicon Systems (ISS) recently extended adaptive differential pulse code modulator (ADPCM) megafunction offering include 32-, 64-, 128- 256-channel fullduplex ADPCM codecs optimized Altera's APEXTM, ACEXTM, FLEX® programmable logic devices (PLDs). Typical implementation figures these megafunctions shown Table megafunctions fully supported also available OpenCoreevaluation. bit-accurate model, test bench, documentation included. extension ISS's range ADPCM megafunctions direct result exponential growth voice traffic over voice data networks need simultaneous compression/decompression voice data network interface. consequence this growth from system manufacturer's side explosion development systems that economically handle increased capacity. PLDs costeffective solution these implementations
Altera PLDs cost-effective solution implementations systems that used dominated processors.
Table Typical Implementation Figures ADPCM Megafunctions Product Code Duplex Channels
CSC4130AA CSC4130AA
Device
Memory Bits/ Minimum Maximum Pins Logic Embedded System Required Achieved Elements Blocks (ESBs) Clock Rate Clock Rate (LEs)
2.048 8.192 16.384 16.384 12.288 12.288 24.576 24.576 21.90 22.50 20.10 21.83 26.70 30.94 27.90 30.20 4,294 4,302 4,307 3,888 7,174 7,174 7,178 7,178 9,088/11 18,176/16 36,352/24 36,352/12 72,192/47 72,192/47 144,384/72 144,384/72
CSC4110AA CSC4120AA CSC4125AA
EP20K300EBC652-1 EP20K300EBC652-1 EP20K300EBC652-1 EP1K100FC256-1 EP20K300EBC652-1 EP20K200QC240-1 EP20K400EBC652-1 EP20K300EBC652-1
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Designing Switches Routers with APEX
Content-addressable memory (CAM) allows design search table particular item. data supplied user system, uses information provided determine location requested data. especially useful speeding search operations switches routers. This article describes APEXCAM used specific applications such Multi-protocol label switching (MPLS) Internet protocol address resolution Internet supports advanced routing services. This technique solves problematic issues such quality services delivery routing capabilities. Figure shows MPLS indicating that routers edge core network have separate functions. multi-protocol label switching system composed functional components: control forwarding. control component uses standard routing protocol exchange information maintain forwarding table with other routers along network. When router receives packet, forwarding component searches forwarding table, which maintained control component, make routing decision each packet. forwarding component based labelswapping forwarding algorithm. Each control component responsible assigning maintaining other relevant control information.
Multi-Protocol Label Switching
MPLS provides solutions that combine control Internet protocol routing with simplicity layer switching. MPLS technique evolution routing/ forwarding technology core
Figure Multi-Protocol Label Switching Network
Edge: Classify packets
Note
Core: Forwards packet using labels Label indicates service class destination Router
Router
Router
Switching Router
Router
Switching Router
Edge LSR: Edge label switching router
Switching Router
Switching Router
Router
Core LSR: Label switching router Router Router
Note: Routers using MPLS highlighted blue.
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Technical Articles Because MPLS allows different modules assign labels packets, decouples forwarding packet from contents packet's Internet protocol header. ingress edges (entry) network, each incoming packet classified initial label assigned. label switch performs "longest-match routing" table look-up, assigns label packet, then forwards next label-switched path. core network, when labeled packet arrives switch, forwarding component uses input port number label perform exact match search forwarding table. match found, forwarding component retrieves outgoing label, outgoing interface next address from forwarding table. forwarding component then replaces incoming label with outgoing label directs packet outbound interface transmission next label-switched path. When packet reaches egress edge, forwarding component searches forwarding table. next label switch, egress switch discards label forwards packet using conventional longest-match Internet protocol forwarding. Figure shows MPLS basic operation. block implement required table perform fast search operation multi-protocol label switching operation. block finds appropriate label incoming packet searching look-up table (LUT) ingress label switch. label used index into table that specifies next label. packet forwarded next with label attached. last edge network egress label switch section, block efficiently implement table remove label from incoming packet forward packet using Internet protocol forwarding. combination used implement table, which routes incoming labeled packet next finds label. Typical MPLS switches store 1,024 labels time, therefore requiring 1,024 block. This only takes ESBs, implemented within APEX devices. Because out-label another label, 1,024 block that consumes ESBs assign appropriate label incoming label. total ESBs perform multi-protocol label switching operation (see Figure
Internet Protocol Address Resolution
Internet protocol address resolution used layer switches convert Internet protocol addresses Ethernet media access control (MAC) addresses vice versa. Internet protocol address 32-bit value that identifies each sender receiver information that sent packets across Internet. When source attempts send data over Internet, Internet protocol portion transmission control protocol/Internet protocol (TCP/IP) includes source Internet protocol continued page
Figure MPLS Basic Operation
Edge Core Label Switching Label 192.4.16 Assign Initial Label Data Address Label Address Data Core Core Label Switching Label Data Address Label Address Data 192.2.3.1 Edge
Ingress Label Switch 192.3.4.1 Address Label
Egress Label Switch Label Next 192.2.3.1
Remove Label
Label-Switched Path Header MPLS Label Header MPLS Label Header Header
Data
Data
Data
Data
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Technical Articles Designing Switches Routers with APEX CAM, continued from page address destination Internet protocol address packet. Once required information delivery included packet, TCP/IP stack sends entire packet across Internet destination. destination receives data, response sent source using existing Internet protocol address. address, Ethernet address, unique physical address designated hardware device (such when manufactured. When computer connected local area network (LAN), correspondence table relates Internet protocol address device's address. combination used implement table maintain correlation between each address corresponding Internet protocol address perform address conversion both directions. contains Internet protocol addresses that point corresponding locations RAM, which contain Ethernet address. Address resolution protocol (ARP) used Internet protocol address recognized address local network. When host machine receives packet, runs search verify that packet's
Figure Address Resolution
Internet Protocol Address Data 192.2.41.53 192.63.12.3 192.21.42.3 Address Address Address Address Data 92:ad:26:7e:81:ae 12:84:ea:72:9e:bd ae:b3:f4:87:2e:81
combination used maintain correlation between each address corresponding Internet protocol address.
destination address particular network. combination, implemented ARP, compares Internet protocol address against content table find appropriate address RAM. contains Internet protocol address, packet converted appropriate length format, then sent destination device. match found, broadcasts request packet devices search corresponding address. device recognizes Internet protocol addresses, sends message claiming Internet protocol address. updates contents future reference sends packet destination machine. Figure shows this Internet protocol address resolution process. This process implemented software; however, implementing search hardware improves system performance.
Conclusion
Many networking applications require fast search operation. APEX provide solution search operations critical applications such multi-protocol label switching, Internet protocol address resolution. Using simplifies accelerates these functions applications increasing performance table look-up translation implementation.
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LVDS Timing Analysis
LVDS standard allows data transmitted very high speeds. This high data transmission rate results better overall system performance. take advantage this high system performance, designers need understand analyze timing LVDS. LVDS timing analysis different from traditional synchronous timing analysis techniques; rather than focusing clock-tooutput setup times, LVDS timing analysis based skew between data clock signals. verify overall timing budget, high-speed LVDS data transmission requires LVDS timing parameters provided Altera other LVDS vendors. Designers must also consider board skew, cable skew, clock jitter. using LVDS designs, data transmitted rates megabits second (Mbps). This article defines LVDS timing parameters APEX20KE devices explains LVDS timing parameters determine design's maximum performance.
Figure LVDS Timing Diagram
External Input Clock
Time Unit Interval (TUI)
Internal Clock TCCS RSKM Sampling Window (SW) RSKM TCCS
Receiver Input Data
TPPos (min)
TPPos (max)
(min)
Internal Clock Rising Edge
(max)
TPPos (min)
TPPos (max)
Table LVDS Timing Parameters Parameter
fINLVDS tLHT tHLT Time unit interval (TUI)
Description
LVDS receiver/transmitter input output clock period LVDS receiver/transmitter input output clock frequency Low-to-high transmission time High-to-low transmission time Timing budget allowed transition times, skew, propagation delays, data sampling window (TUI 1/receiver input clock frequency_multiplication factor)
LVDS Timing Parameters
Typically, LVDS used source synchronous implementation where clock forwarded along with data from transmitting device receiving device. Timing analysis source synchronous LVDS involves verifying that there sufficient receiver input skew margin (RSKM) after taking into account transmitter channel-to-channel skew (TCCS) receiver sampling window (SW) requirements. Figure shows APEX 20KE LVDS timing diagram that defines relationship these LVDS timing parameters with respect internal clock period LVDS data positions. Table defines LVDS parameters.
fLVDSDR Channel-tochannel skew (TCCS) Receiver input skew margin (RSKM) Sampling window (SW) Input jitter (peak-to-peak) Output jitter (RMS) tDUTY tLOCK
Maximum LVDS data transfer rate (fLVDSDR 1/TUI) Timing difference between fastest slowest output edges LVDS transmitter clock data, including variation clock skew Timing margin between clock input data input user board design, which allows LVDS interconnect (cable connector) skew jitter LVDS (RSKM (TUI TCCS SW)/2) Defines period time during which data must valid order correctly captured (max) (min)) Tolerable input jitter LVDS PLLs
output jitter LVDS PLLs
Duty cycle LVDS transmitter output clock Lock time LVDS transmitter receiver PLLs
continued page
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Technical Articles LVDS Timing Analysis, continued from page RSKM parameter must large enough allow clock jitter cable board skew. meet system's requirements, designers must consider jitter system skew that both affect RSKM evaluating application's margin. This equation shown below: Margin RSKM (input clock jitter system skew) System skew difference propagation delays signals between devices includes skew introduced from cables, connectors, differences signal lengths printed circuit circuit board (PCB) traces. input clock jitter allowed jitter input clock that will received APEX 20KE LVDS receiver PLL. skew (based electrical length traces) System skew cable skew connector skew skew Margin RSKM (input clock jitter system skew)
Because margin positive, circuit will operate required speed. longer cable desired, margin sufficient. this case, APEX 20KE deskew circuit used increase RSKM assure circuit functionality. Preliminary test data shows that EP20K400E EP20K600E devices transmit data Mbps over twisted pair (CAT5) cable under nominal conditions. When designing high-speed data transfer rates, designers must consider various factors that affect margin correct data sampling. completing calculations described this section, designers calculate margin LVDS designs that APEX 20KE devices calculate LVDS transfer speed over cables connectors. skew cables connectors also improve margin overall system performance. APEX 20KE LVDS circuitry provides TCCS parameters that allow high-speed LVDS data transfers. APEX 20KE devices timing electrically compatible with source synchronous LVDS buffers offered National Semiconductor, Texas Instruments, other devices that comply EIA/TIA-644 LVDS standard.
APEX 20KE LVDS circuitry provides TCCS parameters that allow high-speed LVDS data transfers.
Design Example
This section describes LVDS design example using APEX 20KE-to-APEX 20KE connection data transfer rate Mbps over cable. This design uses cable (14526-EZ5B) connector (10226-1A10VE) from Company. Figure shows design example APEX 20KE-to-APEX 20KE connection with Company cable assembly.
Figure LVDS Design Example
APEX 20KE
APEX 20KE
design Figure following characteristics: 0.44 TCCS RSKM (TUI TCCS) (1.6 0.44 0.4) Cable skew meter (max) Connector skew (max) (Values obtained from Company) Because LVDS balls located outer edge FineLine BGApackages, traces easily routed with little skew.
Conclusion
When designing high-speed data transfer rates, designers must consider various factors that affect margin correct data sampling. completing calculations described this article, designers calculate margin LVDS designs that APEX 20KE devices calculate LVDS transfer speed over cables connectors. skew cables connectors improve margin overall system performance. APEX 20KE LVDS circuit provides TCCS parameters that allows high-speed LVDS data transfers.
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7000B: Standards High-Speed Applications
most cases today, buffers transceiver chips used convert GTL+ signals LVCMOS/LVTTL before performing control/ decode logic. 7000B devices eliminate need such standard translation, saving board space, reducing costs, contributing overall system throughput. It's unique support this popular standard makes 7000B device only product-termbased solution these applications.
System demands increasing clock speeds voltage levels driving adoption high-performance, low-voltage standards support faster microprocessors high-speed memory. Product-term-based MAX® 7000B devices increasingly found many these applications, where they utilized variety glue logic control logic circuitry. Today's product-term-based devices must support only variety advanced standards also must support multiple standards within single device. Such flexibility allows pins configured both LVCMOS SSTL-2. 7000B devices meet these advanced support needs. flexible buffers within 7000B devices designed meet voltage, drive strength, characteristics necessary comply with advanced standards such GTL+and SSTL. implementing these standards, 7000B devices also help save board space increase chip-to-chip performance eliminating external buffers, drivers, transceivers.
SSTL-2 SSTL-3 Standard
7000B devices also support both SSTL-2 SSTL-3, Class Class standard. primary application SSTL interfacing with SDRAMs. SSTL used high-speed memory interface applications, specifying switching characteristics that reach operating frequencies MHz. 2.5-V systems SSTL-2, 3.3-V systems SSTL-3. Computer servers even high-end laptop computers SDRAMs SDRAMs. SSTL interface standard choice these high-speed memory modules. High-speed SDRAMs also used variety networking applications such ALAN switches, Internet protocol routers switches, frame buffer interfaces. SSTL interfacing widely used these applications. Support advanced standards, coupled with split bank architecture, gives added flexibility allows 7000B devices meet virtually your interfacing requirements. 7000B device family productterm leader standard support, enabling high-speed design applications such processor interfaces, backplane drivers, peripheral devices, SDRAM memory interfaces.
Support advanced standards, coupled with split bank architecture, allows 7000B devices meet virtually your interfacing requirements.
GTL+ Standard
GTL+ standard characteristics (i.e., reduced swing level, output capacitance, output generated noise, high noise immunity) make dominant standard high-performance system backplanes motherboards. GTL+ also used high-end computer servers laptops. example, Intel Pentium Pentium processors interface with their core logic using GTL+ standard. GTL+ also found backplanes many communication applications such Aswitches, Layer switches, other highspeed routers. these data communication applications, system board typically communicates with other modules GTL+-based backplane bus.
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7000B Devices Outperform Competition
Altera® MAX® 7000B devices industry's fastest product-term-based device. Ranging from macrocells, 7000B devices offer propagation delays fast counter frequencies over MHz. addition, 7000B devices support today's advanced standards, providing simple integration into high-speed design applications. Fabricated 2.5-V, 0.22-µm CMOS technology, 7000B devices industry's most advanced product-term-based device date.
Industry's Fastest Product-Term Device
fast pin-to-pin propagation delays 7000B devices maintain Altera's performance leadership marketplace. Table shows, 7000B devices outperform competition's fastest available devices.
Advanced Process Technology
Behind 7000B device's impressive performance advanced process technology.
Table Typical Propagation Delays Available 2.5-V Devices Macrocell Range Pin-to-Pin Propagation Delays (ns) 7000B
higher
Advanced Standards Support
Altera 7000B devices also lead competition advanced standards support. shown Table 7000B devices only product-term-based device capable supporting GTL+, SSTL-3, SSTL-2 standards. Support advanced standards allow designers 7000B devices highspeed design applications such processor interfaces, backplane drivers, SDRAM memory interfaces. 7000B devices available today ready meet your performance needs. Fabricated 0.22-µm CMOS process with support today's advanced standards, high-performance 7000B solution unmatched industry.
XC9500XV
10.0 10.0 10.0 15.0
ispLSI2000VL
Note: This fastest available device through distribution December 2000.
Table Advanced Standards Support Standard
GTL+ SSTL-2 class SSTL-3 class LVTTL LVCMOS 64-bit, 66-MHz
7000B
XC9500XV
ispLSI2000VL
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EPM7128 Celebrates Million Units
Driven Internet revolution, Altera sold million units industry-leading MAX® EPM7128 device. Marking this historic programmable logic device (PLD) milestone, Altera delivered symbolic millionth device Cisco Systems, leading network customers. From earliest Ethernet switches most popular Internet routers nextgeneration optical networking systems, almost EPM7128 devices shipped have been designed into communications systems. EPM7128 architecture, which includes EPM7128, EPM7128A, EPM7128AE, EPM7128S, EPM7128B devices, held wide popularity since release 1991. Popular DSL, VOIP, Wireless, high-speed routers, mass storage applications, 7000A devices represent fastestgrowing product term architecture within various 7000 product generations. Altera plans maintain extend this product-term market leadership investing heavily development products well expanding current customer support efforts devices. Recently released 7000B devices illustrate this commitment that 7000B devices only 2.5-V, ISP-based devices currently available. more information devices, visit Altera site (http://www.altera.com) contact your local sales representative.
Questions
Answers Table shows slew rates measured both rising falling edges under following conditions: From output voltage swing Under 35-pF unterminated load VCCIO Room temperature Nominal
What effects slew rate control MAX® 7000B devices?
7000B devices offer slow slew rate feature that allows select either normal slew rate fastest performance slow slew rate reduce board-level signal integrity issues. signal's output slew rate varies significantly based load conditions. Altera's input/output buffer information specification (IBIS) models model effect turning slow slew rate option determine board's transmission line effects require slowing slew rate.
Table 7000B Slew Rates VCCIO
Normal Slew Rate (V/ns)
Slow Slew Rate (V/ns)
continued page
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Questions Answers Questions Answers, continued from page Slow Slew Rate logic synthesis option turned globally MAX+PLUS® software using following steps: Choose Global Project Logic Synthesis (Assign menu). Select Define Synthesis Style (Global Project Logic Synthesis box). Turn Slow Slew Rate off. Choose twice.
"Failed find INSTANCE `/instance_name'" error when performing timing simulation ModelSim simulator? This error will only occur have modified VHDL Output File (.vho) Verilog Output File (.vo) removing reference Standard Delay Format Output File (.sdo). ModelSim will flag this error when applied wrong instance. default, File referenced QuartusTM- MAX+PLUS II-generated Files. When test bench simulate File generated Quartus MAX+PLUS software, File must applied entity File top-level test bench entity. apply File correct instance, follow steps below: Open Load Design dialog ModelSim. Click then click button. Browse choose file. Apply Region box, type path instance which file should applied. Click
Error: "Unknown problem <design>.vhd (DLS-E-IllNodeRef, Consumers Channel node (number 130) unit SynthesisView refers unattached BitWrite node; CheckAttachNode.)" This VHDL code error occurs MAX+PLUS software when Statements nested within Loop. following example demonstrates syntax that causes error:
LOOP (a(i) `1') THEN (b(i) `0') THEN c(i) d(i);
ELSE c(i) d(i); ELSE c(i) `Z'; LOOP;
Library error: "primary unit <text> denoted prefix <text> must exist library." MAX+PLUS Help lists most common cause this error. However, this error also generated your VHDL design files appended with .vhdl rather than .vhd. workaround, rename your VHDL files with .vhd extension.
following example demonstrates compensate this error modifying Statement that nested:
LOOP (a(i) b(i) `0') THEN c(i) d(i);
ELSIF (a(i) b(i) `1') THEN ELSE c(i) `Z'; LOOP;
connect tri-state signal connected input pins Altera® device? tri-state signal connected inputs will cause damage device.
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Questions Answers However, when tri-state signal drives high impedance, input unpredictable your logic produce desired outputs. Tri-stated inputs cause device draw more current than would signal were pulled logic level high low. prevent this from happening, pull-up pull-down resistors these signals. Another option bus-hold feature 7000B device Open MSDOS Command Prompt window. prompt, directory that holds jbi.exe File created MAX+PLUS software. prompt, type following command File STAPL format: -aconfigure <filename>.jbc
assign register cell location Quartus software version 2000.09? There three ways assign register cell Quartus software version 2000.09: Apply Fast Input Register Fast Output Register assignment pins registers directly. Optimize Timing assignment with less assignment register. ATOMs your synthesis tool
Files binary counter part STAPL Files (.jam). Files ASCII format. Since Files binary, file size usually smaller. Altera recommends using Files Player. Files; however, they require Player (jam.exe), available download site http://www.jamisp.com.
fixed-node MegaCore® license with Quartus MAX+PLUS floating license? Fixed-node floating licenses used simultaneously License Setup window Quartus MAX+PLUS software. example, have fixed-node license stored c:\license.dat floating license port@host (e.g., 1800@arnold), could enable licenses follows: Select Licensing (Tools menu Options) Quartus software. Select License Setup (Options menu) MAX+PLUS software. License File dialog box, type: c:\license.dat; 1800@arnold Select
Standard Test Programming Language (STAPL) JamByte-Code Player configure ACEXor FLEX® devices? Yes. STAPL Byte-Code player configure ACEX FLEX devices. following steps configure ACEX FLEX device with STAPL Byte-Code Player: Download Byte-Code Player from site http://www.jamisp.com. download contains jbi.exe Byte-Code player executable. Create option MAX+PLUS software create STAPL Byte-Code File (.jbc) JTAG chain. Connect Altera download cable your PC's parallel port other Joint Test Action Group (JTAG) chain printed circuit board (PCB). Power board.
different standards CLKLK_FBIN pins APEX20KE devices? CLKLK_FBIN pins must have same standard. phase-locked loop (PLL) cannot accurately phase-match these pins external feedback mode they have different standards. phase-locked loops (PLL) cannot accurately phase-match these pins external feedback mode they have different standards. Quartus software will give error these pins assigned different standards.
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have been data standard speeds, higher low-volta clock used formance increasin standard High-per pace with These keep devices. introduc backplan low-volta microprocessors, rates, these with memory, want highto interface Designer nary need flexible, devices. revolutio mable logic peripher buffers. Altera'shighest with program ndard standard density, nce, multi-sta offer highest necessary performa with 20KE devices solution industrie APEX mable logic compute program ication performa commun term leader standard lthe productmacrocel devices only MAX® 7000B (GTL+), devices Altera logic plus 7000B transceiv SSTL-3. support: Gunning standard 3.3-V support (SSTL-2) based devices logic terminat stub series supporte standard mable single device program With 7000B devices, standards, well buses multiple APEX 20KE eously support low-voltage memory different simultan low-volta with high-spe include 622.08 million interface standard data rates These simplify supports backplan standard into mable (LVDS), which signaling (Mbps). Program like LVDS integrate reducing space, circuitry bits second Dedicate saving board board design. logic devices (PLDs), nce. mable performa program improvin with usage, designin following guideline covers note provides devices This applicati standards Altera selectabl topics: ions Applicat Standard Standard Overview 7000B APEX 20KE Conditio Operatin Using LVDS Schemes Board Terminat
Introduction
publications available from Altera Literature Services lit_req@altera.com (888)-3-Altera. When ordering, please specify part number shown parentheses. On-line documents available Altera site http://www.altera.com. Altera Digital Library CD-Rom, Version (P-CD-ADL2000-06) APEX Devices Brochure (M-GB-APEX-20K-04) Simulating a8259 Model with Visual Software User Guide (A-UG-A8259VIS-01) APEX 20KC Programmable Logic Devices Advance Information Brief (A-AIB-APEX20KC-01)
Interleaver/Deinterleaver MegaCore Function (A-SB-042-01) Reed-Solomon Compiler MegaCore Function (A-SB-048-01) Compiler MegaCore Function (A-SB-049-01) Turbo Encoder/Decoder MegaCore Function (A-SB-050-01) Board Design Guidelines LVDS Systems White Paper (M-WP-DESLVDS-01) Designing Switches Routers with APEX White Paper (M-WP-APEXCAM-01) Configuring PLDs with Flash Memory White Paper (M-WP-M3KPLD-01)
Current Software Versions
Quartussoftware version 2000.09 latest release, available following operating systems: Microsoft Windows 2000 Microsoft Windows Microsoft Windows version higher Solaris version HP-UX version 10.2x 11.0 MAX+PLUS® software version 10.0 available following operating systems: Microsoft Windows 2000 Microsoft Windows Windows Microsoft Windows version higher Solaris version HP-UX version 10.2x version higher
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Altera Programming Support
Table Altera Programming Adapters (Part Note Device
EPM7064S
Programming Hardware Support
Table contains latest programming hardware information Altera® MAX® 9000, 7000, 3000, configuration devices. correct programming, software version shown "Current Software Versions" page
Table Altera Programming Adapters (Part Note Device
EPC1064 EPC1064V EPC1441 EPC1 EPC1213 EPC2 J-lead TQFP EPM9320 J-lead (84-pin) RQFP (208-pin) (280-pin) EPM9320A J-lead (84-pin) RQFP (208-pin) EPM9400 J-lead (84-pin) RQFP (208-pin) RQFP (240-pin) EPM9480 RQFP (208-pin) RQFP (240-pin) EPM9560 RQFP (208-pin) RQFP (240-pin) (280-pin) RQFP (304-pin) EPM9560A RQFP (208-pin) RQFP (240-pin) EPM7032 J-lead (44-pin) PQFP (44-pin) TQFP (44-pin) PLMJ1213 PLMT1064 PLMJ9320-84 PLMR9000-208 PLMG9000-280 PLMJ9320-84 PLMR9000-208NC PLMJ9400-84 PLMR9000-208 PLMR9000-240 PLMR9000-208 PLMR9000-240 PLMR9000-208 PLMR9000-240 PLMG9000-280 PLMR9000-304 PLMR9000-208NC PLMR9000-240NC DIP, J-lead PLMJ1213
Package
J-lead (44-pin) J-lead (84-pin) TQFP (44-pin) TQFP (100-pin)
Adapter
PLMJ7000-44 PLMJ7000-84 PLMT7000-44 PLMT7000-100NC PLMJ7000-44 PLMT7000-44 PLMT7000-100NC PLMF7000-100
EPM7064AE EPM7064B
J-lead (44-pin) TQFP (44-pin) TQFP (100-pin) FineLine (100-pin)
Package
DIP, J-lead TQFP
Adapter
PLMJ1213 PLMT1064 EPM7096
J-lead (68-pin) J-lead (84-pin) PQFP (100-pin)
PLMJ7000-68 PLMJ7000-84 PLMQ7000-100 PLMJ7000-84 PLMQ7000-100 PLMQ7128/7160-160 PLMJ7000-84 PLMQ7000-100NC PLMT7000-100NC PLMT7000-144NC PLMQ7128/7160160NC PLMF7000-100 PLMF7000-256
EPM7128E
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
EPM7128A EPM7128AE EPM7128B EPM7128S
J-lead (84-pin) PQFP (100-pin) TQFP (100-pin) TQFP (144-pin) PQFP (160-pin) FineLine (100-pin) FineLine (256-pin)
EPM7160E
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
PLMJ7000-84 PLMQ7000-100 PLMQ7128/7160-160 PLMJ7000-84 PLMQ7000-100NC PLMQ7128/7160160NC
EPM7160S
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
EPM7192E
(160-pin) PQFP (160-pin)
PLMG7192-160 PLMQ7192/7256-160 PLMQ7192/7256160NC
PLMJ7000-44 PLMQ7000-44 PLMT7000-44
EPM7192S
PQFP (160-pin)
EPM7032S EPM7032AE EPM7032B EPM7064
J-lead (44-pin) TQFP (44-pin)
PLMJ7000-44 PLMT7000-44
J-lead (44-pin) TQFP (44-pin) J-lead (68-pin) J-lead (84-pin) PQFP (100-pin)
PLMJ7000-44 PLMT7000-44 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100
continued page
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Table Altera Programming Adapters (Part Note Device
EPM7256E
Table Third-Party Programming Hardware Support Device Data
Microsystems
System General
Package
PQFP (160-pin) (192-pin) PQFP (208-pin) RQFP (208-pin)
Adapter
PLMQ7192/7256-160 PLMG7256-192 PLMR7256-208 PLMR7256-208 PLMT7000-100NC PLMT7000-144NC PLMR7256-208NC PLMT7256-208NC PLMF7000-100 PLMF7000-256
EPC1064 EPC1213 EPC1 EPC1441 EPC2
EPM7256A EPM7256S EPM7256AE EPM7256B
TQFP (100-pin) TQFP (144-pin) PQFP (208-pin) RQFP (208-pin) FineLine (100-pin) FineLine (256-pin)
EPM3032A EPM3064A EPM3128A EPM3256A EPM7032 EPM7032AE EPM7032B
EPM7512AE EPM7512B
TQFP (144-pin) PQFP (208-pin) (256-pin) FineLine (256-pin)
PLMT7000-144NC PLMR7256-208NC PLMB7000-256 PLMF7000-256
EPM7032S EPM7064 EPM7064AE EPM7064B
EPM3032A
J-lead (44-pin) TQFP (44-pin)
PLMJ3000-44 PLMT3000-44 PLMJ3000-44 PLMT3000-44 PLMT3000-100NC PLMT3000-100NC PLMT3000-144NC PLMT3000-144NC PLMR3256-208NC
EPM7064S EPM7096 EPM7128A EPM7128S EPM7128AE EPM7128B EPM7128E EPM7160E EPM7192S EPM7192E EPM7256A EPM7256AE EPM7256B EPM7256S EPM7256E EPM7512AE EPM7512B
EPM9320 EPM9320A
EPM3064A
J-lead (44-pin) TQFP (44-pin) TQFP (100-pin)
EPM3128A
TQFP (100-pin) TQFP (144-pin)
EPM3256A
TQFP (144-pin) PQFP (208-pin)
Notes: Refer Altera Programming Hardware Data Sheet device adapter information Classicdevices. FLEX® 8000 configuration device. FLEX 10K, FLEX 8000, FLEX 6000 configuration device. APEX20K, FLEX 10K, FLEX 6000 configuration device. These devices shipped carriers.
Third-Party Programming Support
Data I/O, Microsystems, System General provide programming hardware support selected Altera devices. Algorithms available these companies' respective sites (http://www.data-io.com, http://www.bpmicro.com, http://www.sg.com.tw). Programming support information configuration, 9000, 7000 devices shown Table information subject change.
EPM9400 EPM9480 EPM9560 EPM9560A
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Notes Table These devices supported Data UniSite programmer version 6.4. These devices supported Microsystems programmers version 3.51A. These devices supported System General programmers version 1.0. Contact Data I/O, Microsystems, System General about programming support these devices.
Table Download Cable Compatibility Device
APEX APEX 20KE ACEX FLEX FLEX 10KA FLEX 10KE
MasterBlaster
ByteBlasterMV
BitBlaster
Download Cables
Table provides programming configuration compatibility information MasterBlasterserial universal serial (USB) communications cable BitBlasterserial ByteBlasterMVparallel port download cables. (The ByteBlasterdownload cable been replaced with ByteBlasterMV cable.)
FLEX 8000 FLEX 6000 9000 9000A 7000S 7000A 7000B 3000A
Notes: MasterBlaster communications cable used with Quartus software device download SignalTap logic analysis. also used with MAX+PLUS software version later device downloads. BitBlaster download cable must operate ByteBlasterMV download cable must operate these devices, except 5.0-V tolerant APEX devices with ordering code suffix. VCCIO pins either
Contact Altera
Getting information services from Altera easier than ever. table below lists some ways reach Altera.
Information Type
Literature
Access
News Views Subscriptions
U.S. Canada
Other Locations
lit_req@altera.com
General Literature Request lit_req@altera.com
n_v@altera.com News Views Address Changes Non-Technical Customer Service Technical Support Telephone Hotline Telephone Hotline (800) SOS-EPLD (408) 544-6403 (800) 800-EPLD a.m. p.m. Pacific Time) (408) 544-7000 (7:30 a.m. 5:30 p.m. Pacific Time) Electronic Mail Site General Product Information Telephone World-Wide (408) 544-6401 support@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com https://websupport.altera.com n_v@altera.com
n_v@altera.com n_v@altera.com
(408) 544-7000 (408) 544-6403 (408) 544-7000 (7:30 a.m. 5:30 p.m. Pacific Time)
(408) 544-6401 support@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com https://websupport.altera.com
Notes: Quartus Installation Licensing MAX+PLUS Getting Started manuals available from Altera® site. obtain other MAX+PLUS® software manuals, contact your local distributor. also contact your local Altera sales office sales representative. Altera site listing.
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Altera Device Selection Guide
Current information Altera® ExcaliburTM, APEX20K, ACEX1K, FLEX® 10K, FLEX 6000, MAX® 9000, 7000, 3000, configuration devices listed here. Information other Altera products located Altera
Excalibur Devices
DEVICE
EPXA1 EPXM1 EPXA4 EPXM4 EPXA10 EPXM10
Component Selector Guide. most up-todate information, Altera site http://www.altera.com. Some devices listed available. Contact Altera your local sales office latest device availability.
GATES
100,000 100,000 400,000 400,000 1,000,000 1,000,000
PIN/PACKAGE OPTIONS
484-Pin BGA2, 672-Pin BGA2, 612-Pin 484-Pin BGA2, 672-Pin BGA2, 612-Pin
PINS
173, 178, 173, 178, 275, 360, 215, 275, 360, 215, 521, 521,
SUPPLY VOLTAGE
LOGIC ELEMENTS
4,160 4,160 16,640 16,640 38,400 38,400
BITS
53,248 53,248 212,992 212,992 327,680 327,680
EMBEDDED PROCESSOR
ARM922T 32-bit MIPS32 ARM922T 32-bit MIPS32 ARM922T 32-bit MIPS32
672-Pin BGA2, 1020-Pin BGA2, 612-Pin BGA, 864-Pin 672-Pin BGA2, 1020-Pin BGA2, 612-Pin BGA, 864-Pin
1020-Pin BGA2, 864-Pin 1020-Pin BGA2, 864-Pin
APEX Devices
DEVICE
EP20K30E EP20K60E
GATES
30,000 60,000
PIN/PACKAGE OPTIONS
144-Pin TQFP, 144-Pin BGA2, 208-Pin PQFP, 324-Pin BGA2 144-Pin TQFP, 144-Pin BGA2, 208-Pin PQFP, 240-Pin PQFP, 324-Pin BGA2, 356-Pin
PINS
128, 148, 151, 196, 101, 159, 189, 252, 151, 183, 246, 143, 175, 271, 144, 174, 277, 136, 168, 271, 376, 376, 152, 408, 502, 488,
SUPPLY VOLTAGE
LOGIC ELEMENTS
1,200 2,560
BITS
24,576 32,768
EP20K100
100,000
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 324-Pin BGA2, 356-Pin
4,160
53,248
EP20K100E
100,000
144-Pin TQFP, 144-Pin BGA2, 208-Pin PQFP, 240-Pin PQFP, 324-Pin BGA2, 356-Pin
4,160
53,248
EP20K160E
160,000
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA2
6,400
81,920
EP20K200 EP20K200E
200,000 200,000
208-Pin RQFP, 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA2 208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 484-Pin 652-Pin BGA, 672-Pin BGA2 BGA2,
8,320 8,320
106,496 106,496
EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E
300,000 400,000 400,000 600,000 1,000,000 1,500,000
240-Pin RQFP, 652-Pin BGA, 672-Pin BGA2 652-Pin BGA, 672-Pin BGA2 652-Pin BGA, 672-Pin BGA2 652-Pin BGA, 672-Pin BGA2, 1,020-Pin BGA2
11,520 16,640 16,640 24,320 38,400 51,840
147,456 212,992 212,992 311,296 327,680 442,368
488, 508, 488, 508, 488,
652-Pin BGA, 672-Pin BGA2, 1,020-Pin BGA2 652-Pin BGA, 1,020-Pin BGA2
ACEX Devices
DEVICE
EP1K10 EP1K30 EP1K50 EP1K100
GATES
10,000 30,000 50,000 100,000
PIN/PACKAGE OPTIONS
100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2, 484-Pin BGA2 208-Pin PQFP, 256-Pin BGA2, BGA2
PINS
102, 130, 102, 147, 102, 147, 186, 147, 186,
SUPPLY VOLTAGE
LOGIC ELEMENTS
1,728 2,880 4,992
BITS
12,288 24,576 40,960 49,152
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FLEX Devices
DEVICE
EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K30E EPF10K40 EPF10K50 EPF10K50V EPF10K50E EPF10K50S
GATES
10,000 10,000 20,000 30,000 30,000 30,000 40,000 50,000 50,000 50,000 50,000
PIN/PACKAGE OPTIONS
84-Pin PLCC, 144-Pin TQFP, 208-Pin PQFP 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2 144-Pin TQFP, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2, 356-Pin BGA, 484-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2, 484-Pin BGA2 208-Pin RQFP, 240-Pin RQFP 240-Pin RQFP, 356-Pin BGA, 403-Pin 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2, 484-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2, 356-Pin BGA, 484-Pin BGA2
PINS
102, 102, 134, 102, 147, 147, 189, 102, 147, 189, 191, 246, 102, 147, 176, 147, 189, 274, 189, 274, 102, 147, 189, 191, 102, 147, 189, 191, 220, 189, 189, 274, 369, 147, 189, 147, 189, 191, 274, 470, 186, 274, 369, 424, 470, 470, 182, 274, 369, 470, 470,
SUPPLY VOLTAGE
SPEED GRADE
LOGIC ELEMENTS
1,152 1,728 1,728 1,728 2,304 2,880 2,880 2,880 2,880
BITS
6,144 6,144 12,288 12,288 12,288 24,576 16,384 20,480 20,480 40,960 40,960
EPF10K70 EPF10K100 EPF10K100A EPF10K100B EPF10K100E
70,000 100,000 100,000 100,000 100,000
240-Pin RQFP, 503-Pin 503-Pin 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA2, 600-Pin 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2, 356-Pin BGA, 484-Pin BGA2
3,744 4,992 4,992 4,992 4,992
18,432 24,576 24,576 24,576 49,152
EPF10K130V EPF10K130E
130,000 130,000
599-Pin PGA, 600-Pin 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA2, 600-Pin 672-Pin BGA2 599-Pin PGA, 600-Pin BGA, 672-Pin BGA2 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA2, 600-Pin BGA, 672-Pin BGA2
6,656 6,656
32,768 65,536
EPF10K200E EPF10K200S
200,000 200,000
9,984 9,984
98,304 98,304
EPF10K250A
250,000
599-Pin PGA, 600-Pin
12,160
40,960
FLEX 6000 Devices
DEVICE
EPF6010A EPF6016 EPF6016A
GATES
10,000 16,000 16,000
PIN/PACKAGE OPTIONS
100-Pin TQFP, 144-Pin TQFP 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin 100-Pin TQFP, 100-Pin BGA2, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2
PINS
117, 171, 199, 117, 171, 117, 171, 199, 218,
SUPPLY VOLTAGE
SPEED GRADE
FLIPFLOPS
1,320 1,320
LOGIC ELEMENTS
1,320 1,320
EPF6024A
24,000
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA, 256-Pin BGA2
1,960
1,960
Configuration Devices APEX FLEX Devices
DEVICE
EPC1064 EPC1064V EPC1213 EPC14413 EPC13 EPC23
PIN/PACKAGE OPTIONS
8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC 8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC 20-Pin PLCC, 32-Pin TQFP
SUPPLY VOLTAGE
3.3/5.0 3.3/5.0 3.3/5.0
DESCRIPTION
64-Kbit serial configuration device designed configure FLEX 8000 devices 64-Kbit serial configuration device designed configure FLEX 8000 devices 213-Kbit serial configuration device designed configure FLEX 8000 devices 441-Kbit serial configuration device designed configure FLEX devices 1-Mbit serial configuration device designed configure APEX FLEX devices 2-Mbit serial configuration device designed configure APEX, FLEX 10K, FLEX 10KE, FLEX 6000 devices
EPC44
44-Pin PLCC, 100-Pin TQFP, 144-Pin BGA2
1.8/2.5
4-Mbit serial/parallel configuration device designed configure APEX FLEX devices.
continued page
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7000 Devices
DEVICE
EPM7032S EPM7032AE EPM7032B EPM7064S EPM7064AE EPM7064B
MACROCELLS
44-Pin PLCC/TQFP 44-Pin PLCC/TQFP
PIN/PACKAGE OPTIONS
PINS
SUPPLY VOLTAGE
SPEED GRADE
44-Pin PLCC/TQFP, 48-Pin BGA5 44-Pin PLCC/TQFP, 84-Pin PLCC, 100-Pin TQFP 44-Pin PLCC/TQFP, 49-Pin BGA5, 100-Pin TQFP, 100-Pin BGA2 44-Pin PLCC/TQFP, 48-pin TQFP, 49-Pin BGA1, 100-Pin TQFP, 100-Pin BGA2
100, 100, 100, 100, 100, 120, 164, 120, 164, 120, 140, 164, 164, 120, 176, 212, 120, 140, 212, 212,
EPM7128S EPM7128A EPM7128AE
84-Pin PLCC, 100-Pin PQFP/TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 100-Pin BGA2, 144-Pin TQFP, 256-Pin BGA2 84-Pin PLCC, 100-Pin TQFP, 100-Pin BGA2, 144-Pin TQFP, 169-Pin BGA5, 256-Pin BGA2 49-Pin BGA5, 100-Pin TQFP, 100-Pin BGA2, 144-Pin TQFP, 49-Pin BGA5 169-Pin BGA5, 256-Pin BGA2
-10, -10, -5,-7,-10
EPM7128B
EPM7160S EPM7192S EPM7256S EPM7256A EPM7256AE EPM7256B
84-Pin PLCC, 100-Pin TQFP, 160-Pin PQFP 160-Pin PQFP 208-Pin PQFP 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2 100-Pin TQFP, 100-Pin BGA2, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2 100-Pin TQFP, 144-Pin TQFP, 169-Pin BGA5, 208-Pin PQFP, 256-Pin BGA2, 256-Pin
-10, -10, -10, -10,
EPM7512AE EPM7512B
144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2, 256-Pin 144-Pin TQFP, 169-Pin BGA5, 208-Pin PQFP, 256-Pin BGA2, 256-Pin
-10,
3000 Devices
DEVICE
EPM3032A EPM3064A EPM3128A EPM3256A
MACROCELLS
PIN/PACKAGE OPTIONS
44-Pin PLCC, 44-Pin TQFP 44-Pin PLCC, 44-Pin TQFP, 100-Pin TQFP 100-Pin TQFP, 144-Pin PQFP 144-Pin TQFP, 208-Pin PQFP
PINS
116,
SUPPLY VOLTAGE
SPEED GRADE
9000 Devices
DEVICE
EPM9320A EPM9320 EPM9400 EPM9480 EPM9560A EPM9560
MACROCELLS
PIN/PACKAGE OPTIONS
84-Pin PLCC, 208-Pin RQFP, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 280-Pin PGA, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP, 356-Pin
PINS
132, 132, 139, 146, 153, 191, 153, 191,
SUPPLY VOLTAGE
SPEED GRADE
-15, -15, -15, -15,
Notes Tables: Preliminary. Contact Altera latest information. This package space-saving FineLine package. This device programmed user operate either This device programmed user operate either This package space-saving Ultra FineLine package, Altera's 0.8-mm pitch package.
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