Excalibur Solutions Altera Announces Nios Processor Embedded Syst
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Altera Announces Nios Processor Embedded Systems Development
Altera leader providing elements required successful system-on-aprogrammable-chip (SOPC) designs, including high performance, full-featured devices, integrated development tools, comprehensive portfolio intellectual property (IP). Recognizing importance microprocessors designs, Altera established itself preeminent source processor through strong partnerships with industry leaders. Altera enhances this processor selection with Excaliburembedded processor programmable logic device (PLD) solutions. Consisting both hard soft core technologies that integrate RISC processors into PLDs, Excalibur embedded processor solutions offer widest range capabilities high performance dedicated hardware implementation. With introduction Excalibur embedded processor solutions, designers reap benefits SOPC design. time, explore different system architectures feature sets deliver best possible combination their product. fully integrating processor into design flow, Excalibur solutions give system designers unprecedented freedom determine which functions should executed software which would benefit most from dedicated hardware implementation.
Altera Excalibur solutions consist following families: Niosfamily soft core embedded processors-a configurable 32-bit embedded RISC processor ARM®-based embedded processor family-an ARM9 Thumb® embedded processor core with 32-bit architecture 32-bit RISC engine MIPS-based® embedded processor family-a MIPS 4Kcembedded processor core with 32-bit architecture R4000TLB privileged-mode extensions.
Advantages SOPC
strengths design include higher integration increased system performance. SOPC designs additional benefits such programmability fast time-to-market, with flexibility PLDs. With these programmable devices, designer implement several different iterations system hardware fraction time required implement custom component version. This flexibility allows designers only develop product shorter amount
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first Excalibur embedded processor solution Nios family, 32-bit embedded RISC soft core processor that easily configured meet several different demands, rapidly integrated into Altera-based design. Although Nios embedded processors initially optimized APEXdevices, they
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Programmable Solutions Company®
Altera Corporation
Introducing Excalibur Development Featuring Nios
Development that Gets Cutting Edge
Niossoft core embedded processor, first Altera's Excaliburembedded processor solutions ship, delivers just what need create system-on-aprogrammable-chip (SOPC) designs. This flexible embedded processor solution offers 32-bit configuration, MIPS performance, equivalent volume price point development available with everything need started.
Free Hands-on Workshops
Intensive three-hour workshops, starting June, will teach create SOPC design using Nios soft core embedded processor APEX device. will develop compile code, then execute troubleshoot development board. will also learn about GNUPro Compiler Debugger from Cygnus, company, included Excalibur Development Kit.
Register Now!
reserve your space FREE Excalibur workshop nearest you, find more about this revolutionary development system, visit Altera's site http://www.altera.com/workshop.
Complete Solution Only $995
This Excalibur Development contains: Nios Configurable RISC Embedded Processor Core Peripherals QuartusProgrammable Logic Development Software GNUPro® C/C++ Compiler Debugger from Cygnus®, Hat® Company ByteBlasterMVDownload Cable Development Board Including APEXEP20K200E Device Reference Design Documentation
Free Excalibur Development Kit!
Each workshop will feature drawing free Excalibur Development Kit. must present win, sign today.
Copyright 2000 Altera Corporation. Altera, APEX, APEX 20K, APEX 20KE, ByteBlasterMV, Excalibur, Nios, Quartus, specific designations trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. rights reserved.
Table
Contents
FLEX Product Transitions FLEX 10KE Industrial-Temperature Devices 7000A Devices 7000B Devices Support Advanced Standards 7000S Family 3000A Devices 4-Mbit Configuration Device Coming Soon Quartus Software Version 2000.05 Available Quartus Operating System Update MAX+PLUS Software Version Shipping MAX+PLUS Version 9.62 Available Altera Site Renewal Price Promotion Customers Active Subscription License Files World-Class Synthesis Simulation Tools Available Today Discontinued Devices Update Technical Articles Nios Architecture Customization Successful In-System Programming Implementation Questions Answers Every Issue Current Software Versions Altera Publications Altera Programming Support Contact Altera. Altera Device Selection Guide
Features Altera Announces Nios Processor Embedded Systems Development Design Tips: Improving Quartus Design Performance Customer Application: Bridging Gap: dataBlizzard Reliaspan Altera News Altera Form Partnership Provide Development Software Nios Sign Free Excalibur Workshops ACEX Devices Address Communications Market Need Low-Cost Programmable Logic Altera's SignalTap Plus System Analyzer Provides Simultaneous On-Chip Off-Chip Debug Capabilities Technologies' CoreX-V10: Increased Performance Produces Faster Megafunctions True-LVDS Solution Provides 840-Mbps Data Transfer Rates Altera's Turbo Encoder Decoder Push Technology Envelope High-Speed Wireless Applications Devices Tools Eight APEX 20KE Devices Shipping True-LVDS Support APEX 20KE Devices 5.0-V Tolerant APEX APEX 20KE Devices APEX Product Transition ACEX Devices Shipping Now. ACEX Devices Coming Soon FLEX 10KE Devices Available
Altera, ACCESS Program, ACEX, ACEX ACEX AMPP, APEX, APEX 20K, APEX 20KE, Atlas, BitBlaster, ByteBlaster, ByteBlasterMV, Classic, ClockBoost, ClockLock, ClockShift, CoreSyn, E+MAX, EPC2, Excalibur, FastTrack, FineLine BGA, FLEX, FLEX 10K, FLEX 10KE, FLEX 10KA, FLEX 8000, FLEX 6000, FLEX 6000A, Jam, MasterBlaster, 9000, 9000A, 7000, 7000E, 7000S, 7000A, 7000AE, 7000B, 3000, 3000A, MAX, MAX+PLUS, MAX+PLUS MegaCore, MegaLAB, MegaWizard, MultiCore, MultiVolt, NativeLink, Nios, nSTEP, OpenCore, OptiFLEX, Quartus, SignalTap, SignalTap Plus, True-LVDS, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: Adobe Acrobat registered trademarks Adobe Systems Incorporated. ARM, Thumb, Powered logo registered trademarkes Limited. Microsystems registered trademark Microsystems. Data UniSite registered trademarks Data Corporation. HP-UX trademark Hewlett-Packard Company. Mentor Graphics registered trademark LeonardoSpectrum ModelSim trademarks Mentor Graphics. Microsoft, Windows, Windows Windows registered trademarks Microsoft Corporation. R4000, 4Kc, MIPS-based, MIPS Technologies logo trademarks MIPS Technologies, Inc. Cygnus, GNU, GNUPro, registered trademarks Hat, Inc. Rochester Electronics registered trademark Rochester Electronics, Inc. dataBLIZZARD trademark Technologies, Inc. registered trademark Solaris trademark Microsystems, Inc. Synopsys registered trademark FPGA Express trademark Synopsys, Inc. System General registered trademark System General. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. actual availability Altera's products features could differ from those projected this publication provided solely estimate reader. Copyright 2000 Altera Corporation. rights reserved. Printed recycled paper.
Lau, Publisher Greg Steinke, Technical Editor Innovation Drive Jose, 95134 Tel: (408) 544-7000 Fax: (408) 544-7809 n_v@altera.com
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Features Altera Announces Nios Processor Embedded Systems Development, continued from page will also available other Altera device architectures, including ACEXdevices low-cost implementations future device families enhanced performance. hard core Excalibur solutions based MIPS Technologies, Inc. processors. They implemented Altera's APEX architecture, will provide high-performance, embedded
Figure Excalibur Embedded Processor Solutions
peripherals within royalty-free, off-the-shelf products. Excalibur solutions ideal many embedded applications, including computer peripherals, industrial automotive control, image processing, set-top boxes, other communications applications. Figure shows families Excalibur embedded processor solution their relative performance levels. Figure shows roadmap future Nios embedded processors.
Nios Family Configurable Soft Core Embedded Processors
Nios family embedded processors first 32-bit processor core designed specifically programmable logic implementation, result, perform speeds million instructions second (MIPS). Designed with five-stage pipeline that executes instruction clock cycle, Nios family also user-configurable meeting different embedded design needs, supporting 32-bit data width register file depth ranging from general-purpose registers (for more information Nios architecture, page 20). Besides performance configurability, Nios processors also optimized resource efficiency, resulting lower-cost implementation than most offthe-shelf processors. Nios configured many ways suit different applications. Table illustrates Nios configurations, their speed resource utilizations, resulting costs.
Embedded Processor
MIPS Embedded Processor
Performance (MIPS)
Nios Embedded Processor
Soft Core
Hard Core
Figure Nios Roadmap
Future Architectures
Nios Development Environment
Performance (MIPS) Nios Embedded Processor APEX Devices
ACEX Devices
Table Nios Configurations Resource Usage EP20K100E Device Nios Data Address Configuration Width Width
Total
Total ESBs
Cost Implementation
Note: Based register file size.
Nios processor more than latest generation processor optimized programmable logic. Altera also provides elements necessary designer develop Nios-based system. Nios users integrate Nios embedded processor into their Altera designs with MegaWizard® Plug-In. MegaWizard Plug-In menu-driven application that allows users specify parameters they desire their Nios embedded processor. Based those parameters, MegaWizard Plug-In Manager generates netlist description specific Nios embedded processor that integrated into Altera design Quartusdevelopment system.
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Features Several peripherals also available with Nios family embedded processors, including universal asynchronous receiver/ transmitter (UART), timer/counter, memory controller (SRAM, ROM, FLASH), parallel (PIO) module. these easily integrated into user's design along with their unique Nios configuration. coding support, Altera partnered with Cygnus®, Hat® company, provide powerful familiar GNU®-based C/C++ compiler assembler. source-level debugger accesses device through serial port, providing control access memory register file. Figure shows development flow Excalibur embedded processor solution. embedded processor, which contains software hardware components designer needs begin using Nios embedded processor immediately. includes following items: Nios soft-core embedded processor C/C++ compiler, assembler, debugger, documentation Nios peripherals (UART, memory interface, timer/counter, module) Quartus development software (supports APEX devices SignalTapembedded logic analysis) ByteBlasterMVdownload cable Development board (including APEX EP20K200E device, SRAM/FLASH, expansion/prototype connectors, processor trace port) Software drivers (UART, timer/counter, module) SOPC reference design Nios user manual programmer reference manual
Excalibur Development Kit, Featuring Nios
support Nios family soft core embedded processors, Altera offers Excalibur Development Kit, featuring Nios
Figure Excalibur Workflow Simplifies SOPC Designs
Select Configure Processor
Select Configure Peripherals
Configure Registers
Quartus Software Industry-Standard Tools
Verilog
Generate Peripheral Module
Code
Cygnus/Red GNUPro Compiler Debugger
SignalTap Plus Trace JTAG
APEX Architecture
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Features Altera Announces Nios Processor Embedded Systems Development, continued from page based designs free charge. Products that ship with Nios embedded processor subject zero-cost license which available on-line Altera site (http://www.altera.com). Excalibur Development available contains information obtaining product license. also contact your local Altera sales office representative visit Altera's site. more detailed information developing with Nios family, attend free Nios workshops scheduled worldwide (see "Sign Free Excalibur Workshops" below more information).
Licensing Availability
Nios embedded processor first member Excalibur solutions available now. ARM- MIPS-based members Excalibur family will available royalty-free standard products fourth quarter 2000. Designers Nios embedded processor develop Nios-
Altera Form Partnership Provide Development Software Nios
Altera Hat®, Inc. worked together provide Altera users with powerful complete software development environment Niosfamily soft core embedded processors. Through close collaboration, they created suite GNUPro® embedded system tools, including C/C++ compiler, assembler debugger, specifically optimized support Nios instruction set. This suite tools from Cygnus®, Hat® company, included ExcaliburDevelopment Kit, along with other components needed begin using Nios embedded processor immediately. "Our work with signifies commitment deliver robust open development platform embedded systems designers," said Cliff Tong, Corporate Marketing. "With Excalibur Development featuring Nios embedded processor, Altera provides valuable integrated platform hardware software codevelopment." "Cygnus well known embedded systems industry most highly-respected providers tools operating systems," added Mike Phipps, Director Marketing Altera. "With Hat's backing, users familiar dependable tools that fully supported, tested certified." Altera will continue their future support Nios embedded processor with port eCos, embedded configurable real time operating system.
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Devices
Tools Table APEX 20KE Device Quartus Software Support Availability Device Package Software Support Availability
2000 2000 2000 2000 EP20K30E 144-pin TQFP 144-pin FineLine 208-pin PQFP 324-pin FineLine EP20K60E 144-pin TQFP 144-pin FineLine 208-pin PQFP 240-pin PQFP 324-pin FineLine 356-pin EP20K100E 144-pin TQFP 144-pin FineLine 208-pin PQFP 240-pin PQFP 324-pin FineLine 356-pin EP20K160E 144-pin TQFP 208-pin PQFP 240-pin PQFP 356-pin 484-pin FineLine EP20K200E 208-pin PQFP 240-pin PQFP 356-pin 484-pin FineLine 652-pin 672-pin FineLine EP20K300E 240-pin RQFP 652-pin 672-pin FineLine EP20K400E 652-pin 672-pin FineLine EP20K600E 652-pin 672-pin FineLine 1,020-pin FineLine
APEX
Eight APEX 20KE Devices Shipping
Four more APEX20KE devices have been released, making total eight APEX 20KE devices shipping: EP20K60E, EP20K100E, EP20K200E, EP20K300E, EP20K400E, EP20K600E, EP20K1000E, EP20K1500E devices. These devices available many advanced packages, including FineLine BGApackages. remaining APEX 20KE devices scheduled ship third quarter 2000. Software support currently available Quartussoftware version 2000.05 devices except EP20K30E device (see Table
True-LVDS Support APEX 20KE Devices
Altera® APEX 20KE devices offer TrueLVDSsolution with data transfer rate megabits second (Mbps) channel. This specification exceeds widely accepted low-voltage differential signaling (LVDS) standard data transfer rate Mbps. APEX 20KE programmable LVDS bandwidth 26.8 gigabits second (Gbps).
5.0-V Tolerant APEX APEX 20KE Devices
APEX device family been enhanced provide 5.0-V tolerant buffer, providing full compliance with 5.0-V peripheral component interconnect (PCI) specification. These 5.0-V tolerant devices shipping. APEX 20KE devices with additional external resistor make these devices 5.0-V tolerant provide flexibility system design. technical details this improvement described 5.0-V Tolerance APEX 20KE Devices White Paper Altera site (http://www.altera.com).
EP20K1000E 652-pin 672-pin FineLine 1,020-pin FineLine EP20K1500E 652-pin 1,020-pin FineLine
Note: TQFP: thin quad flat pack, PQFP: plastic quad flat pack, BGA: ball-grid array, RQFP: power quad flat pack
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Devices Tools Devices Tools, continued from page Full software support ACEX devices available from MAX+PLUS® software version 9.6. addition, wide range ACEXoptimized intellectual property (IP) functions found Altera MegaStoreonline store.
APEX Product Transition
Altera migrating 2.5-V EP20K400 device from 0.25-µm process 0.22-µm process. Information regarding this device migration found process change notification (PCN) 0005, available Altera site.
ACEX Devices Coming Soon
1.8-V ACEX device family will released soon. These devices range from 20,000 150,000 typical gates provide additional benefits cost performance highvolume communications designs. These devices also offer feature that includes enhanced capabilities, advanced standard support, dual-port embedded RAM. ACEX device support will available from Quartus software second half 2000.
ACEX
ACEX Devices Shipping
ACEX devices shipping packages 30,000, 50,000, 100,000 gate densities. ACEX1K devices shipping packages 30,000, 50,000, 100,000 gate densities (see Table These cost-optimized devices especially well suited low-cost, high-performance communications applications, used attain lowest cost programmable logic device (PLD) high-volume designs.
Table ACEX Device Offerings Device
EP1K10
FLEX
FLEX 10KE Devices Available
Package
100-pin TQFP 144-pin TQFP 208-pin PQFP 256-pin FineLine
Availability
August 2000 August 2000 August 2000 August 2000
EP1K30
144-pin TQPF 208-pin PQFP 256-pin FineLine
EPF10K30E, EPF10K50S, EPF10K100E, EPF10K130E, EPF10K200S devices shipping speed grades. These devices fabricated 0.22-µm process have programmable input buffer delay full 64-bit, 66-MHz compliance. FLEX® 10KE devices offered with feature speed grades reduce clock skew allow clock multiplication. These devices have suffix ordering code (e.g., EPF10K100EQC208-1X). assist designers implementing their projects FLEX 10KE devices, MAX+PLUS software offers design support device package options. Table shows 2.5-V FLEX 10KE device packages speed grades.
EP1K50
144-pin TQFP 208-pin PQFP 256-pin FineLine 484-pin FineLine
EP1K100
208-pin PQFP 256-pin FineLine 484-pin FineLine
ACEX devices provide full phase-locked loop (PLL) capability ClockLockand ClockBoostfeatures every speed grade device, embedded dual-port RAM, full 64-bit, 66-MHz compliance. Developed innovative 0.22-µm/0.18-µm hybrid process, featuring 2.5-V core operating voltage, ACEX devices offer ideal combination cost, performance, features.
FLEX Product Transitions
2.5-V EPF10K50E EPF10K200E devices have migrated from 0.25-µm process 0.22-µm process. other members FLEX 10KE family already manufactured 0.22-µm process. EPF10K50V devices migrating from 0.30-µm, 3-layer-metal
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Table FLEX 10KE Devices Device
EPF10K30E
Table FLEX Device Migration
Speed Grade
-1X, Sept. 9915 0.30 -1X, -1X, -1X, -1X, EPF10K50E EPF10K200E Done Done EPF10K50 Done EPF10K30 Done EPF10K20 Done EPF10K100A EPF10K10 Done Done 9810 9901 9909 9901 9909 9901 9909 9901 9909 9911 9911 0.22 0.22 0.42 0.42 0.42 0.30 0.42 2000 EPF10K10A EPF10K30A EPF10K50V
Offerings
144-pin TQFP 208-pin PQFP 256-pin FineLine 484-pin FineLine (all packages)
Device
Core Voltage
Date
Reference Process (µm)
9810 9810 9810 0.30 0.30 0.30
Done Done Done
EPF10K50S
144-pin TQFP 208-pin PQFP 240-pin PQFP 256-pin FineLine 356-pin 484-pin FineLine (all packages)
EPF10K100E
208-pin PQFP 240-pin PQFP 256-pin FineLine 356-pin 484-pin FineLine (all packages)
EPF10K130E
240-pin PQFP 356-pin 484-pin FineLine 600-pin 672-pin FineLine (all packages)
Notes: 3-layer metal process. 4-layer metal process.
EPF10K200S 240-pin RQFP 356-pin 484-pin FineLine 600-pin 672-pin FineLine (all packages)
Table FLEX 10KE Industrial-Temperature Device Availability Device
EPF10K30EQI208-2 EPF10K30EFI256-2 EPF10K50ETI144-2
Availability
FLEX 10KE devices available industrial-temperature grades.
process 0.30-µm, 4-layer-metal process September 2000. Table outlines process migration schedule lists reference documentation associated with this migration. download these documents from Customer Notifications page Altera site http://www.altera.com.
EPF10K50EQI240-2 EPF10K50EFI256-2 EPF10K50SQI208-2 EPF10K50SBI356-2 EPF10K50SFI484-2 EPF10K100EQI208-2 EPF10K100EFI256-2 EPF10K100EFI484-2
FLEX 10KE Industrial-Temperature Devices
FLEX 10KE devices available industrial-temperature grades. Table lists industrial-temperature FLEX 10KE devices.
EPF10K130EQI240-2 EPF10K130EBI356-2 EPF10K130EFI484-2 EPF10K200EBI600-2 EPF10K200SRI240-2 EPF10K200SBI356-2 EPF10K200SFI672-2
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Devices Tools Devices Tools, continued from page
7000B Devices Support Advanced Standards
With support advanced standards such Gunning transceiver logic plus (GTL+) stub-series terminated logic (SSTL-2) 3.3-V SSTL-3, 7000B devices offer flexible solution design requirements. 2.5-V 7000B devices range from macrocells with propagation delays fast Additionally, 7000B devices feature enhanced ISP, MultiVolt pins, compatibility with industry-standard 7000 devices. Table shows commercial package speed grade options. Contact your Altera sales representative device availability.
Table 7000B Commercial-Temperature Devices Device Package
44-pin PLCC 44-pin TQFP 48-pin TQFP 49-pin Ultra FineLine EPM7064B 44-pin PLCC 44-pin TQFP 48-pin TQFP 49-pin Ultra FineLine 100-pin TQFP 100-pin FineLine EPM7128B 49-pin Ultra FineLine 100-pin TQFP 100-pin FineLine 144-pin TQFP 169-pin Ultra FineLine 256-pin FineLine EPM7256B 100-pin TQFP 144-pin TQFP 169-pin Ultra FineLine 208-pin PQFP 256-pin FineLine EPM7512B 100-pin TQFP 144-pin TQFP 169-pin Ultra FineLine 208-pin PQFP 256-pin 256-pin FineLine
7000A Devices
feature-rich MAX® 7000A devices support enhanced in-system programmability (ISP), MultiVoltI/O pins, hot-socketing capability compatibility with industrystandard 7000 devices. 3.3-V 7000A devices range from macrocells with propagation delays fast 7000A devices available industrialtemperature grades. Table shows 7000A device commercial package speed-grade options.
Table 7000AE Commercial-Temperature Devices Device
EPM7032AE
Speed Grade
EPM7032B
Package
44-pin PLCC 44-pin TQFP
Speed Grade
-10, -10, -10, -10,
EPM7064AE
44-pin PLCC 44-pin TQFP 49-pin Ultra FineLine 100-pin TQFP 100-pin FineLine
7000B devices feature enhanced ISP, MultiVolt pins, compatibility with industry standard 7000 devices.
EPM7128AE
84-pin PLCC 100-pin TQFP 100-pin PQFP 144-pin TQFP 169-pin Ultra FineLine 256-pin FineLine
EPM7256AE
100-pin TQFP 100-pin FineLine 144-pin TQFP 208-pin PQFP 256-pin FineLine
EPM7512AE
144-pin TQFP 208-pin PQFP 256-pin 256-pin FineLine
Notes: PLCC: plastic J-lead chip carrier. Ultra FineLine packages Altera's 0.8-mm pitch packages.
Note: Ultra FineLine packages Altera's 0.8-mm pitch packages.
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7000S Family
5.0-V 7000S devices offer features such 5-ns speed grades, in-system programming, open-drain output option, IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry devices with more macrocells. 7000S devices available industrial-temperature grades. Table shows packages speed grades available commercial-temperature grade.
Table Commercial-Temperature 7000S Devices Device
EPM7032S
CONFIGURATION
4-Mbit Configuration Device Coming Soon
4-Mbit EPC4E configuration device scheduled release third quarter 2000. This device will offered 44-pin 100-pin TQFP packages well 0.8-mm, 144-pin Ultra FineLine package. 9-Mbit EPC9E configuration device also being developed slated release third quarter 2000. single EPC4E device will configure 400,000-gate EP20K400E device, single EPC9E device will configure 1-million-gate EP20K1000E device. These devices will include features such faster configuration times parallel configuration. Additionally, single device configure several APEX FLEX devices parallel further speed configuration time.
Package
44-pin PLCC 44-pin TQFP
Speed Grade
-10, -10, -10, -10, -10, -10,
EPM7064S
44-pin PLCC 44-pin TQFP 84-pin PLCC 100-pin TQFP
EPM7128S
84-pin PLCC 100-pin TQFP 100-pin PQFP 160-pin PQFP
EPM7160S
84-pin PLCC 100-pin TQFP 160-pin PQFP
TOOLS
Quartus Software Version 2000.05 Available
Quartus software version 2000.05 shipping customers with current subscription single upgrade package that includes MAX+PLUS software version 9.6, Synopsys FPGA Express-Altera version synthesis software, Exemplar Logic LeonardoSpectrum-Altera version 1999.j synthesis software. Version 2000.05 Quartus software provides significant performance fitting improvements large designs. also provides support device packages shown Table addition device packages supported version 2000.03.
EPM7192S EPM7256S
160-pin PQFP 208-pin PQFP
3000A Devices
3000A devices ideal low-cost solution designers looking high performance price-per-macrocell cost. 3.3-V product-term-based 3000A devices targeted high-volume, low-cost designs. These devices have enhanced feature range density from macrocells (see Table with propagation delays fast
Table 3000A Devices Device
EPM3032A
Package
44-pin PLCC 44-pin TQFP
Speed Grade
Quartus Operating System Update
Quartus software version 2000.05 supports operating systems listed Table Support Windows 2000 HP-UX 11.0 operating systems will added later this year. continued page
EPM3064A
44-pin PLCC 44-pin TQFP 100-pin TQFP
EPM3128A
100-pin TQFP 144-pin PQFP
EPM3256A
144-pin TQFP 208-pin PQFP
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Devices Tools Devices Tools, continued from page
Table Devices Supported Quartus Version 2000.05 Support
Full Compilation, Simulation EP20K200 356-pin 652-pin BGA, 672-pin FineLine EP20K300E EP10K600E EP20K1000E Compilation, Simulation, Pin-Out Support Only EP20K1500E EP20K160E 652-pin 144-pin TQFP, 208-pin PQFP, 240-pin PQFP, 356-pin BGA, 484-pin FineLine 652-pin BGA, 1,020-pin FineLine 240-pin PQFP, 652-pin BGA, 672-pin FineLine 672-pin FineLine
MAX+PLUS software version shipping customers with current subscriptions features support ACEX device family.
Device
EP20K100 EP20K100E
Package
356-pin 324-pin FineLine
advanced pin-out support devices listed Table This update also includes several software improvements Quartus fitter, timing model changes, EPM7128B EPM7256B device programming. This software update available opening Software Tools menu left Altera site selecting MAX+PLUS Updates. using MAX+PLUS BASELINE E+MAXdevelopment system, eleminate problems using version 9.62 MAX+PLUS BASELINE E+MAX software, which available.
Table Devices Supported MAX+PLUS Version Support
Full Compilation, Simulation Programming Support EP1K30 EPM7256B
Programming EP20K200E Support
Device
EPM7128B
Package
100-pin FineLine BGA, 256-pin FineLine 100-pin TQFP, 144-pin TQFP, 208-pin PQFP, 256-pin FineLine 144-pin TQFP, 208-pin PQFP, 256-pin FineLine
Note: Quartus software version 2000.05 supports these devices with without PLLs.
EP1K50
144-pin TQFP, 208-pin PQFP, 256-pin FineLine BGA, 484-pin FineLine
Table Quartus Operating System Support Platform
UNIX
Operating System
Windows Windows Solaris 2.6, HP-UX 10.20
Compilation, Simulation,
EP1K100
208-pin PQFP, 256-pin FineLine BGA, 484-pin FineLine
EPM7128B
49-pin Ultra FineLine BGA, 169-pin Ultra FineLine
MAX+PLUS Software Version Shipping
MAX+PLUS software version shipping customers with current subscriptions features support ACEX device family. ACEX family Altera's mid-range density, look-up table (LUT)-based family offering cost high performance necessary pricesensitive communications applications. complete list device support MAX+PLUS software version 9.6, Table
Pin-Out Support Only
EPM7256B EPM7512B
169-pin Ultra FineLine 169-pin Ultra FineLine
EPM7064AE 49-pin Ultra FineLine EPM7128AE 169-pin Ultra FineLine
Table Additional Devices Supported MAX+PLUS Version 9.62 Support
Full Support
Device
EPM7128BFC256, EPM7256BFC256, EPM7512BQC208
Advanced Pin-Out Support
EP1K10TC100, EP1K10TC144, EP1K10QC208, EP1K10FC256, EPM7032BUC49, EPM7064BUC49
MAX+PLUS Version 9.62 Available Altera Site
MAX+PLUS software version 9.62 update platform adds full support
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Renewal Price Promotion Customers Active Subscription
limited time, Altera customers with current subscriptions will receive discount renewal subscription list price long renewal subscription ordered before their current subscription expires. This offer valid customers active subscription. renewal ordering code used renew FIXEDPC, FLOATPC, FLOATNET subscriptions. discount applies orders received before subscription expiration date. renewal subscription extends subscription months from existing expiration date. Customers lose months their existing subscription renewing early. will receive updates both Quartus MAX+PLUS software additional months after your current subscription expire. also receive world-class synthesis simulation software with renewal your subscription. synthesis, Synopsys FPGA Express-Altera Exemplar Logic LeonardoSpectrum-Altera included with your renewal. will also receive Model Technology ModelSim-Altera behavioral simulation test bench support. renewing subscription before expires, guaranteed receive latest version Quartus MAX+PLUS software without interruption gain access world class synthesis simulation software.
capabilities with Altera software. FPGA Express only available platform, working with FIXEDPC FLOATPC products. LeonardoSpectrum ModelSim software Altera available UNIX workstations fixed floating configurations. Synopsys FPGA Express Altera supports mixed-HDL synthesis VHDL Verilog designs. feature FPGA Express software that Altera ships identical standard FPGA Express software. However, FPGA Express software only targets Altera devices. LeonardoSpectrum license files, request either VHDL Verilog support each Altera subscription, both-you only have support Altera subscription. LeonardoSpectrum Level Altera Level software tools support mixed-HDL synthesis. LeonardoSpectrum Level synthesis tool provided Altera includes features LeonardoSpectrum Level configuration, only allows designers target Altera devices. ModelSim-Altera simulation software consists ModelSim features including standard debugging environment scripting capability supporting Altera libraries gate-level simulation. request either VHDL Verilog support within ModelSim software each Altera subscription, both. ModelSim-Altera software tools support mixed-HDL simulation. indefinitely versions Synopsys FPGA Express software Altera received during your active subscription. However, cannot enable versions FPGA Express released after your subscription expires. This identical licensing Quartus MAX+PLUS software. License files Exemplar Logic LeonardoSpectrum Model Technology ModelSim software provided Altera expire months from date license request. These products will longer operate after expiration. However, request license extend expiration another months long your subscription remains active.
Altera entered into agreements with Synopsys Mentor Graphics provide Altera customers with world-class synthesis simulation products.
License Files World-Class Synthesis Simulation Tools Available Today
Altera entered into agreements with Synopsys Mentor Graphics provide Altera customers with world-class synthesis simulation products. Altera shipping Synopsys FPGA Express version Exemplar Logic LeonardoSpectrum Level version 1999.1j synthesis software customers with current subscriptions. Model Technology ModelSim-Altera simulation software will shipping customers shortly. Visit Altera site request license file enable software tools. license file will e-mailed directly enable these synthesis simulation
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Design
Tips
Improving Quartus Design Performance
Quartussoftware version 2000.02 higher introduces improved timingdriven compilation algorithms core performance well more capability cliques. most cases, push-button performance Quartus software achieve desired requirements core fMAX timing. Many additional techniques used achieve even better performance APEXdesigns with Quartus software, including: Timing-driven compilation Cliques other logic options Back-annotation manual placement Speed Area setting, Auto-Global Memory Control Signals setting. Cliques Version 2000.02 higher Quartus software provides cliques different target sizes, controlling tightly pack logic. Target areas small logic array block (LAB) half device. cliques with timing-driven compilation off. Altera recommends that enable timing-driven compilation with hierarchical-based cliques based your knowledge your design. cliques (except Best cliques, Figure considered hard assignments that create complications they cannot met. no-fit result much logic placed into small area (i.e., placing logic cells into LAB). unsure size cliqued logic, Best clique type, which allows Quartus software modify size clique target needed. After initial compilation results with timingdriven compilation hierarchical cliques,
Figure Clique Selection Assignment Organizer
Timing-Driven Compilation
Quartus software very flexible, offers large number options that within. global timing-driven compilation target entire design, several timingdriven compilation target settings, each individual clock domain several exist design). Individual clock settings usually provide better fMAX results (and required multiple clock domain analysis hold-time validation). optimal results, experiment with both global individual settings. Quartus software version 2000.02 higher, either select Normal compilation Extra effort. Extra effort setting usually provides better fMAX results, increase compile times either case, should target fMAX about higher than required vary target until find best results. target high, though, over-constrain Quartus software, producing slower results.
Cliques Other Logic Options
options settings Quartus software improve results, including cliques,
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Design Tips analyze critical paths, determine logic common between multiple critical paths, apply clique place logic cells closer together (see Figure should cliques only when your design performance much slower than what required; avoid assigning logic haphazardly into cliques without verifying that logic cells placed into multiple cliques same size. This more logic into original clique size, which result no-fit. Settings settings make affect performance results Quartus software. significant settings are: Speed Area: Optimization Technique option Option Parameter Settings (Project menu) either Speed optimize design performance (tight routing, redundant logic fanout) Area optimize device space (loose routing, minimal/optimized logic). this option files, although most effective Altera Hardware Description Language (AHDL) Text Design Files (.tdf) Block Design Files (.bdf). should synthesize Verilog VHDL designs with other third-party synthesis tools. Auto-Global Memory Control Signals: improve your design's performance turning this setting off. This setting enabled default instructs Quartus software global-control interconnect lines whenever possible memory control signals. However, this slow memory performance internallygenerated control signals able drive memory blocks directly without using global control lines. Extra delay incurred when routing onto global control lines prior memory blocks.
Figure Cliquing Common Logic Cells
manually moving logic yourself speed your design. Back-annotation very powerful because Allows maintain fitting results from version Quartus software other versions Quartus software, either older newer improve fitting time (from hours down minutes), since Quartus software devotes less time with logic placement Locks down specific parts design, maintaining speed those portions design
drawback that design changes significantly, some most backannotated assignments lost resynthesis renaming node names. following indicators help determine should back-annotate your design: design stable (will there more code changes)? Path dependencies: there logic common multiple critical paths? there only paths that meet performance goals? compile times long?
Back-Annotation Manual Placement
Your timing-driven compilation targets, cliques, options settings bring your design performance close required specifications, they enough. then back-annotate design results placement,
back-annotate your design, should consider several guidelines. well-utilized designs (60% higher), should backannotate logic array blocks (LABs) instead logic cells ensure second-time fitting after logic rearranged. have demote assignments MegaLABblocks. Here additional guidelines: Always ignore disable cliques back-annotate your design; these assignments will override cliques. continued page
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Altera Corporation
Design Tips Design Tips: Improving Quartus Design Performance, continued from page Archive back-up project files from your best compilation date. next round changes slower than your best fMAX results, should revert back files from your best compilation. This easily done archived files. determine which cells move, look cells that have smallest fan-in fan-out. These cells that will likely have least impact other potentially critical paths. should avoid making other critical paths worse when moving logic cells another critical path. However, some cases, increasing delay some paths when fixing other critical paths good tradeoff slowed paths critical. Short paths (i.e., back-to-back registers) with plenty margin good candidates balance delay (see Figure Logic common multiple critical paths also resolved with manual placement. Create efficient layout moving logic cells that appear several paths (e.g., control signals such enables, address decoders, other high fanout situations). Figure fixing path, several others. Critical paths should cross MegaLAB columns infrequently possible (avoid using rowinterconnect lines). When using MAX+PLUS® software FLEX® designs, improve performance when keep paths same row. However, this does hold true APEX designs Quartus software. Essentially, MegaLAB blocks MegaLAB columns APEX devices equivalent LABs rows LABs FLEX devices. This also applies when clique large blocks logic together.
goal minimize amount interconnect delays used path (see Figure hence consolidating logic much possible. Determine where critical paths cross MegaLAB boundaries. Logic cells should always moved into MegaLAB bins, instead specific logic cell locations. Quartus software determines legal placement routing you.
Figure Making LAB-Based Location Assignments
Figure Increasing Path Delay Helps Path Timing
Path Delay Specification Path Delay Timing still met.
Summary
Quartus software version 2000.02 higher comes equipped allow achieve performance goals various ways. cannot meet performance with push-button timing-driven compilation operation, combination cliques, settings, backannotation, manual placement often extra performance necessary APEX designs. important realize that there "best" method achieve performance Quartus software. options that work best vary design, steps outlined this article should help improve your performance.
Path Delay Specification
Path Delay Timing met.
Figure Assigning Common Logic Cells LABs
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Altera News
Sign Free Excalibur Workshops
Intensive three-hour workshops, starting June, will teach implement Niosfamily soft core embedded processors APEXdevices. These hands-on workshops will allow work with ExcaliburDevelopment Kit, from creating design running development board tracking down correcting design errors. will also learn about GNUPro® compiler debugger from Cygnus®, Hat® company, which included Excalibur Development Kit. Visit http://www.altera.com/workshop reserve your space North American workshops. sign free workshops outside North America, contact your local Altera representative.
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North Carolina Reasearch Triangle Park July June June July July July August July July August August August August August August August August July England London France Paris Germany Munich Israel Aviv Italy Milan Sweden Stockholm Ohio Fairborn Ontario, Canada Kanata Mississauga Oregon Beaverton Texas Richardson Austin Utah Salt Lake City Washington Bellvue Europe
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Altera Corporation
Customer
Application
Bridging Gap: dataBLIZZARD Reliaspan
Ultimate performance, high availability, redundancy three demanding requirements telecom industry heralds generation communications interfaces. Technologies Connectivity Products addressed these demands with breakthrough product lines: dataBLIZZARDand Reliaspan products. telecom computer telephony applications that were once previously limited number cards that host could support. Historically, designed interfaces, dataBLIZZARD software Reliaspan, chose move into 64-bit, 66-MHz realm intellectual property (IP). Using programmable logic device (PLD) with function, entered market quickly without losing design flexibility. thoroughly evaluated cores offered programmable logic vendors applied following criteria: performance, flexibility, stability features, documentation, allowable design re-use. result this evaluation, selected Altera® FLEX® family both dataBLIZZARD Reliaspan products over companies that working 64-bit, 66-MHz function designs. Only Altera could offer four more base address registers-an essential feature that allowed maintain compatibility with suite software drivers written earlier generation products. William Molyneux, vice president engineering, Connectivity Products, stated that "Reliaspan dataBLIZZARD software represent significant breakthroughs SBS. Both will shipped high volumes will have very long product life cycles." Molyneux also affirmed that "Altera sole vendor with bridge experience using core which substantially lowered risk. Altera became more partner than vendor. They made every effort support developments with their engineering resources."
dataBLIZZARD product family includes PCI, mezzanine card (PMC), CompactPCI formats, which will used medical imaging, telecommunications, other industrial applications.
dataBLIZZARD software ultimateperformance, point-to-point communications interface that enables computers share data hardware level with little software overhead (see Figure dataBLIZZARD peripheral component interconnect (PCI) interface that supports data sharing flexible, providing highest performance allowed bus. integrated direct memory access (DMA) engine transfer data between systems sustained transfer rates megabytes second. Programmed processes completed over link less than data transferred meters over dataBLIZZARD's gigabit fiber-optic transceivers. dataBLIZZARD product family includes PCI, mezzanine card (PMC), CompactPCI formats, which will used medical imaging, telecommunications, other industrial applications. Reliaspan, SBS' exceptionally fast, highthroughput 64-bit expansion systems CompactPCI computers, designed provide servers with expansion capabilities through addition seven CompactPCI slots. With Reliaspan, host server gracefully scaled accommodate more CompactPCI slots, they needed. This especially important high-availability
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Customer Application Reliaspan CompactPCI expansion systems were introduced Computer Telephony Exposition last March. dataBLIZZARD family introduced Intel's Applied Computing Show May. Both dataBLIZZARD software Reliaspan have already been designed into several major projects. Technologies, Inc., Connectivity Products premier provider high-performance reliable connectivity products that include bridges expansion units that designed operate most demanding applications. Technologies, Inc. leading manufacturer standard embedded computer components VME, CompactPCI, embedded custom standalone applications. product lines include (Pentium PowerPC) boards, input/output (I/O) modules, avionics modules analyzers, interconnection products, expansion units, real-time networks, telemetry boards, data acquisition software, DIN-rail embedded PCs, industrial-grade computers. Technologies' embedded computer components used variety applications, such communications, medical imaging, industrial control flight instrumentation commercial aerospace markets. Connectivity Products 1284 Corporate Center Drive Paul, 55121-1245 (651)905-4700 http://www.sbs-cp.com
Figure dataBLIZZARD Connection
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Altera Corporation
Technical
Articles
Nios Architecture Customization
Inside Nios Embedded Processor
first RISC processors developed specifically programmable logic, Niosfamily soft core embedded processors contains many configurable elements meet wide range needs. block diagram Figure shows basic elements Nios embedded processor. configure address data widths maximum bits. register file, stored embedded system blocks (ESBs), words deep with 32-bit viewable window. Nios interrupt controller supports internal external sources. peripherals Nios family, including universal asynchronous receiver/transmitter (UART), counter/timer, memory controllers, parallel (PIO) connection. Other peripherals, such SDRAM controller, SPI, PWM, 10/100 Ethernet MAC, disk controller will released later this year. MegaWizard® Plug-In Manager, also included, lets connect configure your Nios peripherals Nios embedded processor. Wait states, interrupt control, variable sizers, address decoding automatically generated MegaWizard Plug-In Manager within peripheral module (PBM), shown Figure example, MegaWizard Plug-In Manager specify which peripherals interrupt Nios embedded processor; each peripheral that does, MegaWizard Plug-In Manager automatically assigns address interrupt look-up table (LUT) generates corresponding interrupt control logic. also choose number wait states each peripheral needs, allow peripheral generate wait signal Nios embedded processor; either case, MegaWizard Plug-In Manager designs wait state generator accordingly. MegaWizard Plug-In Manager uses size converters adapt 32-bit peripherals Nios 16-bit configurations needed. Finally, MegaWizard Plug-In Manager creates address decoding within generate necessary chip selects. addition generating PBM, MegaWizard Plug-In Manager also defines connection between Nios embedded processor PBM, between peripherals. MegaWizard Plug-In Manager outputs Verilog files containing connectivity, PBM, Nios design that easily integrated into APEX20K device through Quartussoftware.
Using Nios Peripherals
ExcaliburDevelopment Kit, featuring Nios embedded processor, includes several
Figure Nios Block Diagram
Excalibur Nios RISC Processor (32-bit configuration)
address
Program Counter
data
Effective Address data
Instruction Decoder
read/write ifetch byte enable wait
Control
Operand Fetch
Clock Enable
irq#
Interrupt Control
General-Purpose Register File
clock reset
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Figure Nios Embedded Processor
Peripheral Module Peripherals
UART Address Decode Port Interface Timer Interrupt Control
Nios Processor
External Memory
Wait State Generation
Internal Memory
Data Multiplexer
User-defined Peripheral
User-defined Peripheral Sizing (Optional)
Customizing Nios Embedded Processor
addition customization userselectable parameters, design other peripherals supplement Nios embedded processor. These peripherals anything supported APEX device resources, including custom memory controllers, functions such filters FFTs, encoders/decoders,
proprietary interfaces, etc. User-defined peripherals handled same Altera peripherals; assign interrupts wait states using MegaWizard Plug-In Manager, which automatically generates necessary logic connectivity files (users also have choice creating their connections).
Current Software Versions
Quartussoftware version 2000.05 latest release, available following operating systems: Microsoft Windows Microsoft Windows Solaris version HP-UX version 10.20 higher; however, HP-UX version 11.0 higher supported MAX+PLUS® software version available following operating systems: Microsoft Windows Windows Microsoft Windows version 3.51 higher Solaris version higher HP-UX version 10.20 higher; however, HP-UX version 11.0 higher supported version higher
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Altera Corporation
Technical Articles
Sucessful In-System Programming Implementation
Altera supports JamStandard Test Programming Language (STAPL) format, which allows program IEEE 1149.1 Joint Test Action Group (JTAG)-compliant devices independent platform vendor. In-system programmability (ISP) accomplished through 4-wire JTAG interface. addition, STAPL simplifies software support allowing programming software environment: workstation, over network, embedded environment. successfully, must plan following areas product development: Board Layout-connecting JTAG chain. Treat clock trace, task often overlooked embedded systems where originates processor's general pin. Lack signal integrity this trace often source programming errors. Embedded Memory Requirement-for infield upgrades. embedded environment, STAPL Byte-Code software requires memory program devices JTAG chain. important consider this requirement before choosing memory processors used in-field upgrade.
Figure Error Flow Chart
Case Unrecognized Device
Port address provided?
option. Re-run player.
Successful? Done.
using Windows ByteBlasterMV driver installed? Install driver.
Using 16-bit jbi.exe?
32-bit (16-bit cannot port).
Re-run player. Successful? Done.
Does idcode.jam produce successful execution?
cable connected correct parallel port?
Connect cable parallel port.
Yes.
cable powered correct level?
cable that given provide correct VCC.
more information these topics Application Note (In-System Programmability Guidelines), Application Note (Using STAPL Embedded ICR). Following steps listed Application Note Application Note 122, reduce your costs improve product quality. encounter error during programming, flow chart shown Figure will help determine source problem. addition, download idcode.jam STAPL file from Altera® site: ftp:\\ftp.altera.com\pub\misc. this file read JTAG IDCODE Altera devices. cannot read IDCODE, then have signal integrity JTAG connectivity issue. flow chart Figure determine where problem
Have used cable program device.
another cable. Successful?
Done.
cable program known "good" board. Successful?
Cable bad; different one. Successful?
Done.
Cable good. using Lattice ByteBlasterMV cable? Lattice using command-line option? ByteBlasterMV using command-line option? option.
optio
Notes: Application Note (In-System Programmability Guidelines)
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Technical Articles
TCK, TMS, device pins wiggle? ground proper levels? Adjust accordingly re-apply idcode.jam file. idcode.jam There open short board that must fixed. execution successful. ground pins connected properly? Connect pins re-apply idcode.jam file.
Case (Device programming failure)
Case (idcode.jam file execution successful).
noisy device pin?
suggestions buffering termination. Done.
Case (Device verify failure)
Case (idcode.jam file execution successful).
Does while programming file? Supply strong enough. supply re-apply idcode.jam file.
Does meet tR,tF parameters?
buffer alter board improve edge rates.
free running clocks signals running?
Does wiggle?
Lift pin. Player. Does wiggle?
excessive undershoot overshoot?
Clean signals re-apply idcode.jam file.
short open trace. Done.
Device damaged. Replace. back beginning.
device hotter cooler than recommended
Adjust ambient temperature accordingly re-apply idcode.jam file.
Noisy?
buffering termination. Done.
error reproduced Altera with factory device?
Work with Altera solution. Done.
Does show accurate IDCODE? Functional issue.
Blank check device. Does pass?
Unrecognized device "Device blank" message?
Device Issue. Work with Altera solution. Find device that passes.
idcode.jam file uses wrong IDCODE.
Solder new, good device board. Programming successful? Previous device functional. Done.
Case Successful Error)
Default: (All other error codes)
Does Returned Error device Code operate?
Done.
Does Altera failure analysis reveal functional issue? Device issue, Work with Altera Applications. Done.
Contact Altera with error code, file, device-type being programmed.
initialization values actions provided command line.
Case (Device revision supported)
Board issue. Work with Altera Applications. Done.
Generate file from most recent version MAX+PLUS Quartus software.
device data sheet IDCODEs.
Work with local contact Altera Applications (800) 800-3753
continued page
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Technical Articles Sucessful In-System Programming Implementation, continued from page
Figure Error Flow Chart (continued)
Case (Device blank)
device been programmed before?
Expected behavior. Done. Examine device save Programmer Object File .pof). Contact Altera with device POF. Solder device board. Successful?
Previous device functional; work with Altera failure analysis. Done.
Does MAX+PLUS ByteBlasterMV produce identical result?
Contact Altera with file MAX+PLUS version. Done.
Does failure analysis reveal previous device them have excessive undershoot overshoot? Clean signals repeat steps. functional?
free running clocks other signals switching during execution?
Device issue; work with Altera solution. Done.
Board issue; work with Altera solution.
Altera
News
ACEX Devices Address Communications Market Need Low-Cost Programmable Logic
communications marketplace experiencing rapid dynamic growth. Increased pressures flexibility fast timeto-market brought about shortened design cycles continually evolving standards. Programmable logic achieving successful solution this rapidly changing marketplace. However, highvolume applications, need cost-efficiency historically restricted programmable logic devices (PLDs). replacement communications marketplace.
ACEX Applications
need high-volume, low-cost programmable solution communications marketplace skyrocketing price-sensitive applications abound explosive growth networking telecommunications sectors. xDSL cable modem growth rates tremendous expansion Internet traffic, Dataquest projections expect these modem growths reach high 141% compounded annual growth rate (CAGR). ACEX devices perfectly into these applications, replacing blocks such protocol transceiver modules, which currently implemented ASICs ASSPs. Remote access concentrators access routers provide another example enormous potential ACEX devices, demand high-speed
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Now, low-cost communications applications eagerly awaiting programmable advantage have attractively priced solution.
Altera eliminated this cost barrier with ACEXdevice family. Now, low-cost communications applications eagerly awaiting programmable advantage have attractively priced solution. Furthermore, ACEX devices meet requirements inherent communications systems without sacrificing performance. ACEX devices provide low-cost, high-performance solution, ideal ASIC application-specific standard product (ASSP)
Altera Corporation
Altera News communication channels satellite offices grows. Laser printers, peripherals, lowcost switches provide just more examples many applications communications marketplace that benefit from ACEX devices. ACEX device pricing competitive with ASICs, freeing designers from expensive timeconsuming ASIC implementation. Additionally, typical benefits PLDs over ASICs still apply, including fast time-to-market, flexibility design reprogrammability, advanced development tools, drop-in intellectual property (IP). ACEX devices also eliminate nonrecoverable engineering (NRE) costs, risk associated with ASIC re-spins, errors, design changes, time associated with ASIC conversion process. advanced versatile nature ACEX feature set, ACEX devices also eliminate specialized inflexible ASSP implementations design elements. integrate discrete phaselocked loops (PLLs), first-in first-out (FIFO) circuitry, RAM, peripheral component interconnect (PCI) other advanced interface standard interfaces within ACEX device. operating voltage while improving size over standard 0.22-µm processes. This size improvement provides two-fold advantage: creating inherent cost improvements large number available wafer, improving yield constant defect density. addition, patented Altera redundancy feature ensures that even dies with impurities repaired rendered fully functional, further improving yield numbers reducing costs. four ACEX devices range from 10,000 100,000 typical gates (56,000 257,000 maximum system gates) deliver high performance, with typical system speeds exceeding MHz. ACEX devices specifically designed support 64-bit/66-MHz compliance, ensuring compatibility with high-performance communications systems using what become facto standard open systems emerging standard embedded applications. ACEX devices feature embedded that simultaneously generate ClockLock ClockBoost modified clock signals manage on-chip clock domains, improve device utilization, improve board-level clock management whole. Embedded dual-port memory blocks provide significant enhancement well, ensuring fast effective RAM, ROM, dual-port RAM, FIFOs with tremendous ease implementation. EP1K30, EP1K50, EP1K100 devices shipping wide range advanced packages, including thin-quad flat pack (TQFP) FineLine BGApackaging. EP1K10 devices will ship third quarter 2000 with volume pricing beginning $3.50 device.
ACEX Device Families
ACEX device families broad-based, intended provide programmable solutions across platforms generations. ongoing line ACEX families will introduced, beginning with 2.5-V ACEX family that shipping, continuing with 1.8-V ACEX family released later this year. ACEX families will span variety processes operating voltages, smaller process geometries will increase performance while decreasing cost power consumption. Future ACEX families will continue make variety architectures will have range different feature sets.
ACEX Devices
ACEX devices will available second half 2000. These devices will based upon advanced 0.18-µm process will make Altera's process technology leadership ensure high production yields costs 1.8-V operating voltage. ACEX devices will range from 20,000 150,000 gates (75,000 400,000 maximum system gates) will incorporate additional advanced features such advanced standards enhancedcapability PLL.
ACEX Devices
ACEX family currently available represents optimal union price, performance, features this low-cost, 2.5-V device family. ACEX device's price advanced hybrid process, combining 0.22-µm transistors with 0.18-µm metal interconnect layers. This combination maintains desired 2.5-V
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Altera Corporation
Altera News
Altera's SignalTap Plus System Analyzer Provides Simultaneous On-Chip Off-Chip Debug Capabilities
ultimate success digital designs relies overall system operation. However, programmable logic devices (PLDs) become larger faster, their circuitry becomes more complex challenging debug. Altera's SignalTapPlus system analyzer addresses these challenges. Crossing boundary between board-level logic analysis, SignalTap Plus system analyzer presents complete picture signal activity, accelerates debug process. Figure shows interaction between SignalTap Plus analyzer system under test. SignalTap Plus system analyzer next generation debug tools, featuring enhanced on-chip debug capabilities with added 32-channel external logic analyzer true system-level signal acquisition. This system analyzer captures signals from internal nodes external, board-level nodes simultaneously, displaying data from both single, time-correlated display. display. SignalTap Plus system analyzer provides powerful logic analyzers-one embedded other connected board-level signals-that perform cause effect analysis system level, triggering analyzer based signal activity captured other. Access internal signals provided SignalTap embedded logic analyzer, introduced June 1999 included with Quartusdevelopment system. embedded logic analyzer captures signals from internal nodes while device running in-system at-speed. stores captured data internal embedded system blocks (ESBs), data then streamed off-chip same JTAG port used configure your PLD. Adding embedded logic analyzer design simple selecting nodes from list compiling. have modify your hardware description language (HDL) source code-the Quartus software automatically creates embedded logic analyzer when compile design based signals selected.
Internal External Logic Analyzers Combined
Until now, bench-top logic analyzers that cost thousands dollars could neither provide this seamless interface internal (PLD) external (board level) logic analysis present both sets data common, time-correlated
Figure SignalTap Plus Analyzer
System Under Test
Bench-Top Analysis
SignalTap Plus system analyzer provides channels external logic analysis that rivals
Quartus SignalTap Front Panel Software
Embedded Logic Analyzer
SignalTap Plus System Analyzer JTAG Port Computer Interface (Serial USB)
Sample Buffer (ESB)
Trigger
External Logic Analyzer
Sample Buffer Cross-trigger between internal external analyzers
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Altera News performance many bench-top logic analyzers fraction cost. 166-MHz synchronous asynchronous sample rate provides plenty speed capture fast signals. robust, four-level trigger sequencer with built-in event count, pattern duration, trigger timeout allows trigger analyzer based sequence events. 1-Mbyte sample channel acquisition buffer allows capture long traces-critical analysis communications signals. external logic analyzers. Trigger conditions, sample depth, sample rate settings provided each analyzer. view acquired data waveforms tabular lists that time-correlated based common clock common trigger point. four dedicated trigger patterns trigger logic analyzer locate highlight specific data. share data acquired SignalTap Plus system analyzer email analyze offline without acquisition hardware using SignalTap Front Panel software. SignalTap Front Panel software downloaded free from Altera site http://www.altera.com. SignalTap solution makes easy debug analyze your design. only does SignalTap Plus system analyzer have features SignalTap embedded logic analyzer, also lets view board-level signals. SignalTap Front Panel software manage both embedded external analyzers. This combination makes SignalTap Plus system analyzer powerful analysis tool that accelerates system debugging reduces your time market. share data acquired SignalTap Plus system analyzer email analyze off-line without acquisition hardware using SignalTap Front Panel software.
SignalTap Front Panel Software
SignalTap Front Panel software supports both embedded external logic analyzers. This software integrated into Quartus development system version 2000.05 provides complete development debug environment. only need debug facilities SignalTap Plus analyzer, laptop computer SignalTap Front Panel software stand-alone application with Windows 95/98 Windows operating system. SignalTap Front Panel software provides control data display both internal
Discontinued Devices Update
Altera distributes advisories (ADVs) product discontinuance notices (PDNs) that provide information discontinued devices. obtain copy specific PDN, contact your local Altera® sales representative. Selected ADVs, PDNs, complete listing discontinued devices also available Altera's site http://www.altera.com. Rochester Electronics, after-market supplier, offers many discontinued Altera products. Contact Rochester Electronics (978) 462-9332 their site http://www.rocelec.com.
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Altera News
Technologies' CoreX-V10: Increased Performance Produces Faster Megafunctions
Peripheral component interconnect (PCI) local specifications made their debut 1992 improve server performance increasing flow data between processor peripheral devices. Since then, bandwidth requirements peripheral devices have grown steadily. Fast technology such Gigabit Ethernet, Fiber Channel, Ultra-3 SCSI demand faster interconnect buses. PCI-X architecture designed fill this increasingly important position. PCI-X functions over 64-bit path incorporates many features, including registerto-register protocol, that enhance performance system achieve internal timing requirements with less effort compared conventional PCI. Technologies leader implementing PCI-X architecture first offer commercially-available PCI-X function, their CoreX-V10 product. Technologies develops functions programmable logic devices (PLDs), with many applications communications networks. APEX 20KE devices supports configuration, memory, transactions. This PCI-X function runs APEX 20KE device. Technologies rigorously tested CoreX-V10 function ensure that complies with PCI-X revision specifications Local Specification, Revision 2.2. Bundled with test environment that allows check functional correctness protocol violations, CoreX-V10 function backed with support from more than PCI-X trained engineers. leader core design, comes together with number utilities test environment with function. These items included with CoreX-V10 function: CoreX-V10 (netlist source applications) Self-checking PCI-X test bench comprised Automatic test-case generator (TCG) PCI-X monitor, arbiter functional models (BFMs) CoreX-V10 wizard setup, synthesis, verification, documentation On-site training support three days addition continuous phone email support
ALTERA MEGAFUNCTION PARTNERS PROGRAM
PCI-X Power Hits Commercial Market
CoreX-V10 function first PCI-X solutions 133-MHz, 64-bit PCI-X Initiator/Target function that provides speeds gigabyte second highspeed applications flexible interface between PCI-X application interface. CoreX-V10 supports 64-bit widths synchronous application interface. optimized Altera
implement this function current future designs, contact Technologies immediate service support. Technologies 39675 Cedar Blvd., #220 Newark, 94560 (510) 623-8826 http://www.dcmtech.com
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Altera News
CoreX V-10 Features
CoreX V-10 offers following features: flexible general purpose interface that customized specific peripheral requirements 32/64-bit, 133-MHz PCI-X function. Fully compliant with PCI-X revision specifications Local Specification, Revision Optimized APEX architecture. Compliant with 66-MHz APEX devices Supports full speed burst Gbyte second initiator target flexible general logic interface similar Altera's pci_c function Fully synchronous design
Figure CoreX-V10 Block Diagram
preqn pgntnn l_cbeni[7.0] lm_req32n lm_req64n pframen pirdyn ptrdyn lm_dxfrn pdevseln pstopn lm_tsr[9.0] l_ldat_ackn l_hdat_ackn MSTIN Master Control lm_rdyn lm_lastn lm_ackn lm_adr_ackn l_adi[63.0] l_dato[63.0] Local
RAMIF Data Buffers
l_cmdo[3.0] l_beno[7.0] l_adro[31.0]
Initiator Features
initiator offers following features: Initiates PCI-X commands including configuration read/write, memory read/ write block, memory write, split completion, read /write Initiates commands including configuration read/write, memory read/ write, read/write, memory write invalidate (MWI), memory read line (MRL) Initiates 64-bit cycles Initiates 64-bit addressing, using dual address cycle (DAC) parking Address stepping configuration cycles PCI-X mode Generates checks parity
preq64n pack64n TGTIN Target Control
lt_rdyn lt_discn lt_abortn lt_ackn lt_dxfrn lt_framen lt_tsr[11.0] User Back-End Application
pad[63.0] pcben[7.0]
OFLIP Data Control
AD-OE Output Enable
ppar64 ppar PARIF Parity Calculation Reporting
pserrn pperrn
cache[7.0] pidsel CSPAC Configuration Space stat_req[5.0] cmd_req[5.0]
prstn pclk BARHT Address Decoder
Target Features
Target Control offers following features: Type zero configuration space Decode PCI-X slow mode Support capabilities list pointer Parity error detection base address registers (BARs) with adjustable memory size type (64-bit memory 32-bit BAR) User logic interface request retry, disconnect abort Responds 64-bit transactions. 64-bit addressing capability Becomes initiator (master) complete split cycles follows initiator rules
2000
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Altera Corporation
Altera News
True-LVDS Solution Provides 840-Mbps Data Transfer Rates
Bandwidth performance requirements next-generation communication designs always increasing. address these needs, designers either Altera® TrueLVDSsolution found APEX20KE devices emulated low-voltage differential signaling (LVDS) solution found other programmable devices. LVDS standard becoming increasingly accepted communication applications because high noise immunity, high performance, power consumption characteristics. This article compares APEX 20KE True-LVDS dedicated circuitry LVDS standard found other programmable logic devices (PLDs). APEX 20KE devices provide most robust LVDS solution programmable marketplace, shown through superior APEX 20KE LVDS support: megabits channel bandwidth Dedicated LVDS circuitry Push-button Quartussoftware compilation support Carefully planned on-chip LVDS placement Integrated deskew capability Considerably lower power consumption Simpler board level design requirements timing constraints generates appropriate differential signals. also performs critical serial-to-parallel parallel-to-serial conversions required convert high-speed LVDS signals rates that easily accommodated device. Other PLDs have this dedicated LVDS receiver LVDS transmitter circuitry must emulate through logic RAM, which quickly consumes valuable resources needed user's design considerably reduces remaining memory capacity. Furthermore, difficult achieve high data throughput without dedicated circuitry. phase-locked loops (PLLs) APEX 20KE devices provide versatile LVDS support. Designers implement LVDS standard APEX 20KE devices data transfer modes. APEX devices support multiple 840-megabits second (Mbps) LVDS channels without difficulty, shown Figure
Figure APEX 20KE LVDS Interface
Mbit 1-Bit Data Serial-to-Parallel Converter 8-Bit Data
Logic Mbit 1-Bit Data Parallel-to-Serial Converter 8-Bit Data
LVDS Comparison
True-LVDS solution found APEX 20KE devices unique marketplace that provides dedicated LVDS circuitry. This circuitry greatly facilitates LVDS implementation ensures that complex device-level timing issues handled with minimal design work. example, APEX 20KE dedicated LVDS receiver LVDS transmitter circuitry, designed support multiple channels. This circuitry ensures compliance with LVDS high-speed LVDS interface critical complex communications applications such dense wave division multiplexing (DWDM) systems. Current DWDM systems require optical components ensure high-quality transmission Mbps channel. Altera offers solution reduce cost ownership utilizing Altera Reed-Solomon forward error correction (FEC) intellectual property (IP) function correct errors that introduced lower-cost optical components. This function adds data SONET OC-12 data,
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Altera News which increases LVDS bandwidth requirement Mbps channel. APEX 20KE True-LVDS solution easily supports this additional bandwidth requirement. Altera's True-LVDS solution provides optimum price highest performance communications application such terabit routers, switch fabrics, enterprise storage network equipment. APEX 20KE devices contain dedicated circuitry implement deskew feature, which ensures accurate data capture compensates board-level skew. This added circuitry creates robust LVDS solution. absence dedicated deskew circuitry other PLDs requires designers external trace adjustments printed circuit board (PCB) align clock data channels, process that both challenging cumbersome.
Board-Level Issues
APEX 20KE devices true differential output drivers LVDS channels. built-in circuitry provides low-power, electromagnetic interference (EMI), highnoise immunity benefits. absence these dedicated output drivers other PLDs leads high power consumption creates noise rather than reducing them. Further difficulties seen board-level design placement. pins corresponding each LVDS channel physically adjacent pairs placed near outer edge APEX device package, shown Figure page This placement minimizes board-level skew commonly associated with unequal trace lengths between channel signals simplifies trace layout. Often, other PLDs take these factors into account, placing pins associated with given channel apart. This distance cause significant differential impedance board-level skew, forcing board designer manually compensate unequal trace lengths. Poor placement also decreases common mode rejection ratio (CMRR), degrading LVDS interface performance. This discontinuity occurs because LVDS sensitive unbalanced noise pins. lack closely-matched signal traces results poor noise immunity. APEX 20KE TrueLVDS solution easy implement true push-button support within Quartus development tool.
True-LVDS Implementation
APEX 20KE True-LVDS solution easy implement true push-button support within Quartus development tool. Quartus software features megafunctions, altlvds_rx altlvds_tx, that directly implement LVDS receiver LVDS transmitter, respectively. Incorporating these megafunctions within design allows pushbutton compilation LVDS interface implementation multiple channels with frequencies Mbps. Dedicated APEX 20KE LVDS circuitry ensures that timing requirements data transfer properly met. Other PLDs require considerable time effort meet necessary timing requirements. Emulating LVDS circuit tremendously difficult task, designers have handroute LVDS receiver transmitter circuitry within other field-programmable gate arrays (FPGAs). Furthermore, receivers transmitters typically very sensitive propagation delays associated with derived clock data channels. result, must ensure that these delays matched process, voltage, temperature (PVT) variations.
Summary
APEX 20KE devices offer comprehensive solution True-LVDS standard that been proven fast, effective simple implement. Though other devices claim have LVDS solution, very complex difficult implement. True-LVDS solution APEX 20KE devices simpler more efficient advantages such higher performance, dedicated LVDS circuitry, lower power consumption.
continued page
2000 News Views Altera Corporation
Altera News True-LVDS Solution Provides 840-Mbps Data Transfer Rates, continued from page
Figure LVDS Placement APEX 20KE Devices
LVDSTXINCLK LVDSTXOUTCLK
LVDS input pairs placed outer rows balls minimize skew.
LVDS Transmitter Data Channels
LVDSRXINCLK
Altera's Turbo Encoder Decoder Push Technology Envelope High-Speed Wireless Applications
Altera adding portfolio Forward Error Correction MegaCore® functions wide third-generation (3G) wireless applications. addition Reed-Solomon Viterbi cores, latest addition this family Turbo Encoder (ordering code: PLSM-TURBO/ENC) Turbo Decoder (ordering code: PLSMTURBO/DEC) megafunctions. Turbo MegaCore function targeted towards wireless applications, satellite communications, digital video broadcast, sub-marine data transfer applications, where high speed high data integrity paramount. Optimized APEXfamily devices, Altera's Turbo MegaCore function, like Reed-Solomon core, comes with separate encoder decoder cores, shown Figure also compliant with ThirdGeneration Partnership Project (3GPP) error correction high-speed data services megabits second (Mbps). Because dynamic state 3GPP, current 3GPP compliant application-specific standard products (ASSPs) ASICs exist. Digital signal processors, hovering around Kbits second (Kbps), cannot achieve high throughput possible Altera's programmable logic devices (PLDs). Turbo Encoder function stream-driven uses block-based coding scheme. interleaved convolutional encoders generate
Optimized APEX family devices, Altera's Turbo MegaCore function, like Reed-Solomon core, comes with separate encoder decoder cores.
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Altera News parity output streams. These streams then punctured save bandwidth. 3GPP code rates approximately puncturing used with puncturing. After depuncturing received data stream, information parity bits into decoder equalizer (not shown Figure delivers probabilities received values decoder Decoder then received value confidence level that value. Decoder evaluates these results combines them with probabilities (parity bits), which into decoder with information bits parity bits. After predefined number iterations, decoding process completed output available. purpose interleaving combat burst errors. Convolutional codes excellent defense against random errors. However, since errors typically come bursts, interleavers disperse corrupt data, making easier correct. turbo decoder interleaver, defined 3GPP, rigorous algebraic interleaver based sets prime numbers. this function labor-intensive implement, essential component Altera's Turbo Decoder. Altera's turbo decoder takes advantage logarithmic maximal a-posteriori (maxlogMAP) algorithm (see Figure This computationally intensive algorithm, which utilizes banks memory-Alpha memory Parity memory. Altera's Turbo MegaCore function gives user total flexibility with memory configuration MegaWizard® Plug-In Manager (see Table
Table Turbo Decoder Memory Configuration Examples Soft Bits
Figure Turbo CODEC Block Diagram
Medium which noise introduced.
max-logMAP Decoder Interleaver De-Puncture Encoder Encoder Interleaver De-Interleaver
Puncture
max-logMAP Decoder
Turbo Encoder
Turbo Decoder
Figure Turbo Decoder Block Diagram
Alpha Memory
Parity Memory
max-logMAP Decoder
Control Processor
3GPP Interleaver
Information Memory
Apiori Memory
Turbo Decoder Core
max-logMAP decoder requires clock cycles information bit. Since there decoders, each iteration requires four clock cycles bit. Five iterations require clock cycles bit, plus about five cycles loading unloading data. decoder approximately speed grade APEX 20KE device, producing data transfer rate Mbps. Altera's Turbo CODEC includes OpenCorefeature both Encoder Decoder functions MegaWizard Plug-In easy customization. VHDL Verilog simulation models, model bit-error rate (BER) simulation, VHDL source code Reference Design also included verification purposes. absence ASSP ASIC solutions, Altera's Turbo CODEC MegaCore function addresses necessary requirements emerging wireless applications.
Alpha Memory
On-chip Off-chip Off-chip Off-chip On-chip Off-chip Off-chip
Parity Memory
On-chip On-chip Off-chip On-chip On-chip Off-chip On-chip
Number ESBs
Suitable Device
EP20K300E EP20K200 EP20K200 EP20K300E EP20K600E EP20K200 EP20K400
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Altera Corporation
Questions
Answers
program configure Altera® device Windows 2000 platform? addition operating systems listed readme.txt file, Quartussoftware version 2000.03 MAX+PLUS® software version support device programming configuration Windows 2000 operating system. There file installing Programmer hardware Windows 2000 platform. This file exists <system>\drivers\win2000 directory Quartus software version 2000.03 MAX+PLUS software version 9.6. installation procedure follows: Open Control Panel (Start menu Settings Control Panel). Double-click Add/Remove Hardware icon start Add/Remove Hardware Wizard click Next continue. Choose Hardware Task panel, select Add/Troubleshoot device click Next continue. Windows 2000 will search Plug Play hardware (New Hardware Detection window). Choose Hardware Device window, select device click Next continue. Find Hardware window, select want select hardware from list click Next continue. Hardware Type window, select Sound, video game controllers click Next continue. Select Device Driver window, select Have Disk. Specify full directory path win2000.inf file (e.g., <max+plus directory>\drivers\win2000) click Digital Signature Found warning dialog box, click continue installation. Select Device Driver window, select hardware install click Next continue. Start Hardware Installation window displays hardware being installed. Click Next continue. Digital Signature Found warning dialog box, click continue installation. Completing Add/Remove Hardware Wizard window, click Finish continue. system dialog appears which prompts reboot that settings take effect.
multiple functions single device. only limiting factor size megafunction resources available particular device.
multiple peripheral component interconnect (PCI) functions single Altera device? Yes. multiple functions single device. only limiting factor size megafunction resources available particular device. example PCI/MT64 function consumes approximately 1,500 logic elements (LEs) FLEX® device. Therefore, PCI/MT64 functions EPF10K100E (4,992 LEs) larger device. second factor timing issues while fitting multiple functions single device. Assignment Configuration File (.acf) provided Altera megafunctions designed single megafunction only. want multiple functions single device, then have modify ACFs meet timing requirements related PCI.
What behavior phase-locked loop (PLL) output input clock disabled while user mode? remove input clock, output drifts voltage-controlled oscillator's (VCO's) lower frequency limit (nominally MHz) divided depending whether using clock0 clock1 output. value output dividers outputs clock0 clock1. Additionally, lock goes low. Once clock input starts again, re-locks signal.
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Questions Answers VCO's lower frequency limit extend below depending process, voltage, temperature. simulation, output will show because simulator cannot model frequency drift. lock indication this time, should monitor this indication valid clock. Once input clock starts again, clock output will show simulation. simulator assumes delta delay lock indication. APEX 20K, APEX 20KE, 7000S, 7000A, 7000AE, 7000B devices, both falling rising edges affected this feature.
Error: "Bounds non-constant index addressing array reach beyond bounds array." This error message occurs variable without range constraint specify array index. avoid this error, specify range constraint variable declaration. example, following code produces this error message MAX+PLUS software: architecture test signal my_array std_logic_vector(7 downto signal bitpos std_logic_vector(2 downto begin begin process (my_array) variable integer; begin conv_integer(bitpos); my_array(i) `1'then error message will occur code changed follows: architecture test signal my_array std_logic_vector(7 downto signal bitpos std_logic_vector(2 downto begin process (my_array) variable integer range begin conv_integer(bitpos); my_array(i) `1'then
Error: "The project more than chip. Multi chip designs supported this version." this error message project's Compiler Settings File (.csf) more than chip section. example, following code your produce error: CHIP(Block1) DEVICE AUTO; CHIP(Block2) DEVICE AUTO; compiler interprets this multiple-device design. order problem, remove additional CHIP section reload project.
Altera's APEX20K, APEX 20KE, ACEX1K, FLEX 10K, FLEX 10KA, FLEX 10KE, FLEX 6000, MAX® 7000E, 7000S, 7000A, 7000AE, 3000A devices have slew rate option that allows users select slow-slew rate each pin. ACEX FLEX 10K, FLEX 10KA, FLEX 10KE, FLEX 6000, 7000E devices, this option slows slew rate falling edges. rising edge affected this feature.
What type slow-slew rate control Altera's devices have output signals?
continued page
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Questions Answers Questions Answers, continued from page Instead, device data sheets parameter fcnt represent fMAX reported MAX+PLUS software, where data sheet shows fastest possible fcnt given speed grade. this case fcnt parameter shows clock frequency fastest register-to-register path (i.e., register logic array block (LAB) driving second register within same LAB). device data sheets historical, discrete transistor-to-transistor (TTL) definition fMAX. However, EPLDs have evolved, fcnt become more useful description device performance from registered path point view. result, data sheet also provides this information form fcnt parameter.
does MAX+PLUS software report slower fMAX value than what shown data sheet device? fMAX reported MAX+PLUS software provides fastest clock frequency slowest registered path (i.e., longest registered path delay) entire design. fMAX parameter device data sheet represents fastest frequency global clock when data path represented single register that both input feeds output pin. This same calculation fMAX reported MAX+PLUS software.
Altera Publications
have been data standard speeds, higher low-volta clock used formance increasin standard High-per pace with These keep devices. introduc backplan low-volta microprocessors, rates, these with memory, want highto interface Designer nary need flexible, devices. revolutio mable logic peripher buffers. Altera'shighest with program standard ndard nce, multi-sta offer highest density,the necessary performa with 20KE devices solution industrie APEX mable logic compute program ication performa commun term leader standard product-only macrocell® 7000B devices (GTL+), devices Altera logic plus 7000B transceiv SSTL-3. support: Gunning standard 3.3-V support (SSTL-2) based devices logic terminat stub series supporte standard mable single device program With 7000B devices, standards, well buses multiple APEX 20KE eously support low-voltage memory different simultan low-volta with high-spe include 622.08 million interface standard data rates These simplify supports backplan standard (LVDS), which mable into signaling (Mbps). Program like LVDS integrate reducing space, circuitry bits second Dedicate saving board board design. logic devices (PLDs), nce. mable performa program improvin with usage, designin following guideline covers note provides devices This applicati standards Altera selectabl topics: ions Applicat Standard Standard Overview 7000B APEX 20KE Conditio Operatin Using LVDS Schemes Board Terminat
Introduction
publications available from Altera Literature Services. Individual documents available Altera site http://www.altera.com. Document part numbers shown parentheses. Altera Digital Library CD-ROM, 2000 (P-CD-ADL2000-03) Component Selector Guide (M-SG-COMP-08) Development Tools Selector Guide (M-SG-TOOLS-16) Intellectual Property Selector Guide (M-SG-MEGAFCTN-03) ACEX Programmable Logic Device Family Data Sheet (A-DS-ACEX-01.01) Excalibur Development with Nios Embedded Processor Data Sheet (A-DS-ACEX-01.01) Nios Soft Core Embedded Processor Data Sheet (A-DS-EXCNIOS-01) SignalTap Plus System Analyzer Data Sheet (A-DS-SIGTPPLUS-01) 115: Using ClockLock ClockBoost Features APEX Devices (A-AN-115-02)
122: Using STAPL Embedded Processor (A-AN-122-01) 125: Evaluating AMPP MegaCore Functions (A-AN-125-01) System-on-a-Programmable Chip (SOPC) Development Board (A-SB-047-01) Features Quartus Software Version 2000.02 (M-TB-64-01) Design Fitting: 7000AE ispLSI 2000VE Devices (M-TB-065-01) Advanced Synthesis with LeonardoSpectrum (M-TB-067-01) Advanced Synthesis with FPGA Express (M-TB-068-01) Simulation with ModelSimAltera Software (M-TB-069-01) 5.0-V Tolerance APEX 20KE Devices White Paper (A-WP-APEX5V-01.01) Using APEX 20KE with Quartus Software Design Tool White Paper (M-WP-CAM-01) Using LVDS Quartus Software White Paper (A-WP-LVDSQUARTUS-01) Serial Viterbi Decoders White Paper (M-WP-HCORES-VSERAB-01)
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Altera Programming Support
Table Altera Programming Adapters (Part Note Device
EPM7064S
Programming Hardware Support
Table contains latest programming hardware information Altera® MAX® 9000, 7000, 3000, configuration devices. correct programming, software version shown "Current Software Versions" page
Table Altera Programming Adapters (Part Note Device
EPC1064 EPC1064V EPC1441 EPC1 EPC1213 EPC2 J-lead TQFP EPM9320 J-lead (84-pin) RQFP (208-pin) (280-pin) EPM9320A J-lead (84-pin) RQFP (208-pin) EPM9400 J-lead (84-pin) RQFP (208-pin) RQFP (240-pin) EPM9480 RQFP (208-pin) RQFP (240-pin) EPM9560 RQFP (208-pin) RQFP (240-pin) (280-pin) RQFP (304-pin) EPM9560A RQFP (208-pin) RQFP (240-pin) EPM7032 J-lead (44-pin) PQFP (44-pin) TQFP (44-pin) EPM7032S EPM7032AE EPM7032B EPM7064 J-lead (44-pin) TQFP (44-pin) J-lead (68-pin) J-lead (84-pin) PQFP (100-pin) PLMJ7000-44 PLMT7000-44 PLMJ7000-68 PLMJ7000-84 PLMQ7000-100 J-lead (44-pin) TQFP (44-pin) PLMJ1213 PLMT1064 PLMJ9320-84 PLMR9000-208 PLMG9000-280 PLMJ9320-84 PLMR9000-208NC PLMJ9400-84 PLMR9000-208 PLMR9000-240 PLMR9000-208 PLMR9000-240 PLMR9000-208 PLMR9000-240 PLMG9000-280 PLMR9000-304 PLMR9000-208NC PLMR9000-240NC DIP, J-lead PLMJ1213
Package
J-lead (44-pin) J-lead (84-pin) TQFP (44-pin) TQFP (100-pin)
Adapter
PLMJ7000-44 PLMJ7000-84 PLMT7000-44 PLMT7000-100NC PLMJ7000-44 PLMT7000-44 PLMT7000-100NC PLMF7000-100
EPM7064AE EPM7064B
J-lead (44-pin) TQFP (44-pin) TQFP (100-pin) FineLine (100-pin)
Package
DIP, J-lead TQFP
Adapter
PLMJ1213 PLMT1064 EPM7096
J-lead (68-pin) J-lead (84-pin) PQFP (100-pin)
PLMJ7000-68 PLMJ7000-84 PLMQ7000-100 PLMJ7000-84 PLMQ7000-100 PLMQ7128/7160-160 PLMJ7000-84 PLMQ7000-100NC PLMT7000-100NC PLMT7000-144NC PLMQ7128/7160160NC PLMF7000-100 PLMF7000-256
EPM7128E
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
EPM7128A EPM7128AE EPM7128B EPM7128S
J-lead (84-pin) PQFP (100-pin) TQFP (100-pin) TQFP (144-pin) PQFP (160-pin) FineLine (100-pin) FineLine (256-pin)
EPM7160E
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
PLMJ7000-84 PLMQ7000-100 PLMQ7128/7160-160 PLMJ7000-84 PLMQ7000-100NC PLMQ7128/7160160NC
EPM7160S
J-lead (84-pin) PQFP (100-pin) PQFP (160-pin)
EPM7192E
(160-pin) PQFP (160-pin)
PLMG7192-160 PLMQ7192/7256-160 PLMQ7192/7256160NC
PLMJ7000-44 PLMQ7000-44 PLMT7000-44 PLMJ7000-44 PLMT7000-44
EPM7192S
PQFP (160-pin)
continued page
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Every Issue Altera Programming Support, continued from page
Table Altera Programming Adapters (Part Note Device
EPM7256E
Third-Party Programming Support
Data I/O, Microsystems, System General provide programming hardware support selected Altera devices. Algorithms available these companies' respective sites (http://www.data-io.com, http://www.bpmicro.com, http://www.sg.com.tw). Programming support information configuration, 9000, 7000 devices shown Table information subject change.
Table Third-Party Programming Hardware Support Device Data
Package
PQFP (160-pin) (192-pin) PQFP (208-pin) RQFP (208-pin)
Adapter
PLMQ7192/7256-160 PLMG7256-192 PLMR7256-208 PLMR7256-208 PLMT7000-100NC PLMT7000-144NC PLMR7256-208NC PLMT7256-208NC PLMF7000-100 PLMF7000-256
EPM7256A EPM7256S EPM7256AE EPM7256B
TQFP (100-pin) TQFP (144-pin) PQFP (208-pin) RQFP (208-pin) FineLine (100-pin) FineLine (256-pin)
Microsystems
System General
EPM7512AE EPM7512B
TQFP (144-pin) PQFP (208-pin) (256-pin) FineLine (256-pin)
PLMT7000-144NC PLMR7256-208NC PLMB7000-256 PLMF7000-256
EPC1064 EPC1213 EPC1 EPC1441 EPC2
EPM3032A
J-lead (44-pin) TQFP (44-pin)
PLMJ3000-44 PLMT3000-44 PLMJ3000-44 PLMT3000-44 PLMT3000-100NC PLMT3000-100NC PLMT3000-144NC PLMT3000-144NC PLMR3256-208NC
EPM3032A EPM3064A
EPM3064A
J-lead (44-pin) TQFP (44-pin) TQFP (100-pin)
EPM3128A EPM3256A
EPM3128A
TQFP (100-pin) TQFP (144-pin)
EPM7032 EPM7032AE EPM7032S EPM7064 EPM7064AE EPM7064S EPM7096 EPM7128A EPM7128S EPM7128AE EPM7128E EPM7160E EPM7192S EPM7192E EPM7256A EPM7256AE EPM7256S EPM7256E EPM7512AE EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A
(4), (4),
EPM3256A
TQFP (144-pin) PQFP (208-pin)
Notes: Refer Altera Programming Hardware Data Sheet device adapter information Classicdevices. FLEX® 8000 configuration device. FLEX 10K, FLEX 8000, FLEX 6000 configuration device. APEX20K, FLEX 10K, FLEX 6000 configuration device. These devices shipped carriers.
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Notes Table These devices supported Data UniSite programmer version 6.3. These devices supported Microsystems programmers version 3.49A. These devices supported System General programmers version 1.0. Although these devices currently supported, Altera process verifiying programming hardware support. Contact Data I/O, Microsystems, System General about programming support these devices. Contact Data I/O, Microsystems, System General about programming support 256-pin ball-grid array (BGA) FineLine BGApackages.
Table Download Cable Compatibility Device
APEX APEX 20KE ACEX FLEX FLEX 10KA FLEX 10KE FLEX 8000 FLEX 6000 9000 9000A 7000S
MasterBlaster
ByteBlasterMV
BitBlaster
Download Cables
Table provides programming configuration compatibility information MasterBlasterserial universal serial (USB) communications cable BitBlasterserial ByteBlasterMVparallel port download cables. (The ByteBlasterdownload cable been replaced with ByteBlasterMV cable.)
7000A 7000B 3000A
Notes: MasterBlaster communications cable used with Quartus software device download SignalTap logic analysis. also used with MAX+PLUS software version device downloads. BitBlaster download cable must operate ByteBlasterMV download cable must operate these devices. VCCIO pins either
Contact Altera
Getting information services from Altera easier than ever. table below lists some ways reach Altera.
Information Type
Literature
Access
News Views Subscriptions
U.S. Canada
Other Locations
lit_req@altera.com
General Literature Request lit_req@altera.com
n_v@altera.com News Views Address Changes Non-Technical Customer Service Technical Support Telephone Hotline Telephone Hotline (800) SOS-EPLD (408) 544-6403 (800) 800-EPLD a.m. p.m. Pacific Time) (408) 544-7000 (7:30 a.m. 5:30 p.m. Pacific Time) Electronic Mail Site General Product Information Telephone World-Wide (408) 544-6401 support@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com https://websupport.altera.com n_v@altera.com
n_v@altera.com n_v@altera.com
(408) 544-7000 (408) 544-6403 (408) 544-7000 (7:30 a.m. 5:30 p.m. Pacific Time)
(408) 544-6401 support@altera.com ftp.altera.com (408) 544-7104 http://www.altera.com https://websupport.altera.com
Notes: MAX+PLUS Getting Started Quartus Tutorial manuals available from Altera® site. obtain other Quartusand MAX+PLUS® software manuals, contact your local distributor. also contact your local Altera sales office sales representative. Altera site listing.
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Altera Device Selection Guide
Current information Altera® APEX20K, ACEX1K, FLEX® 10K, FLEX 8000, FLEX 6000, MAX® 9000, 7000, 3000, configuration devices listed here. Information other Altera products located Altera
APEX Devices
DEVICE
EP20K30E EP20K60E
Component Selector Guide. most up-todate information, Altera site http://www.altera.com. Some devices listed available. Contact Altera your local sales office latest device availability.
GATES
30,000 60,000
PIN/PACKAGE OPTIONS
144-Pin TQFP, 144-Pin BGA2, 208-Pin PQFP, 324-Pin BGA2 144-Pin TQFP, 144-Pin BGA2, 208-Pin PQFP, 240-Pin PQFP, 324-Pin BGA2, 356-Pin
PINS
108, 128, 108, 151, 183, 204, 101, 159, 189, 252, 108, 151, 183, 246, 143, 175, 273, 144, 174, 279, 136, 168, 273, 376, 376, 152, 408, 502, 502, 488, 488, 508, 488, 508, 488,
SUPPLY VOLTAGE
LOGIC ELEMENTS
1,200 2,560
BITS
24,576 32,768
MACROCELLS
EP20K100
100,000
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 324-Pin BGA2, 356-Pin
4,160
53,248
EP20K100E
100,000
144-Pin TQFP, 144-Pin BGA2, 208-Pin PQFP, 240-Pin PQFP, 324-Pin BGA2, 356-Pin
4,160
53,248
EP20K160E
160,000
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA2
6,400
81,920
EP20K200 EP20K200E
200,000 200,000
208-Pin RQFP, 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA2 208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 484-Pin 652-Pin BGA, 672-Pin BGA2 BGA2,
8,320 8,320
106,496 106,496
EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E
300,000 400,000 400,000 600,000 1,000,000 1,500,000
240-Pin RQFP, 652-Pin BGA, 672-Pin BGA2 652-Pin BGA, 655-Pin PGA, 672-Pin BGA2 652-Pin BGA, 672-Pin BGA2
11,520 16,640 16,640 24,320 38,400 51,840
147,456 212,992 212,992 311,296 327,680 442,368
1,152 1,664 1,664 2,432 2,560 3,456
652-Pin BGA, 672-Pin BGA2, 1,020-Pin BGA2 652-Pin BGA, 672-Pin BGA2, 1,020-Pin BGA2 652-Pin BGA, 1,020-Pin BGA2
ACEX Devices
DEVICE
EP1K10 EP1K30 EP1K50 EP1K100
GATES
10,000 30,000 50,000 100,000
PIN/PACKAGE OPTIONS
100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2, 484-Pin BGA2 208-Pin PQFP, 256-Pin BGA2, BGA2
PINS
102, 130, 102, 147, 102, 147, 186, 147, 186,
SUPPLY VOLTAGE
LOGIC ELEMENTS
1,728 2,880 4,992
BITS
12,288 24,576 40,960 49,152
Altera Corporation
News Views
2000
Every Issue
FLEX Devices
DEVICE
EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K30E EPF10K40 EPF10K50 EPF10K50V EPF10K50E EPF10K50S
GATES
10,000 10,000 20,000 30,000 30,000 30,000 40,000 50,000 50,000 50,000 50,000
PIN/PACKAGE OPTIONS
84-Pin PLCC, 144-Pin TQFP, 208-Pin PQFP 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2 144-Pin TQFP, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2, 356-Pin BGA, 484-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2, 484-Pin BGA2 208-Pin RQFP, 240-Pin RQFP 240-Pin RQFP, 356-Pin BGA, 403-Pin 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2, 484-Pin BGA2 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2, 356-Pin BGA, 484-Pin BGA2
PINS
102, 102, 134, 102, 147, 147, 189, 102, 147, 189, 191, 246, 102, 147, 176, 147, 189, 274, 189, 274, 102, 147, 189, 191, 102, 147, 189, 191, 220, 189, 189, 274, 369, 147, 189, 147, 189, 191, 274, 470, 186, 274, 369, 424, 470, 470, 182, 274, 369, 470, 470,
SUPPLY VOLTAGE
SPEED GRADE
LOGIC ELEMENTS
1,152 1,728 1,728 1,728 2,304 2,880 2,880 2,880 2,880
BITS
6,144 6,144 12,288 12,288 12,288 24,576 16,384 20,480 20,480 40,960 40,960
EPF10K70 EPF10K100 EPF10K100A EPF10K100B EPF10K100E
70,000 100,000 100,000 100,000 100,000
240-Pin RQFP, 503-Pin 503-Pin 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA2, 600-Pin 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA2, 356-Pin BGA, 484-Pin BGA2
3,744 4,992 4,992 4,992 4,992
18,432 24,576 24,576 24,576 49,152
EPF10K130V EPF10K130E
130,000 130,000
599-Pin PGA, 600-Pin 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA2, 600-Pin 672-Pin BGA2 599-Pin PGA, 600-Pin BGA, 672-Pin BGA2 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA2, 600-Pin BGA, 672-Pin BGA2
6,656 6,656
32,768 65,536
EPF10K200E EPF10K200S
200,000 200,000
9,984 9,984
98,304 98,304
EPF10K250A
250,000
599-Pin PGA, 600-Pin
12,160
40,960
FLEX 6000 Devices
DEVICE
EPF6010A EPF6016 EPF6016A
GATES
10,000 16,000 16,000
PIN/PACKAGE OPTIONS
100-Pin TQFP, 144-Pin TQFP 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin 100-Pin TQFP, 100-Pin BGA2, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2
PINS
117, 171, 199, 117, 171, 117, 171, 199, 218,
SUPPLY VOLTAGE
SPEED GRADE
FLIPFLOPS
1,320 1,320
LOGIC ELEMENTS
1,320 1,320
EPF6024A
24,000
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin BGA, 256-Pin BGA2
1,960
1,960
Configuration Devices APEX FLEX Devices
DEVICE
EPC1064 EPC1064V EPC1213 EPC14413 EPC13 EPC23
PIN/PACKAGE OPTIONS
8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC 8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP 8-Pin PDIP, 20-Pin PLCC 20-Pin PLCC, 32-Pin TQFP
SUPPLY VOLTAGE
3.3/5.0 3.3/5.0 3.3/5.0
DESCRIPTION
64-Kbit serial configuration device designed configure FLEX 8000 devices 64-Kbit serial configuration device designed configure FLEX 8000 devices 213-Kbit serial configuration device designed configure FLEX 8000 devices 441-Kbit serial configuration device designed configure FLEX devices 1-Mbit serial configuration device designed configure APEX FLEX devices 2-Mbit serial configuration device designed configure APEX, FLEX 10K, FLEX 10KE, FLEX 6000 devices
EPC4E4
44-Pin TQFP, 84-Pin
BGA5
2.5/3.3
4-Mbit serial/parallel configuration device designed configure APEX FLEX devices.
continued page
2000 News Views Altera Corporation
Every Issue Altera Device Selection Guide, continued from page
7000 Devices
DEVICE
EPM7032S EPM7032AE EPM7032B EPM7064S EPM7064AE EPM7064B
MACROCELLS
44-Pin PLCC/TQFP 44-Pin PLCC/TQFP
PIN/PACKAGE OPTIONS
PINS
SUPPLY VOLTAGE
SPEED GRADE
44-Pin PLCC/TQFP, 48-Pin TQFP 44-Pin PLCC/TQFP, 84-Pin PLCC, 100-Pin TQFP 44-Pin PLCC/TQFP, 49-Pin BGA5, 100-Pin TQFP, 100-Pin BGA2 44-Pin PLCC/TQFP, 48-pin TQFP, 49-Pin BGA1, 100-Pin TQFP, 100-Pin BGA2
100, 100, 100, 100, 100, 120, 164, 120, 164, 120, 140, 164, 164, 120, 176, 212, 120, 140, 212, 212,
EPM7128S EPM7128A EPM7128AE
84-Pin PLCC, 100-Pin PQFP/TQFP, 160-Pin PQFP 84-Pin PLCC, 100-Pin TQFP, 100-Pin BGA2, 144-Pin TQFP, 256-Pin BGA2 84-Pin PLCC, 100-Pin TQFP, 100-Pin BGA2, 144-Pin TQFP, 169-Pin BGA5, 256-Pin BGA2 49-Pin BGA5, 100-Pin TQFP, 100-Pin BGA2, 144-Pin TQFP, 169-Pin BGA5, 256-Pin BGA2
-10, -10, -5,-7,-10
EPM7128B
EPM7160S EPM7192S EPM7256S EPM7256A EPM7256AE EPM7256B
84-Pin PLCC, 100-Pin TQFP, 160-Pin PQFP 160-Pin PQFP 208-Pin PQFP 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2 100-Pin TQFP, 100-Pin BGA2, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2 100-Pin TQFP, 144-Pin TQFP, 169-Pin BGA5, 208-Pin PQFP, 256-Pin BGA2, 256-Pin
-10, -10, -10, -10,
EPM7512AE EPM7512B
144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA2, 256-Pin 100-Pin TQFP, 144-Pin TQFP, 169-Pin BGA5, 208-Pin PQFP, 256-Pin BGA2, 256-Pin
-10,
3000 Devices
DEVICE
EPM3032A EPM3064A EPM3128A EPM3256A
MACROCELLS
PIN/PACKAGE OPTIONS
44-Pin PLCC, 44-Pin TQFP 44-Pin PLCC, 44-Pin TQFP, 100-Pin TQFP 100-Pin TQFP, 144-Pin PQFP 144-Pin TQFP, 208-Pin PQFP
PINS
116,
SUPPLY VOLTAGE
SPEED GRADE
9000 Devices
DEVICE
EPM9320A EPM9320 EPM9400 EPM9480 EPM9560A EPM9560
MACROCELLS
PIN/PACKAGE OPTIONS
84-Pin PLCC, 208-Pin RQFP, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 280-Pin PGA, 356-Pin 84-Pin PLCC, 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP 208-Pin RQFP, 240-Pin RQFP, 356-Pin 208-Pin RQFP, 240-Pin RQFP, 280-Pin PGA, 304-Pin RQFP, 356-Pin
PINS
132, 132, 139, 146, 153, 191, 153, 191,
SUPPLY VOLTAGE
SPEED GRADE
-15, -15, -15, -15,
Notes Tables: Preliminary. Contact Altera latest information. This package space-saving FineLine package. This device programmed user operate either This device programmed user operate either This package space-saving Ultra FineLine package, Altera's 0.8-mm pitch package.
Altera Corporation
News Views
2000
Anything they
better.
ASICs Custom chips with high costs. Chips that have large minimum order quantities. Chips that require months develop cannot changed: ASICs take forever design verify. (see inflexible.)
ACEX off-the-shelf standard family devices that user-programmable have costs. family chips with minimum order quantities. high-volume family characterized costs fast development times: company's products were consistently first market because they used ACEX devices. (see time-to-market, cost.)
ACEX. Better, definition.
Find more about ACEXprogrammable devices from Altera. Visit online http://www.altera.com/lowcost.
http://www.altera.com/lowcost
Copyright 2000 Altera Corporation. Altera, ACEX, Programmable Solutions Company trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. rights reserved.
When ball your court,
need APEX.
High-density advantage.
With devices offering million gates (2.5 million maximum system gates), Altera's APEXdevice family allows highperformance integration system-on-aprogrammable-chip (SOPC) designs. APEX MultiCorearchitecture combines with dualport high-speed content-addressable memory enhanced core performance MHz. Embedded LVDS circuitry that supports bandwidth Gbits/second combines with other high-speed allow overall device bandwidt
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