56A, 115V, 0.025 Ohm, N-Channel UltraFET Power MOSFET Title anraF OST)
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HUF75639S3R4851
56A, 115V, 0.025 Ohm, N-Channel UltraFET Power MOSFET Title anraF OST) utho eyrds terrpoon, anraF OSThis N-Channel power MOSFETs manufactured using innovative UltraFET® process. This advanced process technology achieves lowest possible on-resistance silicon area, resulting outstanding performance. This device capable withstanding high energy avalanche mode diode exhibits very reverse recovery time stored charge. designed applications where power efficiency important, such switching regulators, switching converters, motor drivers, relay drivers, low-voltage switches, power management portable battery-operated products. Formerly developmental type TA75639.`
56A, 115V Simulation Models Temperature Compensated PSPICE® SABERElectrical Models Spice Saber Thermal Impedance Models www.Intersil.com Peak Current Pulse Width Curve Rating Curve
Ordering Information
PART NUMBER HUF75639S3R4851 PACKAGE TO-262AA R4851 BRAND
Related Literature TB334, "Guidelines Soldering Surface Mount Components Boards"
NOTE: When ordering, entire part number.
Packaging
JEDEC TO-262AA
SOURCE DRAIN GATE
Symbol
Absolute Maximum Ratings
25oC, Unless Otherwise Specified HUF75639S3R4851 Figure Figures 1.35 UNITS
Drain Source Voltage (Note VDSS Drain Gate Voltage (RGS 20k) (Note VDGR Gate Source Voltage Drain Current Continuous (Figure Pulsed Drain Current .IDM Pulsed Avalanche Rating Power Dissipation Derate Above 25oC Operating Storage Temperature TSTG Maximum Temperature Soldering Leads 0.063in (1.6mm) from Case 10s. Package Body 10s, Techbrief Tpkg
W/oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: 25oC 150oC. Product reliability information found severe environments, Automotive HUFA series. Intersil semiconductor products manufactured, assembled tested under ISO9000 QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75639S3R4851 Rev.
HUF75639S3R4851
Electrical Specifications
PARAMETER STATE SPECIFICATIONS Drain Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS 250µA, (Figure 95V, 90V, 150oC Gate Source Leakage Current STATE SPECIFICATIONS Gate Source Threshold Voltage Drain Source Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction Case Thermal Resistance Junction Ambient SWITCHING SPECIFICATIONS Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge Threshold Gate Charge Gate Source Gate Charge Reverse Transfer Capacitance CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS 25V, 1MHz (Figure 2000 Qg(TOT) Qg(10) Qg(TH) 50V, 56A, 0.89 Ig(REF) 1.0mA (Figure (VGS 10V) td(ON) td(OFF) tOFF 50V, 56A, 0.89, 10V, (Figure TO-262 0.74
oC/W oC/W
25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS UNITS
±100
IGSS
±20V
VGS(TH) rDS(ON)
VDS, 250µA (Figure 56A, (Figure
0.021
0.025
Source Drain Diode Specifications
PARAMETER Source Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL 56A, dISD/dt 100A/µs 56A, dISD/dt 100A/µs TEST CONDITIONS 1.25 UNITS
©2001 Fairchild Semiconductor Corporation
HUF75639S3R4851 Rev.
HUF75639S3R4851 Typical Performance Curves
POWER DISSIPATION MULTIPLIER CASE TEMPERATURE (oC) DRAIN CURRENT CASE TEMPERATURE (oC)
FIGURE NORMALIZED POWER DISSIPATION CASE TEMPERATURE
FIGURE MAXIMUM CONTINUOUS DRAIN CURRENT CASE TEMPERATURE
ZJC, NORMALIZED THERMAL IMPEDANCE DUTY CYCLE DESCENDING ORDER 0.05 0.02 0.01 NOTES: DUTY FACTOR: t1/t2 PEAK 10-2 RECTANGULAR PULSE DURATION 10-1
SINGLE PULSE 0.01 10-5 10-4 10-3
FIGURE NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000 25oC PEAK CURRENT TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT FOLLOWS:
TRANSCONDUCTANCE LIMIT CURRENT THIS REGION 10-5 10-4 10-3 10-2 PULSE WIDTH 10-1
FIGURE PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF75639S3R4851 Rev.
HUF75639S3R4851 Typical Performance Curves
1000 IAS, AVALANCHE CURRENT RATED 25oC DRAIN CURRENT
(Continued)
(L)(IAS)/(1.3*RATED BVDSS VDD) (L/R)ln[(IAS*R)/(1.3*RATED BVDSS VDD)
STARTING STARTING 150C
100µs
OPERATION THIS AREA LIMITED rDS(ON) DRAIN SOURCE VOLTAGE VDSS(MAX) 115V 10ms
0.001
0.01
TIME AVALANCHE (ms)
NOTE: Refer Intersil Application Notes AN9321 AN9322. FIGURE FORWARD BIAS SAFE OPERATING AREA FIGURE UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
DRAIN CURRENT DRAIN CURRENT
PULSE DURATION 80µs DUTY CYCLE 0.5% 175oC
PULSE DURATION 80µs DUTY CYCLE 0.5% 25oC
25oC GATE SOURCE VOLTAGE -55oC
DRAIN SOURCE VOLTAGE
FIGURE SATURATION CHARACTERISTICS
FIGURE TRANSFER CHARACTERISTICS
NORMALIZED DRAIN SOURCE RESISTANCE PULSE DURATION 80µs DUTY CYCLE 0.5% 10V, NORMALIZED GATE
VDS, 250µA THRESHOLD VOLTAGE
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
FIGURE NORMALIZED DRAIN SOURCE RESISTANCE JUNCTION TEMPERATURE
FIGURE NORMALIZED GATE THRESHOLD VOLTAGE JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUF75639S3R4851 Rev.
HUF75639S3R4851 Typical Performance Curves
NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE 250µA 2500 CAPACITANCE (pF) 2000 CISS 1500 1000 COSS CRSS JUNCTION TEMPERATURE (oC) DRAIN SOURCE VOLTAGE
(Continued)
3000 1MHz CISS CRSS COSS
FIGURE NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE JUNCTION TEMPERATURE
GATE SOURCE VOLTAGE
FIGURE CAPACITANCE DRAIN SOURCE VOLTAGE
WAVEFORMS DESCENDING ORDER:
GATE CHARGE (nC)
NOTE: Refer Intersil Application Notes AN7254 AN7260. FIGURE GATE CHARGE WAVEFORMS CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
HUF75639S3R4851 Rev.
HUF75639S3R4851 Test Circuits Waveforms
BVDSS VARY OBTAIN REQUIRED PEAK
0.01
FIGURE UNCLAMPED ENERGY TEST CIRCUIT
FIGURE UNCLAMPED ENERGY WAVEFORMS
Qg(TOT)
Qg(10) Qg(TH) Ig(REF)
IG(REF)
FIGURE GATE CHARGE TEST CIRCUIT
FIGURE GATE CHARGE WAVEFORM
td(ON)
tOFF td(OFF)
PULSE WIDTH
FIGURE SWITCHING TIME TEST CIRCUIT
FIGURE RESISTIVE SWITCHING WAVEFORMS
©2001 Fairchild Semiconductor Corporation
HUF75639S3R4851 Rev.
HUF75639S3R4851 PSPICE Electrical Model
SUBCKT R4851
2.8e-9 2.65e-9 1.9e-9 DBODY DBODYMOD DBREAK DBREAKMOD DPLCAP DPLCAPMOD EBREAK EVTHRES EVTEMP LDRAIN 2e-9 LGATE 1e-9 LSOURCE 0.47e-9 RLGATE RLDRAIN RLSOURCE 4.69 MMED MMEDMOD MSTRO MSTROMOD MWEAK MWEAKMOD
LGATE GATE RLGATE EVTEMP RGATE DPLCAP RSLC1 ESLC RLDRAIN DBREAK EBREAK
Oct.
LDRAIN DRAIN
RSLC2
EVTHRES
MSTRO LSOURCE RSOURCE RLSOURCE SOURCE
RBREAK RBREAKMOD RDRAIN RDRAINMOD 1.3e-2 RGATE RSLC1 RSLCMOD 1e-6 RSLC2 RSOURCE RSOURCEMOD 4.5e-3 RVTHRES RVTHRESMOD RVTEMP RVTEMPMOD S1AMOD S1BMOD S2AMOD S2BMOD
VBAT ESLC VALUE .MODEL DBODYMOD 1.4e-12 3.3e-3 TRS1 2e-3 TRS2 0.1e-5 3.3e-9 6.1e-8 0.7) .MODEL DBREAKMOD 3.5e-1 TRS1 1e-3 TRS2 1e-6) .MODEL DPLCAPMOD (CJO 2.2e-9 1e-30 0.95 1.0) .MODEL MMEDMOD NMOS (VTO 1e-30 0.7) .MODEL MSTROMOD NMOS (VTO 3.97 56.5 1e-30 .MODEL MWEAKMOD NMOS (VTO =3.11 0.085 1e-30 0.1) .MODEL RBREAKMOD (TC1 0.8e-3 1e-6) .MODEL RDRAINMOD (TC1 1e-2 1.75e-5) .MODEL RSLCMOD (TC1 2.8e-3 14e-6) .MODEL RSOURCEMOD (TC1 .MODEL RVTHRESMOD -2.0e-3 -1.75e-5) .MODEL RVTEMPMOD (TC1 -2.75e-3 0.05e-9) .MODEL S1AMOD VSWITCH (RON 1e-5 .MODEL S1BMOD VSWITCH (RON 1e-5 .MODEL S2AMOD VSWITCH (RON 1e-5 .MODEL S2AMOD VSWITCH (RON 1e-5 .ENDS ROFF ROFF ROFF ROFF -6.0 VOFF -3.5) -3.5 VOFF -6.0) -2.5 VOFF 4.95) 4.95 VOFF -2.5)
NOTE: further discussion PSPICE model, consult PSPICE Sub-Circuit Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written William Hepp Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
RDRAIN
DBODY
MWEAK MMED
RBREAK RVTEMP
VBAT
RVTHRES
HUF75639S3R4851 Rev.
HUF75639S3R4851 SABER Electrical Model
temp=25 115v Ultrafet
Oct. template r4851 n2,n1,n3 electrical n2,n1,n3 iscl d.model dbodymod (is=1.4e-12, xti=4.7, cjo=33e-10,tt=6.1e-8, m=0.7) d.model dbreakmod d.model dplcapmod vj=1.0) m.model mmedmod tox=1) m.model mstrongmod tox=1) m.model mweakmod tox=1) sw_vcsp.model s1amod sw_vcsp.model s1bmod sw_vcsp.model s2amod sw_vcsp.model s2bmod
LDRAIN DPLCAP RSLC1 RSLC2 ISCL RLDRAIN RDBREAK DBREAK MWEAK DBODY MMED MSTRO EBREAK RDBODY DRAIN
EVTHRES
RDRAIN
c.ca 28.5e-10 c.cb 26.5e-10 c.cin 19e-10 d.dbody model=dbodymod d.dbreak model=dbreakmod d.dplcap model=dplcapmod i.it l.ldrain 2.0e-9 l.lgate 1e-9 l.lsource 4.69e-10
GATE
LGATE
EVTEMP RGATE
RLGATE
RSOURCE
LSOURCE RLSOURCE SOURCE
RBREAK RVTEMP
m.mmed model=mmedmod, l=1u, w=1u m.mstrong model=mstrongmod, l=1u, w=1u m.mweak model=mweakmod, l=1u, w=1u res.rbreak tc1=0.8e-3,tc2=-1e-6 res.rdbody 3.3e-3, tc1=2.0e-3, tc2=0.1e-5 res.rdbreak 3.5e-1, tc1=1e-3, tc2=1e-6 res.rdrain 13e-3, tc1=1e-2,tc2=1.75e-5 res.rgate res.rldrain res.rlgate res.rlsource 4.69 res.rslc1 1e-6, tc1=2.8e-3,tc2=14e-6 res.rslc2 res.rsource 4.5e-3, tc1=0,tc2=0 res.rvtemp tc1=-2.75e-3,tc2=0.05e-9 res.rvthres tc1=-2e-3,tc2=-1.75e-5 spe.ebreak spe.eds spe.egs spe.esg spe.evtemp spe.evthres sw_vcsp.s1a model=s1amod sw_vcsp.s1b model=s1bmod sw_vcsp.s2a model=s2amod sw_vcsp.s2b model=s2bmod v.vbat dc=1
VBAT
RVTHRES
equations (n51->n50) +=iscl iscl: v(n51,n50)
©2001 Fairchild Semiconductor Corporation
HUF75639S3R4851 Rev.
HUF75639S3R4851 Spice Thermal Model
1999 R4851 CTHERM1 5.0e-3 CTHERM2 1.9e-2 CTHERM3 7.95e-3 CTHERM4 9.0e-3 CTHERM5 2.95e-2 CTHERM6 12.55 RTHERM1 5.04e-3 RTHERM2 1.25e-2 RTHERM3 3.54e-2 RTHERM4 1.98e-1 RTHERM5 2.99e-1 RTHERM6 3.97e-2
JUNCTION
RTHERM1
CTHERM1
RTHERM2
CTHERM2
Saber Thermal Model
Saber thermal model R4851 template thermal_model thermal_c ctherm.ctherm1 5.0e-3 ctherm.ctherm2 1.9e-2 ctherm.ctherm3 7.95e-3 ctherm.ctherm4 9.0e-3 ctherm.ctherm5 2.95e-2 ctherm.ctherm6 12.55 rtherm.rtherm1 5.04e-3 rtherm.rtherm2 1.25e-2 rtherm.rtherm3 3.54e-2 rtherm.rtherm4 1.98e-1 rtherm.rtherm5 2.99e-1 rtherm.rtherm6 3.97e-2
RTHERM3
CTHERM3
RTHERM4
CTHERM4
RTHERM5
CTHERM5
RTHERM6
CTHERM6
CASE
©2001 Fairchild Semiconductor Corporation
HUF75639S3R4851 Rev.
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