80V, 0.030 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC
|
|
|
Top Searches for this datasheet
HUF75531SK8
80V, 0.030 Ohm, N-Channel, UltraFET Power MOSFET Packaging
JEDEC MS-012AA
BRANDING DASH
Features
Ultra On-Resistance rDS(ON) 0.030,
Simulation Models Temperature Compensated PSPICE® SABERElectrical Models Spice SABER Thermal Impedance Models www.intersil.com Peak Current Pulse Width Curve
Symbol
SOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN
Rating Curve
Ordering Information
PART NUMBER HUF75531SK8 PACKAGE MS-012AA BRAND 75531SK8
NOTE: When ordering, entire part number. suffix obtain variant tape reel, e.g., HUF75531SK8T.
Absolute Maximum Ratings
25oC, Unless Otherwise Specified HUF75531SK8 UNITS Figure Figures mW/oC
Drain Source Voltage (Note VDSS Drain Gate Voltage (RGS 20k) (Note .VDGR Gate Source Voltage Drain Current Continuous (TA= 25oC, 10V) (Figure Continuous (TA= 100oC, 10V) (Figure Pulsed Drain Current Pulsed Avalanche Rating Power Dissipation Derate Above 25oC Operating Storage Temperature TSTG Maximum Temperature Soldering Leads 0.063in (1.6mm) from Case 10s. Package Body 10s, Techbrief TB370 .Tpkg NOTES: 25oC 125oC. 50oC/W measured using FR-4 board with 0.76 (490.3 mm2) copper second. 152oC/W measured using FR-4 board with 0.054 (34.8 mm2) copper 1000 seconds 189oC/W measured using FR-4 board with 0.0115 (7.42 mm2) copper 1000 seconds
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
Product reliability information found severe environments, Automotive HUFA series. Intersil semiconductor products manufactured, assembled tested under ISO9000 QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75531SK8 Rev.
HUF75531SK8
Electrical Specifications
PARAMETER STATE SPECIFICATIONS Drain Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS IGSS VGS(TH) rDS(ON) 250µA, (Figure 75V, 70V, 150oC Gate Source Leakage Current STATE SPECIFICATIONS Gate Source Threshold Voltage Drain Source Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction Ambient Area 0.76 (490.3 mm2) (Note Area 0.054 (34.8 mm2) (Note Area 0.0115 (7.42 mm2)(Note SWITCHING SPECIFICATIONS (VGS 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge Threshold Gate Charge Gate Source Gate Charge Gate Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS 25V, 1MHz (Figure 1210 Qg(TOT) Qg(10) Qg(TH) 40V, Ig(REF) 1.0mA (Figures td(ON) td(OFF) tOFF 40V, 10V, (Figures 10.5
oC/W oC/W oC/W
25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS UNITS
±100 0.030
±20V VDS, 250µA (Figure (Figure
0.025
Source Drain Diode Specifications
PARAMETER Source Drain Diode Voltage SYMBOL Reverse Recovery Time Reverse Recovered Charge dISD/dt 100A/µs dISD/dt 100A/µs TEST CONDITIONS 1.25 1.00 UNITS
©2001 Fairchild Semiconductor Corporation
HUF75531SK8 Rev.
HUF75531SK8 Typical Performance Curves
POWER DISSIPATION MULTIPLIER AMBIENT TEMPERATURE (oC)
10V, 50oC/W
DRAIN CURRENT
AMBIENT TEMPERATURE (oC)
FIGURE NORMALIZED POWER DISSIPATION CASE TEMPERATURE
FIGURE MAXIMUM CONTINUOUS DRAIN CURRENT CASE TEMPERATURE
DUTY CYCLE DESCENDING ORDER 0.05 0.02 0.01
THERMAL IMPEDANCE
50oC/W
ZJA, NORMALIZED
0.01
NOTES: DUTY FACTOR: t1/t2 PEAK 10-2 10-1
SINGLE PULSE 0.001 10-5 10-4 10-3 RECTANGULAR PULSE DURATION
FIGURE NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
50oC/W
IDM, PEAK CURRENT
25oC TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT FOLLOWS:
TRANSCONDUCTANCE LIMIT CURRENT THIS REGION 10-5 10-4 10-3 10-2 10-1 PULSE WIDTH
FIGURE PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF75531SK8 Rev.
HUF75531SK8 Typical Performance Curves
DRAIN CURRENT
(Continued)
50oC/W
IAS, AVALANCHE CURRENT
(L)(IAS)/(1.3*RATED BVDSS VDD) (L/R)ln[(IAS*R)/(1.3*RATED BVDSS VDD)
100µs OPERATION THIS AREA LIMITED rDS(ON) SINGLE PULSE RATED 25oC VDS, DRAIN SOURCE VOLTAGE
STARTING 150oC
STARTING 25oC
10ms
0.01
tAV, TIME AVALANCHE (ms)
NOTE: Refer Intersil Application Notes AN9321 AN9322. FIGURE FORWARD BIAS SAFE OPERATING AREA FIGURE UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
VGS, GATE SOURCE VOLTAGE 150oC -55oC PULSE DURATION 80µs DUTY CYCLE 0.5%
25oC
DRAIN CURRENT
DRAIN CURRENT
PULSE DURATION 80µs DUTY CYCLE 0.5% 25oC
VDS, DRAIN SOURCE VOLTAGE
FIGURE TRANSFER CHARACTERISTICS
FIGURE SATURATION CHARACTERISTICS
NORMALIZED DRAIN SOURCE RESISTANCE PULSE DURATION 80µs DUTY CYCLE 0.5% NORMALIZED GATE THRESHOLD VOLTAGE
VDS, 250µA
10V, JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
FIGURE NORMALIZED DRAIN SOURCE RESISTANCE JUNCTION TEMPERATURE
FIGURE NORMALIZED GATE THRESHOLD VOLTAGE JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUF75531SK8 Rev.
HUF75531SK8 Typical Performance Curves
NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE 250µA
(Continued)
3000 1MHz 1000 CISS
CAPACITANCE (pF)
COSS
CRSS
JUNCTION TEMPERATURE (oC)
DRAIN SOURCE VOLTAGE
FIGURE NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE JUNCTION TEMPERATURE
GATE SOURCE VOLTAGE
FIGURE CAPACITANCE DRAIN SOURCE VOLTAGE
WAVEFORMS DESCENDING ORDER: GATE CHARGE (nC)
NOTE: Refer Intersil Application Notes AN7254 AN7260. FIGURE GATE CHARGE WAVEFORMS CONSTANT GATE CURRENT
Test Circuits Waveforms
BVDSS VARY OBTAIN REQUIRED PEAK
0.01
FIGURE UNCLAMPED ENERGY TEST CIRCUIT
FIGURE UNCLAMPED ENERGY WAVEFORMS
©2001 Fairchild Semiconductor Corporation
HUF75531SK8 Rev.
HUF75531SK8 Test Circuits Waveforms
(Continued)
Qg(TOT)
Qg(10) Qg(TH) Ig(REF)
Ig(REF)
FIGURE GATE CHARGE TEST CIRCUIT
FIGURE GATE CHARGE WAVEFORMS
td(ON)
tOFF td(OFF)
PULSE WIDTH
FIGURE SWITCHING TIME TEST CIRCUIT
FIGURE SWITCHING TIME WAVEFORM
Thermal Resistance Mounting Area
maximum rated junction temperature, TJM, thermal resistance heat dissipating path determines maximum allowable device power dissipation, PDM, application. Therefore application's ambient temperature, (oC), thermal resistance (oC/W) must reviewed ensure that never exceeded. Equation mathematically represents relationship serves basis establishing rating part.
dissipation ratings. Precise determination complex influenced many factors: Mounting area onto which device attached whether there copper side both sides board. number copper layers thickness board. external heat sinks. thermal vias. flow board orientation. steady state applications, pulse width, duty cycle transient thermal response part, board environment they Intersil provides thermal information assist designer's preliminary application evaluation. Figure defines
HUF75531SK8 Rev.
(EQ.
using surface mount devices such SOP-8 package, environment which applied will have significant influence part's current maximum power
©2001 Fairchild Semiconductor Corporation
HUF75531SK8
device function copper (component side) area. This horizontally positioned FR-4 board with copper after 1000 seconds steady state power with flow. This graph provides necessary information calculation steady state junction temperature power dissipation. Pulse applications evaluated using Intersil device Spice thermal model manually utilizing normalized maximum transient thermal impedance curve. Displayed curve values listed Electrical Specifications table. points were chosen depict compromise between copper board area, thermal resistance ultimately power dissipation, PDM. Thermal resistances corresponding other copper areas obtained from Figure calculation using Equation defined natural area times coefficient added constant. area, square inches copper area including gate source pads.
83.2 23.6
(oC/W)
graph. Spice SABER thermal models provided each listed areas. Copper area perceivable effect transient thermal impedance pulse widths less than 100ms. pulse widths less than 100ms transient thermal impedance determined package. Therefore, CTHERM1 through CTHERM5 RTHERM1 through RTHERM5 remain constant each thermal models. listing model component values available Table
83.2 23.6*ln(AREA) 189oC/W 0.0115in2
152oC/W 0.054in2
Area
(EQ.
0.01 AREA, COPPER AREA (in2)
transient thermal impedance (ZJA) also effected varied copper board area. Figure shows effect copper area single pulse transient thermal impedance. Each trace represents copper area square inches corresponding descending list
COPPER BOARD AREA DESCENDING ORDER 0.04 0.28 0.52 0.76 1.00
FIGURE THERMAL RESISTANCE MOUNTING AREA
ZJA, THERMAL IMPEDANCE (oC/W)
10-1 RECTANGULAR PULSE DURATION
FIGURE THERMAL IMPEDANCE MOUNTING AREA
©2001 Fairchild Semiconductor Corporation
HUF75531SK8 Rev.
HUF75531SK8 PSPICE Electrical Model
.SUBCKT HUF75531SK8
2.00e-9 2.00e-9 1.09e-9 DBODY DBODYMOD DBREAK DBREAKMOD DPLCAP DPLCAPMOD
2000
LDRAIN DPLCAP RLDRAIN DBREAK EBREAK DRAIN RSLC1 ESLC
RSLC2
LGATE GATE RLGATE EVTEMP RGATE EVTHRES
LDRAIN 1.0e-9 LGATE 1.12e-9 LSOURCE 1.29e-10 MMED MMEDMOD MSTRO MSTROMOD MWEAK MWEAKMOD RBREAK RBREAKMOD RDRAIN RDRAINMOD 9.30e-3 RGATE 1.70 RLDRAIN RLGATE 11.2 RLSOURCE 1.29 RSLC1 RSLCMOD 1e-6 RSLC2 RSOURCE RSOURCEMOD 11.35e-3 RVTHRES RVTHRESMOD RVTEMP RVTEMPMOD S1AMOD S1BMOD S2AMOD S2BMOD
MSTRO LSOURCE RSOURCE RLSOURCE SOURCE
VBAT ESLC .MODEL DBODYMOD 1.06e-12 5.86e-3 TRS1 4.97e-5 TRS2 2.11e-6 1.51e-9 1.05e-7 0.53) .MODEL DBREAKMOD 4.45e-1 TRS1 1.02e-3 TRS2 .MODEL DPLCAPMOD (CJO 1.48e-9 1e-30 0.78) .MODEL MMEDMOD NMOS (VTO 3.18 2.55 1e-30 1.70) .MODEL MSTROMOD NMOS (VTO 3.67 1e-30 .MODEL MWEAKMOD NMOS (VTO 2.83 1e-30 17.0 0.10) .MODEL RBREAKMOD (TC1 1.21e-3 .MODEL RDRAINMOD (TC1 1.32e-2 3.21e-5) .MODEL RSLCMOD (TC1 4.00e-3 .MODEL RSOURCEMOD (TC1 1.00e-3 .MODEL RVTHRESMOD (TC1 -2.56e-3 -9.91e-6) .MODEL RVTEMPMOD (TC1 -2.44e-3 .MODEL S1AMOD VSWITCH (RON 1e-5 .MODEL S1BMOD VSWITCH (RON 1e-5 .MODEL S2AMOD VSWITCH (RON 1e-5 .MODEL S2BMOD VSWITCH (RON 1e-5 .ENDS ROFF ROFF ROFF ROFF -6.0 VOFF= -4.0) -4.0 VOFF= -6.0) -3.0 VOFF= 0.0) VOFF= -3.0)
NOTE: further discussion PSPICE model, consult PSPICE Sub-Circuit Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written William Hepp Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
EBREAK 86.60 EVTHRES EVTEMP
RDRAIN
DBODY
MWEAK MMED
RBREAK RVTEMP
VBAT
RVTHRES
HUF75531SK8 Rev.
HUF75531SK8 SABER Electrical Model
2000 template huf75531sk8 n2,n1,n3 electrical n2,n1,n3 iscl dp.model dbodymod 1.06e-12, rs=5.86e-3, trs1=4.97e-5, trs2=2.11e-6, 1.51e-9, 1.05e-7, 0.53) dp.model dbreakmod (rs=4.45e-1, trs1=1.02e-3, trs2= dp.model dplcapmod (cjo 1.48e-9, 1e-30, 0.78) m.model mmedmod (type=_n, 3.18, 2.55, 1e-30, m.model mstrongmod (type=_n, 3.67, 1e-30, m.model mweakmod (type=_n, 2.83, 0.1, 1e-30, sw_vcsp.model s1amod (ron 1e-5, roff 0.1, -6.0, voff -4.0) DPLCAP sw_vcsp.model s1bmod (ron =1e-5, roff 0.1, -.4.0, voff -6.0) sw_vcsp.model s2amod (ron 1e-5, roff 0.1, -3.0, voff 0.0) sw_vcsp.model s2bmod (ron 1e-5, roff 0.1, 0.0, voff -3.0) RSLC1 c.ca 2.00e-9 c.cb 2.00e-9 c.cin 1.09e-9 dp.dbody model=dbodymod dp.dbreak model=dbreakmod dp.dplcap model=dplcapmod i.it l.ldrain 1.00e-9 l.lgate 1.12e-9 l.lsource 1.29e-10
GATE RLGATE LGATE RSLC2 ISCL
LDRAIN DRAIN RLDRAIN
EVTEMP RGATE EVTHRES
RDRAIN
DBREAK MWEAK MMED EBREAK
DBODY
MSTRO
m.mmed model=mmedmod, l=1u, w=1u m.mstrong model=mstrongmod, l=1u, w=1u m.mweak model=mweakmod, l=1u, w=1u res.rbreak 1.21e-3, res.rdrain 9.30e-3, 1.32e-2, 3.21e-5 res.rgate 1.70 res.rldrain res.rlgate 11.2 res.rlsource 1.29 res.rslc1 1e-6, 4.00e-3, res.rslc2 res.rsource 11.35e-3, 1.00e-3, res.rvtemp -2.44e-3, res.rvthres -2.56e-3, -9.91e-6 spe.ebreak 86.60 spe.eds spe.egs spe.esg spe.evtemp spe.evthres sw_vcsp.s1a model=s1amod sw_vcsp.s1b model=s1bmod sw_vcsp.s2a model=s2amod sw_vcsp.s2b model=s2bmod v.vbat dc=1 equations (n51->n50) +=iscl iscl: v(n51,n50)
LSOURCE RLSOURCE
SOURCE
RSOURCE RBREAK RVTEMP
VBAT
RVTHRES
©2001 Fairchild Semiconductor Corporation
HUF75531SK8 Rev.
HUF75531SK8 SPICE Thermal Model
2000 HUF75531SK8 Copper Area 0.04 CTHERM1 2.0e-3 CTHERM2 5.0e-3 CTHERM3 1.0e-2 CTHERM4 4.0e-2 CTHERM5 9.0e-2 CTHERM6 1.2e-1 CTHERM7 CTHERM8 RTHERM1 RTHERM2 RTHERM3 RTHERM4 RTHERM5 RTHERM6 RTHERM7 RTHERM8
JUNCTION
RTHERM1
CTHERM1
RTHERM2
CTHERM2
RTHERM3
CTHERM3
RTHERM4
CTHERM4
SABER Thermal Model
Copper Area 0.04 template thermal_model thermal_c ctherm.ctherm1 2.0e-3 ctherm.ctherm2 5.0e-3 ctherm.ctherm3 1.0e-2 ctherm.ctherm4 4.0e-2 ctherm.ctherm5 9.0e-2 ctherm.ctherm6 1.2e-1 ctherm.ctherm7 ctherm.ctherm8 rtherm.rtherm1 rtherm.rtherm2 rtherm.rtherm3 rtherm.rtherm4 rtherm.rtherm5 rtherm.rtherm6 rtherm.rtherm7 rtherm.rtherm8 TABLE THERMAL MODELS COMPONENT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.04 1.2e-1 0.28 1.5e-1 38.7 0.52 2.0e-1 31.3
RTHERM5
CTHERM5
RTHERM6
CTHERM6
RTHERM7
CTHERM7
RTHERM8
CTHERM8
CASE
0.76 2.0e-1 29.7
2.0e-1
©2001 Fairchild Semiconductor Corporation
HUF75531SK8 Rev.
TRADEMARKS
following registered unregistered trademarks Fairchild Semiconductor owns authorized intended exhaustive list such trademarks.
Quiet SeriesDISCLAIMER
FAST
PACMANPOPPowerTrench QFETQSQT OptoelectronicsQuiet SeriesSILENT SWITCHER SMART STARTStar* PowerStealth
SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8
FAIRCHILD SEMICONDUCTOR RESERVES RIGHT MAKE CHANGES WITHOUT FURTHER NOTICE PRODUCTS HEREIN IMPROVE RELIABILITY, FUNCTION DESIGN. FAIRCHILD DOES ASSUME LIABILITY ARISING APPLICATION PRODUCT CIRCUIT DESCRIBED HEREIN; NEITHER DOES CONVEY LICENSE UNDER PATENT RIGHTS, RIGHTS OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices critical component component life support device system whose failure perform systems which, intended surgical implant into reasonably expected cause failure life body, support sustain life, whose support device system, affect safety failure perform when properly used accordance with instructions provided labeling, effectiveness. reasonably expected result significant injury user. PRODUCT STATUS DEFINITIONS Definition Terms Datasheet Identification Advance Information Product Status Formative Design Definition This datasheet contains design specifications product development. Specifications change manner without notice. This datasheet contains preliminary data, supplementary data will published later date. Fairchild Semiconductor reserves right make changes time without notice order improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves right make changes time without notice order improve design.
Preliminary
First Production
Identification Needed
Full Production
Obsolete
Production
This datasheet contains specifications product that been discontinued Fairchild semiconductor. datasheet printed reference information only.
Rev.
Other recent searches
SF1142B - SF1142B SF1142B Datasheet
MK11-1A66B-1200W - MK11-1A66B-1200W MK11-1A66B-1200W Datasheet
MK11-1A71B-1200W - MK11-1A71B-1200W MK11-1A71B-1200W Datasheet
IS45S32400B - IS45S32400B IS45S32400B Datasheet
FIT106-5 - FIT106-5 FIT106-5 Datasheet
FD1774G - FD1774G FD1774G Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
