75A, 55V, 0.007 Ohm, N-Channel UltraFET Power MOSFETs Title UF75 5P3,
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HUF75345G3, HUF75345P3, HUF75345S3S
75A, 55V, 0.007 Ohm, N-Channel UltraFET Power MOSFETs Title UF75 5P3, UF75 anraF OSTs) utho eyrds terrpoon, anraF
These N-Channel power MOSFETs manufactured using innovative UltraFET® process. This advanced process technology achieves lowest possible on-resistance silicon area, resulting outstanding performance. This device capable withstanding high energy avalanche mode diode exhibits very reverse recovery time stored charge. designed applications where power efficiency important, such switching regulators, switching converters, motor drivers, relay drivers, lowvoltage switches, power management portable battery-operated products. Formerly developmental type TA75345.
Features
75A, Simulation Models Temperature Compensated PSPICE® SABERModels Thermal Impedance SPICE SABER Models Available www.intersil.com Peak Current Pulse Width Curve Rating Curve Related Literature TB334, "Guidelines Soldering Surface Mount Components Boards"
Symbol
Ordering Information
PART NUMBER HUF75345G3 HUF75345P3 HUF75345S3S PACKAGE TO-247 TO-220AB TO-263AB BRAND 75345G 75345P 75345S
NOTE: When ordering, entire part number. suffix obtain TO-263AB variant tape reel, e.g., HUF75345S3ST.
Packaging
JEDEC STYLE TO-247
SOURCE DRAIN GATE
JEDEC TO-220AB
SOURCE DRAIN GATE DRAIN (FLANGE)
DRAIN (TAB)
JEDEC TO-263AB
DRAIN (FLANGE) GATE SOURCE
Product reliability information found severe environments, Automotive HUFA series. Intersil semiconductor products manufactured, assembled tested under ISO9000 QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75345G3, HUF75345P3, HUF75345S3S Rev.
HUF75345G3, HUF75345P3, HUF75345S3S
Absolute Maximum Ratings
25oC, Unless Otherwise Specified Figure Figure 2.17 UNITS
Drain Source Voltage (Note VDSS Drain Gate Voltage (RGS 20k) (Note VDGR Gate Source Voltage Drain Current Continuous (Figure Pulsed Drain Current .IDM Pulsed Avalanche Rating Power Dissipation Derate Above 25oC Operating Storage Temperature TSTG Maximum Temperature Soldering Leads 0.063in (1.6mm) from Case 10s. Package Body 10s, Techbrief Tpkg
W/oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: 25oC 150oC.
Electrical Specifications
PARAMETER STATE SPECIFICATIONS
25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS 250µA, (Figure 50V, 45V, 150oC ±20V VDS, 250µA (Figure 75A, (Figure (Figure TO-247 TO-220, TO-263 UNITS
Drain Source Breakdown Voltage Zero Gate Voltage Drain Current
BVDSS IDSS IGSS VGS(TH) rDS(ON)
±100 0.007
Gate Source Leakage Current STATE SPECIFICATIONS Gate Source Threshold Voltage Drain Source Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction Case Thermal Resistance Junction Ambient
0.006
oC/W oC/W oC/W
0.46
SWITCHING SPECIFICATIONS (VGS 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge Threshold Gate Charge Gate Source Gate Charge Gate Drain "Miller" Charge
td(ON) td(OFF) tOFF Qg(TOT) Qg(10) Qg(TH)
30V, 75A, 0.4, 10V,
30V, 75A, Ig(REF) 1.0mA (Figure
©2001 Fairchild Semiconductor Corporation
HUF75345G3, HUF75345P3, HUF75345S3S Rev.
HUF75345G3, HUF75345P3, HUF75345S3S
Electrical Specifications
PARAMETER CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS 25V, 1MHz (Figure 4000 1450 25oC, Unless Otherwise Specified (Continued) SYMBOL TEST CONDITIONS UNITS
Source Drain Diode Specifications
PARAMETER Source Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL 75A, dISD/dt 100A/µs 75A, dISD/dt 100A/µs TEST CONDITIONS 1.25 UNITS
Typical Performance Curves
POWER DISSIPATION MULTIPLIER DRAIN CURRENT CASE TEMPERATURE (oC)
CASE TEMPERATURE (oC)
FIGURE NORMALIZED POWER DISSIPATION CASE TEMPERATURE
FIGURE MAXIMUM CONTINUOUS DRAIN CURRENT CASE TEMPERATURE
THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE DESCENDING ORDER 0.05 0.02 0.01
NOTES: DUTY FACTOR: t1/t2 PEAK 10-3 10-2 10-1
SINGLE PULSE 0.01 10-5 10-4
RECTANGULAR PULSE DURATION
FIGURE NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2001 Fairchild Semiconductor Corporation
HUF75345G3, HUF75345P3, HUF75345S3S Rev.
HUF75345G3, HUF75345P3, HUF75345S3S Typical Performance Curves
2000
(Continued)
25oC
IDM, PEAK CURRENT
1000
TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT FOLLOWS:
TRANSCONDUCTANCE LIMIT CURRENT THIS REGION
10-5
10-4
10-3
10-2 PULSE WIDTH
10-1
FIGURE PEAK CURRENT CAPABILITY
1000 RATED 25oC DRAIN CURRENT
1000 IAS, AVALANCHE CURRENT (L)(IAS)/(1.3*RATED BVDSS VDD) (L/R)ln[(IAS*R)/(1.3*RATED BVDSS VDD)
100µs
OPERATION THIS AREA LIMITED rDS(ON) VDSS(MAX) DRAIN SOURCE VOLTAGE 10ms
STARTING 25oC
STARTING 150oC
0.01
TIME AVALANCHE (ms)
NOTE: Refer Intersil Application Notes AN9321 AN9322. FIGURE FORWARD BIAS SAFE OPERATING AREA FIGURE UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
PULSE DURATION 80µs DUTY CYCLE 0.5% DRAIN CURRENT
DRAIN CURRENT
25oC 175oC -55oC
PULSE DURATION 80µs DUTY CYCLE 0.5% 25oC
DRAIN SOURCE VOLTAGE
GATE SOURCE VOLTAGE
FIGURE SATURATION CHARACTERISTICS
FIGURE TRANSFER CHARACTERISTICS
©2001 Fairchild Semiconductor Corporation
HUF75345G3, HUF75345P3, HUF75345S3S Rev.
HUF75345G3, HUF75345P3, HUF75345S3S Typical Performance Curves
NORMALIZED DRAIN SOURCE RESISTANCE PULSE DURATION 80µs, 10V, DUTY CYCLE 0.5% NORMALIZED GATE THRESHOLD VOLTAGE
(Continued)
VDS, 250µA
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
FIGURE NORMALIZED DRAIN SOURCE RESISTANCE JUNCTION TEMPERATURE
FIGURE NORMALIZED GATE THRESHOLD VOLTAGE JUNCTION TEMPERATURE
NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE 250µA
7000 6000 CAPACITANCE (pF) 1MHz CISS CRSS COSS CISS
5000 4000 3000 2000 1000
COSS CRSS
JUNCTION TEMPERATURE (oC) DRAIN SOURCE VOLTAGE
FIGURE NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE JUNCTION TEMPERATURE
FIGURE CAPACITANCE DRAIN SOURCE VOLTAGE
GATE SOURCE VOLTAGE
WAVEFORMS DESCENDING ORDER: GATE CHARGE (nC)
NOTE: Refer Intersil Application Notes AN7254 AN7260. FIGURE GATE CHARGE WAVEFORMS CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
HUF75345G3, HUF75345P3, HUF75345S3S Rev.
HUF75345G3, HUF75345P3, HUF75345S3S Test Circuits Waveforms
BVDSS VARY OBTAIN REQUIRED PEAK
0.01
FIGURE UNCLAMPED ENERGY TEST CIRCUIT
FIGURE UNCLAMPED ENERGY WAVEFORMS
Qg(TOT)
Qg(10) Qg(TH) Ig(REF)
IG(REF)
FIGURE GATE CHARGE TEST CIRCUIT
FIGURE GATE CHARGE WAVEFORM
td(ON)
tOFF td(OFF)
PULSE WIDTH
FIGURE SWITCHING TIME TEST CIRCUIT
FIGURE RESISTIVE SWITCHING WAVEFORMS
©2001 Fairchild Semiconductor Corporation
HUF75345G3, HUF75345P3, HUF75345S3S Rev.
HUF75345G3, HUF75345P3, HUF75345S3S PSPICE Electrical Model
.SUBCKT HUF75345
5.55e-9 5.55e-9 3.45e-9 DBODY DBODYMOD DBREAK DBREAKMOD DPLCAP DPLCAPMOD EBREAK 56.7 EVTHRES EVTEMP
LGATE RSLC1 ESLC RLDRAIN DBREAK EBREAK
LDRAIN DPLCAP DRAIN
RSLC2
GATE RLGATE EVTEMP RGATE EVTHRES
LDRAIN 1e-9 LGATE 2.6e-9 LSOURCE 1.1e-9 KGATE LSOURCE LGATE 0.0085 MMED MMEDMOD MSTRO MSTROMOD MWEAK MWEAKMOD
MSTRO LSOURCE RSOURCE RLSOURCE SOURCE
RBREAK RBREAKMOD RDRAIN RDRAINMOD 1e-4 RGATE 0.36 RLDRAIN RLGATE RLSOURCE RSLC1 RSLCMOD 1e-6 RSLC2 RSOURCE RSOURCEMOD 3.15e-3 RVTHRES RVTHRESMOD RVTEMP RVTEMPMOD S1AMOD S1BMOD S2AMOD S2BMOD
VBAT ESLC .MODEL DBODYMOD 6e-12 1.4e-3 TRS1 2.75e-3 TRS2 5.0e-6 5.5e-9 5.9e-8 0.75) .MODEL DBREAKMOD 2.8e-2 TRS1 -4.0e-3 TRS2 1.0e-6) .MODEL DPLCAPMOD (CJO 6.75e-9 1e-30 0.88 1.45 0.5) .MODEL MMEDMOD NMOS (VTO 2.93 13.75 1e-30 0.36) .MODEL MSTROMOD NMOS (VTO 3.23 1e-30 Lambda 0.06) .MODEL MWEAKMOD NMOS (VTO 2.35 =0.02 1e-30 3.6) .MODEL RBREAKMOD (TC1 8.0e-4 4.0e-6) .MODEL RDRAINMOD (TC1 1.5e-1 6.5e-4) .MODEL RSLCMOD (TC1 1.0e-4 1.05e-6) .MODEL RSOURCEMOD (TC1 1.0e-3 .MODEL RVTHRESMOD (TC1 -1.5e-3 -2.6e-5) .MODEL RVTEMPMOD (TC1 -2.75e-3 1.45e-6) .MODEL S1AMOD VSWITCH (RON 1e-5 .MODEL S1BMOD VSWITCH (RON 1e-5 .MODEL S2AMOD VSWITCH (RON 1e-5 .MODEL S2BMOD VSWITCH (RON 1e-5 .ENDS ROFF ROFF ROFF ROFF -9.00 VOFF= -4.00) -4.00 VOFF= -9.00) 0.00 VOFF= 0.50) 0.50 VOFF= 0.00)
NOTE: further discussion PSPICE model, consult PSPICE Sub-Circuit Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written William Hepp Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
RDRAIN
DBODY
MWEAK MMED
RBREAK RVTEMP
VBAT
RVTHRES
HUF75345G3, HUF75345P3, HUF75345S3S Rev.
HUF75345G3, HUF75345P3, HUF75345S3S SABER Electrical Model
February 1999 template huf75345 electrical iscl d.model dbodymod 6e-12, 5.5e-9, 5.9e-8, m=0.5, vj=0.75) d.model dbreakmod d.model dplcapmod (cjo 6.75e-9, 1e-30, 0.88, 1.45,fc=0.5) m.model mmedmod (type=_n, 2.93, 13.75, 1e-30, m.model mstrongmod (type=_n, 3.23, is=1e-30,tox=1, lambda 0.06) DPLCAP m.model mweakmod (type=_n, 2.35, 0.02, 1e-30, sw_vcsp.model s1amod (ron 1e-5, roff 0.1, voff sw_vcsp.model s1bmod (ron 1e-5, roff 0.1, voff sw_vcsp.model s2amod (ron 1e-5, roff 0.1, voff 0.5) sw_vcsp.model s2bmod (ron 1e-5, roff 0.1, 0.5, voff
RSLC2
LDRAIN RLDRAIN RDBREAK DBREAK MWEAK MMED MSTRO EBREAK RDBODY DRAIN RSLC1 ISCL
c.ca 5.55e-9 c.cb 5.55e-9 c.cin 3.45e-9 d.dbody model=dbodymod d.dbreak model=dbreakmod d.dplcap model=dplcapmod i.it
GATE
LGATE EVTEMP RGATE EVTHRES
RDRAIN
DBODY
l.ldrain 1e-9 RLGATE l.lgate 2.6e-9 l.lsource 1.1e-9 k.k1 i(l.lgate) i(l.lsource) l(l.lgate), l(l.lsource), 0.0085 m.mmed model=mmedmod, m.mstrong model=mstrongmod, m.mweak model=mweakmod, res.rbreak 8e-4, 4e-6 res.rdbody 1.4e-3, 2.75e-3, 5e-6 res.rdbreak 2.8e-2, -4e-3, 1e-6 res.rdrain 1e-4, 1.5e-1, 6.5e-4 res.rgate 0.36 res.rldrain res.rlgate res.rlsource res.rslc1 1e-6, 1e-4, 1.05e-6 res.rslc2 res.rsource 3.15e-3, 1e-3, res.rvtemp -2.75e-3, 1.45e-6 res.rvthres -1.5e-3, -2.6e-5 spe.ebreak 56.7 spe.eds spe.egs spe.esg spe.evtemp spe.evthres sw_vcsp.s1a model=s1amod sw_vcsp.s1b model=s1bmod sw_vcsp.s2a model=s2amod sw_vcsp.s2b model=s2bmod v.vbat equations (n51->n50) iscl iscl: v(n51,n50) 3.5))
LSOURCE RLSOURCE
SOURCE
RSOURCE RBREAK RVTEMP
VBAT
RVTHRES
©2001 Fairchild Semiconductor Corporation
HUF75345G3, HUF75345P3, HUF75345S3S Rev.
HUF75345G3, HUF75345P3, HUF75345S3S SPICE Thermal Model
February 1999 HUF75345 CTHERM1 6.3e-3 CTHERM2 1.5e-2 CTHERM3 2.0e-2 CTHERM4 3.0e-2 CTHERM5 8.0e-2 CTHERM6 1.5e-1 RTHERM1 5.0e-3 RTHERM2 1.8e-2 RTHERM3 5.0e-2 RTHERM4 8.5e-2 RTHERM5 1.0e-1 RTHERM6 1.1e-1
RTHERM1 CTHERM1 JUNCTION
RTHERM2
CTHERM2
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model HUF75345 template thermal_model thermal_c ctherm.ctherm1 6.3e-3 ctherm.ctherm2 1.5e-2 ctherm.ctherm3 2.0e-2 ctherm.ctherm4 3.0e-2 ctherm.ctherm5 8.0e-2 ctherm.ctherm6 1.5e-1 rtherm.rtherm1 5.0e-3 rtherm.rtherm2 1.8e-2 rtherm.rtherm3 5.0e-2 rtherm.rtherm4 8.5e-2 rtherm.rtherm5 1.0e-1 rtherm.rtherm6 1.1e-1
RTHERM4
CTHERM4
RTHERM5
CTHERM5
RTHERM6
CTHERM6
CASE
©2001 Fairchild Semiconductor Corporation
HUF75345G3, HUF75345P3, HUF75345S3S Rev.
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