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Publication Number 22247 Revision
Amendment Issue Date November 2002
November 2002
2002 Advanced Micro Devices, Inc.
Advanced Micro Devices reserves right make changes products without notice order improve design performance characteristics.
This publication neither states implies warranty kind, including limited implied warrants merchantability fitness particular application. AMD® assumes responsibility circuitry other than circuitry product. information this publication believed accurate respects time publication, subject change without notice. assumes responsibility errors omissions, disclaims responsibility consequences resulting from information included herein. Additionally, assumes responsibility functioning undescribed features parameters.
Trademarks
AMD, logo, combinations thereof trademarks Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
FBGA User's Guide
Chapter Introduction
Table 1.1: Package Highlights
Chapter Fine-Pitch Ball Grid Array (FBGA)
Package Construction Figure 2-1. FBGA Construction Impact Size Changes FBGA Package Size Impact Size Changes FBGA Package Size FBGA Package Pinouts Figure 2-2. 48-Ball Ball 32Mb, x8/x16, Voltage) Figure 2-3. 48-Ball Voltage) Figure 2-4. 63-Ball x8/x16, Voltage) Figure 2-5. 63-Ball Voltage) Figure 2-6. 84-Ball x16/x32 Voltage) Figure 2-7. 84-Ball x16/x3240-Ball UltraNAND Only)
Chapter Fortified-BGA
Package Construction Figure 3-1. Fortified-BGA Construction Effects Solder Ball Diameter Fortified-BGA Migration Transition Fortified-BGA (FBGA) Pinouts Figure 3-2. 64-Ball Fortified-BGA Figure 3-3. 80-Ball Fortified-BGA
Chapter Multi-Chip Packaging
Package Construction Figure 4-1. 2-Die Construction Figure 4-2. Same-Die Stack (SDS) Construction System integration space savings Figure 4-3. 2-Die Stack (Flash+SRAM) Figure 4-4. Same-Die-Stack (SDS) Package Pinouts Figure 4-5. Am29DL16XD (x8/x16) SRAM Pinout Figure 4-6. Am29DL32XD (x8/x16) SRAM Pinout Figure 4-7. Am29DL32XD (x8/x16) SRAM Pinout Figure 4-8. Am29DL64XD (x8/x16) SRAM Pinout
Chapter Daisy Chains
Figure 5-1. FBGA Mbit Daisy Chain Schematic (Top View) Figure 5-2. FBGA Mbit Board Layout (Top View)
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Figure 5-3. FBGA Mbit Daisy Chain Schematic (Top View) Figure 5-4. FBGA Megabit Board Layout (Top View) Figure 5-5. FBGA Mbit Daisy Chain Schematic (Top View) Figure 5-6. FBGA Mbit Board Layout (Top View) Figure 5-7. FBGA 84-Ball Daisy Chain Schematic (Top View) Figure 5-8. Fortified 84-Ball Board Layout (Top View) Figure 5-9. Fortified 64-Ball Board Layout (Top View) Figure 5-10. Fortified 64-Ball Daisy Chain Schematic (Top View) Figure 5-11. Fortified 80-Ball Daisy Chain Schematic (Top View) Figure 5-12. Fortified 80-Ball Board Layout (Top View)
Chapter Package Physical Description
FBGA Package Materials Descriptions Table 6.1: FBGA-BT FBGA-BT Ball Attach Detail. Figure 6-1. FBGA Package Ball Attach Detail FBGA Thermal Management Figure 6-2. Path Heat Dissipation Table 6.2: Thermal Resistance Data
Chapter Board Design Layout Considerations
General Design Considerations Figure 7-1. Solder Wetting Around During Reflow Recommended Board Design Dimensions. Figure 7-2. Recommended Dimensions 0.30 Solder Ball Routing Considerations Figure 7-3. Example 48-Ball Single Layer Board Routing Figure 7-4. Example 63-Ball Single Layer Board Routing Recommendation Figure 7-5. Example Interstitial Design High Ball Count Packages
Chapter Component Qualification Testing
Preconditioning. Table 8.1: Moisture Sensitivity Levels Temperature Cycling HAST Thermal Shock Data Retention Bake. HTOL Latch-up ESD. FBGA-BT Component Level Test Results.
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Chapter Board Level Characterization Studies
Experimental Design Procedure Assembly Packages Stress Testing Test Procedure
Chapter 10:Miscellaneous
Shipping Container Information. Sockets FBGA-BT Packages FBGA Package Marking FBGA Package Designators
Appendix Article Reprints
Reliability Evaluation Chip Scale Packages FGBAs-The Choice Flash Memories Memo J-T, Case Level Thermal Parameter
Appendix Application Note
Daisy Chain Samples
Revision Summary
Revision (Version 2.2): March 1999. Revision (Version 2.3): 1999 Revision (Version 2.3.1): July 1999 Revision (Version 3.0): January 2001 Revision (Version 3.1): March 2001 Revision (Version 4.0): January 2002 Revision (Version 4.1): April 2002 Revision (Version 4.2): November 2002
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Chapter
Introduction
There trend electron industry miniaturize. From tower lap-tops PocketPCs, from giant cell phones pager size handsets, demand smaller feature rich electronic devices will continue years come. trend Chip Scale Packages (CSP) have grown tremendously since their introduction. Applications such cell phones, home entertainments, automotive engine controllers networking equipments have adopted packages into their systems. address needs different applications such small package size, reliability migration compatibility, offers three families CSP: Fine-Pitch Ball Grid Array (FBGA), Fortified-BGA Stacked-MCM
Table 1.1: Package Highlights Package Highlights FBGA Package Small Package Ideal space constraint designs Ideal low-provide application Superior board level reliability Ideal application with space constraints. Portable application such mobile phones, camcorders PDAs would benefit most Benefits Target Applications
1.2mm package height BT-Resin Fortified-BGA Uniform 11x13mm Package size 1.0mm Ball Pitch 0.6mm Ball Diameter Stacked-MCM Small Package size
Simple smooth migration compatibility across densities 256Mb Allows more relax design rules Improves board level reliabilities
Removes concerns Automotive, Networking, Telecom other applications that demand highest board level reliabilities
Idea space constrain designs
Enabling applications with increase memory higher performance without increase board space. Ideally suited Camcorders, mobile phones, PDAs other wireless applications
1.4mm Height Combines Flash SRAM
Idea low-profile applications Increase memory capacity with increase board spaces
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Table 1.1: Package Highlights Available Combinations: 128Mb Flash Flash 16Mb Flash SRAM 16Mb Flash SRAM 32Mb Flash SRAM 32Mb Flash SRAM 64Mb Flash SRAM 64Mb Flash 16Mb SRAM Flexible memory combinations number design possibilities opportunities
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Chapter
Fine-Pitch Ball Grid Array (FBGA)
FBGA package family offers Flash memory designers significant reduction board real estate over Thin Small Outline Packages (TSOPs). addition FBGA packages provide many advantages over other Flash memory supplies' chip scale packages, sush alternatives robust board level reliability smooth pinout migrations. packages available several popular 1.8-volt 3.0-volt Flash memory densities. FBGA packages constructed similar conventional packages extension proven technologies. assembly, existing equipment proven manufacturing processes used.
Package Construction
FBGA constructed rigid BT-Resin substrates. mounted substrate leads bonded using gold wires. device encapsulated plastic solder balls attached bottom substrate.
Figure 2-1. FBGA Construction
Note: Package Height max.
Impact Size Changes FBGA Package Size
There many costs associated with manufacturing semiconductor devices: cost, assembly cost testing costs just name few. cost typically most impact total manufacturing cost. order drive down cost final product, semiconductor manufacturers
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will stride reduce sizes. AMD's FBGA packages allow smaller, lower cost placed same package without affecting package dimensions requiring board redesigns.
Impact Size Changes FBGA Package Size
minimum distance between balls FBGA, ball pitch, great affects OEM's board technology system routing complexity. Device with ball pitches 0.8mm easily routed with today's widely used cost effect board technology (FR4 with 0.005 inch lines spaces).
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FBGA Package Pinouts
pinouts shown view, with balls facing down.
Figure 2-2. 48-Ball Ball 32Mb, x8/x16, Voltage)
Am29LV400B
Ball
BYTE#
DQ15 /A-1
Am29LV800B Am29DL800B Am29SL800C
Ball
RESET#
DQ14
DQ13
DQ12
DQ11
WP#/
DQ10
Am29LV160D
Ball
Am29DL16xD Am29SL160C
Ball Ball WP#/ACC
Am29LV320D Am29DS323D Am29PDS322D
Ball Ball WP#/ACC
Figure 2-3. 48-Ball Voltage)
Am29LV017D
RESET#
RY/BY#
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pinouts this chapter shown view, balls facing down.
Figure 2-4. 63-Ball x8/x16, Voltage)
Am29DL32X
BYTE#
DQ15/
DQ14
DQ13
Reset#
DQ12
WP#/
Am29LV640DU
DQ10 DQ11
DQ15
Balls shorted together substrate connected
Figure 2-5. 63-Ball Voltage)
Am29LV033C
Reset#
Am29LV065D
Megabit Megabit Megabit Megabit Gigabit
Balls shorted together substrate connected
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pinouts this chapter shown view, balls facing down.
Figure 2-6. 84-Ball x16/x32 Voltage)
Am29PL3200DU
DQ30 RESET# WORD# DQ15 DQ17 DQ13 DQ29 DQ14 DQ31/A-1 RY/BY# DQ16 DQ12 DQ28 DQ18 DQ19 DQ27 DQ11 DQ10 DQ20 DQ26 DQ25 DQ21 DQ24 DQ23 DQ22
A20: A21:128 A22: A23: A24: A25: A26:
Figure 2-7. 84-Ball x16/x3240-Ball UltraNAND Only)
Am30LV0064D
Keep-out Zones Four Corners. required higher density devices with larger packages.
Vccq
keepout zone composed additional balls that will oncenter relative array.
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Chapter
Fortified-BGA
performance driven applications continues demand high board level reliability packages from Flash memories. addition, designs become increasingly complex, assembly-friendly package becomes more desirable. AMD's Fortified-BGA Flash memory combines both superior reliability beyond standard requirements ease-of-use single package. ideal telecom, networking, automotive avionics applications.
Package Construction
AMD's Fortified-BGA offer single easy 13x11mm 1.4mm Package size, with 0.6mm solder ball diameter 1.0mm ball pitch. Designed around AMD's already robust FBGA (0.8mm ball pitch), Fortified-BGA uses industry proven BT-Substrate lower mismatch between substrate PCB.
Figure 3-1. Fortified-BGA Construction
Note: Package Height 1.4mm Max.
Effects Solder Ball Diameter
well known industry that solder ball diameter direct affect solder joint reliability during temperature cycling. Lager solder balls typically yield higher standoff heights after board assembly. importance higher standoff easiest explained through mismatch. describe many papers, higher standoff typically yields higher solder joint reliability during temperature cycling. AMD's Fortified-BGA currently largest solder ball size (0.6mm Diameters)
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package Flash memory. result, AMD's Fortified-BGA offers superior board level reliability, during Temperature Cycling, compared other competitor's packages. When compared competitor's 10x13mm BGA, 64-Ball (8x8 matrix) Fortified-BGA expected have higher relative life factor 4.3X, 80-Ball (8x10 matrix) Fortified-BGA expected 4.6X higher relative life.
Fortified-BGA Migration Transition
AMD's Fortified-BGA taken AMD's tradition simple pinout migration higher density step further. virtually allows migration between densities without board designs. Fortified-BGA's 11x13mm package size designed host Flash density 256Mb. This concept greatly lowers cost customers. anticipating future density needs, customers virtually have board design. Furthermore, this "one-package-fits-all" concept also help trim equipment cost. same socket, test boards, handlers, traces etc. interchangeable between densities. Thereby increases useful life equipments. AMD's Fortified-BGA takes full advantage real estate underneath package. With 1.0mm ball pitch, design rules more relaxed. drill size, 1.0mm pitch provides more clearance traces spaces. example, either 5mil 7mil trace space design rules used. More clearance also allows larger capabilities, ideal multi-layer designs. Board assembly also benefits from 1.0mm ball pitch. AMD's Fortified-BGA aligned with many FPGAs Micro-Controller terms ball pitch. This allows less expensive technology used. AMD's Fortified-BGA, essence, simplifies customers' transition packages. LowCost, highly reliable solution TSOP other traditional leaded packages.
Fortified-BGA (FBGA) Pinouts
pinouts shown view, with balls facing down.
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Figure 3-2. 64-Ball Fortified-BGA
128Mb 256Mb 512MB
Vccq
DQ14 DQ13
AM29LV640X
Ball Ball Ball Ball DQ15
RST#
DQ12
DQ10
DQ11
AM29LV642X
Ball Ball Ball CE2# Ball DQ15
AM29DL640X
Vccq
Ball WP#/ACC Ball BYTE# Ball Ball DQ15/A-1
Figure 3-3. 80-Ball Fortified-BGA
DQ29
VCCQ
VCCQ
DQ20
DQ16
WORD\
AM29BDD160G
VCCQ WORD\ DQ30 IND\, WAIT\
DQ30
DQ26
DQ24
DQ23
DQ18
IND\, WAIT\
RY/BY\
DQ31
DQ28
DQ25
DQ21
DQ19
ADV\
VCCQ
VCCQ
DQ27
RY/BY\
DQ22
DQ17
32Mb 64Mb 128Mb
DQ10
DQ11
ADV\
DQ12
DQ14
VCCQ
VCCQ
DQ13
DQ15
VCCQ
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Chapter
Multi-Chip Packaging
portable consumer product segment such Cell phones, PDAs, digital cameras audio players there demands increase features functionalities well smaller, thinner product size. order meet these demands, launched line (Multi-Chip Package) products. Through system integration optimization, enhances system design numerous ways such reduce size, lower cost, reduce components, lighter weight, smaller system, increase features customer flexibility.
Package Construction
Figure 4-1. 2-Die Construction
Mold Compound (standard) Gold Bond Wire (standard)
Attach (standard)
Resin Substrate
Solder Mask Punch Drill 0.8mm (FBGA) 0.3, 0.35mm (FBGA) Solder Ball
Figure 4-2. Same-Die Stack (SDS) Construction
Mold Compound (standard)
(FBGA) (Fortified-BGA)
DIE-1 Spacer DIE-2
Gold Bond Wire (standard) Attach (standard)
Resin Substrate
Solder Mask Punch Drill 0.8mm (FBGA) 1.0mm (Fortified-BGA) 0.45mm (FBGA) 0.6mm (Fortified-BGA) Solder Ball
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System integration space savings
MCPs gaining momentum industry system integration solution. cellular phone market, Flash SRAM combinations have become very popular. stacks other rigid BT-substrate. Both chips wire- bonded substrate overmolded with encapsulant, solder balls bottom package. This technology allows companies immediately take advantage space savings, with either smaller more feature rich products.
stacking typically size small enough cover bond bottom die. However, both dies similar size Same-Die-Stacking (SDS) must use. uses spacer-die, between bottom, allow addiquiet wire bonding space bottom die. provides powerful flexibility system integration. With SDS, only components different application integrate single package, same components also integrated added feature higher densities, such Flash+Flash.
Figure 4-3. 2-Die Stack (Flash+SRAM)
Figure 4-4. Same-Die-Stack (SDS)
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Package Pinouts
pinouts shown view, with balls facing down.
Figure 4-5. Am29DL16XD (x8/x16) SRAM Pinout
CE#f CE1#s LB#s UB#s DQ10 VCCf DQ11 VCCs CIOs WP#/ACC RESET# RY/BY# CE2s DQ13 DQ12
Flash only SRAM only Shared
DQ15/A-1 DQ14
CIOf
69-Ball FBGA View
Figure 4-6. Am29DL32XD (x8/x16) SRAM Pinout
Flash only
SRAM only
RY/BY#
Shared
WP#/ACC
RESET# CE2s
CE#f
DQ12
DQ13 DQ15/A-1 CIOf
CE1#s
DQ10
VCCf
VCCs
11.6
DQ11
CIOs
DQ14
73-Ball FBGA View
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Figure 4-7. Am29DL32XD (x8/x16) SRAM Pinout
Flash only
SRAM only
RY/BY#
Shared
WP#/ACC
RESET# CE2s
11.6 11.6
CE#f
DQ12
DQ13 DQ15/A-1 CIOf
CE1#s
DQ10
VCCf
VCCs
DQ11
CIOs
DQ14
73-Ball FBGA View
Figure 4-8. Am29DL64XD (x8/x16) SRAM Pinout
Flash only
SRAM only
RY/BY#
Shared
WP#/ACC
RESET# CE2s
11.6
CE#f
DQ12
DQ13 DQ15/A-1 CIOf
CE1#s
DQ10
VCCf
VCCs
DQ11
CIOs
DQ14
73-Ball FBGA View
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Chapter
Daisy Chains
Daisy Chains primarily requested OEMs perform assembly evaluations. Prior production, will generally solder daisy chain samples daisy chain perform Open/Short testing check misalignments. This test will help OEMs characterize assembly process equipment prior full production. Daisy Chains also used Second Level Solder-Joint Board Reliability studies. daisy chain samples assembled onto matching subjected temperature cycling oven. Board Level Reliability tests tools help predict measure expected life packages. more depth information Second Level Solder-Joint Board Reliability, please refer "Reliability Evaluation Chip Scale Packages" Ranjit Gannamani, Viswanath Valluri, Sidharth, MeiLu Zhang (see "Article Reprints"). more in-depth information Daisy Chains please refer "Daisy Chain Samples Application Note". Both listed Appendices.
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Figure 5-1. FBGA Mbit Daisy Chain Schematic (Top View)
Figure 5-2. FBGA Mbit Board Layout (Top View)
input output network this device.
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Figure 5-3. FBGA Mbit Daisy Chain Schematic (Top View)
Figure 5-4. FBGA Megabit Board Layout (Top View)
Notes: input output network device. input output separate network support balls.
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Figure 5-5. FBGA Mbit Daisy Chain Schematic (Top View)
Figure 5-6. FBGA Mbit Board Layout (Top View)
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Figure 5-7. FBGA 84-Ball Daisy Chain Schematic (Top View)
Figure 5-8. Fortified 84-Ball Board Layout (Top View)
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Figure 5-9. Fortified 64-Ball Board Layout (Top View)
Figure 5-10. Fortified 64-Ball Daisy Chain Schematic (Top View)
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Figure 5-11. Fortified 80-Ball Daisy Chain Schematic (Top View)
Figure 5-12. Fortified 80-Ball Board Layout (Top View)
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Chapter
Package Physical Description
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FBGA Package Materials Descriptions
Table 6.1: FBGA-BT Thickness (µm) 25.4 25.4 Material Name SMT-B-1N Silicon Sn/Pb 63/37 Gold Epoxy Resin resin 2.00E+11 2.75E+09 2.60E+10 Ey); 1.10E+10 (Ez) 1.34 6.90 1.50 (CTEx CTEy); 5.20 (CTEz) 0.31 0.11 Young's Modulus (Pa) 1.50E+10 1.24E+09 1.31E+11 3.10E+10 1.21E+11 Poisson's Ratio 0.25 0.28 0.34
Material Type Mold Compound Attach Silicon Eutectic Solder Ball Copper Metallization Wire Plating Solder Resist Substrate Core
ppm/c 1.60 8.00 2.60 2.40 1.70
FBGA-BT Ball Attach Detail
ball attach FBGA-BT package used size soldermask opening 0.25 therefore soldermask defined. ball size nominal. Note that Figure shows ball-to-package attach, ball-to-printed circuit board attach.
Figure 6-1. FBGA Package Ball Attach Detail
copper (0.4 soldermask opening (0.25
ball size (0.3
FBGA-BT
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FBGA Thermal Management
Thermal energy management important today's rapidly changing microelectronics. receive best possible performance electronic product, proper heat dissipation crucial. temperature which microelectronic device operates determines among other things speed reliability product. Proper thermal management achieved when heat transferred dissipated from device system air, which then vented system. most important factors affecting device operation temperature power dissipation, temperature, package construction, cooling mechanisms. combinations these factors determine device's operation temperature.
well FBGA packages dissipate heat measured described junction thermal resistance value.
Figure 6-2. Path Heat Dissipation
Junction Referring Figure 6-2, describes path heat dissipation from active circuit surface through mold compound ambient air. equations that govern this model are:
(TJss TTss)/Pd (TTss TAss)/Pd Thermal characterization parameter from device junction center package surface (°C/W). Package thermal resistance from junction ambient (°C/W). measurement package internal thermal resistance well conductive convective thermal resistance from package exterior ambient. Thermal characterization parameter from surface package-to-air (°C/W) TJss junction temperature steady-state. (oC)
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TTss package (top surface) temperature, steady-state, measured thermocouple, infrared sensor, fluoroptic sensor. TASS Temperature Ambient Steady State Power (watts)
Table 6.2: Thermal Resistance Data Dim. Dim. (mils) (mils) Dim. (mils) Dim. (mils)
Type FBA048
Ext. Num. Thermal
(mW) 1417 1437 1445 1453 1456 1439 1461 1469 1476 1480 2010 2044 2057 2069 2077 2412
(°C/W) (°C/W) (°C/W) (LFPM)
95.8 81.6 71.0 65.8 62.3 49.2 45.5 43.6 42.2 41.4 74.0 65.2 59.8 56.9 42.0 40.3 39.0 38.1 78.8 65.4 56.9 51.9 48.7 35.7 32.2 30.6 29.4 28.5 89.2 74.0 63.1 54.6 53.9 42.5 10.5 14.1
Test Code 1S0P
FBA048
Thermal
2S2P
FBB048
Thermal
1S0P
FBB048
Thermal
2S2P
FBC048
Thermal
1S0P
FBC048
Thermal
2S2P
FGC048
Thermal
1SOP
FGB048
Thermal
2S2P
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Table 6.2: Thermal Resistance Data (Continued) Dim. Dim. (mils) (mils) Dim. (mils) Dim. (mils)
Type FGB048 FBD063
Ext. Num. Thermal Thermal
(mW) 1134 1042 1073 1090 1101 1109
(°C/W) (°C/W) (°C/W) (LFPM)
64.5 51.1 44.2 39.8 37.1
Test Code 1S0P 1S0P
Notes:
measurement date following SEMI G38-87 wind tunnel), unless marked. TEST CODE describes test PCB. signal layer+2 power layer" signal layer+0 power layer" more information Thermal Management please refer "Memo Case level Thermal Parameter" Appendix. Theta junction moving air. (LFPM) Speed moving air, terms "Linear Feet Minute".
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Chapter
Board Design Layout Considerations
General Design Considerations
first decisions made when designing boards chip scale packages whether will possible conventional technology design rules, whether microvia technology will necessary. Recently, microvia (High Density Interconnects) boards have been adopted several volume applications, particularly cell-phones camcorders, prices microvia boards have been falling quickly. defined having vias with diameter less than 0.006 inch size 0.014 inch smaller. However they still more expensive. Measured basis price unit area metal layer, microvia boards least twice expensive high-density conventional multilayer PCBs, even with blind buried vias. Furthermore, there also question availability: easy find suppliers with production capacity microvia boards. this reason that pitch been chosen AMD's FBGA. shown next section, single-layer routing Flash Memory FBGA accomplished with line space widths 0.005 inch more. Because relatively lead count, this done layer, desired, connections down inner layers accomplished through interstitial vias.
Solder-Mask Defined Versus Non-Solder-Mask Defined
There been much discussion about relative merits solder-mask defined (SMD) nonsolder-mask defined (NSMD) lands attaching area array packages such conventional fine pitch BGA. AMD's FBGA used with either, there important benefits NSMD pads. that smaller copper pads used, thus providing more generous clearance routing channels. (Another that solder around sides during reflow (see Figure 7-1) thus providing stronger joint.)
Figure 7-1. Solder Wetting Around During Reflow
Copper attachment
Note that kind wetting shown Figure desired, important provide sufficient clearance solder mask around pad. supplier consider edge solder mask touching edge acceptable, however, this condition would prevent solder from completely wetting side pad.
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Board Surface Finish
Another design consideration selection surface finish board. While solder leveled (HASL) boards have been successfully used FBGA, generally felt that domed shape pads makes more difficult achieve consistent assembly yields. other hand, excellent yields have been achieved with both Ni/Au plated pads also with bare copper pads coated with organic solderability preservatives (OSP). case Ni/Au plated pads, important control plating quality prevent embrittlement solder joint. This occur gold thick; gold thickness mils maximum recommended. There been some concern industry that certain kinds nickel plating cause embrittlement-your supplier should able give advice this subject.
Recommended Board Design Dimensions
Figure 7-2. Recommended Dimensions 0.30 Solder Ball
Package Side
Package side mask defined Solder wets only
Printed Circuit Board
Recommended Design Value Dimension Function Solder Mask Opening Package Copper Dimension Copper Solder Mask Clearance Trace Width 0.30 Solder Ball 0.25 0.03 0.23 0.01 0.075 0.025 0.125 0.25 0.35 Solder Ball 0.30 0.03 0.27 0.015 0.075 0.025 0.125 0.25 0.60 Solder Ball 0.50 0.03 0.40 0.03 0.075 0.025 0.125 0.25
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Routing Considerations
Figure 7-3. Example 48-Ball Single Layer Board Routing
Trace 0.007 (0.175
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Figure 7-4. Example 63-Ball Single Layer Board Routing Recommendation
Note: Recommended dimensions same 48-ball FBGA.
Figure 7-5. Example Interstitial Design High Ball Count Packages
Pitch 0.800
Diameter 0.21 0.24
Diameter 0.36 0.41
Capture Diameter 0.56 0.61
Diagonal Pitch 1.132
Capture 0.20
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Chapter
Component Qualification Testing
highest reliability standards industry. Beginning from wafer sort shipping products, implemented vary stages testing ensure high quality reliability. Samples subjected accelerated stress tests. advantages accelerated stress testing that these tests fewer parts make failures occur faster. stress levels used these tests more severe than that seen field with welldesigned tests resulting same failure mechanisms. Component level testing includes: Preconditioning (Moisture Level Testing) Temperature Cycling Highly Accelerated Stress Test (HAST) Thermal Shock Data Retention Bake High Temperature Operating Life (HTOL) Latch-up Electrostatic Discharge (ESD)
Preconditioning
Moisture Level Testing modeled after JEDEC/IPC Standard J-STD-020A. This test designed determine safe environmental conditions product exposure, thus reducing risk moisture induced damages. Moisture damages include, delamination, package cracks during reflows board assembly, "popcorn" effects. There level moisture sensitivity (See Table 8.1). Products tested Level-1 conditions, fail, next higher level tested until passes. only difference between each level parameter moisture soak (also know preconditioning). There basic components: hour bake 125°C Preconditioning: Moisture storage parameters depending JEDEC Moisture Sensitivity Level which package being qualified (See Table 8.1).
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Table 8.1: Moisture Sensitivity Levels Soak Requirements Floor Life Level Time Unlimited Year Weeks Hours Hours Hours Hours Conditions 30°C/85% 30°C/60% 30°C/60% 30°C/60% 30°C/60% 30°C/60% 30°C/60% Standard Time (Hours) 48/72 Conditions 85°C/85% 85°C/60% 30°C/60% 30°C/60% 30°C/60% 30°C/60% 30°C/60% 60°C/60% 60°C/60% Accelerated Equivalent Time (Hours) Conditions
Three exposures conditions simulate passage through Convection Reflow. first passes intended simulate assembly double-sided board, third pass simulate rework operation-as follows. Ramp-up rate: +3°C/second max. Temperature maintained ±25°C: seconds max. Time maximum temperature: 10-20 seconds Maximum temperature: 235+5/-0°C Ramp-down rate: -6°C/second max.
Temperature Cycling
Temperature cycling designed simulate stress that device experience temperature range -40°C 150°C 1000 cycles, rate cycles/hour.
HAST
Highly Accelerated Stress Test (HAST) design accelerate possible corrosion, delamination, possible wirebond failure, intermetallic growths. HAST performed constant temperature relative humidity duration time. Example: 110°C/85% unbiased hours.
Thermal Shock
Thermal shock test integrity device under extreme temperate gradients.
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Data Retention Bake
This test ensures that device loses data. Test performed constant temperature with specific duration, example, 150°C hours.
HTOL
High Temperature Operating Life (HTOL) sometimes refer Infant Mortality. This test used weed early life failures typically performed hours 150°C.
Latch-up
withstand accidental shorting, device pins must meet specification requirements withstand stress from
Electrostatic Discharge (ESD) test sensitivity device. kinds tests are: HBM: Human Body Model simulates event from human finger CDM: Charge Device Model simulates spark between single charged leadframe metallic ground. Component level testing consists limited above accelerated tests. feasible monitor reliability each device types that produces, device representative extend test selected based complexity wafer fabrication process package type.
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FBGA-BT Component Level Test Results
Package Qualification Data-Contingent Release
Package: Package Body Size: Product:
Fine Pitch (FBGA-BT) Am29LV160, Flash
Test Preconditioning JEDEC Level 235+5/-0 degrees Temp cycle (-40 150°C) 1000 cycles HAST (110°C/85%) unbiased Thermal Shock cycles Data Retention Bake HTOL hours Latch-up ESD-HBM ±1.1
FBGA-BT package 0/448
0/150
0/150
0/32
0/195
0/150 Pass
Pass
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Chapter
Board Level Characterization Studies
part internal characterization study ongoing product improvement program, conducted board-level testing FBGA package Flash memory. testing includes copper lead frame TSOP benchmark. late January 1999, results follows.
FBGA-BT (ASE) Test: 0/100°C Cycles completed: 7847 Sample size: Failure Cycle
TSOP 48-Pin Test: 0/100°C Cycles completed: 7847 Sample size: Failure Cycle
5800 6521 6581 7312 7512 7512 7662
5560 5708 5868
intends continue testing until failures occurs until 9,000 cycles completed, whichever occurs sooner.
Experimental Design Procedure
Board Design
test boards were designed have packages package type) each board, ensure adequate spacing between adjacent packages. Space considerations limited TSOP boards four TSOPs board. each board, half packages were oriented other half. These precautions ensure that data collected free effects location orientation. packages have daisy chained them. daisy chain circuit completed board level that each package consists single net. failure solder ball immediately captured break daisy chain. board mils thick, which replicates construction standard PCMCIA card.
Board Fabrication
Standard printed circuit board (PCB) processes were used fabrication boards.
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Materials
Most laminates PCBs industry produced using epoxy resins. choice epoxy resin made because outstanding electrical, mechanical, thermal properties. FR-4 epoxy fiberglass laminate standard high technology professional electronic assemblies, material selected this study.
Design Parameters
defined land pattern CSPs chosen order achieve good interface between solder balls pads. circular diameter mils, dipped with eutectic 63Sn/37Pb solder with thickness mils. clearance spacing) between solder mask pads mils; registration mils. solder mask allowed pads. Liquid photo imageable solder mask coated over base Copper with maximum thickness mils. nominal trace width used trace routing.
Assembly Packages
test boards were panelized during assembly. Only piece board each panel. Fixtures were used stages process, including printing. boards were taped onto fixtures using Kapton tape. clean process used this study because stand height CSPs very low, cleaning drying under package could lead contamination.
Solder Paste Screen Printing
265Lt screen printer with metal squeegee equipment used solder paste printing process. LR737 rosin, no-clean paste from Alpha Metals used study. designed stencil application surface mounting process where post reflow cleaning required. mesh size -325, which equivalent particle size less than diameter. criteria stencil performance vertical wall straightness, wall smoothness dimensional precision. Laser stencils were used, since laser cutting processes produce stencils with smooth straight vertical walls. While screen printing solder paste, stencil thickness aperture dimensions combined achieve balance between printing resolution avoidance either starved solder joints bridging. stencil designed have thickness mils aperture mils this study. During solder printing process, visual inspection smear, slump, missing, bridging performed each board. Paste height random locations measured through scanning laser microscopy (LSM) every five boards. average paste height controlled mils with deviation mils.
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Convection Reflow
Heller 1800, forced convection reflow system used assembly boards. High concentrations Oxygen using reflow) degrade components oxidation when they elevated temperatures. particular, problem combustion flux gives rise only small available process-temperature window reflow process. Using Nitrogen significantly eliminate oxidation parts extends available process-temperature window test boards fluxes. Therefore, Nitrogen used reflow process. preferred control Oxygen level below during reflow process. However, there Oxygen analyzer available contractor manufacturer site measure actual Oxygen level when processing test boards. only state this time that maximum Oxygen level 100ppm during reflow. reflow profile characteristics were follows: Ramp 110°C with rate 1.2°C/sec. Dwell between 135°C seconds. Maintain time above liquidus (183°C) seconds. Reach peak temperature 215°C. Cool down with ramp rate 1.5°C/sec.
Stress Testing
assembled boards were subjected temperature cycling. This appropriate stress test accelerate wearout failure mechanism being investigated which solder joint fatigue, primarily driven coefficient thermal expansion (CTE) mismatches. 0/100°C temperature cycling range most commonly used test condition industry board level reliability assessment CSPs accelerates correct failure mechanism. also probably going future High Density Packaging Users Group (HDPUG) standard, there consensus among North American users manufacturers this test condition. exact temperature profile used was: cycles ramp up/down soak cold temperatures
This profile again consistent with future HDPUG standard CSPs.
Test Procedure
following brief description various steps involved carrying board level temperature cycling experiment.
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Initial Resistances Harnessing
initial resistance values each nets (each package forms single net) being monitored recorded. These resistance values serve baseline. packages that open Time-Zero considered experiment. This occur manufacturing assembly defects. this study however, there were Time-Zero failures. individual boards then harnessed, that they connected event detection equipment. Harnessing essentially soldering Teflon coated ribbon wire connectors test boards.
Temperature Cycling Chamber Profiling
This done ensure uniform temperature across different boards chamber. Fluke Hydra Data Bucket used collect thermal mapping data. Measurements made three boards (top, middle, bottom). each board, measurements made three locations, i.e. sides center. These precautions ensure that boards subjected exact temperature cycling profile conditions.
Event Detection Continuous Monitoring
AnaTech LY515 (Analysis Technology) channel event detector used monitor nets real time. Event detectors detect resistance spikes over some preset resistance level. instance measured resistance value exceeding threshold resistance value shall considered OPEN. OPEN followed additional OPENS within time first OPEN shall considered FAILURE TIME FAILURE shall time which first OPEN occurred. This avoid measurement glitch noise.
Test Strategy
Data collected includes number failures, any, cycles failure their location (specific board, specific net, etc.). intended continue tests approximately failure. completion testing, failed units will analyzed microsectioning confirm validity failures.
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Chapter Miscellaneous
Shipping Container Information
date shipping container information FBGA package found site: Packages Packing.
Sockets FBGA-BT Packages
Vendor FBGA Wells Open 703-1048-07 FBGA Wells Yamaichi Open 703-1048-04 Open NP351-04878 FBGA 8x14 Balls) Wells Yamaichi Open 703-1063-01 Open NP351-06377-N SOCKET
Closed socket available. Contact socket vendor.
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FBGA Package Marking
Spaces
LOGO @97-AMD DEVICE DESIGNATION
Year Week Assembly Loc. Info
Spaces
Fab/Technology Definition
Architecture Voltage
Density Sector Org.
Technology 0.32µ m/CS39S Thin Oxide 0.32 m/CS39LS 0.23 µm/CS49S
Boot Uniform Bottom Uniform
Speed (ns)
Voltage Range Regulated Full
Temp. Range
FBGA Package Designators
Fine-pitch
Fortified
Note: These package codes marked package ordering purposes only.
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Appendix Article Reprints
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Reliability Evaluation Chip Scale Packages
RELIABILITY EVALUATION CHIP SCALE PACKAGES
Ranjit Gannamani, Viswanath Valluri, Sidharth, MeiLu Zhang Advanced Micro Devices Sunnyvale, California
ABSTRACT This paper evaluates various Chip Scale Packages (CSP's) with respect board level reliability under accelerated temperature cycling stress tests. solder joint reliability three different types (based substrate material) Fine Pitch Ball Grid Array (FBGA) packages MicroBGA package compared. results analyzed using Weibull data analysis extrapolated cumulative percentage fails. effect package board design parameters such solder ball size board thickness also presented. words: CSP, BGA, FBGA, solder joints, reliability. INTRODUCTION goal smaller portable electronic products driving development CSPs. CSPs close size much smaller than conventional packages. density Flash memory example, TSOP48 (Thin Small Outline Package) measures about 18.4mm 12mm whereas comparable (FBGA) would measure only 9mm. Often, different CSPs offer similar reliability component package level. Once they mounted boards, their `second level' `board level' reliability could however very different, based unique material construction each package type. This study undertaken evaluate board level reliability some CSPs different construction, (ii) effect package board design parameters such solder ball size board thickness. PACKAGES EVALUATED following packages were evaluated: FBGA with Polyimide (PI) tape substrate, FBGA-PI, (ii) FBGA with (Bismaleimide Triazine) substrate, FBGA-BT rigid epoxy glass laminate used conventional plastic ball grid arrays), (iii) FBGA with ceramic substrate, FBGA-Cer, (iv) MicroBGA. Each package different material structural construction. Figure Figure Table illustrate differences between various FBGAs. FBGA-PI uses thin 0.08mm tape substrate, while FBGA-BT uses relatively thick 0.36mm substrate. Both packages conform same overall package height 1.2mm, which maximum package body height specified
0.35 standoff 0.80 Pitch 0.40 Ball
JEDEC FBGA specification. Consequently, FBGA-BT uses 0.3mm solder balls while FBGA-PI uses 0.4mm solder balls. differences between physical dimensions FBGA-Cer FBGA-BT minimal.
MOLD COMPOUND
Figure Cross-section FBGA-PI
Mold Compound Bond Wire
Resin Substrate
0.25 standoff 0.80 pitch
0.30 Ball
Figure Cross-section FBGA-BT
FBGA-PI Ball size 0.4mm Solder eutectic Substrate thickness 0.08 Substrate material Polyimide thickness height (measured)0.96 when mounted boar FBGA-BT 0.3mm eutectic 0.36 resin 0.26 1.07 FBGA-Cer eutectic 0.35 Alumina 0.26 1.18
Table Differences FBGA construction basic construction these FBGA packages some extent similar that conventional ball grid arrays. MicroBGA (Figure however unique construction. uses compliant elastomer material between polyimide tape. type beam leads bonded onto
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die, `face down' exposed back side.
Interconnect Encapsulant
different boards chamber. Wherever possible, tests were continued fail greater. MODELING TECHNIQUE After temperature cycling completed, failure data fitted Weibull statistical distribution. Weibull parameters (N63.2%) (slope) were obtained test, data extrapolated cumulative failure percentage (100 PPM). test data then extrapolated field conditions projected field life PPM) calculated, order enable more intuitive comparison reliability different packages. Norris-Landzberg modified Coffin-Manson equation used calculate acceleration factor. example field conditions used this paper shown Table
Example Field Conditions Temperature Swing Cycles
Elastomer
1.00 Adhesive 0.23 PolyimideTape (50um) Pitch: 0.75 via: 0.33 nom. Ball Dia: 0.35 nom.
Solder Ball (63/37 PbSn)
Figure Cross-section MicroBGA TEST BOARDS Each FR-4 test board measured 3.5" Both 20mil 62mil boards were used this study. CSPs were assembled each board (Figure each board, half packages were oriented degrees other half, precautions were taken layout board ensure that data collected free effects location orientation. boards Solder Mask Defined pads with HASL finish. Standard best practices such no-clean solder paste, laser stencils, Nitrogen convection reflow were used assembly CSPs boards. Each contains daisy chained die. daisy chain circuit completed board such that each package consists single through joints.
Table Example field conditions RESULTS Extensive temperature cycling data different CSPs collected. test program included various experimental splits with different combinations package board types. clarity, presentation results been divided into following five sections. Comparison Different Package Types Weibull plots 8x9mm FBGA-BT, 8x9mm FBGA-PI, MicroBGA, 6x9mm FBGA-Cer shown Figure Here, FBGA-Cer contains density Flash device, while other three CSPs contain 16Mb density Flash device. This data collected 20mil (0.5mm) boards under 0/100 degC cycling. Weibull slope cycles 63.2% failure (N63.2%) shown Table Weibull plots show that FBGA-BT MicroBGA packages have significantly larger N63.2% values than FBGA-PI FBGA-Cer packages. noted that initial MicroBGA failures solder joint failures discussion follows later section. From Figure Table seen that slope distribution different various sets data hence direct comparison N63.2% fails feasible whole data. pertinent compare results cumulative percentage failure mark. Hence, number, which seems very conservative number accepted industry, chosen. Figure shows comparative life projections example field conditions defined Table termsof board level reliability, seen from Figure that FBGA-BT MicroBGA ranked much higher than other packages. Both these packages demonstrated
Figure typical test board TEMPERATURE CYCLING 100°C, minute single chamber air-to-air temperature cycling profile with minute ramps minute dwells used. This commonly used test profiles industry. event detector used monitor daisy chained test boards real time. event detector record resistance spikes greater than ohms nanoseconds. spike greater than ohms considered "open". package considered failed when first open followed additional opens within time first open. thermal cycling chamber profiled before starting test, ensure uniform temperature across
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Weibull plot various CSPs
99.99%
different bars true representation comparative reliability different CSPs board level. higher reliability FBGA-BT package attributed thick rigid substrate isolating silicon (low CTE) from solder joint board. case MicroBGA package, compliant elastomer material isolates silicon from solder joint board, contributes high reliability. comparatively lower reliability FBGA-PI fact that package construction dominated Silicon die. seen package cross section, only attach layer Copper traces substrate that separate solder ball from die. tape itself path; openings that define pads ball attachment. lower reliability FBGA-Cer packages expected since there both global local mismatch with FR-4 board. potential this package might Ceramic boards, that issue discussed this study. completion tests, failure analysis carried sample test vehicles. Figure shows microsections FBGA-PI FBGA-BT test boards. Solder joint cracks interface component side seen. This consistent with classic solder joint failure mechanism that well documented literature. Figure shows results failure analysis some initial MicroBGA failures. lifted beam lead detected. isolation compliant elastomer results beam leads absorbing most cyclic fatigue stress temperature cycling.
Ln(Ln(1/(1-F(x))))
63.2%
-2.3
FBGA-BT FBGA-PI FBGA-Cer uBGA
-4.6
-6.9
0.1% (1000) (10000) 11.5 (100000)
(100)
Ln(Cycles)
Figure Weibull plots various CSPs
Package FBGA-BT FBGA-PI FBGA-Cer MicroBGA
N63.2 (cyc) 11586 2295 1918 9240
Beta
fails
Table Weibull parameters various CSPs
Comparison packagesat cume fail 60C, cyc/day
Projected Life (yrs)
uBGA 8x9mm FBGA-BT 8x9mm FBGA-PI 6x9mm FBGA-Cer
Comparison packagesat cume fail -15C 25C, cyc/day
Projected Life (yrs
uBGA 8x9mm FBGA-BT 8x9mm FBGA-PI 6x9mm FBGA-Cer
Figure Failure analysis FBGA-PI (left) FBGA (right). Cracks component side.
Figure Field life projections lifetimes considerably higher than requirements most customer applications. 8x9mm FBGA-PI 6x9mm FBGA-Cer data translated lower field life projections. life projections "years" shown Figure-6 those specific field conditions only. estimation lifetimes would vary depending upon specific field conditions model used calculate acceleration factors between test field. However, observation made that relative size
Figure Failure analysis MicroBGA
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these experiments, FBGA-BT packages (0.3mm solder balls) were assembled test boards that were initially designed FBGA-PI package (0.4mm solder balls). test boards were designed have 0.3mm pads that matched 0.3mm openings tape (where solder balls attached) FBGA-PI package. corresponding opening solder mask FBGA-BT package 0.25mm. hence expected that test boards designed optimized FBGA-BT package could result even better FBGA-BT data than that presented here. Effect Package Body Size FBGA-PI FBGA-PI test discussed earlier section 8x9mm body size, which package 16Mb density Flash product. 6x9mm FBGA-PI, package size density device, also 0/100 degC test. this case also, 20mil test boards were used. Figure shows Weibull plots both 8x9mm 6x9mm FBGA-PI packages. relevant Weibull parameters Table field life projections Figure seen Weibull plots field life projections, larger 8x9mm package demonstrated lower lifetime than 6x9mm package. This difference attributed larger package body size larger size 16Mb device, i.e. domination Silicon more pronounced larger package higher density Flash product. Based these findings, anticipated that even larger packages higher density products (32/64Mb) would show poorer solder joint lifetimes FBGA-PI package same reasons.
Effect Package Body Size Weibull plot FBGA-PI
Comparison packagesat cume fail -15C 25C, cyc/day
Projected Life (yrs
6x9mm FBGA-PI 8x9mm FBGA-PI
Figure Field life projections material, attach compliancy, solder ball size, etc. package design variable evaluated here solder ball size. solder ball size initial FBGA-PI package 0.40mm nominal. This ball size increased 0.45mm nominal. Though ball size increased, overall height package maintained below 1.2mm. tape opening increased from 0.3mm 0.38mm. test boards 0.35mm pads. Based industry practice, this deliberately maintained little smaller than 0.38mm tape openings FBGA-PI package. Figure shows Weibull plots both 0.4mm ball 0.45mm ball FBGA-PI packages. relevant Weibull parameters Table Figure shows field life projections FBGA-PI packages with 0.40mm 0.45mm solder balls. expected, larger solder balls results improved solder joint lifetime.
99.99%
Ln(Ln(1/(1-F(x))))
63.2%
-2.3
99.99%
FBGA-PI with Larger Solder Balls
Ln(Ln(1/(1-F(x))))
-4.6
FBGA-PI
0.1% (1000) (10000)
63.2%
FBGA-PI
11.5 (100000)
-6.9
-2.3
(100)
Ln(Cycles)
FBGA-PI ball FBGA-PI 0.45 ball
-4.6
-6.9 11.5
Figure Effect package body size FBGA-PI
Package FBGA-PI FBGA-PI N63.2 (cyc) 2295 2685 Beta fails
Ln(Cycles)
Figure larger solder balls FBGA-PI
Table Weibull parameters different body sizes Larger Solder Balls FBGA-PI Design package changes improve board level reliability FBGA-PI were investigated. Design parameters that impact board level reliability substrate material, substrate thickness, mold compound
Package FBGA-PI, 0.40 ball FBGA-PI, 0.45 ball
N63.2 (cyc) 2295 2424
Beta
fails
Table Weibull Parameters solder ball size From Weibull plots seen that challenging quantify improvement larger solder
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balls. While N63.2% values relatively close, different slopes tend amplify difference between datasets, especially when projected lower PPM. example, 1000 criterion used, improvement obtained 1.8X) significantly lower than that shown Figure (2.1X). average picture whole data slopes from datasets were pooled obtain common slope 4.7, N63.2% fitted both datasets. comparing N63.2% values results improvement 1.13X with larger solder balls. From this analysis seen that even best case scenario larger solder balls, improved lifetime still lower than that FBGA-BT MicroBGA packages.
section) exists these sets FBGA-PI data well. Using technique pooling common slope recomputing N63.2% values, found that average, solder joint life thinner board exceeds that thicker board 1.34X FBGA-PI package. slope (beta) thicker board higher than that thinner board, projections value showed minimal difference (Figure 15). FBGA-BT package results preliminary tests 62mil boards still progress. Initial data shows minimal difference failures obtained have lined existing data 20mil boards (see Figure preliminary life projections Figure 15). should also noted that that 62mil boards were assembled different site. Hence, while these exact comparisons information presented still useful demonstrate that there significant difference lifetimes projected even when same packages assembled thicker boards.
FBGA-PI boards
Comparison packagesat cume fail -15C 25C, cyc/day
Projected Life (yrs
8x9mm FBGA-PI, ball 8x9mm FBGA-PI, 0.45 ball
99.99%
Ln(Ln(1/(1-F(x)))
63.2%
-2.3
Figure Field Life Projection should also noted that 0.45mm, solder ball size quite close maximum possible solder ball array with pitch 0.8mm, order retain sufficient room route traces internal solder balls. Additionally, eventual move 0.5mm pitch solder ball array (necessitated shrinking sizes improved processes, need smaller form factor packages) will make 0.45mm ball impossible. FBGA-BT package that currently uses 0.3mm solder balls would able transition 0.5mm solder ball pitch without requiring change ball size. Evaluation Test Vehicles built Boards data discussed earlier sections collected test boards that were 20mil thick. Testing (0/100 degC cycling) also carried 62mil (1.6mm) boards evaluate effect these thicker boards solder joint lifetimes. Figure shows Weibull plots 6x9mm FBGA-PI both 20mil 62mil boards. Figure shows similar plots 8x9mm FBGA-BT package. relevant Weibull parameters listed Table should noted here that FBGA-BT 62mil board data presented here preliminary. This will updated more failures collected. seen from Figure that same challenge quantifying difference outlined previous
-4.6
FBGA-PI/20 board FBGA-PI/62 board
(1000) (10000) 11.5 (100000)
-6.9
0.1%
(100)
Ln(Cycles)
Figure FBGA-PI 62mil boards
FBGA-BT boards
99.99%
Ln(Ln(1/(1-F(x))))
63.2%
-2.3
FBGA-BT/20 board FBGA-BT/62 board
-4.6
-6.9
0.1% (10000) 11.5 (100000)
(1000)
Ln(Cycles)
Figure FBGA-BT 62mil boards
Package FBGA-PI, 20mil board FBGA-PI, 62mil board FBGA-BT, 20mil board FBGA-BT, 62mil board
N63.2 (cyc) 2685 1932 11586 11757
Beta
fails
Table Weibull parameters
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Effect Board Thickness Comparison cume -15C 25C, cyc/day Projected Life (yrs) FBGA-PI, 20mil board FBGA-PI, FBGA-BT, FBGA-BT, 62mil board 20mil board 62mil board
Figure Evaluation 62mil boards Temperature Cycling degC limited amount data also collected -40/100 degC, minute cycle test condition 20mil boards. Table summary that data. 8x9mm FBGA-BT 8x9mm FBGA-PI packages were evaluated. test terminated 2507 cycles. that point, there were zero fails (0/60) FBGA-BT test vehicles extensive failures (49/60) FBGA-PI test vehicles. While field projections included here, this information again gives indication relative robustness packages.
still lower than that FBGA-BT MicroBGA packages. Feasibility using 0.45mm ball size would challenged migration 0.5mm ball pitch made. (iv) significant difference board level reliability detected both FBGA-BT FBGA-PI packages assembled thicker 62mil boards when compared those mounted 20mil boards. Limited data -40/100 degC test condition indicates relative robustness FBGA-BT over FBGA-PI with respect board level reliability, that consistent with rest 0/100 degC data discussed this paper. ACKNOWLEDGMENT authors would like acknowledge Melissa Lee, John Hunter, Bruce Schupp, James Hayward, Fontecha their guidance support, Dave Morken analysis Robert Dudero cross-sectioning samples. REFERENCES Norris Landzberg, Journal Research Dev, 266, 1969. Ano, "Reliability study chip scale package using flex substrate", Proc, pp44-47, 1997. Darveaux, Heckman, Mawer, "Effect test board design level reliability fine pitch package", Proc SMI, 105-111, 1998. C.F. Coombs Jr., "Printed Circuits Handbook", McGraw Hill, 1995.
Test Condition: degC
FBGA-BT Cycles completed Data First fail Test status 2507 fails Stopped FBGA-PI 2507 fail Stopped
Table Board Level Reliability Data -40/100 degC test condition
CONCLUSIONS packages evaluated, FBGA-BT MicroBGA demonstrated lifetimes considerably higher than FBGA-PI FBGA-Ceramic packages. These differences board level reliability explained differences package construction material sets. (ii) FBGA-PI package, larger 8x9mm package higher density 16Mb device (larger Silicon die) demonstrated lower reliability than 6x9mm package device. Based this trend, anticipated that even larger packages (for 32/64Mb) would show lower solder joint lifetimes FBGA-PI construction. (iii) larger solder balls (0.45mm 0.4mm) FBGA-PI package resulted improved solder joint fatigue life. Even best case scenario larger solder balls, improved lifetime
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FGBAs-The Choice Flash Memories
CHOICE
FBGAs
FLASH MEMORIES
2000 publication manufacturing services group
RECENTLY PLAYED pivotal role emergence FBGA (fine pitch ball grid array) chip scale package (CSP) choice flash memory devices. This time years ago, micro ball grid array (µBGA) only available downsizing from larger, traditional leaded packages used flash memories (such thin small outline plastic (TSOP) package). That changed last year when began offering FBGA design that afforded many advantages,
product applications (e.g., cellular phones, pagers, hand-held computers, etc.). this story unfolds, will persevered face established preference Intel's µBGA overwhelming acceptance FBGA preferred these applications.
PACKAGE SIZE MATTERS
applications where miniaturization priority, CSPs
When comes package technology flash memories, anything that done. have licenses, technology, ability.
Bruce Schupp, product marketing
fork package roadmap flash memories automotive, telecom, consumer
crucial stepping stone direct chip attach (DCA), which bonded directly
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Figure shows smaller size CSPs next comparable density TSOP.
end-use printed circuit board (PCB). While technology offers ultimate miniaturization, infrastructure established enough cost competitive. Moreover, viable option when been designed wirebonded interconnects (i.e., bond pads located around periphery die), case with flash memories traditional leaded packages. better suited having bond pads array across surface, enabling connections made with flip-chip technology instead conventional wirebonding. Figure shows smaller footprint next comparable density TSOP. smaller form/fit factor saves considerable board space provides lower profile which needed when trying cram more memory capacity onto ever smaller motherboards, products striving into palm your hand.
JUST WILL
acceptance already established. AMD's LV800 flash family initially offered µBGA, shipped modest quantities these early µBGA package designs included polyimide tape embedded with solid gold traces routing signals from external terminals, this costly. polyimide tape replaced with copper core tape that gold-plated copper traces ("beam leads") instead solid gold. This flash gold bondable kept oxidation from growing, copper brought costs down. into roadblock, however, when supplier unable produce copper core tape sufficient quantities. roadblock that soon proved blessing disguise. Faced with reliable, costeffective offer flash customers, turned Fijitsu, AMD's FASL business partner. Fijitsu FBGA with polyimide tape substrate that looked promising, permission adopt their package technology. Besides being cheaper than µBGA, FBGA construction appealing because package size could remain
same even size became smaller. better understand this, helps look configuration FBGA versus µBGA.
µBGA CONSTRUCTION SIZE ONLY PLEASE
µBGA package like standard package which attach die. construction that built die, package nearly same size itself. crosssection drawing Figure shows die-down configuration, interconnected gold-plated beam leads traces that route through polyimide tape array external solder balls. This package construction presented problem because size. many popular densities time, size smaller than other flash manufacturer's. While this good keeping costs down (more wafer), size small provide room size solder ball array while keeping pitch (the distance between centerlines adjacent solder balls) manageable 0.75 board assembly. Moreover, even could have initially, every time implemented shrink would face
addressing demand flash memory CSP, first looked µBGA, since market
Figure shows cross-section die-down configuration µBGA package.
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Figure shows cross-section die-up configuration FBGA package.
same size problem. Thus, with shrinks occurring regularly, µBGAs attractive solution flash memories either customers because form/fit package must change with every shrink. This becoming painfully apparent several top-tier OEMs were attempting µBGA package flash memories.
FBGA CONSTRUCTION SHRINK FRIENDLY
BUILDING INFRASTRUCTURE
FBGA construction, wirebonded substrate then overmolded with epoxy, construction very much like that standard (see Figure minimum package size winds being about times size die, slightly larger than comparable density µBGA. this size advantage wins points when comes shrinks. Because FBGA construction, what µBGA cannot: accommodate reduction size with change package dimensions. This renders shrink transparent mechanically both AMD's customers' manufacturing lines clearly, winwin situation.
package technology, critical that there supporting industry infrastructure. already knew that flash market OEMs want: smallest, most powerful flash memory they package that largest pitch; multiple supply sources; package designs that change with every shrink. sights qualifying FBGA fortifying infrastructure latter which small task market where µBGA already synonymous with CSP. With appreciable tooling reliability data available time FBGA, knew needed tackle these four prerequisites market acceptance: board level reliability; board level rework ability; socket suppliers; alternative supply sources. Board Level Reliability began testing reliability FBGA after mounted onto similar those major customers. soon
learned that substrate FBGA polyimide tape thin absorb stress incurred from different (coefficient thermal expansion) rates silicon versus (using material). When heated, expands much higher rate than silicon, package substrate manage this difference. Although polyimide substrate proved reliable enough many applications, meet long-lifetime reliability that needed commercial industrial outdoor applications, such telecommunications infrastructure automotive environments.
Tape Rigid Substrate While were testing tape FBGA, also evaluated FBGA design that organic substrate (Bismaleimide Triazine) resin. Because this material thicker closer that PCB, could better manage stress than could thinner polyimide tape. switched. results extensive tests board level reliability performance found white paper, "Reliability Evaluation Chip Scale Packages," published 1999 following AMDers: Ranjit Gannamani, Valluri, Sidharth Sidharth, MeiLu Zhang. copy this paper obtained from Engineering (x26415). µBGA, board-level reliability performance comparable that FBGA ability elastomer layer absorb stress from different rates. These reliability
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results also presented white paper referenced earlier.
Board Level Rework Ability Socket Suppliers engineers teamed familiarize boardlevel rework companies with FBGA package. They also worked with socket suppliers, those customers programming prior system assembly, arrange support AMD's FBGA package. Alternative Supply Sources Marketing contacted some competitors showed them footprints pinouts flash memory parts. After negotiating some pinout changes, their commitment support both µBGA FBGA pack-age styles same flash memo-
ries. also worked with industry-wide JEDEC JC-42.4 Committee establish AMD's version FBGA pinout official industry standard. Because this, FBGA packaged flash memories manufactured world today conform footprint. continuing work with JEDEC adoption additional FBGA footprints designed accommodate future generations very high-density, high-performance flash memories.
FRUITS LABORS
This infrastructure work took about year come fruition and, because AMD's success this effort, FBGAs most preferred package flash memories used commercial industrial applications. µBGA shipments still
outnumber FBGAs three cellular telephone OEMs using them large quantities; however, number OEMs choosing FBGAs flash exceeds those preferring µBGA. With able produce flash memory roadmaps knowing what package footprint will look like years future, whether burst mode, page mode, random access types flash memory, even OEMs committed µBGA wanting FBGAs future designs. Thanks following AMDers their valuable contributions this article instrumental roles they played bringing industry around embracing FBGA: Bruce Schupp, Melissa Lee, Ranjit Gannamani, Valluri, Sidharth Sidharth.
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Memo J-T, Case Level Thermal Parameter
Engineering
Memo Case Level Thermal Parameter Introduction thermal parameter been developed EIA/JEDEC JC15.1 subcommittee thermal phenomenon electronic packaging. parameter called J-T, (psi j-t) modification replacement much abused junction-to-case thermal resistance, value plastic packages. This memo outlines history physical description measurements, shows they poor performance indicators plastic packages. parameter introduced explained. History measurement that used describe internal thermal resistance packaged semiconductor device. Originally, measurement developed method calculating junction temperature from known reference point outside package. natural place this reference point defined "the shortest thermal path from junction outside package," which also best heat sinking surface. days when specification generated, mainstream package ceramic DIP, which military, were mounted onto 'cold rails'; flat liquid cooled tubes that contacted bottoms DIPS application. These cold rails were held constant temperature served reference point calculating test method performed bringing desired package surface thermal equilibrium, isothermal case condition some defined temperature, using large cold plate heat sink. idea keep external package temperature constant while device powered Heating voltage current supplied device power while keeping package surface initial defined temperature. When device comes steady-state temperature power conditions, junction temperature measured junction case thermal resistance calculated using equation (1). TJ-TR/PD where: junction temperature reference temperature (case) Power dissipation Heat Flow Microelectronic Packaging Heat flow hermetic package well defined illustrated figure diagram seen that attached ceramic substrate inside cavity. When package assembled, cavity left intact, that only some other comes contact with surfaces bonded cavity. Since thermal conductivity ceramic
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quite high when compared other gasses, most heat generated (~90%) from circuitry surface conducted through silicon into ceramic substrate. heat travels through ceramic dissipated into into heat sink. Some spreading occurs ceramic approximate angle), analysis almost purely one-dimensional. This approach works well type hermetic package including PGAs, CQFPs, CBGAs, other ceramic packages.
Heat Flow
surface
Figure Heat Flow Hermetic Package When plastic packages gained popularity, much thermal analysis left intact, such (junction-to-air thermal resistance) parameter, assumed, incorrectly, that junction-to-case value could used plastic packages predict junction temperature same used hermetic packages. problem with plastic packages fundamental, easily seen physical construction plastic packages negates this simple parameter. Figure shows typical construction heat flow plastic quad flat pack (PQFP). Heat flow paths represented resistor network analogy diagram. seen from figure, heat flow plastic package very complex when compared hermetic package. plastic packages, usually mounted onto copper alloy pad, wire bonded lead fingers which radially orthogonally emanate from area, finally encapsulated plastic moulding compound. Because contacted sides solid matter, heat flow easily multitude directions. copper alloy's high thermal conductivity, heat immediately spreads into attach paddle, subsequently into lead frame. Some heat also flows into moulding compound released convection from package external surfaces. this complex heat flow that defined plastic packages. Problematic Plastic First, shortest thermal path difficult determine. package thin, paddle close exterior package, this shortest path. other hand, lead fingers close paddle, most direct path through lead frame into printed circuit board(PCB). latter these possible paths
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more likely, case, external environment plays crucial role thermal performance plastic surface mount devices. example, relatively thermal conductivity, e.g. internal planes minimized metal traces surface, then shortest path well through bottom package. But, internal voltage heat spreading planes, leads dominate heat flow. Secondly, these surfaces made isothermal satisfy original intent ceramic based measurements? believed that using well stirred fluid bath with fluorinert liquid would force surfaces plastic package isothermal state. nature stirred fluids, measurement breaks down moving fluid measurement package surfaces isothermal. Recently methods have been developed impingement create high heat transfer coefficients package surfaces, very nearly creating isothermal specification. Although these methods useful creating specific boundary conditions conduction models, measurement still useful predicting junction temperature from known package temperature.
Figure Heat Flow Plastic Packages Customer Through years, real identity diluted, today most system houses predict temperature placing thermocouple package surface using manufacturer's published values compute junction temperature. This fallacy wholly inaccurate. Today, common practice accepted correct. hermetic packages, correct method install heat sink surface identified isothermal reference plane, then thermocouple imbedded heat sink touching case properly calculate junction temperature using plastic packages, there equivalent method.
Enter During discussions with industry leading suppliers, became obvious that practices described above were regularly without question. Users semiconductors grown accustomed placing thermocouple calculating junction temperature without really understanding implications their actions. counter this trend
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provide more meaningful method predict junction temperature plastic packaged devices, parameter created. excerpt from EIA/JESD51-2 standard follows describing method J-T.
THERMAL CHARACTERIZATION PARAMETER JUNCTION-TO-TOP PACKAGE thermal characterization parameter, proportional temperature difference between center package junction temperature. Hence, useful value engineer verifying device temperatures actual environment. measuring package temperature device, junction temperature estimated thermal characterization parameter been measured under similar conditions. should confused with which thermal resistance from device junction external surface package case nearest attachment case held constant temperature. reporting case temperature during junction ambient thermal resistance test optional. measurement made using temperature transducer such thermocouple, fluoroptic sensor, infrared sensor. THERMOCOUPLE PLACEMENT LOCATION thermocouple bead shall attached package geometric center surface. position must reported, cases, along with measurement data. PACKAGE THERMOCOUPLE APPLICATION CAUTION: Usefulness this measurement dependent procedure. Application thermocouple critical ensure proper thermal contact package ensure that measurement disturbed. Determination package surface temperature, conductance package body, requires that following factors considered: 4.2.1 thermocouple wire bead shall touch surface package. 4.2.2 Best practice attaching wire thermocouple bead minimal amount thermally conducting epoxy. distance across epoxy bead shall exceed (2.54 direction. 4.2.3 thermocouple wire shall routed next package body down board along board. This reduces cooling thermocouple junction heat flowing along wire. 4.2.4 Thermocouple wire size shall small such that heat loss along wire does cause anomalous readings. Recommended maximum thermocouple sizes gauge. type thermocouples, gauge preferred.
PROCEDURE junction temperature package temperatures determined steady-state condition measurement specified above. junction-to-top center package thermal characterization parameter, calculated using following equation:
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(TJss TTss)/PH
where thermal characterization parameter from device junction center package surface( °C/W) TJss junction temperature steady-state. TTss package (top surface) temperature, steady-state, measured thermocouple, infrared sensor, fluoroptic sensor. relationship between junction-to-ambient thermal resistance, junction-to-top center package thermal characterization parameter, described equation
where thermal characterization parameter from surface package-to-air °C/W) package-to-air thermal characterization parameter, based steady-state ambient temperature shown here: (TTss TAss)/PH
thermal characterization parameters, have units °C/W mathematical constructs rather than thermal resistances because heating power flows through exposed case surface. necessary report because determined from relationship between Also, very dependent application-specific environment.
Conclusion This memo attempted educate inform package, process, product engineers correct temperature measurements external surface package determine junction temperature. educate customers, system level thermal analysis will more accurate, allowing larger application range products, especially critical situations. Because measurement relatively new, process generating values surface mount plastic packages. value needed particular product, please contact Package Characterization Group Engineering. References
"Methodology Thermal Measurement Component Packages (Single Semiconductor Device), EIA/ JESD51 Standard, Electronic Industries Association, 1995 "Integrated Circuit Thermal Measurement Method Electrical Test Method (Single Semiconductor Device), EIA/JESD 51-1 Standard, Electronic Industries Association, 1995 "Integrated Circuit Thermal Test Method Environmenatl Conditions Natural Convection (Still Air), EIA/JESD 51-2 Standard, Electronic Industries Association, 1995 "Low Effective Thermal Conductivity Test Board Leaded Surface Mount Packages," EIA/JESD 51-3 Standard, Electronic Industries Association, 1996 "Thermal Test Chip Guideline (Wire Bond Type Chip)," EIA/JESD 51-4 Standard, Electronic Industries Association, 1996 Extension Thermal Test Board Standards Packages with Direct Attach Mechanisims" EIA/JESD 51-5, Electronic Industries Association, 1999
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Integrated Circuit Thermal Test Method Environmental Conditions Forced Convection (Moving Air), EIA/JESD 51-6, Electronic Industries Association, 1999 Effective Thermal Conductivity Test Board Leaded Surface Mount Packages" EIA/JESD 51-7, Electronic Industries Association, 1999 "Accepted Practices Making Microelectronic Device Thermal Characteristics Tests User's Guide," JEDEC Engineering Bulletin Electronic Industries Association, Washington, "Thermal Characteristics," Method 1012.1, MIL-STD-883C Test Methods Procedures Microelectronics, Department Defense, Washington, "Unencapsulated Thermal Test Chip," SEMI G32-86 Guideline, 1989 Book SEMI Standards, Vol. Packaging Division, SEMI, Inc. Mountain View, "Junction-to-Case Thermal Resistance Measurements Molded-Plastic Packages," SEMI G43-87 Test Method, 1989 Book SEMI Standards, Vol. Packaging Division, SEMI, Inc. Mountain View, "Thermal Test Board Standardization Measuring Junction-to-Ambient Thermal Resistance Semiconductor Packages," SEMI G42-88 Specification, 1989 Book SEMI Standards, Vol. Packaging Division, SEMI, Inc. Mountain View, Junction-to-Case Thermal Resistance Measurements Ceramic Packages," SEMI G30-88 Test Method, 1989 Book SEMI Standards, Vol. Packaging Division, SEMI, Inc. Mountain View, "Thermal Transient Testing Attachment Evaluation Integrated Circuits," SEMI G46-88 Test Method, 1989 Book SEMI Standards, Vol. Packaging Division, SEMI, Inc. Mountain View, "Still-and Forced-Air Junction-to-Ambient Thermal Resistance Measurements Integrated Circuit Packages," SEMI G38-87 Test Method, 1989 Book SEMI Standards, Vol. Packaging Division, SEMI, Inc. Mountain View,
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Appendix Application Note
following information excerpted from published Application Note, number 22142.
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Daisy Chain Samples
Application Note
Daisy Chain samples non-functional parts with pattern inter-connected balls. These samples typically assembled onto printed circuit board (PCB)
with matching patterns. Once assembled matching PCB, balls connected creating continuous network. Refer Figure
Notes: Solid traces Daisy Chain patterns FBGA package. Dash traces Daisy Chain patterns PCB. `a', input output network device. `c', input output separate network support balls.
Figure
FBGA Silicon Daisy Chain with Matching Schematic (Top View)
Daisy Chain samples primarily requested OEMs perform assembly evaluations. Prior production, will generally solder daisy chain samples daisy chain perform Open/Short testing check misalignments. This test will help characterize assembly process equipment prior full production.
Daisy Chains also used Second Level SolderJoint Board Reliability studies. daisy chain samples assembled onto matching subjected temperature cycling oven. Board Level Reliability tests tools help predict measure expected life packages. more depth information Second Level Solder-Joint Board Reliability,
Publication# 22142 Rev: Amendment/+2 Issue Date: April 2002
FBGA User's Guide please refer "Reliability Evaluation Chip Scale Packages" Ranjit Gannamani, Viswanath Valluri, Sidharth, MeiLu Zhang. Currently three types FBGA daisy chains: Stitched Daisy Chains, Metal Mask Daisy Chains Substrate Daisy Chains. Since main purpose characterize assembly process equipment, OEMs typically have preference type daisy chain used. bonding. There wire bonds from dummy silicon slug substrate.
Metal Mask Daisy Chains
functional substrate used with special daisy chained wafer. There active circuitry wafer, only simulated bond-pads. Adjacent bond-pads shorted metal mask. Daisy chain patterns produced wire bonding bond-fingers substrate bond-pads wafer.
DESCRIPTIONS Stitched Daisy Chains
functional substrate used with dummy silicon slug. Daisy chain patterns produced shorting pairs adjacent bond-fingers substrate wire
Substrate Daisy Chains
dummy silicon slug used with special daisy chained substrate. Shorting adjacent balls substrate produces daisy chain patterns.
FINE PITCH-BGA (WC) DAISY CHAIN SCHEMATIC
Package Connection (Bottom View)
Board Connection (Top View)
Note: input output network.
48-BALL FINE PITCH-BGA DAISY CHAIN SCHEMATIC
Package Connection (Bottom View) Board Connection (Top View)
Note: input output network.
B-87
FBGA User's Guide
63-BALL FINE PITCH-BGA DAISY CHAIN SCHEMATIC
Package Connection (Bottom View)
Board Connection (Top View)
Note: input output network. input output separate network support balls.
64-BALL FORTIFIED-BGA DAISY CHAIN SCHEMATIC
Package Connection (Top View)
Board Connection (Top View)
Note: input output network.
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80-BALL FORTIFIED-BGA DAISY CHAIN SCHEMATIC
Package Connection (Top View)
Note: input output network.
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ORDERING INFORMATION
standard products available several packages operating ranges. order number (Valid Combination) formed combination following: Am29LV160D
SUBSTRATE TYPE internal/intermediate layers shorted substrate Bottom layer shorted substrate Wirebond DAISY CHAIN CONNECTION Daisy chain connection (metal mask) Daisy chain connection substrate SOLDER MASK OPENING GROUND PLANE ground plane 0.25 solder mask opening 0.27 solder mask opening 0.50 solder mask opening 0.55 solder mask opening DAISY CHAIN PACKAGE TYPES 80-ball Fortified Ball Grid Array (FBGA) 1.00 pitch, package 64-ball Fortified Ball Grid Array (FBGA) 1.00 pitch, package 48-ball Fine Pitch Ball Grid Array (FBGA) 0.80 pitch, package 63-ball Fine Pitch Ball Grid Array (FBGA) 0.80 pitch, package 48-ball Fine Pitch Ball Grid Array (FBGA) 0.80 pitch, package DEVICE NUMBER/DESCRIPTION
Valid Combinations Daisy Chain Density Package Fine Pitch (WC) Fortified (PB) FBGA (WM) Fine Pitch (WH) Fortified (PC) Order Number AM29LV160DWCD22B AM29BDD160GPBD62B AM29DL323DWMD22B AM29DL640DWHD22B AM29LV640DPCD62B Package Marking LV160DD22B BDAFGD62B DL323DD22B DL640DD22B LCEDD62B
place order, please contact your local sales representative. current list contacts Internet
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Revision Summary
Revision (Version 2.2): March 1999
Chapter Modified daisy chain board layout drawings. pinout drawings show outrigger balls that shorted.
Revision (Version 2.3): 1999
Construction FBGA-BT figure Revised following callouts: Mold Compound (deleted "Multi-Functional"), Attach (deleted "Non-conductive"), Solder Mask (deleted "50µ Nom"), Copper Foil (deleted "12µ"), Plating (deleted thickness from Au). FBGA Package Materials Descriptions table, renamed following parameters: Rigid Substrate; Molding Compound; Attach Material. Deleted "Interposer" from Copper Metallization. FBGA Ball Attach Detail Clarified type attach. Component Level Testing, FBGA-BT Changed JC-14.1-98-135, Level qualifications planned 1999 JCB-98-104. table, added rows through item changed ramp-up rate 3°C, time max. temperature 10-20 seconds. FBGA-BT Component Level Test Results Replaced reformatted data table. Test Strategy Deleted reference data supplied weekly. FBGA Package Marking Added technology designator. Revised explanatory table. FBGA Package Dimensions Renamed designators respectively.
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Revision (Version 2.3.1): July 1999
Chapter Daisy Chain Board Layout figures. Added 99xx date code daisy chain schematic board layout. Added 98xx date code previous drawings.
Revision (Version 3.0): January 2001
Chapter Replaced FGBA pinout figures with illustrations. Chapter Updated package outline diagrams with specification 16-038-9 illustrations. Replaced Table FBGA-BT with information. Section "FBGA Thermal Resistance Data" replaced with section "FBGA Thermal Management". Chapter Added information "General Design Considerations" section. Replaced "Routing Dimensions" section with "Routing Recommendation" section. Added "gold thickness mils recommended" Board Surface Finish" subsection. Updated "Recommended Design Values" table below Figure 4-2. Replaced "Routing Dimensions" "Routing 32-Megabit" figure with "Example Routing" figures. Chapter Replaced entire chapter with information. Appendix article reprints. Appendix application note.
Revision (Version 3.1): March 2001
Chapter 2-Daisy Chains Added "Both listed Appendices." second paragraph.
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Chapter 3-FBGA Thermal Management Added "TASS Temperature Ambient Steady State" Junction Air" equations Table 3-2. Thermal Resistance Data: Changed table headings (°C/W)" "JMA (°C/W)" "JMA (°C/W)" "J-T (°C/W). Shifted down values (°C/W) table column. Moved data FGC048 (°C/W) table cell FGC048 (°C/W) location. Added following table notes: Theta junction moving air." (LFPM) Speed moving air, terms "Linear Feet Minute"." Corrected FBD063 (°C/W) data.
Revision (Version 4.0): January 2002
Chapters Chapters were completely rewritten. recommended that users previous editions read through these chapters familiarize themselves with revised content. Chapter daisy chain schematics board layouts have been added. first figures from previous User's Guide have been deleted.
Revision (Version 4.1): April 2002
Chapter Figure 2-3: Added Am29PDS322D list devices package. Figure 2-7: corrected Chapter Corrected figure from ball; figure from ball, figure 5-10 from ball. Chapter Table 6.1: Corrected units measure thickness column from Deleted E-05 from specifications ppm/c column. Added descriptions FLA069, FLB073, LAA064, LAA080, 080, LBA176 Chapter Recommended Board Desin Dimensions: Modified table show both 0.30 0.60 balls.
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Chapter FBGA Package Designators: Added sizes. Appendix Updated information from October 2001 revision application note.
Revision (Version 4.2): November 2002
Chapter Modified table include values 0.35 solder balls. Changed tolerances dimension 0.30 0.60 solder balls. Changed dimension 0.30 solder balls.
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Printed 11/01/02 22142J
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