User's Manual Order #22004B 2001 Advanced Micro Devices, Inc
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Microcontroller
User's Manual
Order #22004B
2001 Advanced Micro Devices, Inc. rights reserved.
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Microcontroller User's Manual
Microcontroller User's Manual
TABLE CONTENTS
PREFACE
INTRODUCTION XXIII Microcontroller. xxiii Purpose this Manual xxiii Intended Audience xxiii Overview this Manual xxiii Related Documents xxiv Documentation xxiv Additional Information Documentation Conventions ARCHITECTURAL OVERVIEW Microcontroller 1.1.1 Distinctive Characteristics Block Diagram Architectural Overview 1.3.1 Industry-Standard Architecture. 1.3.2 AMDebugTechnology Advanced Debugging 1.3.3 Industry-Standard Interface 1.3.4 High-Performance SDRAM Controller 1.3.5 ROM/Flash Controller 1.3.6 Flexible Address-Mapping 1.3.7 General-Purpose (GP) Interface 1.3.8 Clock Generation. 1.3.9 Integrated Peripherals 1.3.10 JTAG Boundary Scan Test Interface 1.3.11 System Testing Debugging Features Applications 1.4.1 Smart Residential Gateway 1.4.2 Thin Client 1.4.3 Digital 1.4.4 Telephone Line Concentrator INFORMATION Overview. Logic Symbols Signal Descriptions. SYSTEM INITIALIZATION Overview. 3.1.1 Native Embedded Initialization Sequence 3.1.2 BIOS Initialization Sequence 3.1.3 Memory-Mapped Configuration Region (MMCR) 3.1.4 Reset Event 3.1.5 Reset Vector Reset Segment Configuring SDRAM Controller Identifying Core Setting Speed Configuring External Devices Configuring Multiplexing Configuring Programmable Address Region (PAR) Registers 3.7.1 Specifying Pages Regions
CHAPTER
CHAPTER
CHAPTER
Microcontroller User's Manual
Table Contents Address Region Attributes. 3-12 3.7.2.1 Write-Protect Attribute 3-12 3.7.2.2 Cacheability Control Attribute 3-12 3.7.2.3 Code Execution Attribute 3-12 3.7.2.4 Performance Considerations 3-12 3.7.3 Register Priority 3-13 3.7.4 External Devices 3-13 3.7.4.1 Single Device Converter) Using Chip Select. 3-14 3.7.4.2 Single Device That Performs Decode 3-14 3.7.4.3 Multiple Devices Chip Select 3-14 3.7.5 Devices 3-15 3.7.5.1 Controller 3-15 3.7.5.2 Network Adapter Remote Program Loading 3-16 3.7.6 External Devices 3-17 3.7.6.1 Boot Device Mapping BIOS Shadowing 3-17 3.7.6.2 Banks Flash Execute-In-Place (XIP) Operating System 3-17 3.7.7 SDRAM Regions 3-18 3.7.7.1 Setting Buffers 3-18 3.7.7.2 Write-Protected Code Segments 3-18 Configuring Interrupt Mapping 3-19 3.8.1 Edge-Sensitive Level-Triggered Interrupts 3-19 3.8.2 Interrupt Mapping 3-19 3.8.3 Interrupt Polarity 3-20 Configuring Programmable Pins. 3-20 3.10 Configuring Host Bridge Arbitration 3-20 3.11 Disabling Internal Peripherals. 3-21 CHAPTER SYSTEM ADDRESS MAPPING Overview. Registers Operation 4.3.1 Programming External Memory, Buses, Chip Selects 4.3.2 Programmable Address Region (PAR) Registers 4.3.3 Memory Space 4.3.3.1 SDRAM Space. 4.3.3.2 ROM/Flash Space 4.3.3.3 Memory Space 4.3.3.4 Memory Space 4.3.3.5 Memory-Mapped Configuration Region (MMCR) Registers Space. 4.3.4 Space 4-11 4.3.4.1 Configuration Base Address (CBAR) Register 4-11 4.3.4.2 Configuration Space 4-12 4.3.4.3 Space 4-12 4.3.4.4 PC/AT-Compatible Peripherals Region. 4-13 4.3.4.5 Region 4-15 4.3.5 Configuration Information 4-15 4.3.5.1 Configuring ROM/Flash Space 4-15 4.3.5.2 Configuring SDRAM Address Space 4-15 4.3.5.3 Configuring Peripheral Space. 4-16 4.3.5.4 Configuring Microcontroller Windows® Compatibility 4-17 4.3.5.5 Configuring Devices. 4-18 4.3.6 Interrupts 4-18 4.3.7 Software Considerations 4-18 Initialization. 4-21 Microcontroller User's Manual 3.7.2
Table Contents CHAPTER CLOCK GENERATION CONTROL Overview. Block Diagram System Design 5.3.1 Clock Loading 5.3.2 Selecting Crystal 5.3.2.1 Running Microcontroller 33.333 5.3.3 Bypassing Internal Oscillators Registers Operation 5.5.1 Internal Clocks 5.5.1.1 5.5.1.2 5.5.1.3 SDRAM Controller 5.5.1.4 ROM/Flash Interface 5.5.1.5 Bus. 5.5.1.6 GP-DMA Controller 5.5.1.7 Programmable Interval Timer. 5.5.1.8 General-Purpose Timers 5.5.1.9 Software Timer. 5.5.1.10 Watchdog Timer. 5.5.1.11 Real-Time Clock 5.5.1.12 UART Serial Ports 5.5.1.13 Synchronous Serial Interface. 5.5.2 Using CLKTIMER[CLKTEST] Initialization. RESET GENERATION Overview. Block Diagram System Design Registers Operation 6.5.1 System Reset 6.5.2 System Reset with SDRAM Retention 6.5.3 Soft Reset 6.5.4 Reset 6.5.5 Reset 6.5.6 Reset 6.5.7 Determining Reset Sources 6.5.8 Gate Support 6.5.9 Clocking Considerations 6.5.10 Software Considerations 6.5.11 Latency Initialization.
CHAPTER
Microcontroller User's Manual
Table Contents CHAPTER Am5X86® Overview. Block Diagram Registers Operation 7.4.1 Floating Point Unit (FPU) 7.4.2 Cache Memory Management 7.4.3 Clocking Considerations 7.4.4 Interrupts 7.4.5 Latency Initialization. 7.5.1 Hard Reset 7.5.2 Soft Reset SYSTEM ARBITRATION Overview. Block Diagram Registers Operation 8.4.1 Operating Modes 8.4.1.1 Nonconcurrent Arbitration Mode 8.4.1.2 Concurrent Arbitration Mode 8.4.2 Arbiter 8.4.2.1 Arbitration Protocol 8.4.2.2 Cache Snooping 8.4.2.3 Accessing Host Bridge Target. 8.4.2.4 Arbitration 8.4.2.5 Arbitration During Clock Speed Changes 8.4.3 Arbiter 8.4.3.1 Arbitration Protocol 8.4.3.2 Parking 8-10 8.4.3.3 Rearbitration 8-10 8.4.4 Cycles 8-11 8.4.4.1 Arbitration. 8-11 8.4.4.2 Cache Write-Back 8-12 8.4.4.3 CPU-to-PCI Cycle 8-14 8.4.4.4 Arbitration 8-15 8.4.4.5 Arbitration Parking 8-16 8.4.4.6 Nonconcurrent Mode Arbitration 8-18 8.4.5 Interrupts 8-19 8.4.6 Software Considerations 8-19 8.4.7 Latency 8-20 8.4.7.1 Simple Rotating Priority Latency 8-20 8.4.7.2 High-Priority Queue Latency 8-21 8.4.7.3 Low-Priority Queue Latency. 8-21 8.4.7.4 Latency 8-21 8.4.7.5 Nonconcurrent Arbitration Mode Latency 8-21 8.4.7.6 Concurrent Arbitration Mode Latency 8-22 8.4.7.7 Concurrent Arbitration Mode Parking Latency 8-22 Initialization. 8-22 HOST BRIDGE Overview. Block Diagram System Design 9.3.1 Clocking 9.3.1.1 Running Microcontroller 33.333
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Microcontroller User's Manual
Table Contents Registers Operation 9.5.1 Unsupported Functions 9.5.1.1 Unsupported Configuration Registers 9.5.2 Configuration Information 9.5.2.1 Generating Configuration Cycles 9-10 9.5.3 Microcontroller's Host Bridge Master 9-11 9.5.3.1 Write Posting 9-11 9.5.3.2 Read Cycles. 9-12 9.5.3.3 Delayed Transaction Support 9-12 9.5.3.4 Host Bridge Master Cycles 9-12 9.5.4 Microcontroller's Host Bridge Target 9-18 9.5.4.1 Host Bridge Target Address Space. 9-18 9.5.4.2 Command Support 9-19 9.5.4.3 DEVSEL Timing 9-19 9.5.4.4 Delayed Transaction Support 9-19 9.5.4.5 Address FIFO. 9-20 9.5.4.6 Host Bridge FIFOs Prefetching 9-20 9.5.4.7 Burst Ordering 9-21 9.5.4.8 Maintaining Data Coherency 9-21 9.5.4.9 Host Bridge Target Cycles 9-22 9.5.5 Interrupts 9-27 9.5.6 Latency 9-28 9.5.6.1 Master Latency 9-28 9.5.6.2 Target Latency 9-28 Initialization. 9-29 CHAPTER SDRAM CONTROLLER 10-1 10.1 Overview. 10-1 10.2 Block Diagram 10-1 10.3 System Design 10-1 10.3.1 SDRAM Pins 10-5 10.3.2 SDRAM Clocking 10-6 10.3.3 SDRAM Loading 10-8 10.4 Registers 10-10 10.5 Operation 10-11 10.5.1 SDRAM Support 10-11 10.5.2 SDRAM Addressing 10-12 10.5.2.1 Supported SDRAM Devices. 10-13 10.5.2.2 Page Size. 10-16 10.5.3 Error Correction Code (ECC) 10-16 10.5.4 Buffering 10-17 10.5.5 SDRAM Control Configuration 10-18 10.5.5.1 Refresh Control 10-18 10.5.5.2 Drive-Strength Selection 10-19 10.5.5.3 Write Buffer Test Mode 10-19 10.5.5.4 Operation Mode Select 10-20 10.5.6 SDRAM Timing Configuration 10-20 10.5.6.1 Latency (CL) 10-20 10.5.6.2 Precharge (TRP) 10-21 10.5.6.3 RAS-to-CAS Delay (TRCD) 10-21 10.5.6.4 RAS-to-RAS Auto-Refresh-to-RAS (TRC) 10-21 10.5.6.5 Minimum (TRAS). 10-22 10.5.7 Cycles 10-22 10.5.7.1 SDRAM Burst Read Cycle 10-22 10.5.7.2 SDRAM Write Cycle. 10-23 10.5.7.3 SDRAM Cycles 10-24 10.5.7.4 SDRAM Auto Refresh Cycle 10-26 Microcontroller User's Manual
Table Contents 10.5.7.5 SDRAM Mode Register Access Cycles 10-27 10.5.8 Interrupts 10-27 10.5.9 Software Considerations 10-28 10.5.9.1 Errors. 10-28 10.5.9.2 Buffer Disabling During SDRAM Configuration 10-28 10.5.9.3 Write Protection 10-28 10.5.10 Latency 10-28 10.6 Initialization. 10-29 10.6.1 Programmable Reset 10-29 10.6.2 SDRAM Device Initialization 10-30 10.6.2.1 Operation Mode Select 10-30 10.6.2.2 Command 10-31 10.6.2.3 Precharge Command. 10-31 10.6.2.4 Auto Refresh Command 10-31 10.6.2.5 Mode Register Programming 10-31 10.6.3 Boot Process 10-32 10.6.4 SDRAM Sizing Algorithm 10-32 10.6.4.1 Determining Number Columns External Bank 10-33 10.6.4.2 Determining Number Internal Banks 10-34 10.6.4.3 Determining True External Bank Ending Address 10-35 CHAPTER WRITE BUFFER READ BUFFER 11-1 11.1 Overview. 11-1 11.2 Block Diagram 11-2 11.3 System Design 11-3 11.4 Registers 11-4 11.5 Operation 11-4 11.5.1 Write Buffer 11-5 11.5.1.1 Write Buffer Disabled 11-5 11.5.1.2 Write Buffer Enabled 11-5 11.5.1.3 Write Buffer Watermark 11-9 11.5.2 Read Buffer Read-Ahead Feature 11-10 11.5.2.1 Read-Ahead Feature Disabled. 11-10 11.5.2.2 Read-Ahead Feature Enabled 11-10 11.5.3 Considerations 11-11 11.5.4 Considerations 11-12 11.5.4.1 Write Cycles. 11-12 11.5.4.2 Read Cycles. 11-12 11.5.5 Software Considerations 11-13 11.5.6 SDRAM Bandwidth Improvements 11-13 11.6 Initialization. 11-15 CHAPTER ROM/FLASH CONTROLLER 12-1 12.1 Overview. 12-1 12.2 Block Diagram 12-2 12.3 System Design 12-2 12.3.1 Voltage Isolation 12-3 12.4 Registers 12-5 12.5 Operation 12-5 12.5.1 Support 12-5 12.5.1.1 Supported Device Types 12-6 12.5.2 Control Timing Configuration 12-7 12.5.2.1 Location 12-7 12.5.2.2 Width 12-7 12.5.2.3 Operating Mode 12-7 12.5.2.4 Access Timing 12-8
Microcontroller User's Manual
Table Contents 12.5.3 Cycles 12-9 12.5.3.1 Single Read Access 12-9 12.5.3.2 Page-Mode Read Access 12-10 12.5.3.3 Cache-Line Fill 12-11 12.5.3.4 Writing Flash Devices 12-11 12.5.4 Software Considerations 12-12 12.5.4.1 Address Decoding 12-12 12.5.4.2 Programming Flash Memory 12-12 12.5.5 Latency 12-13 12.6 Initialization. 12-14 CHAPTER GENERAL-PURPOSE CONTROLLER 13-1 13.1 Overview. 13-1 13.2 Block Diagram 13-1 13.3 System Design 13-1 13.3.1 Loading 13-4 13.3.2 Voltage Translation 13-4 13.4 Registers 13-5 13.5 Operation 13-6 13.5.1 Programmable Interface Timing 13-7 13.5.1.1 Timing Requirements. 13-7 13.5.1.2 Using GPRDY with Programmable Timing. 13-8 13.5.1.3 Using Echo Mode with Programmable Timing 13-8 13.5.2 I/O-Mapped Memory-Mapped Device Support 13-9 13.5.3 Chip Select Qualification 13-9 13.5.4 Data Sizing Unaligned Accesses 13-9 13.5.5 Sharing Address Data with ROM/Flash Controller 13-10 13.5.6 Echo Mode 13-10 13.5.7 Interface 13-11 13.5.8 Usage Scenarios 13-11 13.5.8.1 Compatibility with Common Devices 13-11 13.5.8.2 Interfacing with Super Controller 13-13 13.5.8.3 Interfacing with Enhanced Serial Communications Controller MHz) 13-14 13.5.9 Cycles 13-16 13.5.9.1 8-Bit Data Access 8-Bit Device 13-16 13.5.9.2 16-Bit Data Access 16-Bit Device 13-17 13.5.9.3 16-Bit Data Access 8-Bit Device 13-17 13.5.9.4 32-Bit Data Access 8-Bit Device 13-18 13.5.9.5 32-Bit Data Access 16-Bit Device 13-18 13.5.9.6 8-Bit Data Access 16-Bit Device 13-19 13.5.9.7 GPIOCS16 GPMEMCS16 Timing. 13-19 13.5.9.8 Wait States. 13-20 13.5.10 Interrupts 13-21 13.5.11 Latency 13-21 13.5.11.1 8/16-Bit Width 13-21 13.5.11.2 Slow Cycles 13-21 13.5.11.3 Noncacheable Bus. 13-21 13.6 Initialization. 13-22
Microcontroller User's Manual
Table Contents CHAPTER CONTROLLER 14-1 14.1 Overview. 14-1 14.2 Block Diagram 14-1 14.3 System Design 14-3 14.4 Registers 14-4 14.4.1 Memory-Mapped Registers 14-4 14.4.2 Direct-Mapped Registers 14-6 14.5 Operation 14-8 14.5.1 GP-DMA Transfers 14-8 14.5.1.1 GP-DMA Initiators 14-9 14.5.1.2 GP-DMA Channel Mapping 14-10 14.5.2 Operating Modes 14-10 14.5.2.1 Normal GP-DMA Mode 14-10 14.5.2.2 Enhanced GP-DMA Mode 14-11 14.5.3 Addressing GP-DMA Channels 14-11 14.5.3.1 Addressing Normal GP-DMA Mode 14-11 14.5.3.2 Addressing Enhanced GP-DMA Mode 14-12 14.5.4 GP-DMA Transfer Modes 14-12 14.5.4.1 Single Transfer Mode 14-12 14.5.4.2 Demand Transfer Mode 14-12 14.5.4.3 Block Transfer Mode 14-13 14.5.4.4 Transfer Types 14-13 14.5.4.5 Automatic Initialization Control. 14-14 14.5.4.6 Priority 14-15 14.5.4.7 Buffer Chaining 14-15 14.5.5 Cycles 14-16 14.5.5.1 SDRAM. 14-16 14.5.5.2 GP-DMA Read with Cache Hit. 14-17 14.5.6 Echo Mode 14-17 14.5.7 Clocking Considerations 14-18 14.5.8 Interrupts 14-18 14.5.9 Software Considerations 14-18 14.5.10 Latency 14-18 14.5.10.1 Nonpreemptive Latency 14-18 14.5.10.2 Preemptive Latency 14-19 14.6 Initialization. 14-19 14.6.1 Example Configurations 14-19 14.6.1.1 Configuring 8-Bit Channel Normal GP-DMA Mode 14-19 14.6.1.2 Configuring 16-Bit Channel Normal GP-DMA Mode 14-20 14.6.1.3 Configuring 8-Bit Channel Enhanced GP-DMA Mode 14-20 14.6.1.4 Configuring 16-Bit Channel Enhanced GP-DMA Mode 14-21 CHAPTER PROGRAMMABLE INTERRUPT CONTROLLER 15-1 15.1 Overview. 15-1 15.2 Block Diagram 15-2 15.3 System Design 15-2 15.4 Registers 15-4 15.5 Operation 15-7 15.5.1 Interrupt Flow Sequence 15-7 15.5.2 Interrupt Sources 15-8 15.5.2.1 Hardware-Generated Interrupts 15-8 15.5.3 Interrupt Source Routing 15-10 15.5.3.1 Polarity Inversion Interrupt Requests 15-10
Microcontroller User's Manual
Table Contents 15.5.3.2 PC/AT Compatibility 15-12 15.5.3.3 Floating Point Errors 15-12 15.5.3.4 Disabling Slave Controllers 15-13 15.5.4 Edge-Triggered Level-Sensitive Interrupts 15-13 15.5.5 Interrupt Sharing 15-13 15.5.6 Non-Maskable Interrupts Routing 15-14 15.5.6.1 Sharing NMIs 15-14 15.5.7 Priority Types 15-16 15.5.8 Configuration Information 15-16 15.5.8.1 Programming 15-16 15.5.8.2 PC/AT Configuration 15-18 15.5.9 Software Considerations 15-18 15.5.9.1 Interrupt Sharing 15-18 15.5.9.2 Disabling Slave Controllers 15-19 15.5.9.3 Detecting Invalid Interrupt Requests 15-19 15.5.9.4 Floating Point Unit Error Handling 15-19 15.6 Initialization. 15-20 CHAPTER PROGRAMMABLE INTERVAL TIMER 16-1 16.1 Overview. 16-1 16.2 Block Diagram 16-1 16.3 System Design 16-1 16.4 Registers 16-2 16.5 Operation 16-3 16.5.1 Channel 16-3 16.5.2 Channel 16-3 16.5.3 Channel 16-4 16.5.4 Operating Modes 16-4 16.5.4.1 Mode Interrupt Terminal Count 16-4 16.5.4.2 Mode Hardware-Retriggerable One-Shot 16-4 16.5.4.3 Mode Rate Generator 16-5 16.5.4.4 Mode Square Wave Mode 16-5 16.5.4.5 Mode Software-Triggered Strobe 16-5 16.5.4.6 Mode Hardware-Triggered Strobe 16-5 16.5.5 Clocking Considerations 16-6 16.5.5.1 Internal Clock 16-6 16.5.5.2 External Clock 16-6 16.5.6 Interrupts 16-6 16.5.7 Software Considerations 16-6 16.5.7.1 Using Clock Source PC/AT-Compatible Systems 16-6 16.6 Initialization. 16-7 CHAPTER GENERAL-PURPOSE TIMERS 17-1 17.1 Overview. 17-1 17.2 Block Diagram 17-1 17.3 System Design 17-1 17.4 Registers 17-2 17.5 Operation 17-3 17.5.1 Timer Timer 17-3 17.5.2 Timer 17-4 17.5.3 Operating Modes 17-4 17.5.3.1 Interrupt Terminal Count Mode 17-4 17.5.3.2 Hardware Retrigger Mode 17-4 17.5.3.3 Alternate Compare Mode. 17-4 17.5.3.4 Square Wave Mode 17-4 17.5.3.5 Continuous Mode. 17-4 17.5.3.6 Prescaler Mode 17-4
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Table Contents 17.5.4 Configuration Information 17-5 17.5.5 Clocking Considerations 17-5 17.5.5.1 Internal Clock 17-5 17.5.5.2 External Clock 17-6 17.5.6 Interrupts 17-6 17.5.7 Software Considerations 17-6 17.5.7.1 Combining Timer Count Elements. 17-6 17.5.7.2 Reading Cascaded 32-Bit Timer 17-6 17.6 Initialization. 17-8 CHAPTER SOFTWARE TIMER 18-1 18.1 Overview. 18-1 18.2 Block Diagram 18-1 18.3 Registers 18-2 18.4 Operation 18-2 18.4.1 Configuration Information 18-3 18.5 Initialization. 18-3 CHAPTER WATCHDOG TIMER 19-1 19.1 Overview. 19-1 19.2 Block Diagram 19-1 19.3 Registers 19-2 19.4 Operation 19-3 19.4.1 Configuration Information 19-3 19.4.1.1 Keyed Sequences 19-3 19.4.1.2 Interrupt Request Generation 19-4 19.4.1.3 System Reset Generation 19-4 19.4.1.4 Time-Out Duration 19-4 19.4.2 Interrupts 19-5 19.4.3 AMDebugTechnology Interface 19-5 19.4.4 Software Considerations 19-5 19.5 Initialization. 19-6 CHAPTER REAL-TIME CLOCK 20-1 20.1 Overview. 20-1 20.2 Block Diagram 20-1 20.3 System Design 20-3 20.3.1 Backup Battery Considerations 20-3 20.3.1.1 System with External Backup Battery 20-3 20.3.1.2 System without External Backup Battery 20-4 20.3.2 Selecting Interfacing 32.768-kHz Crystal 20-5 20.3.3 Using External 20-5 20.4 Registers 20-6 20.5 Operation 20-7 20.5.1 Configuration Information 20-7 20.5.1.1 Configuring Hour Format 20-7 20.5.1.2 Programming Date Time 20-8 20.5.1.3 Generating Periodic Interrupts 20-8 20.5.1.4 Using Alarm Function 20-9 20.5.1.5 Handling Year 2000 Issues 20-9 20.5.2 Clocking Considerations 20-9 20.5.3 Interrupts 20-9 20.5.4 Software Considerations 20-10 20.5.4.1 Initializing Divider Chain 20-10 20.5.4.2 Accessing CMOS Memory. 20-10 20.5.4.3 Legacy Enable Moved. 20-10 20.6 Initialization. 20-10 20.6.1 Reset 20-11
Microcontroller User's Manual
Table Contents CHAPTER UART SERIAL PORTS 21-1 21.1 Overview. 21-1 21.2 Block Diagram 21-1 21.3 System Design 21-2 21.4 Registers 21-3 21.5 Operation 21-5 21.5.1 Data Transmission 21-6 21.5.1.1 16450-Compatible UART Mode 21-6 21.5.1.2 16550-Compatible UART Mode 21-7 21.5.2 Data Reception 21-7 21.5.2.1 16450-Compatible UART Mode 21-7 21.5.2.2 16550-Compatible UART Mode 21-7 21.5.3 Error Handling 21-8 21.5.3.1 Parity Error 21-8 21.5.3.2 Framing Error 21-8 21.5.3.3 Break Indication 21-8 21.5.3.4 Error Reporting 21-8 21.5.4 Configuration Information 21-9 21.5.4.1 Baud Rate 21-9 21.5.4.2 Hardware Flow Control 21-9 21.5.4.3 Operating Modes 21-9 21.5.5 Interface 21-10 21.5.5.1 Transmit 21-10 21.5.5.2 Receive 21-10 21.5.6 Clocking Considerations 21-10 21.5.7 Interrupts 21-10 21.5.7.1 Serial Port Interrupts 21-12 21.5.7.2 Interrupts. 21-12 21.5.7.3 Interrupt Disable. 21-13 21.6 Initialization. 21-13 CHAPTER SYNCHRONOUS SERIAL INTERFACE 22-1 22.1 Overview. 22-1 22.2 Block Diagram 22-1 22.3 System Design 22-1 22.4 Registers 22-2 22.5 Operation 22-3 22.5.1 Usage Scenarios 22-3 22.5.1.1 Four-Pin Interface 22-3 22.5.1.2 Three-Pin Interface 22-3 22.5.2 Configuration Information 22-5 22.5.2.1 Order. 22-5 22.5.2.2 Clock Idle State 22-5 22.5.2.3 Clock Phase 22-5 22.5.3 Cycles 22-5 22.5.3.1 4-Bit Read Cycle 22-6 22.5.3.2 Burst, 16-Bit, 32-Bit Cycles 22-7 22.5.4 Clocking Considerations 22-7 22.5.5 Interrupts 22-7 22.5.6 Software Considerations 22-8 22.6 Initialization. 22-8
Microcontroller User's Manual
Table Contents CHAPTER PROGRAMMABLE INPUT/OUTPUT 23-1 23.1 Overview. 23-1 23.2 Block Diagram 23-1 23.3 System Design 23-2 23.4 Registers 23-4 23.5 Operation 23-4 23.5.1 Configuration Information 23-5 23.5.1.1 Pins Simple Input. 23-5 23.5.1.2 Pins Simple Output 23-5 23.5.2 Software Considerations 23-5 23.6 Initialization. 23-6 CHAPTER SYSTEM TEST DEBUGGING 24-1 24.1 Overview. 24-1 24.2 System Design 24-1 24.2.1 Loading 24-2 24.3 Registers 24-2 24.4 Operation 24-3 24.4.1 System Test Mode 24-3 24.4.1.1 Functions System Test Mode. 24-3 24.4.1.2 Using System Test Mode Interface 24-4 24.4.1.3 SDRAM Write Cycle System Test Mode 24-4 24.4.1.4 SDRAM Read Cycle System Test Mode 24-5 24.4.1.5 Tracing Transactions Interface 24-5 24.4.1.6 Tracing Transactions Interface 24-6 24.4.2 Write Buffer Test Mode 24-7 24.4.2.1 Using Write Buffer Test Mode Interface 24-7 24.4.2.2 SDRAM Write Cycle Write Buffer Test Mode 24-8 24.4.2.3 SDRAM Read Cycle Write Buffer Test Mode 24-8 24.4.3 Other Debugging Features 24-10 24.4.3.1 Nonconcurrent Arbitration Mode 24-10 24.4.3.2 Echoing Integrated Peripheral Accesses 24-10 24.4.3.3 Summary Additional System Debugging Features 24-10 24.4.4 Software Considerations 24-11 24.4.5 Latency 24-11 24.5 Initialization. 24-12 CHAPTER BOUNDARY SCAN TEST INTERFACE 25-1 25.1 Overview. 25-1 25.2 Block Diagram 25-1 25.3 System Design 25-2 25.3.1 JTAG Strapping 25-2 25.4 Registers 25-2 25.5 Operation 25-2 25.5.1 Instruction Register 25-3 25.5.1.1 Implemented Instructions. 25-3 25.5.2 Configuration Information 25-5 25.5.2.1 Instruction Path 25-5 25.5.2.2 Bypass Path 25-5 25.5.2.3 Main Data Scan Path 25-5 25.5.2.4 Serial Debug Port Data Register 25-14 25.5.2.5 Device Identification Register 25-14 25.5.3 Test Access Port (TAP) Controller 25-15 25.5.3.1 Controller States. 25-15 25.5.4 Cycles 25-19 25.5.5 Clocking Considerations 25-20 25.6 Initialization. 25-20
Microcontroller User's Manual
Table Contents CHAPTER AMDebugTECHNOLOGY 26-1 26.1 Overview. 26-1 26.2 Block Diagram 26-2 26.3 System Design 26-2 26.3.1 Connecting AMDebugPort 26-3 26.3.2 Mechanical Specifications Target Connector 26-5 26.3.3 Locating Connector Target System 26-5 26.4 Operation 26-6 26.4.1 On-Chip Trace Cache 26-7 26.4.2 Software Performance Profiling 26-7 INDEX Index-1
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Table Contents LIST FIGURES Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 8-10 Figure 8-11 Figure 8-12 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 9-10 Figure 9-11 Figure 9-12 Figure 9-13 Figure 9-14 Figure 9-15 Figure 9-16 Figure 10-1 Figure 10-2 Figure 10-3 Figure 10-4 xviii Microcontroller Block Diagram Microcontroller-Based Smart Residential Gateway Reference Design 1-10 Microcontroller-Based Thin Client Reference Design 1-11 Microcontroller-Based Digital Reference Design 1-12 Microcontroller-Based Telephone Line Concentrator Reference Design 1-13 Logic Diagram Interface Logic Diagram Default Function Initial Near Jump Example. Programmable Address Region (PAR) Register Format 3-10 Programmable Address Region (PAR) Register Worksheet 3-11 Programmable Address Region (PAR) Register Format System Memory Map. System Map. 4-11 Clock Source Block Diagram System Clock Distribution Block Diagram Bypassing 32.768-kHz Oscillator. Bypassing 33-MHz Oscillator Clock Routing CLKTEST Reset Controller Block Diagram PRGRESET Timing Power-On Reset Sequence Events Am5x86® Block Diagram System Arbitration Block Diagram Skipped Master Example. Rotating Priority Queue External Master Arbitration Queues Host Bridge Master Arbitration Queue. Arbitration 8-11 Cache Write-Back 8-13 CPU-to-PCI Cycle 8-14 Arbitration 8-15 Concurrent Mode Arbitration Parking 8-16 Nonconcurrent Mode Arbitration 8-18 Simple Rotating Priority Queue 8-20 Interface Block Diagram Microcontroller Connection External Target. Microcontroller Connection External Master Microcontroller SERR PERR Connection Clocking Example Lightly Loaded System Clocking Example Heavily Loaded System Configuration Address (PCICFGADR) Register 9-10 Read Cycle 9-13 Read Cycle with External Target Retry 9-14 Posted Write Cycle 9-15 Am5x86 Non-Posted Write Cycle 9-16 Write Cycles Internal Configuration Registers 9-17 Read Cycles from Internal Configuration Registers 9-18 External Master Posted Write SDRAM 9-23 External Master SDRAM Read (Delayed Transaction) 9-24 Host Bridge Target Disconnect 9-26 SDRAM Controller Block Diagram. 10-2 Detailed Block Diagram SDRAM Controller. 10-3 SDRAM Bank Configuration 10-4 Example Configuration 168-Pin SDRAM DIMM 10-5 Microcontroller User's Manual
Table Contents Figure 10-5 Figure 10-6 Figure 10-7 Figure 10-8 Figure 10-9 Figure 10-10 Figure 10-11 Figure 10-12 Figure 10-13 Figure 11-1 Figure 11-2 Figure 11-3 Figure 11-4 Figure 11-5 Figure 11-6 Figure 12-1 Figure 12-2 Figure 12-3 Figure 12-4 Figure 12-5 Figure 12-6 Figure 12-7 Figure 12-8 Figure 12-9 Figure 12-10 Figure 12-11 Figure 13-1 Figure 13-2 Figure 13-3 Figure 13-4 Figure 13-5 Figure 13-6 Figure 13-7 Figure 13-8 Figure 13-9 Figure 13-10 Figure 13-11 Figure 13-12 Figure 13-13 Figure 13-14 Figure 13-15 Figure 13-16 Figure 14-1 Figure 14-2 Figure 14-3 Figure 14-4 Figure 14-5 Figure 14-6 Figure 14-7 Figure 15-1 Figure 15-2 Figure 15-3 Figure 15-4 Figure 16-1 Figure 17-1 Figure 18-1 SDRAM Clock Generation 10-7 Alternate SDRAM Clock Generation with External Clock Driver 10-7 SDRAM Burst Read Cycle (Read-Ahead Feature Disabled) (Page Miss/Page Hit). 10-22 SDRAM Write Cycle (Write Buffer Disabled) (Page Miss/page Hit) 10-23 SDRAM Burst Write (Write Buffer Disabled) (Page Miss/Page Hit) 10-24 SDRAM Burst Read Cycle with Enabled. 10-25 SDRAM Read-Modify-Write Cycle (for Data Write) with Enabled (Page Hit). 10-26 SDRAM Auto Refresh Cycle 10-27 SDRAM Mode Register Access. 10-27 Write Buffer Read Buffer Block Diagram (SDRAM Subsystem) 11-2 Write Buffer Read Buffer Block Diagram 11-3 Write Buffer Merging Example. 11-7 Write Buffer Collapsing Example 11-8 Write Buffer Read-Merging Example 11-9 Thrashing with Write Buffer Disabled Enabled 11-14 Controller Block Diagram 12-2 Voltage Isolation Examples 12-4 Page-Mode ROM: Fetching Four Words from 16-Bit ROM. 12-6 Non-Page-Mode ROM: Fetching Four Words from 16-Bit 12-8 Page-Mode ROM: Fetching Four Doublewords (Aligned) from 32-Bit ROM. 12-8 Page-Mode ROM: Fetching Four Doublewords (Unaligned) from 8-Bit ROM. 12-8 Multiple Accesses: Data Amounts Smaller than Doubleword Bytes) from 8-Bit ROM. 12-10 Page Access Fetching Four Doublewords from 32-Bit (Burst Sequence: 2-1-1-1) 12-10 Page Access Fetching Doublewords from 16-Bit 12-11 Cache-Line Fill (Fetching Four Doublewords from 32-Bit ROM). 12-11 Word Write Cycle Flash Memory. 12-12 Controller System Block Diagram 13-2 Example: Using External Data Buffer Address Excess Loading 13-4 Example: Using Voltage Translator. 13-5 Timing Format 13-8 Microcontroller Interfacing with Super Controller 13-13 Timing Diagram Super Interface 13-14 Microcontroller Interfacing with Am85C30 13-15 Timing Diagram Am85C30 Interface 13-16 8-Bit Data Access 8-Bit Device 13-16 16-Bit Data Access 16-Bit Device 13-17 16-Bit Data Access 8-Bit Device 13-17 32-Bit Data Access 8-Bit Device 13-18 32-Bit Data Access 16-Bit Device 13-18 8-Bit Data Access 16-Bit Device 13-19 16-Bit Access 16-Bit Device 13-20 GPRDY Timing 13-21 GP-DMA Controller Block Diagram 14-2 Master Slave Core Cascading Diagram 14-3 GP-DMA Read Transfer. 14-13 GP-DMA Write Transfer 14-14 GP-DMA Verify Transfer 14-14 GP-DMA Read Demand Transfer Mode 14-16 GP-DMA Read Transfer with Cache (Write-Back Cache) 14-17 Programmable Interrupt Controller (PIC) Block Diagram 15-3 Interrupt Sources 15-9 Interrupt Source Routing 15-11 Routing. 15-15 Programmable Interval Timer Block Diagram 16-2 General-Purpose Timers Block Diagram 17-2 Software Timer Block Diagram 18-1 Microcontroller User's Manual
Table Contents Figure 19-1 Figure 20-1 Figure 20-2 Figure 20-3 Figure 20-4 Figure 21-1 Figure 21-2 Figure 21-3 Figure 22-1 Figure 22-2 Figure 22-3 Figure 22-4 Figure 22-5 Figure 22-6 Figure 22-7 Figure 22-8 Figure 22-9 Figure 23-1 Figure 24-1 Figure 24-2 Figure 24-3 Figure 24-4 Figure 25-1 Figure 25-2 Figure 25-3 Figure 25-4 Figure 25-5 Figure 25-6 Figure 26-1 Figure 26-2 Figure 26-3 Figure 26-4 Figure 26-5 Watchdog Timer Block Diagram 19-2 Real-Time Clock Block Diagram 20-2 Voltage Monitor Block Diagram 20-3 Circuit with Backup Battery 20-4 Circuit without Backup Battery. 20-5 UART Block Diagram. 21-2 UART Frame Configuration 21-5 UART Frame Transmission 21-5 Block Diagram. 22-2 Four-Pin Interface 22-4 Simultaneous Transmit Receive. 22-4 Three-Pin Interface 22-4 Typical Half-Duplex Communication, Non-Inverted Phase Clock Modes. 22-4 Clock Phase Clock Idle State: Effects Data 22-6 4-Bit Read Cycle: Full-Duplex, Non-Inverted Phase, Non-Inverted Clock 22-6 Back-to-Back Transactions Full-duplex, Microwire-Compatible Configuration 22-7 Timing: TC_INT BSY_STA Bits 22-8 Signal Block Diagram 23-2 System Test Mode Timing During SDRAM Write Cycle (Page Hit) 24-5 System Test Mode Timing During SDRAM Read Cycle (Page Miss) 24-5 Write Buffer Test Mode Timing During SDRAM Write Cycle (Page Hit) 24-8 Write Buffer Test Mode Timing During SDRAM Read Cycle (Page Miss) 24-9 Logical Structure Boundary Scan Register 25-1 Serial Debug Port Data Register Format 25-14 Device Identification Register Format 25-14 Test Access Port Controller State Diagram 25-15 Test Logic Operation: Data Scan 25-19 Test Logic Operation: Instruction Scan 25-20 AMDebugTechnology Software Architecture. 26-2 12-Pin Connector Format 26-4 20-Pin Serial Connector Format 26-4 Mechanical Specifications AMDebugTechnology Target Connector 26-5 Locating Target Connector 26-6
Microcontroller User's Manual
Table Contents LIST TABLES Table Table Table Table Table Table Table Table Table Table Table Table Table 3-10 Table 3-11 Table 3-12 Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 10-1 Table 10-2 Table 10-3 Table 10-4 Table 10-5 Table 10-6 Table 10-7 Table 10-8 Table 10-9 Table 10-10 Table 10-11 Table 10-12 Table 11-1 Table 11-2 Table 12-1 Table 12-2 Table 12-3 Table 12-4 Table 12-5 Table 12-6 Documentation Notation Signal Descriptions Table Definitions Signal Descriptions CPUID Codes Example Programming: Single Device Using Chip Select 3-14 Example Programming: Single Device That Performs Decode 3-14 Example Programming: Multiple Devices Chip Select 3-14 Example Programming: Controller 3-15 Example Programming: COM3 with Present 3-16 Example Programming: Network Adapter Remote Program Loading 3-16 Example Programming: Boot Device Mapping BIOS Shadowing 3-17 Example Programming: First Bank Flash Operating System. 3-17 Example Programming: Second Bank Flash Operating System 3-18 Example Programming: Setting Buffers 3-18 Example Programming: Write-Protected Code Segments 3-19 Address Decoding Registers-Memory-Mapped Address Decoding Registers-Direct-Mapped Master Address Spaces Memory Space Summary PC/AT Peripherals 4-14 Clock Start-up Lock Times Clock Signals Shared with Other Interfaces Timing Error Translates Clock Accuracy Clock Control Registers-Memory-Mapped Reset Generation Registers-Memory-Mapped Reset Generation Registers-Direct-Mapped Microcontroller Reset Sources States Cores after System Reset Am5x86® Registers-Memory-Mapped Am5x86® Registers-Direct-Mapped Cache Configuration Options System Arbitration Registers-Memory-Mapped Host Bridge Registers-Memory-Mapped Host Bridge Registers-Direct-Mapped Host Bridge Registers-PCI Indexed SDRAM Clock Loading Estimates Based Device Width. 10-6 Estimated Capacitance (4-Bit SDRAM Devices) 10-8 Estimated Capacitance (8-Bit SDRAM Devices) 10-8 Estimated Capacitance (16-Bit SDRAM Devices) 10-9 Estimated Capacitance (32-Bit SDRAM Devices) 10-9 SDRAM Controller Registers-Memory-Mapped 10-10 Address Mapping Signals SDRAM Devices 10-12 SDRAM Devices Supported with Column Boundary Specification 10-13 Column Address Configuration Settings SDRAM. 10-15 SDRAM Page Sizes. 10-16 SDRAM Refresh Rates 10-18 Load Mode Register Settings 10-31 SDRAM Signals Shared with Other Interfaces 11-4 SDRAM Buffer Control Registers-Memory-Mapped 11-4 ROM/Flash Data Connection Options 12-1 Signals Shared with Other Interfaces. 12-3 Controller Registers-Memory-Mapped. 12-5 Example: Access Timing Wait States 12-9 Accesses Width. 12-9 CFGx Pinstrap Configuration Options BOOTCS 12-14
Microcontroller User's Manual
Table Contents Table 13-1 Table 13-2 Table 13-3 Table 13-4 Table 13-5 Table 13-6 Table 13-7 Table 13-8 Table 14-1 Table 14-2 Table 14-3 Table 14-4 Table 14-5 Table 14-6 Table 14-7 Table 14-8 Table 15-1 Table 15-2 Table 15-3 Table 15-4 Table 16-1 Table 16-2 Table 16-3 Table 16-4 Table 16-5 Table 17-1 Table 17-2 Table 17-3 Table 17-4 Table 18-1 Table 19-1 Table 19-2 Table 20-1 Table 20-2 Table 20-3 Table 20-4 Table 21-1 Table 21-2 Table 21-3 Table 21-4 Table 21-5 Table 21-6 Table 21-7 Table 22-1 Table 23-1 Table 23-2 Table 23-3 Table 24-1 Table 24-2 Table 24-3 Table 24-4 Table 25-1 Table 25-2 Table 25-3 Table 26-1 Signals Shared with Other Interfaces. 13-3 Registers-Memory-Mapped 13-5 Echo Mode Minimum Timing 13-9 Cross-Reference Table Signals Signals 13-12 Example Super Controller Interface Timing 13-13 Example Enhanced Serial Communications Controller Interface Timing 13-15 Differentiating Upper/Lower Byte Access 16-Bit Devices 13-19 Dynamic Sizing Override Programmed Data Width 13-20 GP-DMA Signals Shared with Other Interfaces. 14-4 GP-DMA Controller Registers-Memory-Mapped. 14-4 GP-DMA Controller Registers-Direct-Mapped 14-7 Supported GP-DMA Initiator/Target Combinations 14-9 GP-DMA Channel Mapping 14-10 8-Bit GP-DMA Channel Address Generation 14-12 16-Bit GP-DMA Channel Address Generation 14-12 GP-DMA Cycle Types 14-16 Programmable Interrupt Controller Signals Shared with Other Interfaces. 15-2 Programmable Interrupt Controller Registers-Memory-Mapped 15-4 Programmable Interrupt Controller Registers-Direct-Mapped. 15-6 PC/AT Interrupt Channel Mapping. 15-12 Programmable Interval Timer Signals Shared with Other Interfaces. 16-1 Programmable Interval Timer Configuration Registers-Memory-Mapped. 16-2 Programmable Interval Timer Configuration Registers-Direct-Mapped 16-3 Internal Clock Source 16-6 External Clock Source 16-6 General-Purpose Timer Signals Shared with Other Interfaces 17-1 General-Purpose Timer Registers-Memory-Mapped 17-2 Timers Internal Clock Sources 17-5 Timers External Clock Sources (Using 33.333 Crystal). 17-6 Software Timer Configuration Registers-Memory-Mapped. 18-2 Watchdog Timer Registers-Memory-Mapped 19-2 Watchdog Timer Time-Out Duration 19-4 Real-Time Clock Registers-Memory-Mapped 20-6 Real-Time Clock Registers-Direct-Mapped. 20-6 Real-Time Clock Registers-RTC Indexed 20-6 Using RATE_SEL Specify Periodic Interrupt Rate 20-8 UART Signals Shared with Other Interfaces 21-2 Connection 21-3 UART Registers-Memory-Mapped 21-3 UART Registers-Direct-Mapped 21-4 Baud Rates, Divisors, Clock Source. 21-9 UART Interrupt Programming Summary 21-11 Serial Port Interrupt Interrupt Priority 21-12 Synchronous Serial Interface Registers-Memory-Mapped 22-2 Signals Shared with Other Interfaces 23-3 Registers-Memory-Mapped 23-4 Configuration Summary 23-5 System Test Debugging Signals Shared with Other Interfaces 24-2 System Test Debugging Registers-Memory-Mapped. 24-2 WBMSTR2-WBMSTR0 Definition During Write Buffer Write Cycles 24-8 WBMSTR2-WBMSTR0 Definition During SDRAM Read Cycles 24-9 Chip Test Debugging Registers 25-2 Test Access Port Instruction 25-3 Main Data Scan Path. 25-5 AMDebugTechnology Connector Pins 26-3
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Microcontroller User's Manual
PREFACE
INTRODUCTION
MICROCONTROLLER
microcontroller full-featured microcontroller developed general embedded market. microcontroller combines 32-bit, low-voltage Am5x86® with complete integrated peripherals suitable both real-time PC/AT-compatible embedded applications.
PURPOSE THIS MANUAL
This manual describes technical features programming interface microcontroller.
Intended Audience
Microcontroller User's Manual, order #22004, intended computer software hardware engineers system architects designing considering designing systems based microcontroller.
Overview this Manual
manual organized into following chapters:
Chapter includes architectural overview microcontroller, along
with applications diagrams.
Chapter describes signals pins microcontroller. Logic
diagrams showing defaults pins with shared signals also found this chapter. Detailed state information available Microcontroller Data Sheet.
Chapter provides overview system initialization shows example
configurations.
Chapter describes system address mapping microcontroller. Chapter provides information clock generation control. Chapter describes reset sources states microcontroller. Chapter includes overview integrated Am5x86 CPU. additional
information about CPU, consult references provided this chapter.
Chapter describes system arbiter microcontroller, which
includes arbiter arbiter.
Chapter describes host bridge implemented
microcontroller.
Chapter describes synchronous DRAM (SDRAM) controller. Chapter describes SDRAM write buffer read buffer with read-ahead
feature.
Chapter describes ROM/Flash controller.
Microcontroller User's Manual
xxiii
Introduction Chapter describes programmable general-purpose (GP) interface included
microcontroller.
Chapter describes controller. Chapter describes programmable interrupt controller (PIC), which includes
three interrupt controllers.
Chapter describes programmable interval timer (PIT), which includes three
timers.
Chapter describes three general-purpose (GP) timers included
microcontroller.
Chapter describes software timer that eases task keeping system time. Chapter describes watchdog timer used guard against runaway software. Chapter describes real-time clock (RTC) voltage monitor included
microcontroller.
Chapter describes UART serial ports. Chapter describes synchronous serial interface (SSI). Chapter describes programmable input/output (PIO) pins
microcontroller.
Chapter summary system test features found
microcontroller.
Chapter describes Joint Test Action Group (JTAG) (IEEE Std. 1149.1-1990)
boundary scan test interface features microcontroller.
Chapter provides overview AMDebugtechnology board
specifications necessary utilize this capability, which supported third-party FusionE86 vendors.
RELATED DOCUMENTS
following documents contain additional information that will useful designing embedded application based microcontroller.
Documentation
addition this manual, documentation microcontroller includes following documents:
Microcontroller Register Manual, order #22005, fully describes
configuration registers required program microcontroller.
Microcontroller Data Sheet, order #22003, includes complete lists,
state tables, timing thermal characteristics, package dimensions microcontroller. Other information interest:
Am486® Microprocessor Software User's Manual, order #18497, includes
complete instruction integrated Am5x86 CPU.
Am5x86® Microprocessor Family Data Sheet, order #19751 Am486® DX/DX2 Microprocessor Hardware Reference Manual, order #17965
xxiv
Microcontroller User's Manual
Introduction Family Products Development Tools order #21058, provides single-
source multimedia tool customer evaluation products, well FusionE86 partner tools technologies that support family. Technical documentation included format. order literature, contact nearest sales office call literature center numbers listed back cover this manual. addition, these documents available form site. access site, www.amd.com follow Embedded Processor link information about family.
Additional Information
following non-AMD documents sources provide additional information that interest microcontroller users:
Local Specification, Revision 2.2, December 1998, Special Interest
Group, 800-433-5177 (US), 503-693-6360 (International), www.pcisig.com.
IEEE 1149.1-1990 Standard Test Access Port Boundary-Scan Architecture,
(order #SH16626-NYF), Institute Electrical Electronic Engineers, Inc., 800-6784333, www.ieee.org.
System Architecture, Mindshare, Inc., Reading, Addison-Wesley, 1995, ISBN
0-201-40993-3.
System Architecture, Mindshare, Inc., Reading, Addison-Wesley, 1995, ISBN
0-201-40996-8.
80486 System Architecture, Mindshare, Inc., Reading, Addison-Wesley, 1995, ISBN
0-201-40994-1.
Indispensable Hardware Book, Hans-Peter Messmer, Wokingham, England:
Addison-Wesley, 1995, ISBN 0-201-87697-3.
DOCUMENTATION CONVENTIONS
Table lists documentation conventions used throughout this manual.
Table
Documentation Notation Notation Reset Default Values Default Read/Write Attributes field read-only. write register this field effect. contents changed hardware. Value after system reset Active High value guaranteed Determined sources external microcontroller Meaning
Microcontroller User's Manual
Introduction Table Documentation Notation (Continued) Notation Meaning field write-only. Reading this register this field does return meaningful value side effects. field read/write. Reading register this field always returns last value written. Reads have side effects. field read/write with conditions. indicates that there side effects using this bit. example, reading register might always return last value written. Note that both reads writes have side effects. "!", sure read description programming notes. field reserved internal test/debug future expansion. This field should written normal system operation. This field always returns when read. field reserved compatibility purposes. example, field might ignored during writes maintain software compatibility. "!", sure read description programming notes.
R/W!
RSV!
Reference Notation MMCR offset index Port index Naming ROMCS1 GPRESET ads, hold ROMCS2-ROMCS1 ROMCSx Numbers Binary number Decimal number Decimal default radix function during hardware reset Alternative function selected software configuration overbar indicates that signal assumes logic state when asserted. absence overbar indicates that signal assumes logic High state when asserted. signal name lowercase indicates internal signal. chip select signals chip select signals microcontroller Memory-Mapped Configuration Region (MMCR) offset register indexed register Direct-mapped register configuration indexed register
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Microcontroller User's Manual
Introduction Table Documentation Notation (Continued) Notation register address Meaning Hexadecimal number several legal values; e.g., using 0xF8h UART Transmit Holding register either 02F8h 03F8h, depending UART field that consists bits through Example: SB_ADDR[23-16] field. Refers system clock frequency being used. This either 33.000 33.333 MHz. Microcontroller User's Manual more information about clock generation.
[X-Y]
General field will bit. field register (one more consecutive related bits) possible perform action properly configured certain action going occur Write Note: referred either register being described, register referred explicitly surrounding text. Change Usually cleared writing however, some bits cleared writing Context-sensitive. refer either resetting default value clearing bit.
Clear bit. Reset bit.
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Introduction
xxviii
Microcontroller User's Manual
CHAPTER
ARCHITECTURAL OVERVIEW
MICROCONTROLLER
microcontroller full-featured microcontroller developed general embedded market. microcontroller combines 32-bit, low-voltage Am5x86 with complete integrated peripherals suitable both real-time PC/AT-compatible embedded applications. integrated host bridge, SDRAM controller, enhanced PC/AT-compatible peripherals, advanced debugging features provide system designer with wide range onchip resources, allowing support legacy devices well devices available current marketplace. Designed medium- high-performance applications telecommunications, data communications, information appliance markets, microcontroller particularly well suited applications requiring high throughput combined with latency.
1.1.1
Distinctive Characteristics
Industry-standard Am5x86® with floating point unit (FPU) 16-Kbyte write-back
cache 100-MHz 133-MHz operating frequencies Low-voltage operation (core tolerant (3.3-V output levels)
E86family embedded processors
Part software-compatible family microprocessors microcontrollers well supported wide variety development tools
Integrated host bridge controller leverages standard peripherals software
MHz, 32-bit Revision 2.2-compliant High-throughput 132-Mbyte/s peak transfer Supports five external masters Integrated write-posting read-buffering high-throughput applications
Synchronous DRAM (SDRAM) controller
Supports 16-, 64-, 128-, 256-Mbit SDRAM. Supports banks total Mbytes. Error Correction Code provides system reliability. Buffers improve read write performance.
technology offers low-cost solution advanced debugging
capabilities required embedded designers. Allows instruction tracing during execution from Am5x86 CPU's internal cache Uses enhanced JTAG port low-cost debugging
Microcontroller User's Manual
Architectural Overview
Parallel debug port high-speed data exchange during in-circuit emulation
General-purpose (GP) with programmable timing 16-bit devices provides
good performance very cost.
ROM/Flash controller 16-, 32-bit devices Enhanced PC/AT-compatible peripherals provide improved performance.
Enhanced programmable interrupt controller (PIC) prioritizes interrupt levels external sources) with flexible routing. Enhanced controller includes double buffer chaining, extended address transfer counts, flexible channel routing. 16550-compatible UARTs operate baud rates 1.15 Mbit/s with optional interface.
Standard PC/AT-compatible peripherals
Programmable interval timer (PIT) Real-time clock (RTC) with battery backup capability bytes
Additional integrated peripherals
Three general-purpose 16-bit timers provide flexible cascading 32-bit operation. Watchdog timer guards against runaway software. Software timer Synchronous serial interface (SSI) offers full-duplex half-duplex operation. Flexible address decoding programmable memory mapping system addressing configuration
programmable input/output (PIO) pins Native support pSOS, QNX, RTXC, VxWorks, Windows® operating systems Industry-standard BIOS support
BLOCK DIAGRAM
Figure page illustrates integrated Am5x86 CPU, structure, on-chip peripherals microcontroller. Three primary interfaces provided:
high-performance, 66-MHz 32-bit synchronous DRAM (SDRAM) interface
Mbytes used Am5x86 code execution, well buffer storage external masters initiators. high-performance ROM/Flash interface also connected SDRAM interface.
industry-standard, 32-bit provided high bandwidth peripherals such
local area network controllers, synchronous communications controllers, disk storage controllers.
simple 8/16-bit, 33-MHz general-purpose bus) provides glueless connection
lower bandwidth peripherals, NVRAM, SRAM, ROM, custom ASICs; supports dynamic sizing compatibility with many common devices. These three buses listed above provided operating modes microcontroller.
Microcontroller User's Manual
Architectural Overview
addition these three primary interfaces, microcontroller also contains internal oscillator circuitry phase locked loop (PLL) circuitry, requiring only simple crystals virtually system clock generation. Diagrams showing microcontroller used various system designs included "Applications" page 1-8.
Figure Microcontroller Block Diagram
Address
SDRAM Controller Interface Address Decode Unit Read/Write Buffers ROM/Flash Controller
Interface Unit
Data
AMDebugTechnology JTAG
Control/Status
GP-DMA Controller
Controller
Control/Status
Request
Address
GP-DMA Request Grant
Clock Generation External Programmable Interrupt Controller Programmable Interval Timer
Data
Interface Arbiter
Watchdog Timer FIFOs FIFO Control Real-Time Clock CMOS
Arbiter
Master
Target
General-Purpose Timers Software Timer
16550 UART
16550 UART
Requests Grants
Synchronous Serial Interface Programmable Controls PC/AT Compatibility Logic
Microcontroller
Microcontroller User's Manual
Architectural Overview
ARCHITECTURAL OVERVIEW
microcontroller designed provide:
balanced high performance low-cost interface mechanisms high-performance, industry-standard 32-bit Glueless interfacing many 16-bit peripherals 16-bit with
programmable timing
cost-effective system architecture that meets wide range performance criteria
while retaining lower cost 32-bit system
high degree leverage from present hardware software technologies
1.3.1
Industry-Standard Architecture (Chapter
Am5x86 microcontroller utilizes industry-standard microprocessor instruction that enables compatibility across variety performance levels from 16-bit Am186processors high-end Athlonprocessor. Software written architecture family compatible with microcontroller. Other benefits Am5x86 include:
Improved time-to-market easy software migration Existing availability multiple operating systems that directly support
architecture. Whether application requires real-time operating system (RTOS) popular Microsoft® operating systems, microcontroller provides consistent compatibility with many off-the-shelf operating systems.
Multiple sources field-proven development tools Integrated floating point unit (FPU) (compliant with ANSI/IEEE standard) 16-KByte unified cache configurable either write-back write-through cache mode
Am5x86 described Chapter
1.3.2
AMDebugTechnology Advanced Debugging (Chapter
microcontroller provides support low-cost, full-featured, in-circuit emulation capability. This in-circuit emulation support developed specifically enable users test debug their software earlier design cycle. Utilizing this capability, software more extensively exercised, full execution speeds. also allows tracing during execution from Am5x86 CPU's internal cache. AMDebug support provides product design team with different communication paths microcontroller, each which supported powerful debug tools from third-party vendors AMD's FusionE86 program.
Serial AMDebug technology uses serial connection based enhanced JTAG
protocol inexpensive 12-pin connector that placed each board design. This low-cost solution satisfies requirement large number software developers.
Parallel AMDebug technology uses parallel debug port exchange commands
data between microcontroller host. higher count requires that extra signal pins provided special bond-out package microcontroller, which only made available tool developers, such in-circuit emulator manufacturers. parallel AMDebug port greatly simplifies task supporting high speed data exchange.
Microcontroller User's Manual
Architectural Overview
1.3.3
Industry-Standard Interface (Chapter
microcontroller provides 33-MHz, 32-bit Revision 2.2-compliant host bridge interface, including integrated write-posting read-buffering capabilities suitable high-throughput applications. host bridge leverages standard peripherals software. also provides:
High throughput (132 Mbytes/s peak transfer rate) Deep buffering support burst transactions from masters SDRAM Flexible arbitration mechanism Support five external masters
1.3.4
High-Performance SDRAM Controller (Chapter
microcontroller provides integrated SDRAM controller that supports popular industry-standard synchronous DRAMs (SDRAM).
SDRAM controller interfaces with SDRAM chips well with most standard
DIMMs enable standard off-the-shelf memory components.
SDRAM controller supports programmable timing options provides required
external clock.
four 32-bit banks SDRAM supported with maximum capacity Mbytes. important reliability-enhancing Error Correction Code (ECC) feature built into
SDRAM controller. resultant increase memory content reliability enables microcontroller effectively utilized applications that require more reliable operation, such communications environments.
SDRAM controller contains write buffer read ahead buffer subsystem that
improves both write read performance.
SDRAM refresh options allow SDRAM contents maintained during reset.
1.3.5
ROM/Flash Controller (Chapter
microcontroller provides integrated controller glueless interfacing Flash devices. microcontroller supports types interfaces such devices-a simple interface 16-bit devices, interface SDRAM memory data higher performance 16-, 32bit devices. ROM/Flash controller:
Reduces system cost gluelessly interfacing static memory with three ROM/
Flash chip selects
Supports execute-in-place (XIP) operating systems applications that require
executing Flash memory instead DRAM
Supports high-performance page-mode devices
1.3.6
Flexible Address-Mapping (Chapter
addition memory management unit (MMU) within Am5x86 core, microcontroller provides Programmable Address Region (PAR) registers that enable flexible placement memory (SDRAM, ROM, Flash, SRAM, etc.) peripherals into address spaces Am5x86 (memory address space address space). hardware allows designers flexibly configure both address
Microcontroller User's Manual
Architectural Overview
spaces place memory and/or external peripherals, required application. internal memory-mapped configuration registers space also remapped accommodate system requirements. registers also allow control important attributes, such cacheability, write protection, code execution protection memory resources.
1.3.7
General-Purpose (GP) Interface (Chapter
microcontroller includes simple general-purpose (GP) that provides programmable timing allows connection 8/16-bit peripheral devices memory microcontroller. operates MHz, which offers good performance very interface cost. microcontroller provides eight chip selects external devices such off-the-shelf peripherals, custom ASICs, SRAM NVRAM. interface supports programmable timing dynamic width cycle stretching accommodate wide variety standard peripherals, such UARTs, 10-Mbit controller chips serial communications controllers. four external channels provide fly-by transfers between peripheral devices system SDRAM. Internally, used provide full complement integrated peripherals, such controller, programmable interrupt controller, timers, UARTs, described "Integrated Peripherals" page 1-7. These internal peripherals designed operate full clock rate bus. internal peripherals also configured operate PC/AT-compatible configuration, generally restricted this configuration. microcontroller provides view accesses internal peripherals external debugging purposes.
1.3.8
Clock Generation (Chapter
microcontroller offers user-configurable core clock speed operation different power/performance points depending application. microcontroller devices support clock rates. maximum supported clock rate device indicated part number printed package. clocking circuitry programmed device higher than rated speeds. However, microcontroller programmed higher clock speed than that which rated, then erroneous operation result, physical damage device occur. microcontroller includes on-chip oscillators PLLs, well most required loop filter components. microcontroller requires standard crystals, 32.768 MHz. clocks required inside microcontroller generated from these crystals. microcontroller also supplies clocks SDRAM bus; however, external clock buffering required some systems.
Note: microcontroller supports either 33.000-MHz 33.333-MHz crystal. this document, generic term MHz" refers system clock derived from whichever 33-MHz crystal frequency being used system.
Microcontroller User's Manual
Architectural Overview
1.3.9
Integrated Peripherals
microcontroller highly integrated single-chip with complete integrated peripherals that superset common PC/AT peripherals, plus memory-mapped peripherals that enhance usability various applications.
programmable interrupt controller (PIC) (see Chapter that provides capability
prioritize interrupt levels, these being external sources. programmed operate PC/AT-compatible mode, also contains extended features, including support more sources flexible routing that allows interrupt request steered input. Interrupt requests programmed generate either non-maskable interrupt (NMI) maskable interrupt requests.
integrated controller (see Chapter included transferring data between
SDRAM peripherals. GP-DMA controller operates single-cycle (flyby) mode more efficient transfers. GP-DMA controller programmed PC/AT compatibility, also contains enhanced features: double buffer-chaining mode provides more efficient software interface. Extended address transfer counts Flexible routing channels
Three general-purpose 16-bit timers (see Chapter that provide flexible cascading
extension 32-bit operation. These timers provide ability configure down resolution four clock periods where clock period 33-MHz clock. Timer input output pins provide ability interface with off-chip hardware.
standard PC/AT-compatible programmable interval timer (PIT) (see Chapter that
consists three 16-bit timers.
software timer (see Chapter that eases task keeping system time. provides
1-ms resolution also used performance monitoring.
watchdog timer (see Chapter guard against runaway software. real-time clock (RTC) with battery backup capability (see Chapter 20). also
provides bytes battery-backed storage configuration parameters.
integrated 16550-compatible UARTs (see Chapter that provide full handshaking
capability with eight pins each. Enhancements enable UARTs operate baud rates 1.152 Mbits/s. UARTs configured integrated controller transfer data between serial ports SDRAM.
synchronous serial interface (SSI) that compatible with SCP, SPI, Microwire
slave devices (see Chapter 22). interface configured either full-duplex half-duplex operation using 4-wire 3-wire interface.
programmable pins provided (see Chapter 23). These pins multiplexed
with other peripherals interface functions.
microcontroller also provides PC/AT-compatible functions control
gate soft reset (Ports 0060h, 0064h, 0092h).
1.3.10
JTAG Boundary Scan Test Interface (Chapter
microcontroller provides full JTAG test port that compliant with IEEE 1149.1-1990 during board testing.
Microcontroller User's Manual
Architectural Overview
1.3.11
System Testing Debugging Features (Chapter
facilitate debugging, microcontroller provides observability many portions internal operation, including:
three-pin interface that used either system test mode write buffer test
mode, determining internal initiators SDRAM cycles, determining when SDRAM data valid interface. additional mode provides observability integrated peripheral accesses.
nonconcurrent arbitration mode reduce debug complexity when masters
initiators also accessing SDRAM.
cache control dynamic core clock speed control under program control. Ability disable write posting read prefetching SDRAM controller simplify
tracing SDRAM cycles.
Notification memory write protection non-executable memory region violations.
APPLICATIONS
figures following pages show microcontroller might used several reference design applications data communications, information appliances, telecommunication markets.
1.4.1
Smart Residential Gateway
Figure page 1-10 shows microcontroller-based Smart Resident Gateway (SRG), which router home network between wide area network (WAN) (the internet) local area network (LAN) intranet computers information appliances home). provides firewall protection from unauthorized access through internet. common internet access medium shared users LAN. variety connections possible both LAN. example, connection V.90 modem, cable modem, ISDN, ADSL, Ethernet. connection
HomePNA-Home Phoneline Networking Alliance, alliance with widely endorsed
home networking specification
Bluetooth-a computing telecommunications industry specification that describes
computing devices easily interconnect with each other with home business phones computers using short-range wireless connection)
Home RF-a standard competing with Bluetooth interconnection computing
devices using radio frequency
Ethernet-local area network technology Power line-a using power distribution network home business
interconnect devices. Digital information transmitted high-frequency carrier signal power.
1.4.2
Thin Client
Figure page 1-11 shows microcontroller-based "thin client," which modern replacement traditional terminal remote computing paradigm. Application programs remotely server, data warehoused centrally managed disks "server farm." efficient communications protocol transmits
Microcontroller User's Manual
Architectural Overview
keyboard mouse commands upstream transmits video BIOS calls downstream. thin client renders displays graphics user. thin client typically connected Ethernet LAN, although remote location connect server connection such modem. minimum speed kbaud required communication protocol, unless application graphics-intensive, which case faster connection required.
1.4.3
Digital
Figure page 1-12 shows microcontroller-based digital (DSTB), which consumer client device that uses television display. Common applications DSTB internet access, e-mail, streaming audio video content. minimal system includes connection modem, ADSL, cable modem; output InfraRed (IR) link remote control wireless keyboard. Expanded systems include drives MPEG2 decoders deliver digital video content. hard drive employed store video data future replay. Keyboard, mouse, printer, video camera options that included.
1.4.4
Telephone Line Concentrator
Figure page 1-13 shows microcontroller-based telephone line concentrator located neighborhood that converts multiple analog subscriber loops into high-speed digitally multiplexed line connection central office switching network.
Microcontroller User's Manual
Architectural Overview Figure Microcontroller-Based Smart Residential Gateway Reference Design
RJ-11
RJ-11
RJ-45
Interface ADSL, Cable Modem V.90
RJ-45
PCnetTM-Home
Interface Am79C978
AD31-AD0
MD31-MD0 Control
Microcontroller
GPD15-GPD0 Control
1-10
Microcontroller User's Manual
33-MHz Crystal
32-kHz Crystal
Flash
MA12-MA0 SDRAM SDRAM
Control GPA25-GPA0
Architectural Overview Figure Microcontroller-Based Thin Client Reference Design
VGA/LCD
CRT/LCD
Controller
PS/2 Keyboard
PS/2 Mouse
Parallel Super
Interface Am79C973/Am79C975 PCnetTM-Fast
RJ-45
AD31-AD0
Control
Control
MA12-MA0 SDRAM SDRAM MD31-MD0 GPD15-GPD0 GPA25-GPA0 Flash Memory
Microcontroller
Control
Control
Microcontroller User's Manual
33-MHz Crystal
32-kHz Crystal
Serial
1-11
Architectural Overview Figure Microcontroller-Based Digital Reference Design
NTSC/PAL
PS/2 Keyboard
PS/2 Mouse
Parallel Super
Interface ADSL, Cable Modem V.90
RJ-11
AD31-AD0
Control
MA12-MA0 SDRAM SDRAM GPD15-GPD0 Flash Memory
MD31-MD0
Control
Microcontroller
GPA25-GPA0
Control
Control
33-MHz Crystal
32-kHz Crystal
1-12
Microcontroller User's Manual
EIDE
GPD15-GPD0
GPA1-GPA0
Control
Figure
ISLIC Am79R241
SDRAM Quad ISLAC Am79Q2241 ISLIC Am79R241 ISLIC Am79R241
ISLIC Am79R241
Analog Phone Lines
MD31-MD0
SDRAM
MA12-MA0
Control
33-MHz Crystal
10X)
Highway
32-kHz Crystal
ISLIC Am79R241 ISLIC Am79R241 Quad ISLAC Am79Q2241 Control ISLIC Am79R241 ISLIC Am79R241
Architectural Overview
Microcontroller-Based Telephone Line Concentrator Reference Design
Microcontroller User's Manual
Microcontroller HDLC GPD15-GPD0 Flash Memory GPA25-GPA0 Control T1/E1 Interface
1-13
Architectural Overview
1-14
Microcontroller User's Manual
CHAPTER
INFORMATION
OVERVIEW
microcontroller contains signal pins plus power ground signals. minimal number signals shared with others. signals organized alphabetically within following functional groups:
Synchronous DRAM controller (page 2-5) ROM/Flash controller (page 2-6) (page 2-6) General-purpose (GP) (page 2-7) Serial ports (page 2-9) Timers (page 2-10) Clocks reset (page 2-10) Chip selects (page 2-11) Programmable (PIO) (page 2-11) JTAG boundary scan test interface (page 2-12) AMDebug interface (page 2-12) System test (page 2-12) Configuration (page 2-13) Power (page 2-14)
LOGIC SYMBOLS
Figure shows logical symbol device, with pins grouped function interface. Figure shows logical symbol with pins grouped default function. Figure also shows multiplexing microcontroller.
Microcontroller User's Manual
Information Figure Logic Diagram Interface1
GPA25-GPA0
GPD15-GPD0 AD31-AD0 CBE3-CBE0 SERR PERR FRAME TRDY IRDY STOP DEVSEL CLKPCIOUT CLKPCIIN INTA-INTD REQ4-REQ0 GNT4-GNT0 GPRESET GPIORD GPIOWR GPMEMRD GPMEMWR GPALE GPBHE GPRDY GPAEN GPTC GPDRQ3-GPDRQ0 GPDACK3-GPDACK0 GPIRQ10-GPIRQ0 GPDBUFOE GPIOCS16 GPMEMCS16
SDRAM
MA12-MA0 BA1-BA0 MD31-MD0 SCS3-SCS0 CLKMEMOUT CLKMEMIN SRASA-SRASB SCASA-SCASB SWEA-SWEB SDQM3-SDQM0 MECC6-MECC0
GPCS7-GPCS0 GPA25-GPA0* GPD15-GPD0* MD31-MD0* BOOTCS ROMCS2-ROMCS1 ROMRD FLASHWR ROMBUFOE TMRIN1-TMRIN0 TMROUT1-TMROUT0
ROM/Flash
Timers
Serial Ports: UART UART
SOUT2-SOUT1 SIN2-SIN1 RTS2-RTS1 CTS2-CTS1 DSR2-DSR1 DTR2-DTR1 DCD2-DCD1 RIN2-RIN1 SSI_CLK SSI_DO SSI_DI
PITGATE2 PITOUT2 JTAG_TRST JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS CMDACK BR/TC STOP/TX TRIG/TRACE WBMSTR2-WBMSTR0 CF_DRAM
JTAG
AMDebug
Programmable Input/Output Clocks Reset
PIO31-PIO0
System Test
32KXTAL2-32KXTAL1 33MXTAL2-33MXTAL1 LF_PLL1 CLKTIMER CLKTEST PWRGOOD PRGRESET BBATSEN
DATASTRB CF_ROM_GPCS DEBUG_ENTER INST_TRCE AMDEBUG_DIS CFG3-CFG0 RSTLD7-RSTLD0
Configuration
Notes: Pins noted with asterisks duplicated this diagram clarify which signals used each interface.
Microcontroller User's Manual
Information Figure
Logic Diagram Default Function1
AD31-AD0 CBE3-CBE0 SERR PERR FRAME TRDY IRDY STOP DEVSEL CLKPCIOUT CLKPCIIN INTA-INTD REQ4-REQ0 GNT4-GNT0 MA12-MA0 GPA25 {DEBUG_ENTER} GPA24 {INST_TRCE} GPA23 {AMDEBUG_DIS} GPA22-GPA15 {RSTLD7-RSTLD0} GPA13-GPA0 GPD15-GPD0 GPRESET GPIORD GPIOWR GPMEMRD GPMEMWR PIO0 [GPALE] PIO1 [GPBHE] PIO2 [GPRDY] PIO3 [GPAEN] PIO4 [GPTC] PIO5-PIO8 [GPDRQ3-GPDRQ0] PIO9-PIO12 [GPDACK3-GPDACK0] PIO13-PIO23 [GPIRQ10-GPIRQ0] PIO24 [GPDBUFOE] PIO25 [GPIOCS16] PIO26 [GPMEMCS16] PIO27 [GPCS0]
SDRAM
BA1-BA0 MD31-MD0 SCS3-SCS0 CLKMEMOUT CLKMEMIN SRASA-SRASB SCASA-SCASB SWEA-SWEB SDQM3-SDQM0 MECC6-MECC0 SOUT2-SOUT1 SIN2-SIN1 RTS2-RTS1 CTS1 DSR1 DTR2-DTR1 DCD1 RIN1 PIO28 [CTS2] PIO29 [DSR2] PIO30 [DCD2] PIO31 [RIN2] SSI_CLK SSI_DO SSI_DI
GPA25-GPA0* GPD15-GPD0* MD31-MD0* BOOTCS ROMCS2-ROMCS1 [GPCS2-GPCS1] ROMRD
ROM/Flash
Serial Ports: UART UART
FLASHWR ROMBUFOE
TMRIN1-TMRIN0 [GPCS4-GPCS5] TMROUT1-TMROUT0 [GPCS6-GPCS7] PITGATE2 [GPCS3] PITOUT2 {CFG3}
Timers
JTAG_TRST JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS
JTAG
CMDACK BR/TC
AMDebug
Clocks Reset
32KXTAL2-32KXTAL1 32MXTAL2-32MXTAL1 LF_PLL1 CLKTIMER [CLKTEST] PWRGOOD PRGRESET BBATSEN
STOP/TX TRIG/TRACE
CF_DRAM [WBMSTR2] {CFG2} DATASTRB [WBMSTR1] {CFG1} CF_ROM_GPCS [WBMSTR0] {CFG0}
System Test
Notes: names bold indicate default function. Brackets, indicate alternate, multiplexed functions. Braces, indicate pinstrap pins. Pins noted with asterisks duplicated this diagram clarify which signals used each interface.
Microcontroller User's Manual
Information
SIGNAL DESCRIPTIONS
Table describes terms used signal description table. general, brackets, indicate alternate, multiplexed functions, braces, indicate reset configuration pins (pinstraps). line over name indicates active signal. word refers physical wire; word signal refers electrical signal that flows through Table 2-2, "Signal Descriptions" page contains description microcontroller signals. descriptions Table organized functional group. Table describes signals that available each interface which signals shared with others. Signal sharing also shown Figure 2-2. Detailed information state, including maximum load values, power-on reset default function, reset state, power-on reset default operation, hold state, voltage, available Microcontroller Data Sheet, order #22003. Connection package diagrams, well number assignments, also included that document.
Table
Signal Descriptions Table Definitions Term signal SIGNAL Signal Types Analog O/TS OD-O
Power STI-OD
Definition Indicates alternate function; defaults signal named without brackets. Indicates reset configuration (pinstrap). Refers physical wire. Refers electrical signal that flows across pin. line over signal name indicates that signal active Low; signal name without line active High. Analog voltage Bidirectional High Input Programmable hold last state Totem pole output Totem pole output/three-state output Open-drain output Open-drain output totem pole output Oscillator Internal pulldown resistor (~100-150
Power pins Internal pullup resistor (~100-150 Schmitt trigger input Schmitt trigger input open-drain output Three-state output
General Terms
Microcontroller User's Manual
Information Table Signal
BA1-BA0 CLKMEMIN
Signal Descriptions Multiplexed Signal
Type
Description
Bank Address SDRAM bank address bus. SDRAM Clock Input SDRAM clock return signal used minimize skew between internal SDRAM clock CLKMEMOUT signal provided SDRAM devices. This signal compensates buffer load delays introduced board design. SDRAM Clock Output 66-MHz clock that provides clock signalling synchronous DRAM devices. This clock require external skew buffer system implementations that result heavy loading SDRAM clock signal. SDRAM Address SDRAM multiplexed address bus. SDRAM Data inputs data during SDRAM read cycles outputs data during SDRAM write cycles. Memory Error Correction Code contains checksum (syndrome) bits used validate correct data errors. Column Address Strobes used combination with SRASA- SRASB SWEA-SWEB encode SDRAM command type. SCASA SCASB same signal provided different pins reduce total load connected CAS. Suggested system connection: SCASA SDRAM banks SCASB SDRAM banks SDRAM Chip Selects SDRAM chip-select outputs. These signals asserted select bank SDRAM devices. chipselect signals enable SDRAM devices decode commands asserted SRASA-SRASB, SCASA-SCASB, SWEA-SWEB. Data Input/Output Masks make SDRAM data output high-impedance blocks data input SDRAM while active. Each four SDQM3-SDQM0 signals associated with byte four throughout array. Each SDQMx signal provides input mask signal write accesses output enable signal read accesses. Address Strobes used combination with SCASA- SCASB SWEA-SWEB encode SDRAM command type. SRASA SRASB same signal provided different pins reduce total load connected RAS. Suggested system connection: SRASA SDRAM banks SRASB SDRAM banks SDRAM Memory Write Enables used combination with SRASA-SRASB SCASA-SCASB encode SDRAM command type. SWEA SWEB same signal provided different pins reduce total load connected Suggested system connection: SWEA SDRAM banks SWEB SDRAM banks
Synchronous DRAM Controller
CLKMEMOUT
MA12-MA0 MD31-MD0 MECC6-MECC0 SCASA-SCASB
SCS3-SCS0
SDQM3-SDQM0
SRASA-SRASB
SWEA-SWEB
Microcontroller User's Manual
Information Table Signal
BOOTCS
Signal Descriptions (Continued) Multiplexed Signal
Type
Description
ROM/Flash Boot Chip Select active output that provides chip select startup and/or ROM/Flash array (BIOS, HAL, O/S, etc.). BOOTCS signal asserts accesses made 64-Kbyte segment that contains Am5x86 boot vector: addresses 3FF0000h-3FFFFFFh. addition this linear decode region, BOOTCS asserts response accesses userprogrammable address regions. Flash Write indicates that current cycle write selected Flash device. When this signal asserted, selected Flash device latch data from data bus. General-Purpose Address provides address system's ROM/Flash devices. also address devices. Twenty-six address lines provide maximum addressable space Mbytes each chip select. General-Purpose Data inputs data during memory read cycles outputs data during memory write cycles. reset configuration (CFG2) allows used boot chip-select interface. Configuration registers used select whether ROMCS2 ROMCS1 data data bus. data supports 16-bit 8-bit interfaces. data buses selectable facilitate mixed voltage system. Memory Data inputs data during SDRAM read cycles outputs data during SDRAM write cycles. Configuration registers used select whether ROMCS2 ROMCS1 data data bus. reset configuration (CFG2) allows data used BOOTCS. memory data supports 16-, 32-bit interface. Buffer Output Enable optional signal used enable buffer ROM/Flash devices they need isolated from microcontroller, other devices, SDRAM system voltage loading considerations. This signal asserts accesses through controller. buffer direction controlled ROMRD FLASHWR signal. ROM/Flash Chip Selects signals that programmed asserted accesses user-programmable address regions. ROM/Flash Read indicates that current cycle read selected ROM/Flash device. When this signal asserted, selected device drive data onto data bus.
ROM/Flash Controller
FLASHWR
GPA25-GPA0
GPD15-GPD0
MD31-MD0
ROMBUFOE
ROMCS2 ROMCS1 ROMRD
[GPCS2] [GPCS1]
Peripheral Component Interconnect (PCI)
AD31-AD0 CBE3-CBE0 Address Data time-multiplexed address/data bus. Command Byte-Enable functions time-multiplexed command that defines type transaction bus, byte enables: CBE0 AD7-AD0 CBE1 AD15-AD8 CBE2 AD23-AD16 CBE3 AD31-AD24 Clock Input 33-MHz clock. This connected CLKPCIOUT systems where microcontroller source clock.
CLKPCIIN
Microcontroller User's Manual
Information Table Signal
CLKPCIOUT
Signal Descriptions (Continued) Multiplexed Signal
Type
Description
Clock Output 33-MHz clock output devices. This signal derived from 33MXTAL2-33MXTAL1 interface. Device Select asserted target when decoded address target current transaction. Frame driven transaction initiator indicate start duration transaction. Grants asserted microcontroller grant access bus. Interrupt Requests asserted request interrupt. These four interrupts same type interrupt GPIRQ10-GPIRQ0 signals, they same interrupt controller. They named INTx match common interrupt naming convention. Configuration registers allow inversion these interrupt requests recognize active interrupt requests. These interrupt requests routed generate NMI. Initiator Ready asserted current master indicate that data ready (write) that master ready accept data (read). Parity driven initiator target indicate parity AD31-AD0 CBE3-CBE0 buses. Parity Error asserted indicate data parity error previous clock cycle. Requests asserted master request access bus. Reset asserted reset devices. System Error used reporting address parity errors other system error where result catastrophic. Stop asserted target request that current transaction stopped. Target Ready asserted currently addressed target indicate ability complete current data phase transaction.
DEVSEL FRAME GNT4-GNT0 INTA-INTD
IRDY
PERR REQ4-REQ0 SERR STOP TRDY
General-Purpose (GP)
GPA14-GPA0 GPA15 GPA16 GPA17 GPA18 GPA19 GPA20 GPA21 GPA22 GPA23 GPA24 GPA25 {RSTLD0} {RSTLD1} {RSTLD2} {RSTLD3} {RSTLD4} {RSTLD5} {RSTLD6} {RSTLD7} {AMDEBUG_DIS} {INST_TRCE} {DEBUG_ENTER} O{I} O{I} O{I} O{I} O{I} O{I} O{I} O{I} O{I} O{I} O{I} General-Purpose Address outputs physical memory port address. Twenty-six address lines provide maximum addressable space Mbytes. This also provides address system's ROM/Flash devices.
Microcontroller User's Manual
Information Table Signal
[GPAEN]
Signal Descriptions (Continued) Multiplexed Signal
PIO3
Type
Description
Address Enable indicates that current address GPA25-GPA0 address memory address, that current cycle cycle. devices should this signal decoding their addresses should respond when this signal asserted. When GPAEN asserted, GPDACKx signals used select appropriate device transfer. GPAEN also asserts when cycle occurring internally. Address Latch Enable driven beginning cycle with valid address. This signal used external devices latch address current cycle. Byte High Enable driven active when data transferred upper bits data bus. General-Purpose Data inputs data during memory read cycles, outputs data during memory write cycles. Acknowledge each mapped seven available channels. They asserted active acknowledge corresponding requests.
[GPALE]
PIO0
[GPBHE] GPD15-GPD0 [GPDACK0] [GPDACK1] [GPDACK2] [GPDACK3] [GPDBUFOE]
PIO1 PIO12 PIO11 PIO10 PIO9 PIO24
Data Buffer Output Enable used control output enable external transceiver that data bus. Using this transceiver optional system design necessary only alleviate loading voltage issues. This asserted external accesses. asserted during accesses internal peripherals even echo mode enabled. Note that configured data bus, then bytes controlled this buffer enable; they controlled ROMBUFOE signal. Request each mapped seven available channels. They asserted active High request service.
[GPDRQ0] [GPDRQ1] [GPDRQ2] [GPDRQ3] [GPIOCS16] GPIORD
PIO8 PIO7 PIO6 PIO5 PIO25
Chip-Select driven active early cycle targeted device request 16-bit transfer. Read indicates that current cycle read currently addressed device bus. When this signal asserted, selected device drive data onto data bus. Write indicates that current cycle write currently addressed device bus. When this signal asserted, selected device latch data from data bus.
GPIOWR
Microcontroller User's Manual
Information Table Signal
[GPIRQ0] [GPIRQ1] [GPIRQ2] [GPIRQ3] [GPIRQ4] [GPIRQ5] [GPIRQ6] [GPIRQ7] [GPIRQ8] [GPIRQ9] [GPIRQ10] [GPMEMCS16]
Signal Descriptions (Continued) Multiplexed Signal
PIO23 PIO22 PIO21 PIO20 PIO19 PIO18 PIO17 PIO16 PIO15 PIO14 PIO13 PIO26
Type
Description
Interrupt Request each mapped available interrupt channels NMI. They asserted when peripheral requires interrupt service. Configuration registers allow inversion these interrupt requests recognize active interrupt requests. These interrupt requests routed generate NMI.
Memory Chip-Select driven active early cycle targeted memory device request 16-bit memory transfer. Memory Read indicates that current cycle read selected memory device. When this signal asserted, selected memory device drive data onto data bus. Memory Write indicates that current cycle write selected memory device. When this signal asserted, selected memory device latch data from data bus. Ready driven open-drain devices. When pulled during access, wait states inserted current cycle. This internal weak pullup that should supplemented stronger external pullup faster rise time. Reset, when asserted, re-initializes reset state devices connected bus. Terminal Count driven from internal controller indicate that transfer count currently active channel reached zero, that current cycle last transfer.
[GPMEMRD]
[GPMEMWR]
[GPRDY]
PIO2
GPRESET [GPTC] PIO4
Serial Ports
CTS1 CTS2 DCD1 [DCD2] DSR1 [DSR2] DTR2-DTR1 RIN1 [RIN2] RTS2-RTS1 SIN2-SIN1 SOUT2-SOUT1 PIO31 PIO29 PIO30 PIO28 Clear Send driven back serial port indicate that external data carrier equipment (DCE) ready accept data. Data Carrier Detect driven back serial port from piece when detected carrier signal from communications target. Data Ready used indicate that external ready establish communication link with internal serial port controller. Data Terminal Ready indicates external that internal serial port controller ready communicate. Ring Indicate used external modem inform serial port that ring signal detected. Request Send indicates external that internal serial port controller ready send data. Serial Data used receive serial data from external serial device into internal serial port controller. Serial Data used transmit serial data from internal serial port controller external serial device DCE.
Microcontroller User's Manual
Information Table Signal
SSI_CLK
Signal Descriptions (Continued) Multiplexed Signal
Type
Description
Clock driven microcontroller port during active transmit receive transactions. idle state clock assertion/sample edge configurable. Data Input receives incoming data from peripheral device port. Data shifted opposite SSI_CLK signal edge which SSI_DO drives data. SSI_DO SSI_DI tied together interface three-pin peripheral. Data Output drives data peripheral device port. Data driven opposite SSI_CLK signal edge which SSI_DI latches data. signal normally high-impedance when transmit transaction active port.
SSI_DI
SSI_DO
Timers
PITGATE2 PITOUT2 TMRIN0 TMRIN1 TMROUT0 TMROUT1 [GPCS3] {CFG3} [GPCS5] [GPCS4] [GPCS7] [GPCS6] O{I} Programmable Interval Timer Gate provides control Channel Programmable Interval Timer Output output from Channel This signal typically used speaker signal. Timer Inputs programmed control clock general-purpose (GP) timers Timer Outputs outputs from timers. These outputs used pulse-width modulation signals.
Clocks Reset
32KXTAL2- 32KXTAL1 32.768-kHz Crystal Interface used connecting external crystal oscillator microcontroller. This clock source used clock real-time clock (RTC). addition, internal PLLs generate clocks timers UARTs based this clock source. When external oscillator used, 32KXTAL1 should grounded clock source driven 32KXTAL2. 33-MHz Crystal Interface main system clock chip. This clock source used derive SDRAM, CPU, clocks. When external oscillator used, 33MXTAL1 should unconnected clock source driven 33MXTAL2. Test Clock Output shared that allows many internal clocks driven externally. CLKTEST drive internal clocks UARTs, PLL1, PLL2, programmable interval timer (PIT), real-time clock (RTC) testing driving external device. Timer Clock Input shared clock that used input frequency programmable interval timer (PIT). Loop Filter Interface used connecting external loop filter components. Component values circuit descriptions contained Microcontroller Data Sheet, order #22003. Programmable Reset programmed reset microcontroller, allow SDRAM refresh continue during reset. This allows system reset without losing information stored SDRAM. power-up, PRGRESET disabled must programmed operational. When disabled, this effect microcontroller. Power Good reset signal that indicates microcontroller that levels within normal operation range. used reset entire chip must held second after signals (except VCC_RTC) chip High. This signal must returned before signals degrade into correct state operation RTC-only mode.
33MXTAL2- 33MXTAL1
[CLKTEST]
CLKTIMER
CLKTIMER LF_PLL1
[CLKTEST]
PRGRESET
PWRGOOD
2-10
Microcontroller User's Manual
Information Table Signal Chip Selects
[GPCS0] [GPCS1] [GPCS2] [GPCS3] [GPCS4] [GPCS5] [GPCS6] [GPCS7] PIO27 ROMCS1 ROMCS2 PITGATE2 TMRIN1 TMRIN0 TMROUT1 TMROUT0 General-Purpose Chip Select signals bus. They used either memory accesses. These chip selects asserted Am5x86 accesses corresponding regions Programmable Address Region (PAR) registers.
Signal Descriptions (Continued) Multiplexed Signal Type Description
Programmable (PIO)
PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 PIO28 PIO29 PIO30 PIO31 [GPALE] [GPBHE] [GPRDY] [GPAEN] [GPTC] [GPDRQ3] [GPDRQ2] [GPDRQ1] [GPDRQ0] [GPDACK3] [GPDACK2] [GPDACK1] [GPDACK0] [GPIRQ10] [GPIRQ9] [GPIRQ8] [GPIRQ7] [GPIRQ6] [GPIRQ5] [GPIRQ4] [GPIRQ3] [GPIRQ2] [GPIRQ1] [GPIRQ0] [GPDBUFOE] [GPIOCS16] [GPMEMCS16] [GPCS0] [CTS2] [DSR2] [DCD2] [RIN2] Programmable Input/Output signals programmed inputs outputs. When they outputs, they driven High programming bits registers.
Microcontroller User's Manual
2-11
Information Table Signal
JTAG_TCK JTAG_TDI
Signal Descriptions (Continued) Multiplexed Signal
Type
Description
Test Clock input clock test access port. Test Data Input serial input stream input data. This weak internal pullup resistor. sampled rising edge JTAG_TCK. driven, this input sampled High internally. Test Data Output serial output stream result data. high-impedance state except when scanning progress. Test Mode Select input controlling test access port. This weak internal pullup resistor. driven, sampled High internally. JTAG Reset test access port (TAP) reset. This weak internal pulldown resistor. driven, this input sampled internally causes controller logic remain reset state.
JTAG Boundary Scan Test Interface
JTAG_TDO JTAG_TMS
O/TS
JTAG_TRST
AMDebug Interface
BR/TC Break Request/Trace Capture requests entry AMDebug technology mode. AMDebug technology serial/parallel interface reconfigure this turn instruction trace capture off. Command Acknowledge indicates command completion status. asserted High when in-circuit emulator logic ready receive commands from host. driven when in-circuit emulator core executing command from host remains until command completed. Stop/Transmit asserted High entry AMDebug mode. During normal mode, this High when there data transmitted host (during operating system/application communication). Trigger/Trace triggers event logic analyzer (optional, from Am5x86 debug registers).The AMDebug technology serial/parallel interface reconfigure this indicate trace status.
CMDACK
STOP/TX
TRIG/TRACE
System Test
CF_DRAM [WBMSTR2] {CFG2} O{I} Code Fetch SDRAM, during SDRAM reads, provides code fetch status. When Low, this indicates that current SDRAM read code fetch demanded CPU, read prefetch initiated demand code fetch CPU. When High during reads, this indicates that SDRAM read code fetch, could have been initiated CPU, master, GP-DMA controller, either demand prefetch. During SDRAM write cycles this provides indication source data, either GP-DMA controller/PCI master CPU. When High, this indicates that either initiator external master contributed current SDRAM write cycle (the also have contributed). indicates that only master that contributed this write cycle. Code Fetch ROM/GPCS provides indication that performing code fetch from either SDRAM data bus), from GPCSx pin. When during read cycle indicated either GPMEMRD ROMRD), performing code fetch from chip select. other times (including writes), this signal High. Data Strobe debug signal that asserted allow external system latch SDRAM data. This used trace data SDRAM interface with in-circuit emulator probe logic analyzer.
CF_ROM_GPCS
[WBMSTR0] {CFG0}
O{I}
DATASTRB
[WBMSTR1] {CFG1}
O{I}
2-12
Microcontroller User's Manual
Information Table Signal
[WBMSTR0]
Signal Descriptions (Continued) Multiplexed Signal
CF_ROM_GPCS {CFG0}
Type
O{I}
Description
Write Buffer Master indicates which block(s) wrote rank write buffer (during SDRAM write cycles) which block reading from SDRAM (during SDRAM read cycles). WBMSTR0, when logical indicates that internal controller contributed write buffer rank (write cycles) reading from SDRAM (read cycles). WBMSTR1, when logical indicates that master contributed write buffer rank (write cycles) reading from SDRAM (read cycles). WBMSTR2, when logical indicates that contributed write buffer rank (write cycles) reading from SDRAM (read cycles).
[WBMSTR1]
DATASTRB {CFG1} CF_DRAM {CFG2}
O{I}
[WBMSTR2]
O{I}
Configuration
{AMDEBUG_DIS} GPA23 AMDebug Disable active High configuration signal latched assertion Power Good (PWRGOOD). This built-in pulldown resistor. Power Good assertion: Normal operation, mode enabled software. High AMDebug mode disabled cannot enabled software. Configuration Inputs latched into chip when PWRGOOD asserted. These signals shared with other features. These signals have built-in pulldown resistors. CFG0: Choose 16-, 32-bit ROM/Flash interface BOOTCS. CFG1: Choose 16-, 32-bit ROM/Flash interface BOOTCS. CFG1 {CFG2} CF_DRAM [WBMSTR2] CFG0 (don't care) BOOTCS Data Width 8-bit 16-bit 32-bit
{CFG0}
CF_ROM_GPCS [WBMSTR0]
{CFG1}
DATASTRB [WBMSTR1]
CFG2: When when PWRGOOD asserted, microcontroller uses data BOOTCS. When seen High during PWRGOOD assertion, BOOTCS access across SDRAM data bus. Default built-in pulldown resistor). CFG3 (Internal test mode enable): normal microcontroller operation, pull High during reset. Enter AMDebug Mode active High configuration signal latched assertion Power Good (PWRGOOD). This enables AMDebug mode, which causes processor fetch execute instruction from BOOTCS device, then enter AMDebug mode where waits debug commands delivered JTAG port. This built-in pulldown resistor. PWRGOOD assertion: High AMDebug mode enabled Normal operation Instruction Trace active High configuration signal latched assertion Power Good (PWRGOOD). Enables trace record generation from Power Good assertion. This built-in pulldown resistor. PWRGOOD assertion: High Trace controller enabled output trace records Normal operation
{CFG3} {DEBUG_ENTER}
PITOUT2 GPA25
{INST_TRCE}
GPA24
Microcontroller User's Manual
2-13
Information Table Signal
{RSTLD0} {RSTLD1} {RSTLD2} {RSTLD3} {RSTLD4} {RSTLD5} {RSTLD6} {RSTLD7}
Signal Descriptions (Continued) Multiplexed Signal
GPA15 GPA16 GPA17 GPA18 GPA19 GPA20 GPA21 GPA22
Type
Description
Reset Latched Inputs shared signals that latched into register when PWRGOOD asserted. They used input static information software (i.e., board revision). These signals have builtin pulldown resistors.
Power
BBATSEN Analog Backup Battery Sense which real-time clock (RTC) backup battery voltage sampled each time PWRGOOD asserted. this samples below Valid Time (VRT) index cleared until read. After read, until BBATSEN sensed subsequent PWRGOOD assertion. BBATSEN also provides power-on-reset signal when backup battery applied first time. Analog Power Supply analog circuits (PLLs). Power Supply microcontroller core logic. Power Supply ring. Power Supply real-time clock 32-kHz oscillator. Digital Ground remaining microcontroller core logic. Analog Ground analog circuits.
VCC_ANLG VCC_CORE VCC_I/O VCC_RTC GND_ANLG
Power Power Power Power Power Power
2-14
Microcontroller User's Manual
CHAPTER
SYSTEM INITIALIZATION
OVERVIEW
This chapter provides information guidelines initializing microcontroller. Several source code examples information described this chapter available site. This CodeKit software tested source code example applications. obtain this software, well other product information tools, access home page www.amd.com follow Embedded Processors link. From software perspective, types systems that developed with microcontroller fall into broad categories, native embedded systems systems that BIOS1. course, these only types systems that built with microcontroller. quite possible develop hybrid systems that have BIOS "desktop" operating system like Windows®, DOS, Unix, Linux. While there many possible ways initialize microcontroller, initialization sequence derived from following techniques.
System initialization with BIOS System initialization native embedded system without BIOS
systems with BIOS, most, all, system initialization done BIOS while system running real mode. After initialization, BIOS loads operating system application from nonvolatile media, which generally disk drive, could Flash memory other media. operating system application begins operating real mode then make transition into protected mode. Windows Windows examples such operating systems. Real-time operating systems also operate this manner. BIOS initialization complex. Some BIOS products make temporary transition into protected mode perform certain operations then revert back real mode, before passing execution operating system application. Such behavior dependent BIOS written features provided beyond scope this discussion. embedded systems, initialization sequence usually much simpler generally occurs primarily protected mode. this scenario, processor comes from reset transitions into protected mode soon possible. only real-mode code system code required jump from reset vector execute code that causes microcontroller transition into protected mode.
3.1.1
Native Embedded Initialization Sequence
Many systems designed with microcontroller native embedded systems that have BIOS. software architecture such systems take many forms.
BIOS software component. real-mode code that responsible initializing system providing standard system services used operating system application level software. These services provided standard interface. Microcontroller User's Manual
System Initialization
Some commercial real-time operating system (RTOS), custom RTOS, simple `main loop' non-preemptive executive. general, executive RTOS generally interfaces hardware using hardware dependent layer called board support package (BSP)1. general, system initialization flow native embedded system follows this sequence:
Reset event Near Jump reset handler from reset vector Switch simple protected mode Determine cause reset Initialize DRAM controller DRAM. Size DRAM Setup Stack begin execution from code (NOT Execute-In-Place) then Copy Operating System DRAM Jump operating system's entry point Global Descriptor Table (GDT), Local Descriptor Table (LDT), Interrupt Descriptor Table (IDT), fault handlers, page tables, Task State Segment (TSS) operating system, application executive. processor speed Configure timings Configure multiplexing Configure chip selects Configure Programmable Address Region (PAR) registers Configure interrupt mappings Configure programmable (PIO) pins Configure controller arbitration mode Initialize periodic timer interrupt necessary) Now, initialize devices external microcontroller otherwise continue start operating system, drivers application.
above example, switch simple protected mode (line sets processor register descriptor cache. This disables redirection reset region reset segment (see "Reset Vector Reset Segment" page more information). line above, term simple protected mode means that protected mode environment (GDT, LDT, IDT, TSS) simplest kind possible. example, both empty contain minimal information. alternatively, empty. This means that exceptions cannot handled, this should problem short period that initialization code runs. More importantly, simple protected mode contained read-only memory (usually Flash) have created runtime. Once DRAM operational, then more extensive GDT, LDT, tables more appropriate setup DRAM.
There standard term this component. Other terms Adaptation Layer (OAL), Hardware Adaptation Layer (HAL), Porting Layer. like BIOS, almost always unique specific executive RTOS. This especially true comercially available RTOS products. vendor's RTOS generally does work with products from another vendor. Also, where BIOS most often 16-bit real-mode entity, usually 32-bit protected mode entity. Lastly, operating systems applications always communicate with BIOS using software interrupts other run-time mechanisms), often linked directly executive application form single executable called directly using CALL instruction. Microcontroller User's Manual
System Initialization
Some embedded systems execute from read-only memory (usually Flash) only DRAM data storage. This style system architecture supported most RTOS products. This reflected line Systems that execute Flash memory need copy operating system and/or application DRAM. Another interesting point that once DRAM controller initialized, then initialization code setup stack finish reset work high-level language (usually
3.1.2
BIOS Initialization Sequence
contrast native embedded system, flow system initialization with BIOS generally follows this sequence:
Reset event Near Jump reset handler from reset vector Memory-Mapped Configuration Region (MMCR) address below 0010FFEFh (real-mode address limit) Determine cause reset Initialize DRAM controller DRAM. Size DRAM, record CMOS Copy BIOS into DRAM (shadowing) Execute Jump within BIOS code start execution shadowed BIOS copy instead copy basic interrupt handlers processor faults Detect display console processor speed Configure timings Configure multiplexing Configure chip selects Configure Programmable Address Region (PAR) registers Configure interrupt mappings Configure programmable (PIO) pins Configure controller arbitration Now, BIOS continue with standard PC-style system initialization
There some important contrasts between steps system with BIOS those native embedded system.
Steps through done real mode while executing from reset segment before
executing first Jump (JMP) instruction. This contrast initialization native embedded system, which transitions simple protected mode before these steps.
Memory-Mapped Configuration Region (MMCR) needs mapped region
below 00100000h accessible real-mode software. 32-bit protected-mode native embedded systems need move MMCR.
remainder system initialization done real mode from BIOS image
running from DRAM. This contrast embedded system, which does initialization from 32-bit protected mode (running either from DRAM Flash).
3.1.3
Memory-Mapped Configuration Region (MMCR)
Memory-Mapped Configuration Region (MMCR) 4-Kbyte area located physical address FFFEF000h contains various configuration control registers microcontroller. Configuring controlling many device's features requires accessing MMCR registers. System initialization code native embedded system access this region directly because most all) initialization takes place from 32-bit protected mode.
Microcontroller User's Manual
System Initialization
contrast, real-mode code cannot access physical memory above 0010FFEFh (the realmode addressing limit), thus cannot access default location MMCR. This problem easily resolved programming Configuration Base Address (CBAR) register (Port FFFCh) place MMCR address somewhere below real-mode addressing limit. This allows real-mode initialization code directly access MMCR. This done step BIOS initialization sequence.
Note: Programming Configuration Base Address (CBAR) register place MMCR address other than default. However, MMCR region always accessible default location FFFEF000h, regardless CBAR register programmed.
3.1.4
Reset Event
microcontroller three primary classes resets.
System reset (often called hard reset power-on reset) System reset with SDRAM retention (called programmable reset) Soft reset (often called warm start)
more information resetting microcontroller, Chapter "Reset Generation", "Initialization" page 7-5. Often, systems have hardware reset button other external devices that cause reset. microcontroller, these cause system reset. However, there many ways implement external reset logic. After reset kind), boot software determine what caused reset examining various status bits. common effective method handling reset determine cause reset record event CMOS memory, some other non-volatile memory such EEPROM, non-volatile DRAM, Flash. Debugging diagnostic software could then examine report causes last resets. This very helpful when trying determine cause system problems. Note that system could record other information well; time date reset event good example. When system reset occurs (regardless source) internal registers logic blocks their power-on reset state. Therefore, system reset occurs, boot software must initialize system from scratch. There exception this, called programmable reset. This function enabled PRG_RST_ENB Reset Configuration (RESCFG) register (MMCR offset D72h). this set, assertion PRGRESET pin, SYS_RST bit, watchdog timer system reset event, AMDebug technology system reset event while PWRGOOD asserted will result system reset which SDRAM configuration (SDRAM type, number banks, refresh rate, etc.) maintained that contents SDRAM preserved. SDRAM controller parameters retained include SDRAM type, number banks, refresh rate, signal drive strength. This feature allows system reset while guaranteeing that contents SDRAM disturbed. This very valuable system debugging systems that require minimal startup time. This reset condition detected software. Note that, once programmable reset been enabled, system resets other than PRWGOOD deassertion converted this type. When soft reset occurs, system able restart operating system saved enough state information. example, 80286-style operating system (e.g., OS/2) causes processor reset order return real mode call 16-bit BIOS routines.
Note: important understand that, most systems, soft reset does need handled much differently than system reset. example, system that does need
Microcontroller User's Manual
System Initialization
explicitly perform soft restart will simply cause system reset when soft reset detected.
Note that watchdog timer generate interrupt (maskable non-maskable) system reset, both. Handling watchdog timer time-outs complex. more information operates, Chapter "Watchdog Timer".
3.1.5
Reset Vector Reset Segment
Immediately after hard soft reset, Am5x86 core begins execution real mode address F000:FFF0. This real-mode address called reset vector. While reset vector real-mode address, redirection physical address FFFFFFF0h, which located physical address memory device selected BOOTCS. This device called boot device. After hard soft reset, 64-Kbyte physical address space from FFFF0000 FFFFFFFFh (resident boot device) redirected into real-mode address space from F000:0000 F000:FFFF. This real-mode region called reset segment. region boot device called reset region. code that resides this area called reset handler. This redirection performed addressing unit, artifact values programmed into descriptor cache reset time. After reset, core sets base value Descriptor Cache register FFFF0000h with limit 0000FFFFh Kbytes). processor CS:EIP register pair F000:0000FFF0. redirection works because, real mode, linear addresses code fetches generated taking offset adding contents base register descriptor cache. Since paging unit disabled reset, these linear addresses directly physical addresses. This simple mechanism causes both redirection reset code region reset segment first instruction fetch occur from reset vector. Note that none other segment registers (and internal descriptor registers) have this behavior. This behavior only applicable Segment register internal descriptor cache. more information configuration processor registers reset, Am486® DX/DX2 Microprocessor Hardware Reference Manual, 1994 (order #17965). What this means that artificial reset segment redirection only active until executes Jump (JMP) instruction. This because Jump instruction causes Segment register reloaded. When segment register loaded real mode, processor sets value corresponding descriptor cache base register times value segment register. Since processor running real mode, internal Descriptor registers their normal real-mode values. Since reset vector F000:FFF0, there only bytes before segment. That only enough instructions. regardless much little) reset code does, instruction reset vector must Near Jump into reset region. example, shown Figure 3-1, reset handler large, then initial Near Jump could F000:0000.
Microcontroller User's Manual
System Initialization Figure Initial Near Jump Example
F000:FFFF F000:FFF0 Reset Vector
Near Jump
F000:C000
Reset Handler
F000:0000
reset vector Near Jump required jump F000:0000. jump anywhere into reset segment. example, reset handler code only Kbytes size, could jump F000:C000, leaving more room boot device other code. This allows reset handler placed right against reset vector, thus using space boot device more efficiently.
Note: debugging using AMDebug technology, only should this first Jump instruction Near Jump, should Jump Near Indirect instruction, which opcode FF/4. Incircuit emulation debug software that uses internal trace cache searches this opcode determining when reset event occurred.
much little system initialization code take place reset handler while system executing from reset segment (i.e., before first Jump instruction). example, native embedded system using 32-bit only RTOS will merely setup protected mode data structures, switch protected mode, jump directly into system boot code (the boot device device selected BOOTCS). contrast, system with PC-style BIOS would initialize SDRAM controller, shadow BIOS SDRAM, then jump BIOS.
CONFIGURING SDRAM CONTROLLER
After system reset, SDRAM controller configuration registers reset their default states. SDRAM controller banks SDRAM refresh disabled default. details enable SDRAM controller SDRAM configuration, "Initialization" page 10-29. Note that microcontroller reset manner that preserves operation SDRAM controller. This condition detected handled properly SDRAM initialization code. Error Correction Code (ECC) logic SDRAM enabled, operation requires that SDRAM associated memory initialized. This accomplished boot code, which must write every location SDRAM. This process initializes SDRAM reflect proper error-checking codes. this procedure performed, false
Microcontroller User's Manual
System Initialization
errors will occur when writing data smaller than 32-bit doubleword. more detailed discussion ECC, "Error Correction Code (ECC)" page 10-16.
IDENTIFYING CORE
Information about integrated Am5x86 core available reading processor register after system reset using CPUID instruction time. CPUID instruction available later model 32-bit processors from leading vendors allows programs determine information about CPU, including manufacturer, cache type, availabili
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