Processor Data Sheet 1999 Advanced Micro Devices, Inc. rights res
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AMD-K6-III
Processor Data Sheet
1999 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, logo, 3DNow!, combinations thereof, K86, Super7 trademarks, AMD-K6 RISC86 registered trademarks Advanced Micro Devices, Inc. Microsoft, Windows, Windows registered trademarks Microsoft Corporation. NetWare registered trademark Novell, Inc. trademark Intel Corporation. State Diagram reprinted from IEEE 1149.1-1990 "IEEE Standard Test Access Port Boundary-Scan Architecture," Copyright 1990 Institute Electrical Electronics Engineers, Inc. IEEE disclaims responsibility liability resulting from placement described manner. Information reprinted with permission IEEE. Other product names used this publication identification purposes only trademarks their respective companies.
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AMD-K6®-III Processor Data Sheet
Contents
Revision History xvii AMD-K6®-III Processor
Super7Platform Initiative Super7Platform Enhancements. Super7Platform Advantages
Internal Architecture
Introduction AMD-K6®-III Processor Microarchitecture Overview Enhanced RISC86® Microarchitecture Cache, Instruction Prefetch, Predecode Bits Cache Prefetching. Predecode Bits Instruction Fetch Decode Instruction Fetch Instruction Decode Centralized Scheduler Execution Units Register Pipelines Branch-Prediction Logic Branch History Table. Branch Target Cache Return Address Stack Branch Execution Unit
Software Environment
Registers General-Purpose Registers Integer Data Types Segment Registers. Segment Usage Instruction Pointer Floating-Point Registers Floating-Point Register Data Types MMXTM/3DNow!Registers. MMXData Types 3DNow!Data Types EFLAGS Register Control Registers. Debug Registers.
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Model-Specific Registers (MSR) Memory Management Registers Task State Segment Paging Descriptors Gates Exceptions Interrupts Instructions Supported AMD-K6®-III Processor
Signal Descriptions
4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 Signal Terminology A20M# (Address Mask) A[31:3] (Address Bus) ADS# (Address Strobe) ADSC# (Address Strobe Copy) AHOLD (Address Hold) (Address Parity) APCHK# (Address Parity Check) BE[7:0]# (Byte Enables) BF[2:0] (Bus Frequency) BOFF# (Backoff) BRDY# (Burst Ready) BRDYC# (Burst Ready Copy) BREQ (Bus Request) CACHE# (Cacheable Access) (Clock) D/C# (Data/Code) D[63:0] (Data Bus) DP[7:0] (Data Parity) EADS# (External Address Strobe) EWBE# (External Write Buffer Empty) FERR# (Floating-Point Error) FLUSH# (Cache Flush) HIT# (Inquire Cycle Hit) HITM# (Inquire Cycle Modified Line) HLDA (Hold Acknowledge) HOLD (Bus Hold Request) IGNNE# (Ignore Numeric Exception) INIT (Initialization) INTR (Maskable Interrupt) (Invalidation Request) KEN# (Cache Enable) LOCK# (Bus Lock) M/IO# (Memory I/O) (Next Address) (Non-Maskable Interrupt) (Page Cache Disable) PCHK# (Parity Check)
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AMD-K6®-III Processor Data Sheet
4.39 4.40 4.41 4.42 4.43 4.44 4.45 4.46 4.47 4.48 4.49 4.50 4.51 4.52 4.53 4.54
(Page Writethrough) RESET (Reset) RSVD (Reserved) SCYC (Split Cycle) SMI# (System Management Interrupt) SMIACT# (System Management Interrupt Active) STPCLK# (Stop Clock) (Test Clock) (Test Data Input) (Test Data Output) (Test Mode Select) TRST# (Test Reset) VCC2DET (VCC2 Detect) VCC2H/L# (VCC2 High/Low) W/R# (Write/Read) WB/WT# (Writeback Writethrough)
Cycles
Timing Diagrams State Machine Diagram Idle Address Data. Data-NA# Requested. Pipeline Address Pipeline Data Transition Memory Reads Writes Single-Transfer Memory Read Write Misaligned Single-Transfer Memory Read Write Burst Reads Pipelined Burst Reads Burst Writeback Read Write Basic Read Write Misaligned Read Write Inquire Arbitration Cycles Hold Hold Acknowledge Cycle HOLD-Initiated Inquire Shared Exclusive Line HOLD-Initiated Inquire Modified Line AHOLD-Initiated Inquire Miss. AHOLD-Initiated Inquire Shared Exclusive Line. AHOLD-Initiated Inquire Modified Line AHOLD Restriction Backoff (BOFF#) Locked Cycles Basic Locked Operation Locked Operation with BOFF# Intervention
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Interrupt Acknowledge Special Cycles Basic Special Cycle Shutdown Cycle Stop Grant Stop Clock States INIT-Initiated Transition from Protected Mode Real Mode
Power-on Configuration Initialization
Signals Sampled During Falling Transition RESET FLUSH# BF[2:0] RESET Requirements State Processor After RESET Output Signals Registers. State Processor After INIT
Cache Organization
MESI States Data Cache Cache Predecode Bits Cache Operation Cache-Related Signals Cache Disabling Flushing Cache Disabling. Cache Disabling Cache Array Testing Cache-Line Fills Cache-Line Replacements Write Allocate Write Cacheable Page Write Sector Write Allocate Limit Write Allocate Logic Mechanisms Conditions Prefetching Hardware Prefetching Software Prefetching. Cache States Cache Coherency Inquire Cycles Internal Snooping FLUSH# PFIR WBINVD INVD Cache-Line Replacement Writethrough versus Writeback Coherency States
7.10 7.11
7.12
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AMD-K6®-III Processor Data Sheet
7.13
A20M# Masking Cache Accesses
Write Merge Buffer
EWBE Control Memory Type Range Registers UC/WC Cacheability Control Register (UWCCR)
Floating-Point Multimedia Execution Units
Floating-Point Execution Unit Handling Floating-Point Exceptions External Logic Support Floating-Point Exceptions Multimedia 3DNow!Execution Units Floating-Point MMXTM/3DNow!Instruction Compatibility Registers. Exceptions FERR# IGNNE#
System Management Mode (SMM)
10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Overview Operating Mode Default Register Values State-Save Area Revision Identifier Base Address Halt Restart Slot Trap Dword Trap Restart Slot Exceptions, Interrupts, Debug
Test Debug
11.1 11.2 11.3 Built-In Self-Test (BIST) Tri-State Test Mode Boundary-Scan Test Access Port (TAP) Test Access Port Signals Registers Instructions Controller State Machine Cache Inhibit Purpose Cache Array Testing Level-2 Cache Array Access Register (L2AAR) Debug Debug Registers.
11.4 11.5 11.6
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Debug Exceptions
Clock Control
12.1 Halt State Enter Halt State Exit Halt State Stop Grant State Enter Stop Grant State Exit Stop Grant State Stop Grant Inquire State Enter Stop Grant Inquire State Exit Stop Grant Inquire State Stop Clock State Enter Stop Clock State Exit Stop Clock State
12.2
12.3
12.4
Power Grounding
13.1 13.2 13.3 Power Connections Decoupling Recommendations Connection Requirements
Electrical Data
14.1 14.2 14.3 14.4 Operating Ranges Absolute Ratings Characteristics Power Dissipation
Buffer Characteristics
15.1 15.2 15.3 Buffer Model Model Application Note Buffer Characteristics
Signal Switching Characteristics
16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 Switching Characteristics Clock Switching Characteristics 100-MHz Operation Clock Switching Characteristics 66-MHz Operation Valid Delay, Float, Setup, Hold Timings Output Delay Timings 100-MHz Operation Input Setup Hold Timings 100-MHz Operation Output Delay Timings 66-MHz Operation Input Setup Hold Timings 66-MHz Operation
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AMD-K6®-III Processor Data Sheet
16.9
RESET Test Signal Timing
Thermal Design
17.1 Package Thermal Specifications Heat Dissipation Path Measuring Case Temperature Layout Airflow Considerations Voltage Regulator Airflow Management System Design
17.2
Description Diagram Designations Package Specifications
20.1 321-Pin Staggered CPGA Package Specification
Ordering Information
Index.
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AMD-K6®-III Processor Data Sheet
List Figures
AMD-K6®-III Processor Block Diagram Cache Sector Organization Instruction Buffer AMD-K6®-III Processor Decode Logic AMD-K6®-III Processor Scheduler Register Functional Units Register with 16-Bit 8-Bit Name Components. Integer Data Registers. Segment Register Segment Usage Floating-Point Register Status Word Register Control Word Register Word Register. Packed Decimal Data Register Precision Real Data Registers MMXTM/3DNow!Registers MMXData Types 3DNow!Data Types EFLAGS Registers Control Register (CR4) Control Register (CR3) Control Register (CR2) Control Register (CR1) Control Register (CR0) Debug Register Debug Register Debug Registers DR4. Debug Registers DR3, DR2, DR1, DR0. Machine-Check Address Register (MCAR) Machine-Check Type Register (MCTR) Test Register (TR12). Time Stamp Counter (TSC) Extended Feature Enable Register (EFER) -MSR C000_0080h Figure SYSCALL/SYSRET Target Address Register (STAR) Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
List Figures
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Figure Write Handling Control Register (WHCR) -MSR C0000_0082h Figure UC/WC Cacheability Control Register (UWCCR) C0000_0085h Figure Processor State Observability Register (PSOR) C000_0087h Figure Page Flush/Invalidate Register (PFIR)- C000_0088h Figure Data Location Figure Data Figure Information Figure Memory Management Registers Figure Task State Segment (TSS) Figure 4-Kbyte Paging Mechanism Figure 4-Mbyte Paging Mechanism Figure Page Directory Entry 4-Kbyte Page Table (PDE) Figure Page Directory Entry 4-Mbyte Page Table (PDE) Figure Page Table Entry (PTE). Figure Application Segment Descriptor Figure System Segment Descriptor Figure Gate Descriptor Figure Logic Symbol Diagram Figure Waveform Definitions Figure State Machine Diagram Figure Non-Pipelined Single-Transfer Memory Read/Write Write Delayed EWBE# Figure Misaligned Single-Transfer Memory Read Write Figure Burst Reads Pipelined Burst Reads Figure Burst Writeback Cache-Line Replacement Figure Basic Read Write Figure Misaligned Transfer. Figure Basic HOLD/HLDA Operation Figure HOLD-Initiated Inquire Shared Exclusive Line Figure HOLD-Initiated Inquire Modified Line. Figure AHOLD-Initiated Inquire Miss Figure AHOLD-Initiated Inquire Shared Exclusive Line Figure AHOLD-Initiated Inquire Modified Line Figure AHOLD Restriction Figure BOFF# Timing. Figure Basic Locked Operation.
List Figures
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Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107.
Locked Operation with BOFF# Intervention. Interrupt Acknowledge Operation Basic Special Cycle (Halt Cycle) Shutdown Cycle Stop Grant Stop Clock Modes, Part Stop Grant Stop Clock Modes, Part INIT-Initiated Transition from Protected Mode Real Mode. Cache Organization Cache Sector Organization. Write Handling Control Register (WHCR) Write Allocate Logic Mechanisms Conditions Page Flush/Invalidate Register (PFIR)-MSR C000_0088h UC/WC Cacheability Control Register (UWCCR) -MSR C000_0085h (Model 8/[F:8]). External Logic Supporting Floating-Point Exceptions. Memory State Diagram Cache Organization. Cache Sector Line Organization Data Location Data Information Byte. Debug Register Debug Register Debug Registers DR4. Debug Registers DR3, DR2, DR1, DR0. Clock Control State Transitions Suggested Component Placement Pulldown Curves Pullup Curves Waveform Diagrams Output Valid Delay Timing Maximum Float Delay Timing Input Setup Hold Timing Reset Configuration Timing Waveform
List Figures
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Figure 108. Figure 109. Figure 110. Figure 111. Figure 112. Figure 113. Figure 114. Figure 115. Figure 116. Figure 117. Figure 118. Figure 119. Figure 120.
TRST# Timing. Test Signal Timing Diagram Thermal Model Power Consumption versus Thermal Resistance Processor Heat Dissipation Path Measuring Case Temperature. Voltage Regulator Placement Airflow Heatsink with Airflow Path Dual-Fan System Airflow Path Form-Factor System AMD-K6®-III Processor Top-Side View AMD-K6®-III Processor Pin-Side View 321-Pin Staggered CPGA Package Specification
List Figures
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List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Execution Latency Throughput Execution Units General-Purpose Registers General-Purpose Register Doubleword, Word, Byte Names Segment Registers AMD-K6®-III Processor Model MSRs Extended Feature Enable Register (EFER)-Model Definition SYSCALL/SYSRET Target Address Register (STAR) Definition Memory Management Registers Application Segment Types System Segment Gate Types Summary Exceptions Interrupts Integer Instructions Floating-Point Instructions MMXInstructions 3DNow!Instructions Processor-to-Bus Clock Ratios. Output Float Conditions Input Types Output Float Conditions Input/Output Float Conditions Test Pins Cycle Definition Special Cycles Bus-Cycle Order During Misaligned Transfers A[4:3] Address-Generation Sequence During Bursts Bus-Cycle Order During Misaligned Transfers Interrupt Acknowledge Operation Definition. Encodings Special Cycles Output Signal State After RESET Register State After RESET Signal Generation Signal Generation CACHE# Signal Generation Cache States Read Write Accesses Valid Cache States Effect Inquire Cycles Cache States Snoops, Flushes, Invalidation EWBEC Settings WC/UC Memory Type
List Tables
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Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Valid Masks Range Sizes Initial State Registers State-Save Area Revision Identifier Trap Dword Configuration Trap Restart Slot Boundary Scan Definitions Device Identification Register Supported Instructions. versus Data Selector Definitions Operating Ranges. Absolute Ratings Characteristics Typical Maximum Power Dissipation Switching Characteristics 100-MHz Operation Switching Characteristics 66-MHz Operation Output Delay Timings 100-MHz Operation Input Setup Hold Timings 100-MHz Operation Output Delay Timings 66-MHz Operation Input Setup Hold Timings 66-MHz Operation RESET Configuration Signals 100-MHz Operation RESET Configuration Signals 66-MHz Operation Waveform TRST# Timing Test Signal Timing Package Thermal Specification 321-Pin Staggered CPGA Package Specification Valid Ordering Part Number Combinations
List Tables
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AMD-K6®-III Processor Data Sheet
Revision History
Date 1999 1999 Initial published release Added AMD-K6-III/400AFR AMD-K6-III/450AFX OPNs corresponding specifications Chapter "Electrical Data", Chapter "Thermal Design", Chapter "Ordering Information". Changed definition Boundary Scan Register (BSR) Table page 229. Description
Revision History
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Revision History
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AMD-K6®-III Processor Data Sheet
AMD-K6®-III Processor
Advanced 6-Issue RISC86® Superscalar Microarchitecture parallel specialized execution units Multiple sophisticated x86-to-RISC86 instruction decoders Advanced two-level branch prediction Speculative execution Out-of-order execution Register renaming data forwarding Issues RISC86 instructions clock Innovative TriLevel Cache Design 320-Kbyte total internal cache Internal split, 64-Kbyte Cache 32-Kbyte instruction cache with additional 20-Kbytes predecode cache 32-Kbyte writeback dual-ported data cache Two-way associative MESI protocol support Internal full-speed, 256-Kbyte cache Four-way associative Multiport internal cache design enabling simultaneous 64-bit reads/writes caches 100-MHz frontside optional Level-3 cache Super7platforms 3DNow!Technology Additional instructions improve graphics multimedia performance Separate multiplier superscalar instruction execution Compatible with Super7 platform Leverages high-speed 100-MHz processor Accelerated Graphic Port (AGP) support High-Performance IEEE 754-Compatible 854-Compatible Floating-Point Unit High-Performance Industry-Standard MMXInstructions Dual integer superscalar execution 321-Pin Ceramic Grid Array (CPGA) Package Industry-Standard System Management Mode (SMM) IEEE 1149.1 Boundary Scan Binary Software Compatibility AMD-K6®-III Processor
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innovative AMD-K6®-III processor brings industry-leading performance systems running extensive installed base software. Super7compatible, 321-pin ceramic grid array (CPGA) package enables processor reduce time-to-market leveraging today's cost-effective, industry-standard infrastructure deliver superior-performing solution. AMD-K6-III processor incorporates 3DNow!technology, significant innovation processor architecture that drives today's personal computers. With 3DNow! technology, new, more powerful hardware software applications enable more entertaining productive platform. Improvements include fast frame rates high-resolution scenes, superior modeling real world environments physics, life-like images graphics, big-screen sound video. taken leadership role developing instructions that enable exciting levels performance realism. 3DNow! technology defined implemented collaboration with Microsoft®, application developers, graphics vendors, received enthusiastic reception. compatible with today's existing software, supported industry-standard APIs, requires operating system support, thereby enabling broad class applications benefit from 3DNow! technology. provide state-of-the-art performance, processor incorporates innovative efficient RISC86® microarchitecture, largest total internal cache shipping processor, powerful IEEE 754-compatible 854-compatible floating-point execution unit, high-performance industry-standard multimedia execution unit executing MMXinstructions. processor includes additional high-performance Single Instruction Multiple Data (SIMD) execution resources support 3DNow! technology. These techniques have been combined deliver leading-edge performance leading consumer business applications both Microsoft Windows® Windows operating environments. AMD-K6-III processor's 6-issue RISC86 microarchitecture decoupled decode/execution superscalar design that implements state-of-the-art design techniques achieve leading-edge performance. Advanced design techniques implemented AMD-K6-III processor include multiple instruction decode, single-clock internal RISC operations, execution units that support superscalar operation, out-of-order execution, data forwarding, speculative execution, register renaming. addition, processor supports advanced branch prediction logic implementing 8192-entry branch history table, branch target cache, return address stack, which combine deliver better than prediction rate. These design techniques enable AMD-K6-III processor issue, execute, retire multiple instructions clock, resulting excellent scaleable performance.
AMD-K6®-III Processor
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AMD-K6®-III Processor Data Sheet
AMD-K6-III processor binary code compatible. AMD's extensive experience through generations processors been carefully integrated into processor enable compatibility with Windows Windows Windows 3.x, Windows DOS, OS/2, Unix, Solaris, NetWare®, Vines, other leading operating systems applications. AMD-K6-III processor Super7 Socket 7-compatible. Super7 platform extension popular robust Socket platform. "Super7Platform Initiative" more information. world's second-leading supplier Windows-compatible processors, having shipped more than million microprocessors, including more than million Windows-compatible processors. AMD-K6-III processor latest member this long line processors. With combination state-of-the-art features, industry-leading performance, high-performance 3DNow! technology multimedia engines, compatibility, low-cost infrastructure, AMD-K6-III superior choice performance PCs.
Super7Platform Initiative
industry partners launched Super7 platform initiative order maintain competitive vitality Socket infrastructure through series enhancements, including development industry-standard 100-MHz processor protocol. addition 100-MHz processor protocol, Super7 initiative includes introduction chipsets that support specification, support backside cache frontside cache. Currently, over motherboard vendors major BIOS chipset vendors offer Super7-based products. Super7Platform Enhancements Super7 platform following enhancements:
100-MHz processor bus-The AMD-K6-III processor supports 100-MHz, Mbyte/second frontside provide high-speed interface Super7 platform-based chipsets. 100-MHz interface frontside cache main system memory speeds access frontside cache main memory percent over 66-MHz Socket interface-resulting significant increase overall system performance. Accelerated graphics port support-AGP improves performance mid-range that have small amounts video memory graphics card. industry-standard specification enables 133-MHz graphics interface will scale even higher levels performance. Support backside frontside cache-The Super7 platform `headroom' support higher-performance AMD-K6 processors, with clock speeds AMD-K6®-III Processor
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scaling beyond. Super7 platform also supports AMD-K6-III processor which features full-speed, internal backside 256-Kbyte cache designed enable levels performance leading-edge desktop systems. This processor also supports optional 100-MHz frontside external cache even higher-performance system configurations. Super7Platform Advantages Super7 platform following advantages:
Delivers performance features competitive with alternate platforms same clock speed, significantly lower cost Takes advantage existing system designs superior value Enables OEMs resellers take advantage mature, high-volume infrastructure supported multiple BIOS, chipset, graphics, motherboard suppliers Reduces inventory design costs with motherboard wide range products Builds huge installed base more than million motherboards Provides easy upgrade path future users, well bridge legacy users
taking advantage low-cost, mature Socket infrastructure, Super7 platform will continue provide superior value leading-edge performance desktop systems.
AMD-K6®-III Processor
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AMD-K6®-III Processor Data Sheet
Internal Architecture
Introduction
AMD-K6-III processor implements advanced design techniques known RISC86 microarchitecture. RISC86 microarchitecture decoupled decode/execution design approach that yields superior sixth-generation performance x86-based software. This chapter describes techniques used functional elements RISC86 microarchitecture.
AMD-K6®-III Processor Microarchitecture Overview
When discussing processor design, important understand implementation. term architecture refers instruction features processor that visible software rchi termines software processor run. industry-standard instruction set. term microarchitecture refers design techniques used processor reach target cost, performance, functionality goals. AMD-K6 family processors based sophisticated RISC core known Enhanced RISC86 microarchitecture. Enhanced RISC86 microarchitecture advanced, second-order decoupled decode/execution design approach that enables industry-leading performance x86-based software. term design implementation refers actual logic circuit designs from which processor created according microarchitecture specifications.
Chapter
Internal Architecture
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Enhanced RISC86® Microarchitecture
anced RISC86 croarchi tecture characteristics AMD-K6 family. innovative RISC86 microarchitecture approach implements instruction internally translating instructions into RISC86 operations. These RISC86 operations were specially designed include direct support instruction while observing RISC performance principles fixed length encoding, regularized instruction fields, large register set. Enhanced RISC86 microarchitecture used performance promotes straightforward extensions, such those added current AMD-K6-III processor those planned future. Instead directly executing complex instructions, which have lengths bytes, AMD-K6-III processor executes simpler easier fixed-length RISC86 operations, while maintaining instruction coding efficiencies found programs. AMD-K6-III processor contains parallel decoders, centralized RISC86 operation scheduler, execution units that support superscalar operation multiple decode, execution, retirement-of instructions. These elements packed into aggressive highly efficient six-stage pipeline. AMD-K6®-III Processor Block Diagram. shown Figure page high-performance, out-of-order execution engine AMD-K6-III processor mated split, level-one, 64-Kbyte, writeback cache with Kbytes instruction cache Kbytes data cache. Backing level-one cache large, unified, level-two, 256-Kbyte, writeback cache. level-one instruction cache feeds decoders and, turn, decoders feed scheduler. issues retires RISC86 operations contained scheduler. system interface demultiplexed bus. AMD-K6-III processor combines latest processor microarchitecture provide highest performance today's personal computers. AMD-K6-III processor offers true sixth-generation performance binary software compatibility.
Internal Architecture
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KByte Level-One Instruction Cache Predecode Logic Entry ITLB KByte Predecode Cache Byte Fetch Level-One Cache Controller Super7Bus Interface Branch Logic Dual Instruction Decoders
RISC86 (8192-Entry BHT) (16-Entry BTC) (16-Entry RAS)
Out-of-Order Execution Engine RISC86® Operation Issue
Four RISC86 Decode Scheduler Buffer
RISC86)
Instruction Control Unit
Branch Resolution Unit
Level-Two Cache
(256 KByte)
Load Unit
Store Unit
Register Unit (Integer/ Multimedia/3DNow!TM)
Register Unit (Integer/ Multimedia/3DNow!)
Floating- Point Unit
Store Queue
Level-One Dual-Port Data Cache
KByte)
Entry DTLB
Figure AMD-K6®-III Processor Block Diagram Decoders. Decoding instructions begins when on-chip level-one instruction cache filled. Predecode logic determines length instruction byte-by-byte basis. This predecode information stored, along with instructions, level-one instruction cache, used later decoders. decoders translate on-the-fly, with additional latency, instructions clock into RISC86 operations. Note: this chapter, "clock" refers processor clock. AMD-K6-III processor categorizes instructions into three types decodes-short, long, vector. decoders process either short, long, vector decode characteristics: Short decodes-x86 instructions less than equal seven bytes length Long decodes-x86 instructions less than equal bytes length Vector decodes-complex instructions
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Short long decodes processed completely within decoders. Vector decodes started decoders then completed fetched sequences from on-chip ROM. After decoding, RISC86 operations delivered scheduler dispatching executions units. Scheduler/Instruction Control Unit. centraliz scheduler buffer managed Instruction Control Unit (ICU). buffers manages RISC86 operations time. This equals from instructions. This buffer size (24) perfectly matched processor's six-stage RISC86 pipeline four RISC86-operations decode rate. scheduler accepts many four RISC86 operations time from decoders retires four RISC86 operations clock cycle. capable simultaneously issuing RISC86 operations time execution units. This consists following types operations: Memory load operation Memory store operation Complex integer, 3DNow! register operation Simple integer, 3DNow! register operation Floating-point register operation Branch condition evaluation Registers. When managing RISC86 operations, uses physical registers contained within RISC86 microarchitecture. physical registers located general register file grouped committed architectural registers plus rename registers. architectural registers consist scratch registers registers that correspond general-purpose registers- EAX, EBX, ECX, EDX, EBP, ESP, ESI, EDI. There analogous registers specifically 3DNow! architectural registers plus MMX/3DNow! rename registers. architectural registers consist scratch register registers that correspond registers (mm0-mm7), shown Figure page Branch Logic. AMD-K6-III processor designed with highly sophisticated dynamic branch logic consisting following:
Branch history/Prediction table Branch target cache Return address stack Internal Architecture Chapter
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AMD-K6®-III Processor Data Sheet
AMD-K6-III processor implements two-level branch prediction scheme based 8192-entry branch history table. branch history table stores prediction information that used predicting conditional branches. Because branch history table does store predicted target addresses, special address ALUs calculate target addresses on-the-fly during instruction decode. branch target cache augments predicted branch performance avoiding clock cache-fetch penalty. This specialized target cache does this supplying first bytes target instructions decoders when branches predicted. return address stack unique device specifically designed optimizing CALL RETURN pairs. summary, AMD-K6-III processor uses dynamic branch logic minimize delays branch instructions that common software. 3DNow!Technology. taken lead role improving multimedia capabilities processor family with introduction 3DNow! technology, which uses packed, single-precision, floating-point data format Single Instruction Multiple Data (SIMD) operations based technology model.
Cache, Instruction Prefetch, Predecode Bits
writeback level-one cache AMD-K6-III processor organized separate 32-Kbyte instruction cache 32-Kbyte data cache with two-way associativity. level-two cache Kbytes, organized unified, four-way setassociative cache. cache line size bytes, lines fetched from external memory using efficient pipelined burst transaction. level-one instruction cache filled from level-two cache from external memory, each instruction byte analyzed instruction boundaries using predecoding logic. Predecoding annotates information bits byte) each instruction byte that later enables decoders efficiently decode multiple instructions simultaneously.
Cache
processor cache design takes advantage sectored organization (see Figure page 10). Each sector consists bytes configured 32-byte cache lines. cache lines sector share common have separate pairs MESI (Modified, Exclusive, Shared, Invalid) bits that track state each cache line. Internal Architecture
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forms cache misses associated cache fills take place-a tag-miss cache fill tag-hit cache fill. case tag-miss cache fill, level-one cache miss mismatch, which case required cache line filled either from level-two cache from external memory, level-one cache line within sector that required marked invalid. case tag-hit cache fill, address matches tag, requested cache line marked invalid. required level-one cache line filled from level-two cache from external memory, level-one cache line within sector that required remains same cache state. Prefetching AMD-K6-III processor conditionally performs cache prefetching which results filling required cache line first, prefetch second cache line making other half sector. From perspective external bus, cache-line fills typically appear 32-byte burst read cycles occurring back-to-back allowed, pipelined cycles. 3DNow! technology includes instruction called PREFETCH that allows cache line prefetched into level-one data cache level-two cache. PREFETCH instruction defined Table "3DN !Instructions," page more detailed information, 3DNow!Technology Manual, order# 21928. Predecode Bits Decoding instructions particularly difficult because instructions variable-length from bytes long. Predecode logic supplies five predecode bits that associated with each instruction byte. predecode bits indicate number bytes start next instruction. predecode bits stored extended instruction cache alongside each instruction byte shown Figure predecode bits passed with instruction bytes decoders where they assist with parallel instruction decoding.
Cache Line Byte Predecode Bits Byte Predecode Bits Byte Predecode Bits MESI Bits Cache Line Byte Predecode Bits Byte Predecode Bits Byte Predecode Bits MESI Bits
Address
Figure Cache Sector Organization
Internal Architecture
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Instruction Fetch Decode
processor fetch bytes clock levelone instruction cache branch target cache. fetched information placed into 16-byte instruction buffer that feeds directly into decoders (see Figure Fetching occur along single execution stream with seven outstanding branches taken. instruction fetch logic capable retrieving contiguous bytes information within 32-byte boundary. There additional penalty when bytes instructions across cache line boundary. instruction bytes loaded into instruction buffer they consumed decoders. Although instructions consumed with byte memory-aligned word (two bytes) organization. Therefore, instructions loaded replaced with word granularity. When control transfer occurs-such instruction- entire instruction buffer flushed reloaded with instruction bytes.
Bytes 32-Kbyte Level-One Instruction Cache Bytes Branch-Target Cache Bytes
Instruction Fetch
Branch Target Address Adders Return Address Stack Bytes Fetch Unit Instruction Bytes plus Sets Predecode Bits
Instruction Buffer
Figure Instruction Buffer Chapter Internal Architecture
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Instruction Decode
AMD-K6-III processor decode logic designed decode multiple instructions clock (see Figure decode logic accepts instruction bytes their predecode bits from instruction buffer, locates actual instruction boundaries, generates RISC86 operations from these instructions. RISC86 operations fixed-length internal instructions. Most RISC86 operations execute single clock. RISC86 operations combined perform every function instruction set. Some instructions decoded into zero RISC86 operations instance RISC86 operation register-to-register add. More complex instructions decoded into several RISC86 operations.
Instruction Buffer
Short Decoder Short Decoder
Long Decoder On-Chip
Vector Decoder
RISC86® Sequencer
Vector Address
RISC86 Operations
Figure AMD-K6®-III Processor Decode Logic
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AMD-K6-III processor uses combination decoders convert instructions into RISC86 operations. hardware consists three sets decoders-two parallel short decoders, long decoder, vector decoder. parallel short decoders translate most commonly-used instructions moves, shifts, branches, ALU, FPU) extensions instruction (including 3DNow! instructions) into zero, one, RISC86 operations each. short decoders only operate instructions that seven bytes long. addition, they designed commonly-used instructions that greater than seven bytes more than bytes long, semi-commonly-used instructions that seven bytes long handled long decoder. long decoder only performs decode clock generates four RISC86 operations. other translations (complex instructions, serializing conditions, interrupts exceptions, etc.) handled combination vector decoder RISC86 operation sequences fetched from on-chip ROM. complex operations, vector decoder logic provides first RISC86 operations vector (initial address) sequence further RISC86 operations. same types RISC86 operations fetched from those that generated hardware decoders. Note: Although three sets decoders simultaneously copy instruction buffer contents, only three types decoders used during decode clock. decoders on-chip RISC86 always generate group four RISC86 operations. decodes that cannot fill entire group with four RISC86 operations, RISC86 operations placed empty locations grouping. example, long-decoded instruction that converts only three RISC86 operations padded with single RISC86 operation then passed scheduler. groups RISC86 operations placed scheduler time. common, uncommon, floating-point instructions (also known instructions) hardware decoded short decodes. This decode generates RISC86 floating-point operation and, optionally, associated Chapter Internal Architecture
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floating-point load store operation. Floating-point instruction decode only allowed first short decoder, non-ESC instructions decoded simultaneously second short decoder along with instruction decode first short decoder. 3DNow! instructions, with exception EMMS, FEMMS, PREFETCH instructions, hardware decoded short decodes. instruction decode generates RISC86 operation and, optionally, associated load store operation. 3DNow! instruction decode generates RISC86 3DNow! operation and, optionally, associated load store operation. 3DNow! instructions decoded either both short decoders.
Centralized Scheduler
scheduler heart AMD-K6-III processor (see Figure page 15). contains logic necessary manage out-of-order execution, data forwarding, register renaming, simultaneous issue retirement multiple RISC86 operations, speculative execution. scheduler's buffer hold RISC86 operations. This equates maximum instructions. scheduler issue RISC86 operations from locations buffer. When possible, scheduler simultaneously issue RISC86 operation available execution unit (store, load, branch, register integer/multimedia, register integer/multimedia, floating-point). total, scheduler issue retire four RISC86 operations clock. main advantage scheduler operation buffer ability examine instruction window equal instructions time. This advantage fact that scheduler operates RISC86 operations parallel allows AMD-K6-III processor perform dynamic on-the-fly instruction code scheduling optimized execution. Although scheduler issue RISC86 operations out-of-order execution, always retires instructions order.
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From Decode Logic RISC86 RISC86 RISC86 RISC86
Centralized RISC86® Operation Scheduler
RISC86 Issue Buses
RISC86 Operation Buffer
Figure AMD-K6®-III Processor Scheduler
Execution Units
AMD-K6-III processor contains parallel execution units-store, load, integer ALU, integer ALU, (X), (Y), MMX/3DNow! multiplier, 3DNow! ALU, floating-point, branch condition. Each unit independent capable handling RISC86 operations. Table page details execution units, functions performed within these units, operation latency, operation throughput. store load execution units two-stage pipelined designs. store unit performs data writes register calculation LEA/PUSH. Data memory register writes from stores available after clock. Store operations held store queue prior execution. From there, they execute order. load unit performs data memory reads. Data available from load unit after clocks.
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executio unit operat operations, multiplies, divides (signed unsigned), shifts, rotates. Integer execution unit operate basic word doubleword operations ADD, AND, CMP, SUB, XOR, zero-extend sign-extend operands. Table Execution Latency Throughput Execution Units
Function LEA/PUSH, Address (Pipelined) Memory Store (Pipelined) Memory Loads (Pipelined) Integer Integer Integer Multiply Integer Shift Multimedia (processes Shifts, Packs, Unpack instructions) Multiply Integer Branch 3DNow! Basic (16-bit 32-bit operands) Resolves Branch Conditions FADD, FSUB, FMUL 3DNow! 3DNow! Multiply 3DNow! Convert Latency Throughput
Functional Unit Store Load
Register Pipelines
onal that 3DNow! instructions share pipeline control with Integer Integer units. register functional units attached issue register execution pipeline issue register execution pipeline both. Each register pipeline dedicated resources that consist integer execution unit execution unit, therefore allowing superscalar operation integer instructions. addition, both issue buses connected 3DNow! ALU, MMX/3DNow! multiplier shifter, which allows appropriate RISC86 operation issued through either bus. Figure page shows details register pipelines.
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Scheduler Buffer RISC86® Operations) Issue Register Execution Pipeline Issue Register Execution Pipeline
Integer
MMXALU
MMX/ 3DNow!Multiplier
Shifter
3DNow!
Integer
Figure Register Functional Units branch condition unit separate from branch prediction logic that resolves conditional branches such LOOP after branch condition been evaluated.
Branch-Prediction Logic
Sophisticated branch logic that minimize hide impact changes program flow designed into AMD-K6-III processor. Branches code into categories unconditional branches, which always change program flow (that branches always taken) conditional branches, which divert program flow (that branches taken not-taken). When conditional branch taken, processor simply continues decoding executing next instructions memory. Typical applications have unconditional branches another conditional branches. AMD-K6-III processor branch logic been designed handle this type
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program behavior negative effects instruction execution, such stalls delayed instruction fetching draining processor pipeline. branch logic contains 8192-entry branch history table, 16-entry 16-byte branch target cache, 16-entry return address stack, branch execution unit. Branch History Table AMD-K6-III processor handles unconditional branches without penalty redirecting instruction fetching target address unconditional branch. However, branch-prediction mechanism built into AMD-K6-III implemented 8192-entry branch history table. This table stores executed branch information, predicts individual branches, predicts behavior groups branches. accommodate large branch history table, AMD-K6-III processor does store predicted target addresses. Instead, branch target addresses calculated on-the-fly using ALUs during decode stage. adders calculate possible target addresses before instructions fully decoded processor chooses which addresses valid. avoid clock cache-fetch penalty when branch predicted taken, built-in branch target cache supplies first bytes instructions directly instruction buffer (assuming target address hits this cache). (See Figure page 11.) branch target cache organized entries bytes. total, branch prediction logic achieves branch prediction rates greater than 95%. return address stack special device designed optimize CALL pairs. Software typically compiled with subroutines that frequently called from various places program. This usually done save space. Entry into subroutine occurs with execution CALL instruction. that time, processor pushes address next instruction memory following CALL instruction onto stack (allocated space memory). When processor encounters instruction (within subroutine), branch logic pops address from stack begins fetching from that location. avoid latency main memory accesses during CALL operations, return address stack caches pushed addresses. Internal Architecture Chapter
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Branch Execution Unit
branch execution unit enables efficient speculative execution. This unit gives processor ability execute instructions beyond conditional branches before knowing whether branch prediction correct. AMD-K6-III processor does permanently update registers memory locations until speculatively executed conditional branch instructions resolved. When prediction incorrect, processor backs point mispredicted branch instruction restores registers. AMD-K6-III processor support seven outstanding branches.
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Software Environment
This chapter provides general overview AMD-K6-III processor's software environment briefly describes data types, registers, operating modes, interrupts, architecture design implementation. AMD-K6-III processor Model implements same MSRs AMD-K6-2 processor Model 8/[F:8], bits fields within these MSRs defined identically. AMD-K6-III processor Model supports additional total eleven MSRs. name AMD-K6-III processor itself refers steppings Model "Model-Specific Registers (MSR)" page definitions.
Registers
AMD-K6-III processor contains registers defined architecture, including general-purpose, segment, floating-point, MMX/3DNow!, EFLAGS, control, task, debug, test, descriptor/memory-management registers. addition, this chapter provides information AMD-K6-III processor MSRs. Note: Areas register designated Reserved should modified software.
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General-Purpose Registers
eight 32-bit general-purpose registers used hold integer data memory pointers used instructions. Table contains list general-purpose registers functions which they used. Table
Register
General-Purpose Registers
Function Commonly used accumulator Commonly used pointer Commonly used counting loop operations Commonly used hold information pass parameters Commonly used destination pointer segment Commonly used source pointer segment Used point stack segment Used point data within stack segment
order support byte word operations, EAX, EBX, ECX, also used 8-bit 16-bit registers. shorter registers overlaid longer ones. example, name 16-bit version (low bits EAX) 8-bit names (high order bits) (low order bits). same naming convention applies EBX, ECX, EDX. EDI, ESI, ESP, used smaller 16-bit registers called respectively, these registers have 8-bit versions. Figure shows register with name components, Table lists doubleword (32-bit) general-purpose registers their corresponding word (16-bit) byte (8-bit) versions.
Figure Register with 16-Bit 8-Bit Name Components
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Table
General-Purpose Register Doubleword, Word, Byte Names
16-Bit Name (Word) 8-Bit Name 8-Bit Name (High-order Bits) (Low-order Bits)
32-Bit Name (Doubleword)
Integer Data Types
Four types data used general-purpose registers-byte, word, doubleword, quadword integers. Figure shows format integer data registers.
Precision Bits
Byte Integer
Word Integer
Precision Bits
Doubleword Integer
Precision Bits
Quadword Integer
Precision Bits
Figure Integer Data Registers Chapter Software Environment
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Segment Registers
16-bit segment registers used pointers areas (segments) memory. Table lists segment registers their functions. Figure shows format segment registers. Table
Segment Register
Segment Registers
Segment Register Function Code segment, where instructions located Data segment, where data located Data segment, where data located Data segment, where data located Data segment, where data located Stack segment
Figure Segment Register Segment Usage operating system determines type memory model that implemented. segment register usage determined operating system's memory model. Real mode memory model segment register points base address memory. Protected mode memory model segment register called selector selects segment descriptor descriptor table. This descriptor contains pointer base segment, limit segment, various protection attributes. more information descriptor formats, "Descriptors Gates" page Figure page shows segment usage Real mode Protected mode memory models.
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Physical Memory
Segment Base Segment Register Real Mode Memory Model Descriptor Table Physical Memory
Base Base
Limit Limit
Base
Segment Selector
Segment Base
Protected Mode Memory Model
Figure Segment Usage Instruction Pointer instruction pointer (EIP used conjunction with code segment register (CS). instruction pointer either 32-bit register (EIP) 16-bit register (IP) that keeps track where next instruction resides within memory. This register cannot directly manipulated, altered modifying return pointers when CALL instruction used. floating-point execution unit AMD-K6-III processor designed perform mathematical operations non-integer numbers. This floating-point unit conforms IEEE standards uses several registers meet these standards eight numeric floating-point registers, status word register, control word register, word register.
Floating-Point Registers
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eight floating-point registers physically bits wide labeled FPR0-FPR7. Figure shows format these floating-point registers. "Floating-Point Register Data Types" page information allowable floating-point data types.
Sign Exponent Significand
Figure Floating-Point Register 16-bit status word register contains information about state floating-point unit. Figure shows format this register.
TOSP
Symbol TOSP
Description Bits Busy Condition Code Stack Pointer 13-11 Condition Code Condition Code Condition Code Error Summary Status Stack Fault Exception Flags Precision Error Underflow Error Overflow Error Zero Divide Error Denormalized Operation Error Invalid Operation Error TOSP Information FPR0 FPR7
Figure Status Word Register
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control word register allows programmer manage processing options. Figure shows format this register.
Reserved Symbol Description Infinity (80287 compatibility) Rounding Control Precision Control Exception Masks Precision Underflow Overflow Zero Divide Denormalized Operation Invalid Operation Bits 11-10 Precision Control Information bits Single Precision Real Reserved bits Double Precision Real bits Extended Precision Real
Rounding Control Information Round nearest even number Round down toward negative infinity Round toward positive infinity Truncate toward zero
Figure Control Word Register word register contains information about registers register stack. Figure shows format this register.
(FPR4) (FPR3) (FPR2) (FPR1) (FPR0)
(FPR7)
(FPR6)
(FPR5)
Values Valid Zero Special Empty
Figure Word Register
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Floating-Point Register Data Types
Floating-point registers four different types data packed decimal, single-precision real, double-precision real, extended-precision real. Figures show formats these registers.
Ignore Zero
Precision Digits, Bits Used, 4-Bits/Digit
Description Bits Ignored Load, Zeros Store 78-72 Sign
Figure Packed Decimal Data Register
Single-Precision Real
Significand
Biased Exponent
Sign
Double-Precision Real
Biased Exponent
Significand
Sign
Extended-Precision Real
Biased Exponent Significand
Sign
Integer
Figure Precision Real Data Registers
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MMXTM/3DNow!Registers
MMX/3DNow! registers multimedia software. These registers mapped floating-point register stack. 3DNow! instructions refer these registers mm7. Figure shows format these registers. more information, AMD-K6® Processor Multimedia Technology Manual, order# 20726 3DNow! Technology Manual, order# 21928.
Figure MMXTM/3DNow!Registers MMXData Types instructions, registers three types data-packed eight-byte integer, packed quadword integer, packed dual doubleword integer. Figure page shows format these data types.
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Packed Bytes Integer
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Packed Words Integer
Word Word Word Word
Packed Doubleword Integer
Doubleword Doubleword
Figure MMXData Types 3DNow!Data Types 3DNow! instructions, MMX/3DNow! registers packed single-precision real data. Figure shows format 3DNow! data type.
Packed Single Precision Floating Point
Significand Significand
Biased Exponent Sign
Biased Exponent Sign
Figure 3DNow!Data Types
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EFLAGS Register
EFLAGS register provides three different types flags system, control, status. system flags provide operating system controls, control flag provides directional information string operations, status flags provide information resulting from logical arithmetic operations. Figure shows format this register.
Reserved Symbol IOPL Description Bits Flag Virtual Interrupt Pending Virtual Interrupt Flag Alignment Check Virtual-8086 Mode Resume Flag Nested Task Privilege Level 13-12 Overflow Flag Direction Flag Interrupt Flag Trap Flag Sign Flag Zero Flag Auxiliary Flag Parity Flag Carry Flag
Figure EFLAGS Registers
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Control Registers
five control registers contain system control bits pointers. Figures through show formats these registers.
Reserved Symbol Description Machine Check Enable Page Size Extensions Debugging Extensions Time Stamp Disable Protected Virtual Interrupts Virtual-8086 Mode Extensions
Figure Control Register (CR4)
Page Directory Base
Reserved Symbol Description Page Cache Disable Page Writethrough
Figure Control Register (CR3)
Page Fault Linear Address
Figure Control Register (CR2)
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Reserved
Figure Control Register (CR1)
Symbol
Description Paging Cache Disable Writethrough
Reserved Symbol Description Alignment Mask Write Protect Numeric Error Extension Type Task Switched Emulation Monitor Co-processor Protection Enabled
Figure Control Register (CR0)
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Debug Registers
Figures through show 32-bit debug registers supported processor.
Symbol Description Length Breakpoint Type Transaction(s) Trap Length Breakpoint Type Transaction(s) Trap Length Breakpoint Type Transaction(s) Trap Length Breakpoint Type Transaction(s) Trap Bits 31-30 29-28 27-26 25-24 23-22 21-20 19-18 17-16
Reserved Symbol Description General Detect Enabled Global Exact Breakpoint Enabled Local Exact Breakpoint Enabled Global Exact Breakpoint Enabled Local Exact Breakpoint Enabled Global Exact Breakpoint Enabled Local Exact Breakpoint Enabled Global Exact Breakpoint Enabled Local Exact Breakpoint Enabled Global Exact Breakpoint Enabled Local Exact Breakpoint Enabled
Figure Debug Register
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Reserved Symbol Description Breakpoint Task Switch Breakpoint Single Step Breakpoint Debug Access Detected Breakpoint Condition Detected Breakpoint Condition Detected Breakpoint Condition Detected Breakpoint Condition Detected
Figure Debug Register
Reserved
Reserved
Figure Debug Registers
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Breakpoint 32-bit Linear Address
Breakpoint 32-bit Linear Address
Breakpoint 32-bit Linear Address
Breakpoint 32-bit Linear Address
Figure Debug Registers DR3, DR2, DR1,
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Model-Specific Registers (MSR)
AMD-K6-III processor provides eleven MSRs. value register selects addressed RDMSR WRMSR instructions. values used inputs outputs RDMSR WRMSR instructions. Table lists MSRs corresponding value register. Figures through show formats. Table AMD-K6®-III Processor Model MSRs
Model-Specific Register Machine Check Address Register (MCAR) Machine Check Type Register (MCTR) Test Register (TR12) Time Stamp Counter (TSC) Extended Feature Enable Register (EFER) Write Handling Control Register (WHCR) UC/WC Cacheability Control Register (UWCCR) Processor State Observability Register (PSOR) Page Flush/Invalidate Register (PFIR) Level-2 Cache Array Register (L2AAR) Value C000_0080h C000_0082h C000_0085h C000_0087h C000_0088h C000_0089h
SYSCALL/SYSRET Target Address Register (STAR) C000_0081h
more information about MSRs, AMD-K6 Processor BIOS Design Application Note, order# 21329. info WRMSR instructions, K86Family BIOS Software Tools Development Guide, order# 21062. MCAR MCTR. AMD-K6-III processor does support generation machine check exception. However, processor does provide 64-bit machine check address register (MCAR), 64-bit machine check type register (MCTR), machine check enable (MCE) CR4. Because processor does support machine check exceptions, contents MCAR MCTR only affected WRMSR instruction RESET being sampled asserted (where bits each register reset
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MCAR
Figure Machine-Check Address Register (MCAR)
MCTR
Reserved
Figure Machine-Check Type Register (MCTR) Test Register (TR12). Test register provides method disabling caches. Figure shows format TR12.
Symbol Description Cache Inhibit
Reserved
Figure Test Register (TR12) Time Stamp Counter. processor increments 64-bit time stamp counter (TSC) MSR. Figure shows format TSC.
Figure Time Stamp Counter (TSC) Software Environment Chapter
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Extended Feature Enable Register (EFER). Enable Register (EFER) contains control bits that enable extended features processor. Figure shows format EFER register, Table defines function each EFER register.
EWBEC
Symbol EWBEC
Reserved Description Cache Disable EWBE Control Data Prefetch Enable System Call Extension
Figure Extended Feature Enable Register (EFER)-MSR C000_0080h Table
63-5
Extended Feature Enable Register (EFER)-Model Definition
Description Reserved Function Writing reserved causes general protection fault occur. reserved bits always read cache completely disabled. This provided debug testing purposes. normal operation maximum performance, this must (this default setting following reset). This 2-bit field controls behavior processor with respect ordering write cycles EWBE# signal. EFER[3] EFER[2] Global EWBE Disable (GEWBED) Speculative EWBE Disable (SEWBED), respectively. must enable data prefetching (this default setting following reset). enabled, cache misses initiated memory read within 32-byte line conditionally followed cache-line fetches other line 64-byte sector. must enable usage SYSCALL SYSRET instructions.
EWBE Control (EWBEC)
Data Prefetch Enable (DPE) System Call Extension (SCE)
more information EWBEC, "EWBE Control" page
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SYSCALL/SYSRET Target Address Register (STAR). SYSCALL/SYSRET target address register (STAR) contains target address used SYSCALL instruction 16-bit code stack segment selector bases used SYSCALL SYSRET instructions. Figure shows format STAR register, Table defines function each STAR register. more information, SYSCALL SYSRET Instruction Specification Application Note, order# 21086.
SYSRET Selector Selector Base SYSCALL Selector Selector Base Target Address
Figure SYSCALL/SYSRET Target Address Register (STAR) Table
63-48 47-32 31-0
SYSCALL/SYSRET Target Address Register (STAR) Definition
Description SYSRET Selector Base SYSCALL Selector Base Target Address
Write Handling Control Register (WHCR). Write Handling Control Register (WHCR) that contains fields-the Write Allocate Enable Limit (WAELIM) field, Write Allocate Enable 15-to-16-Mbyte (WAE15M) (see Figure 36). more information, "Write Allocate" page 189. Note: WHCR register defined Model same Model 8/[F:8].
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WAELIM
Reserved Symbol WAELIM WAE15M Description Bits Write Allocate Enable Limit 31-22 Write Allocate Enable 15-to-16-Mbyte
Note: Hardware RESET initializes this zeros.
Figure Write Handling Control Register (WHCR)-MSR C0000_0082h UC/WC Cacheability Control Register (UWCCR). AMD-K6-III processor provides variable-range Memory Type Range Registers (MTRRs)-MTRR0 MTRR1-that each specify range memory. Each range defined uncacheable (UC) write-combining (WC) memory. more information, "Memory Type Range Registers" page 205.
Symbol Description Uncacheable Memory Type Write-Combining Memory Type Physical Base Address Bits Physical Base Address Symbol Description Uncacheable Memory Type Write-Combining Memory Type Bits
Physical Address Mask
Physical Address Mask
MTRR1
MTRR0
Figure UC/WC Cacheability Control Register (UWCCR)- C0000_0085h Processor State Observability Register (PSOR). AMD-K6-III processor provides Processor State Observability Register (PSOR) (see Figure 38).
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Reserved Symbol NOL2 STEP Description Functionality Processor Stepping Frequency Divisor STEP
Figure Processor State Observability Register (PSOR)- C000_0087h Page Flush/Invalidate Register (PFIR). contains Page Flush/Invalidate Register (PFIR) (see Figure that allows cache invalidation optional flushing specific 4-Kbyte page from linear address space. more detailed information PFIR, "PFIR" page 198.
LINPAGE
Reserved Symbol LINPAGE Description 20-bit Linear Page Address Page Fault Occurred Flush/Invalidate Command 31-12
Figure Page Flush/Invalidate Register (PFIR)- C000_0088h Level-2 Cache Array Access Register (L2AAR). AMD-K6-III processor provides L2AAR register that allows direct access cache arrays. L2AAR register C000_0089h. operation that performed cache function instruction executed-RDMSR WRMSR-and contents register. register specifies location access, whether access cache data tags (refer Figure 40). Software Environment Chapter
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Symbol
Description Selects Data access Selects desired cache
17-16
Octet
Reserved Symbol Line Octet Dword Description Selects desired cache Selects Line1 Line0 Selects four octets Selects upper lower dword 15-6
Figure Data Location cache data read opposed reading information), result (dword) placed format illustrated Figure Similarly, cache data written, write data taken from EAX.
Data
Figure Data
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read opposed reading cache data), result placed format illustrated Figure Similarly, written, write data taken from EAX.
Line1ST Line0ST
Reserved Symbol Line1ST Line0ST Description data read written Line state (M=11, E=10, S=01, I=00) Line state (M=11, E=10, S=01, I=00) bits each 31-15 11-10
Figure Information more detailed information, refer Cache Array Testing" page 237.
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Memory Management Registers Table
AMD-K6-III processor controls segmented memory management with registers listed Table Figure page shows formats these registers.
Memory Management Registers
Register Name Function Contains pointer base global descriptor table Contains pointer base interrupt descriptor table Contains pointer local descriptor table current task Contains pointer task state segment current task
Global Descriptor Table Register Interrupt Descriptor Table Register Local Descriptor Table Register Task Register
Global Interrupt Descriptor Table Registers
32-Bit Linear Base Address 16-Bit Limit
Local Descriptor Table Register Task Register
Selector
32-Bit Linear Base Address
32-Bit Limit
Attributes
Figure Memory Management Registers
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Task State Segment
Figure shows format task state segment (TSS).
Permission Bitmap (IOPB) Kbytes) Limit from
Interrupt Redirection Bitmap (IRB) (eight 32-bit locations)
Operating System Data Structure
Base Address IOPB 0000h 0000h 0000h 0000h 0000h 0000h 0000h EFLAGS 0000h ESP2 0000h ESP1 0000h ESP0 0000h
0000h Selector
Link (Prior Selector)
Figure Task State Segment (TSS)
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Paging
AMD-K6-III processor physically address four Gbytes memory. This memory segmented into pages. size these pages determined operating system design values page directory entries (PDE) page table entries (PTE). processor access both 4-Kbyte pages 4-Mbyte pages, page sizes intermixed within page directory. When page size extension (PSE) set, processor translates linear addresses using either 4-Kbyte translation lookaside buffer (TLB) 4-Mbyte TLB, depending state page size (PS) page directory entry. Figures show 4-Kbyte 4-Mbyte page translations work.
4-Kbyte Page Frame
Page Directory
Page Table
Physical Address
Page Directory Offset
Page Table Offset
Page Offset
Linear Address
Figure 4-Kbyte Paging Mechanism
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4-Mbyte Page Frame
Page Directory
Physical Address
Page Directory Offset
Page Offset
Linear Address
Figure 4-Mbyte Paging Mechanism Figures through show formats PTE. These entries contain information regarding location pages their status.
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Page Table Base Address
Symbol
Description Available Software Reserved Page Size Reserved Accessed Page Cache Disable Page Writethrough User/Supervisor Write/Read Present (valid)
Bits 11-9
Figure Page Directory Entry 4-Kbyte Page Table (PDE)
Physical Page Base Address
Reserved
Symbol
Description Available Software Reserved Page Size Reserved Accessed Page Cache Disable Page Writethrough User/Supervisor Write/Read Present (valid)
Bits 11-9
Figure Page Directory Entry 4-Mbyte Page Table (PDE)
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Physical Page Base Address
Symbol
Description Available Software Reserved Dirty Accessed Page Cache Disable Page Writethrough User/Supervisor Write/Read Present (valid)
Bits 11-9
Figure Page Table Entry (PTE) Descriptors Gates There various types structures registers architecture that define, protect, isolate code segments, data segments, task state segments, gates. These structures called descriptors. Figure page shows application segment descriptor format. Table contains information describing memory segment type which descriptor points. application segment descriptor used point either data code segment. Figure page shows system segment descriptor format. Table contains information describing type segment gate which descriptor points. system segment descriptor used point task state segment, call gate, local descriptor table. AMD-K6-III processor uses gates transfer control between executable segments with different privilege levels. Figure page shows format gate descriptor types. Table contains information describing type segment gate which descriptor points.
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Reserved
Symbol Type
Description Granularity 32-Bit/16-Bit Available Software Present/Valid Descriptor Privilege Level Descriptor Type Table
Bits 14-13 11-8
Base Address 31-24 Segment Limit Type
Base Address 23-16
Base Address 15-0
Segment Limit 15-0
Figure Application Segment Descriptor
Table
Application Segment Types
Description Read-Only Read-Only-Accessed Read/Write Data Read/Write-Accessed Read-Only-Expand-down Read-Only-Expand-down, Accessed Read/Write-Expand-down Read/Write-Expand-down, Accessed Execute-Only Execute-Only-Accessed Execute/Read Code Execute/Read-Accessed Execute-Only-Conforming Execute-Only-Conforming, Accessed Execute/Read-Only-Conforming Execute/Read-Only-Conforming, Accessed
Type Data/Code
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Reserved
Symbol Type
Description Granularity Needed Availability Software Present/Valid Descriptor Privilege Level Descriptor Type Table
Bits 14-13 11-8
Base Address 31-24 Segment Limit Type
Base Address 23-16
Base Address 15-0
Segment Limit 15-0
Figure System Segment Descriptor
Table System Segment Gate Types
Type Description Reserved Available 16-bit Busy 16-bit 16-bit Call Gate Task Gate 16-bit Interrupt Gate 16-bit Trap Gate Reserved Available 32-bit Reserved Busy 32-bit 32-bit Call Gate Reserved 32-bit Interrupt Gate 32-bit Trap Gate
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Reserved
Symbol Type
Description Present/Valid Descriptor Privilege Level Descriptor Type Table
Bits 14-13 11-8
Offset 31-16 Type
Segment Selector
Offset 15-0
Figure Gate Descriptor Exceptions Interrupts Table summarizes exceptions interrupts.
Table Summary Exceptions Interrupts
Interrupt Number 0-255 Interrupt Type Divide Zero Error Debug Breakpoint Overflow Bounds Check Invalid Opcode Device Available Double Fault Reserved Interrupt Invalid Segment Present Stack Segment General Protection Page Fault Floating-Point Error Alignment Check Software Interrupt DIV, IDIV Debug trap fault INTO BOUND Invalid instruction WAIT Fault occurs while handling fault Task switch invalid segment Instruction loads segment present (invalid segment) Stack operation causes limit violation present Segment related miscellaneous invalid actions Page protection violation reference missing page Arithmetic error generated floating-point instruction Data reference unaligned operand. (The flag Cause
Non-Maskable Interrupt signal sampled asserted
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Instructions Supported AMD-K6®-III Processor
This section documents instructions supported AMD-K6-III processor. following tables show instruction mnemonic, opcode, modR/M byte, decode type, RISC86 operation(s) each instruction. Tables through define integer, floating-point, MMX, 3DNow! instructions AMD-K6-III processor, respectively. first column these tables indicates instruction mnemonic operand types with following notations:
reg8-byte integer register defined instruction byte(s) bits modR/M byte mreg8-byte integer register byte integer value memory defined modR/M byte reg16/32-word doubleword integer register defined instruction byte(s) bits modR/M byte mreg16/32-word doubleword integer register, word doubleword integer value memory defined modR/M byte mem8-byte integer value memory mem16/32-word doubleword integer value memory mem32/48-doubleword 48-bit integer value memory mem48-48-bit integer value memory mem64-64-bit value memory imm8-8-bit immediate value imm16/32-16-bit 32-bit immediate value disp8-8-bit displacement value disp16/32-16-bit 32-bit displacement value disp32/48-doubleword 48-bit displacement value eXX-register width depending operand size mem32real-32-bit floating-point value memory mem64real-64-bit floating-point value memory mem80real-80-bit floating-point value memory mmreg-MMX/3DNow! register mmreg1-MMX/3DNow! register defined bits modR/M byte mmreg2-MMX/3DNow! register defined bits modR/M byte Software Environment Chapter
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second third columns list applicable opcode bytes. fourth column lists modR/M byte when used instruction. modR/M byte defines instruction register memory form. modR/M bits documented (memory form), only 10b, 00b. fifth column lists type instruction decode short, long, vector. AMD-K6-III processor decode logic process short, long, vector decode clock. sixth column lists type RISC86 operation(s) required instruction. operation types corresponding execution units follows:
load, fload, mload-load unit store, fstore, mstore-store unit alu-either integer execution units alux-integer execution unit only branch-branch condition unit float-floating-point execution unit meu-Multimedia execution units 3DNow! instructions limm-load immediate, instruction control unit
Table Integer Instructions
Instruction Mnemonic mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8 First Byte 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Second Byte ModR/M Byte Decode Type vector vector vector vector vector vector vector vector vector vector vector vector vector RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8 EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8 EAX, imm16/32 First Byte 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Second Byte ModR/M Byte Decode Type vector vector vector vector vector vector vector short long short long short short short short short short short long short long short long short long short long short short short short short short alux load, alux, store load, alu, store alux load, alux load, alux alux load, alux, store load, alu, store alux load, alux, store alux load, alux, store load, alu, store alux load, alux load, alux RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) ARPL mreg16, reg16 ARPL mem16, reg16 BOUND reg16/32, mreg16/32 reg16/32, mem16/32 reg16/32, mreg16/32 reg16/32, mem16/32 BSWAP BSWAP BSWAP BSWAP BSWAP BSWAP BSWAP BSWAP mreg16/32, reg16/32 mem16/32, reg16/32 mreg16/32, imm8 mem16/32, imm8 mreg16/32, reg16/32 mem16/32, reg16/32 mreg16/32, imm8 mem16/32, imm8 mreg16/32, reg16/32 mem16/32, reg16/32 mreg16/32, imm8 mem16/32, imm8 First Byte 11-xxx-xxx mm-xxx-xxx 11-100-xxx mm-100-xxx 11-xxx-xxx mm-xxx-xxx 11-111-xxx mm-111-xxx 11-xxx-xxx mm-xxx-xxx 11-110-xxx mm-110-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Second Byte ModR/M Byte 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-xxx-xxx mm-xxx-xxx Decode Type short long short long short long vector vector vector vector vector vector vector long long long long long long long long vector vector vector vector vector vector vector vector vector vector vector vector alux load, alux, store load, alu, store alux load, alux, store RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic mreg16/32, reg16/32 mem16/32, reg16/32 mreg16/32, imm8 mem16/32, imm8 CALL full pointer CALL near imm16/32 CALL mem16:16/32 CALL near mreg32 (indirect) CALL near mem32 (indirect) CBW/CWDE CLTS mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8 EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) CMPSB mem8, mem8 CMPSW mem16, mem32 First Byte 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-011-xxx 11-010-xxx mm-010-xxx Second Byte ModR/M Byte 11-xxx-xxx mm-xxx-xxx 11-101-xxx mm-101-xxx Decode Type vector vector vector vector vector short vector vector vector vector vector vector vector vector vector short short short short short short short short short short short short short short long long vector vector alux load, alux load, alux load, alux load, alux alux load, alux load, load, load, store RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic CMPSD mem32, mem32 CMPXCHG mreg8, reg8 CMPXCHG mem8, reg8 CMPXCHG mreg16/32, reg16/32 CMPXCHG mem16/32, reg16/32 CMPXCHG8B EDX:EAX CMPXCHG8B mem64 CPUID CWD/CDQ EDX, mreg8 mem8 mreg16/32 mem16/32 mreg8 mem8 EAX, mreg16/32 EAX, mem16/32 IDIV mreg8 IDIV mem8 IDIV EAX, mreg16/32 IDIV EAX, mem16/32 IMUL reg16/32, imm16/32 IMUL reg16/32, mreg16/32, imm16/32 First Byte 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-110-xxx mm-110-xxx 11-110-xxx mm-110-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-xxx-xxx 11-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Second Byte ModR/M Byte Decode Type vector vector vector vector vector vector vector vector vector vector vector short short short short short short short short vector long vector long vector vector vector vector vector vector vector vector vector vector load, alu, store load, alux, store RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic IMUL reg16/32, mem16/32, imm16/32 IMUL reg16/32, imm8 (sign extended) IMUL reg16/32, mreg16/32, imm8 (signed) IMUL reg16/32, mem16/32, imm8 (signed) IMUL mreg8 IMUL mem8 IMUL EDX:EAX, EAX, mreg16/32 IMUL EDX:EAX, EAX, mem16/32 IMUL reg16/32, mreg16/32 IMUL reg16/32, mem16/32 imm8 imm8 EAX, imm8 EAX, mreg8 mem8 mreg16/32 mem16/32 INVD INVLPG short disp8 JB/JNAE short disp8 First Byte mm-111-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx Second Byte ModR/M Byte mm-xxx-xxx 11-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-xxx-xxx mm-xxx-xxx Decode Type vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector short short short short short short short short vector long vector long vector vector short short branch branch load, alu, store load, alux, store RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic short disp8 JNB/JAE short disp8 JZ/JE short disp8 JNZ/JNE short disp8 JBE/JNA short disp8 JNBE/JA short disp8 short disp8 short disp8 JP/JPE short disp8 JNP/JPO short disp8 JL/JNGE short disp8 JNL/JGE short disp8 JLE/JNG short disp8 JNLE/JG short disp8 JCXZ/JEC short disp8 near disp16/32 near disp16/32 JB/JNAE near disp16/32 JNB/JAE near disp16/32 JZ/JE near disp16/32 JNZ/JNE near disp16/32 JBE/JNA near disp16/32 JNBE/JA near disp16/32 near disp16/32 near disp16/32 JP/JPE near disp16/32 JNP/JPO near disp16/32 JL/JNGE near disp16/32 JNL/JGE near disp16/32 JLE/JNG near disp16/32 JNLE/JG near disp16/32 near disp16/32 (direct) disp32/48 (direct) First Byte Second Byte ModR/M Byte Decode Type short short short short short short short short short short short short short short vector short short short short short short short short short short short short short short short short short vector branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch branch RISC86 Operations branch branch branch branch branch branch branch branch branch branch branch branch branch branch
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Table Integer Instructions (continued)
Instruction Mnemonic disp8 (short) mreg32 (indirect) mem32 (indirect) near mreg16/32 (indirect) near mem16/32 (indirect) LAHF reg16/32, mreg16/32 reg16/32, mem16/32 reg16/32, mem32/48 reg16/32, mem16/32 LEAVE reg16/32, mem32/48 reg16/32, mem32/48 LGDT mem48 reg16/32, mem32/48 LIDT mem48 LLDT mreg16 LLDT mem16 LMSW mreg16 LMSW mem16 LODSB mem8 LODSW mem16 LODSD EAX, mem32 LOOP disp8 LOOPE/LOOPZ disp8 LOOPNE/LOOPNZ disp8 reg16/32, mreg16/32 reg16/32, mem16/32 reg16/32, mem32/48 mreg16 mem16 mreg8, reg8 mem8, reg8 First Byte 11-xxx-xxx mm-xxx-xxx mm-xxx-xxx 11-011-xxx mm-011-xxx 11-xxx-xxx mm-xxx-xxx mm-011-xxx 11-010-xxx mm-010-xxx 11-100-xxx mm-100-xxx mm-010-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx mm-xxx-xxx mm-xxx-xxx 11-101-xxx mm-101-xxx 11-100-xxx mm-100-xxx Second Byte ModR/M Byte Decode Type short vector vector vector vector vector vector vector vector short long vector vector vector vector vector vector vector vector vector long long long short vector vector vector vector vector vector vector short short alux store load, load, load, alu, branch load, load, alu, RISC86 Operations branch
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Table Integer Instructions (continued)
Instruction Mnemonic mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 mreg16, segment mem16, segment segment reg, mreg16 segment reg, mem16 mem8 EAX, mem16/32 mem8, mem16/32, imm8 imm8 imm8 imm8 imm8 imm8 imm8 imm8 EAX, imm16/32 ECX, imm16/32 EDX, imm16/32 EBX, imm16/32 ESP, imm16/32 EBP, imm16/32 ESI, imm16/32 EDI, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 First Byte 11-000-xxx mm-000-xxx 11-000-xxx Second Byte ModR/M Byte 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Decode Type short short short short short short long vector vector vector short short short short short short short short short short short short short short short short short short short short short long short load load store store limm limm limm limm limm limm limm limm limm limm limm limm limm limm limm limm limm store limm store alux load load load RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic mem16/32, imm16/32 MOVSB mem8,mem8 MOVSD mem16, mem16 MOVSW mem32, mem32 MOVSX reg16/32, mreg8 MOVSX reg16/32, mem8 MOVSX reg32, mreg16 MOVSX reg32, mem16 MOVZX reg16/32, mreg8 MOVZX reg16/32, mem8 MOVZX reg32, mreg16 MOVZX reg32, mem16 mreg8 mem8 EAX, mreg16/32 EAX, mem16/32 mreg8 mem8 mreg16/32 mem16/32 (XCHG EAX, EAX) mreg8 mem8 mreg16/32 mem16/32 mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 First Byte 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx Second Byte ModR/M Byte mm-000-xxx Decode Type long long long long short short short short short short short short vector vector vector vector short vector short vector short short vector short vector short long short long short short short short alux load, alux, store load, alu, store alux load, alux load, limm alux alux RISC86 Operations store load, store, alux, alux load, store, alu, load, store, alu, load, load, load, load,
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Table Integer Instructions (continued)
Instruction Mnemonic imm8 EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) imm8, imm8, imm8, mreg 16/32 16/32 POPA/POPAD POPF/POPFD PUSH PUSH First Byte 11-000-xxx mm-000-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx Second Byte ModR/M Byte Decode Type short short short long short long short long vector vector vector vector vector vector vector vector vector vector vector short short short short short short short short short long vector vector long vector load, store load, load, load, load, load, load, load, load, load, load, store, alux alux load, alux, store load, alu, store alux load, alux, store RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH imm8 PUSH imm16/32 PUSH mreg16/32 PUSH mem16/32 PUSHA/PUSHAD PUSHF/PUSHFD mreg8, imm8 mem8, imm8 mreg16/32, imm8 mem16/32, imm8 mreg8, mem8, mreg16/32, mem16/32, mreg8, mem8, mreg16/32, mem16/32, mreg8, imm8 mem8, imm8 mreg16/32, imm8 First Byte 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-010-xxx mm-010-xxx 11-011-xxx mm-011-xxx 11-011-xxx 11-110-xxx mm-110-xxx Second Byte ModR/M Byte Decode Type vector vector vector long short short short short short short short short long long vector long vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector load, store load, store store store store store store store store store store store RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic mem16/32, imm8 mreg8, mem8, mreg16/32, mem16/32, mreg8, mem8, mreg16/32, mem16/32, near imm16 near imm16 mreg8, imm8 mem8, imm8 mreg16/32, imm8 mem16/32, imm8 mreg8, mem8, mreg16/32, mem16/32, mreg8, mem8, mreg16/32, mem16/32, mreg8, imm8 mem8, imm8 mreg16/32, imm8 mem16/32, imm8 mreg8, mem8, mreg16/32, mem16/32, First Byte 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx Second Byte ModR/M Byte mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx Decode Type vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic mreg8, mem8, mreg16/32, mem16/32, SAHF mreg8, imm8 mem8, imm8 mreg16/32, imm8 mem16/32, imm8 mreg8, mem8, mreg16/32, mem16/32, mreg8, mem8, mreg16/32, mem16/32, mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8 EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) First Byte 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-011-xxx mm-011-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-111-xxx mm-111-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Second Byte ModR/M Byte 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx Decode Type vector vector vector vector vector short vector short vector short vector short vector short vector short vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector alux alux alux RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic SCASB mem8 SCASW mem16 SCASD EAX, mem32 SETO mreg8 SETO mem8 SETNO mreg8 SETNO mem8 SETB/SETNAE mreg8 SETB/SETNAE mem8 SETNB/SETAE mreg8 SETNB/SETAE mem8 SETZ/SETE mreg8 SETZ/SETE mem8 SETNZ/SETNE mreg8 SETNZ/SETNE mem8 SETBE/SETNA mreg8 SETBE/SETNA mem8 SETNBE/SETA mreg8 SETNBE/SETA mem8 SETS mreg8 SETS mem8 SETNS mreg8 SETNS mem8 SETP/SETPE mreg8 SETP/SETPE mem8 SETNP/SETPO mreg8 SETNP/SETPO mem8 SETL/SETNGE mreg8 SETL/SETNGE mem8 SETNL/SETGE mreg8 SETNL/SETGE mem8 SETLE/SETNG mreg8 SETLE/SETNG mem8 First Byte 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Second Byte ModR/M Byte Decode Type vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector vector RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic SETNLE/SETG mreg8 SETNLE/SETG mem8 SGDT mem48 SIDT mem48 SHL/SAL mreg8, imm8 SHL/SAL mem8, imm8 SHL/SAL mreg16/32, imm8 SHL/SAL mem16/32, imm8 SHL/SAL mreg8, SHL/SAL mem8, SHL/SAL mreg16/32, SHL/SAL mem16/32, SHL/SAL mreg8, SHL/SAL mem8, SHL/SAL mreg16/32, SHL/SAL mem16/32, mreg8, imm8 mem8, imm8 mreg16/32, imm8 mem16/32, imm8 mreg8, mem8, mreg16/32, mem16/32, mreg8, mem8, mreg16/32, mem16/32, SHLD mreg16/32, reg16/32, imm8 SHLD mem16/32, reg16/32, imm8 SHLD mreg16/32, reg16/32, SHLD mem16/32, reg16/32, SHRD mreg16/32, reg16/32, imm8 First Byte Second Byte ModR/M Byte 11-xxx-xxx mm-xxx-xxx mm-000-xxx mm-001-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-100-xxx mm-100-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx Decode Type vector vector vector vector short vector short vector short vector short vector short vector short vector short vector short vector short vector short vector short vector short vector vector vector vector vector vector alux alux alux alux alux alux RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic SHRD mem16/32, reg16/32, imm8 SHRD mreg16/32, reg16/32, SHRD mem16/32, reg16/32, SLDT mreg16 SLDT mem16 SMSW mreg16 SMSW mem16 STOSB mem8, STOSW mem16, STOSD mem32, mreg16 mem16 mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8 EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) SYSCALL SYSRET First Byte 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-101-xxx mm-101-xxx 11-001-xxx mm-001-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Second Byte ModR/M Byte mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-000-xxx mm-000-xxx 11-100-xxx mm-100-xxx Decode Type vector vector vector vector vector vector vector vector vector vector long long long vector vector short long short long short short short short short short short long short long short long vector vector alux load, alux, store load, alu, store alux load, alux load, alux alux load, alux, store load, alu, store alux load, alux, store store, alux store, alux store, alux RISC86 Operations
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Table Integer Instructions (continued)
Instruction Mnemonic TEST mreg8, reg8 TEST mem8, reg8 TEST mreg16/32, reg16/32 TEST mem16/32, reg16/32 TEST imm8 TEST EAX, imm16/32 TEST mreg8, imm8 TEST mem8, imm8 TEST mreg16/32, imm16/32 TEST mem16/32, imm16/32 VERR mreg16 VERR mem16 VERW mreg16 VERW mem16 WAIT WBINVD XADD mreg8, reg8 XADD mem8, reg8 XADD mreg16/32, reg16/32 XADD mem16/32, reg16/32 XCHG reg8, mreg8 XCHG reg8, mem8 XCHG reg16/32, mreg16/32 XCHG reg16/32, mem16/32 XCHG EAX, XCHG EAX, XCHG EAX, XCHG EAX, XCHG EAX, XCHG EAX, XCHG EAX, XCHG EAX, XLAT First Byte 11-100-xxx mm-100-xxx 11-101-xxx mm-101-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-100-xxx mm-100-xxx 11-101-xxx mm-101-xxx Second Byte ModR/M Byte 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Decode Type short vector short vector long long long long long long vector vector vector vector vector vector vector vector vector vector vector vector vector vector short long long long long long long long vector limm alu, alu, alu, alu, alu, alu, alu, alu, alu, alu, alu, alu, alu, alu, alux alux load, alux load, alux RISC86 Operations
Software Environment
Chapter
21918B/0-October 1999
AMD-K6®-III Processor Data Sheet
Table Integer Instructions (continued)
Instruction Mnemonic mreg8, reg8 mem8, reg8 mreg16/32, reg16/32 mem16/32, reg16/32 reg8, mreg8 reg8, mem8 reg16/32, mreg16/32 reg16/32, mem16/32 imm8 EAX, imm16/32 mreg8, imm8 mem8, imm8 mreg16/32, imm16/32 mem16/32, imm16/32 mreg16/32, imm8 (signed ext.) mem16/32, imm8 (signed ext.) First Byte 11-110-xxx mm-110-xxx 11-110-xxx mm-110-xxx 11-110-xxx mm-110-xxx Second Byte ModR/M Byte 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx Decode Type short long short long short short short short short short short long short long short long alux load, alux, store load, alu, store alux load, alux load, alux alux load, alux, store load, alu, store alux load, alux, store RISC86 Operations
Table Floating-Point Instructions
Instruction Mnemonic F2XM1 FABS FADD ST(0), ST(i) FADD ST(0), mem32real FADD ST(i), ST(0) FADD ST(0), mem64real FADDP ST(i), ST(0) FBLD FBSTP FCHS FCLEX
Note:
First Byte
Second Byte
ModR/M Byte
Decode Type short short
RISC86 Operations float float float fload, float float fload, float float
Note
11-000-xxx mm-000-xxx 11-000-xxx mm-000-xxx 11-000-xxx mm-100-xxx mm-110-xxx
short short short short short vector vector short vector
float
last three bits modR/M byte select stack entry ST(i).
Chapter
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AMD-K6®-III Processor Data Sheet
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Table Floating-Point Instructions (continued)
Instruction Mnemonic FCOM ST(0), ST(i) FCOM ST(0), mem32real FCOM ST(0), mem64real FCOMP ST(0), ST(i) FCOMP ST(0), mem32real FCOMP ST(0), mem64real FCOMPP FCOS FDECSTP FDIV ST(0), ST(i) (single precision) FDIV ST(0), ST(i) (double precision) FDIV ST(0), ST(i) (extended precision) FDIV ST(i), ST(0) (single precision) FDIV ST(i), ST(0) (double precision) FDIV ST(i), ST(0) (extended precision) FDIV ST(0), mem32real FDIV ST(0), mem64real FDIVP ST(0), ST(i) FDIVR ST(0), ST(i) FDIVR ST(i), ST(0) FDIVR ST(0), mem32real FDIVR ST(0), mem64real FDIVRP ST(i), ST(0) FFREE ST(i) FIADD ST(0), mem32int FIADD ST(0), mem16int FICOM ST(0), mem32int FICOM ST(0), mem16int FICOMP ST(0), mem32int FICOMP ST(0), mem16int FIDIV ST(0), mem32int
Note:
First Byte
Second Byte
ModR/M Byte 11-010-xxx mm-010-xxx mm-010-xxx 11-011-xxx mm-011-xxx mm-011-xxx
Decode Type short short short short short short short short short
RISC86 Operations float fload, float fload, float float fload, float fload, float float float float float float float float float float fload, float fload, float float float float fload, float fload, float float float fload, float fload, float fload, float fload, float fload, float fload, float fload, float
Note
11-011-001
11-110-xxx 11-110-xxx 11-110-xxx 11-111-xxx 11-111-xxx 11-111-xxx mm-110-xxx mm-110-xxx 11-111-xxx 11-110-xxx 11-111-xxx mm-111-xxx mm-111-xxx 11-110-xxx 11-000-xxx mm-000-xxx mm-000-xxx mm-010-xxx mm-010-xxx mm-011-xxx mm-011-xxx mm-110-xxx
short short short short short short short short short short short short short short short short short short short short short short
last three bits modR/M byte select stack entry ST(i).
Software Environment
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AMD-K6®-III Processor Data Sheet
Table Floating-Point Instructions (continued)
Instruction Mnemonic FIDIV ST(0), mem16int FIDIVR ST(0), mem32int FIDIVR ST(0), mem16int FILD mem16int FILD mem32int FILD mem64int FIMUL ST(0), mem32int FIMUL ST(0), mem16int FINCSTP FINIT FIST mem16int FIST mem32int FISTP mem16int FISTP mem32int FISTP mem64int FISUB ST(0), mem32int FISUB ST(0), mem16int FISUBR ST(0), mem32int FISUBR ST(0), mem16int ST(i) mem32real mem64real mem80real FLD1 FLDCW FLDENV FLDL2E FLDL2T FLDLG2 FLDLN2 FLDPI
Note:
First Byte
Second Byte
ModR/M Byte mm-110-xxx mm-111-xxx mm-111-xxx mm-000-xxx mm-000-xxx mm-101-xxx mm-001-xxx mm-001-xxx
Decode Type short short short short short short short short short vector
RISC86 Operations fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float
Note
mm-010-xxx mm-010-xxx mm-011-xxx mm-011-xxx mm-111-xxx mm-100-xxx mm-100-xxx mm-101-xxx mm-101-xxx 11-000-xxx mm-000-xxx mm-000-xxx mm-101-xxx mm-101-xxx mm-100-xxx
short short short short short short short short short short short short vector short vector short short short short short short
fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float fload, float float float float float float
last three bits modR/M byte select stack entry ST(i).
Chapter
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AMD-K6®-III Processor Data Sheet
21918B/0-October 1999
Table Floating-Point Instructions (continued)
Instruction Mnemonic FLDZ FMUL ST(0), ST(i) FMUL ST(i), ST(0) FMUL ST(0), mem32real FMUL ST(0), mem64real FMULP ST(0), ST(i) FNOP FPATAN FPREM FPREM1 FPTAN FRNDINT FRSTOR FSAVE FSCALE FSIN FSINCOS FSQRT (single precision) FSQRT (double precision) FSQRT (extended precision) mem32real mem64real ST(i) FSTCW FSTENV FSTP mem32real FSTP mem64real FSTP mem80real FSTP ST(i) FSTSW FSTSW mem16
Note:
First Byte
Second Byte
ModR/M Byte 11-001-xxx 11-001-xxx mm-001-xxx mm-001-xxx 11-001-xxx
Decode Type short short short short short short short short short short vector short
RISC86 Operations float float float fload, float fload, float float float float float float float
Note
mm-100-xxx mm-110-xxx mm-010-xxx mm-010-xxx 11-010-xxx mm-111-xxx mm-110-xxx mm-011-xxx mm-011-xxx mm-111-xxx 11-011-xxx mm-111-xxx
vector vector short short vector short short short short short short vector vector short short vector short vector vector float fstore fstore float float float fstore fstore fstore float float
last three bits modR/M byte select stack entry ST(i).
Software Environment
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Table Floating-Point Instructions (continued)
Instruction Mnemonic FSUB ST(0), mem32real FSUB ST(0), mem64real FSUB ST(0), ST(i) FSUB ST(i), ST(0) FSUBP ST(0), ST(i) FSUBR ST(0), mem32real FSUBR ST(0), mem64real FSUBR ST(0), ST(i) FSUBR ST(i), ST(0) FSUBRP ST(i), ST(0) FTST FUCOM FUCOMP FUCOMPP FXAM FXCH FXTRACT FYL2X FYL2XP1 FWAIT
Note:
First Byte
Second Byte
ModR/M Byte mm-100-xxx mm-100-xxx 11-100-xxx 11-101-xxx 11-101-xxx mm-101-xxx mm-101-xxx 11-100-xxx 11-101-xxx 11-100-xxx
Decode Type short short short short short short short short short short short short short short short
RISC86 Operations fload, float fload, float float float float fload, float fload, float float float float float float float float float float float float
Note
11-100-xxx 11-101-xxx 11-001-xxx
short vector short short vector
last three bits modR/M byte select stack entry ST(i).
Table MMXInstructions
Instruction Mnemonic EMMS MOVD mmreg, mreg32 MOVD mmreg, mem32 MOVD mreg32, mmreg MOVD mem32, mmreg MOVQ mmreg1, mmreg2
Note:
Prefix First Byte(s) Byte
ModR/M Byte 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx
Decode Type vector short short short short short
RISC86 Operations mload mstore, load mstore
Note
Bits modR/M byte select integer register.
Chapter
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AMD-K6®-III Processor Data Sheet
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Table MMXInstructions (continued)
Instruction Mnemonic MOVQ mmreg, mem64 MOVQ mmreg2, mmreg1 MOVQ mem64, mmreg PACKSSDW mmreg1, mmreg2 PACKSSDW mmreg, mem64 PACKSSWB mmreg1, mmreg2 PACKSSWB mmreg, mem64 PACKUSWB mmreg1, mmreg2 PACKUSWB mmreg, mem64 PADDB mmreg1, mmreg2 PADDB mmreg, mem64 PADDD mmreg1, mmreg2 PADDD mmreg, mem64 PADDSB mmreg1, mmreg2 PADDSB mmreg, mem64 PADDSW mmreg1, mmreg2 PADDSW mmreg, mem64 PADDUSB mmreg1, mmreg2 PADDUSB mmreg, mem64 PADDUSW mmreg1, mmreg2 PADDUSW mmreg, mem64 PADDW mmreg1, mmreg2 PADDW mmreg, mem64 PAND mmreg1, mmreg2 PAND mmreg, mem64 PANDN mmreg1, mmreg2 PANDN mmreg, mem64 PCMPEQB mmreg1, mmreg2 PCMPEQB mmreg, mem64 PCMPEQD mmreg1, mmreg2 PCMPEQD mmreg, mem64
Note:
Prefix First Byte(s) Byte
ModR/M Byte mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
Decode Type short short short short short short short short short short short short short short short short short short short short short short short short short short short short short short short
RISC86 Operations mload mstore mload, mload, mload, mload, mload, mload, mload, mload, mload, mload, mload, mload, mload, mload,
Note
Bits modR/M byte select integer register.
Software Environment
Chapter
21918B/0-October 1999
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Table MMXInstructions (continued)
Instruction Mnemonic PCMPEQW mmreg1, mmreg2 PCMPEQW mmreg, mem64 PCMPGTB mmreg1, mmreg2 PCMPGTB mmreg, mem64 PCMPGTD mmreg1, mmreg2 PCMPGTD mmreg, mem64 PCMPGTW mmreg1, mmreg2 PCMPGTW mmreg, mem64 PMADDWD mmreg1, mmreg2 PMADDWD mmreg, mem64 PMULHW mmreg1, mmreg2 PMULHW mmreg, mem64 PMULLW mmreg1, mmreg2 PMULLW mmreg, mem64 mmreg1, mmreg2 mmreg, mem64 PSLLD mmreg1, mmreg2 PSLLD mmreg, mem64 PSLLD mmreg, imm8 PSLLQ mmreg1, mmreg2 PSLLQ mmreg, mem64 PSLLQ mmreg, imm8 PSLLW mmreg1, mmreg2 PSLLW mmreg, mem64 PSLLW mmreg, imm8 PSRAD mmreg1, mmreg2 PSRAD mmreg, mem64 PSRAD mmreg, imm8 PSRAW mmreg1, mmreg2 PSRAW mmreg, mem64 PSRAW mmreg, imm8
Note:
Prefix First Byte(s) Byte
ModR/M Byte 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-110-xxx 11-xxx-xxx mm-xxx-xxx 11-110-xxx 11-xxx-xxx mm-xxx-xxx 11-110-xxx 11-xxx-xxx mm-xxx-xxx 11-100-xxx 11-xxx-xxx mm-xxx-xxx 11-100-xxx
Decode Type short short short short short short short short short short short short short short short short short short short short short short short short short short short short short short short
RISC86 Operations mload, mload, mload, mload, mload, mload, mload, mload, mload, mload, mload, mload, mload,
Note
Bits modR/M byte select integer register.
Chapter
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AMD-K6®-III Processor Data Sheet
21918B/0-October 1999
Table MMXInstructions (continued)
Instruction Mnemonic PSRLD mmreg1, mmreg2 PSRLD mmreg, mem64 PSRLD mmreg, imm8 PSRLQ mmreg1, mmreg2 PSRLQ mmreg, mem64 PSRLQ mmreg, imm8 PSRLW mmreg1, mmreg2 PSRLW mmreg, mem64 PSRLW mmreg, imm8 PSUBB mmreg1, mmreg2 PSUBB mmreg, mem64 PSUBD mmreg1, mmreg2 PSUBD mmreg, mem64 PSUBSB mmreg1, mmreg2 PSUBSB mmreg, mem64 PSUBSW mmreg1, mmreg2 PSUBSW mmreg, mem64 PSUBUSB mmreg1, mmreg2 PSUBUSB mmreg, mem64 PSUBUSW mmreg1, mmreg2 PSUBUSW mmreg, mem64 PSUBW mmreg1, mmreg2 PSUBW mmreg, mem64 PUNPCKHBW mmreg1, mmreg2 PUNPCKHBW mmreg, mem64 PUNPCKHDQ mmreg1, mmreg2 PUNPCKHDQ mmreg, mem64 PUNPCKHWD mmreg1, mmreg2 PUNPCKHWD mmreg, mem64 PUNPCKLBW mmreg1, mmreg2 PUNPCKLBW mmreg, mem64
Note:
Prefix First Byte(s) Byte
ModR/M Byte 11-xxx-xxx mm-xxx-xxx 11-010-xxx 11-xxx-xxx mm-xxx-xxx 11-010-xxx 11-xxx-xxx mm-xxx-xxx 11-010-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx 11-xxx-xxx mm-xxx-xxx
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