purpose this application note show user interface Am188TMEM microcontr

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Interfacing Am188TMEM Controller DSLACTM/QSLACDevices Using
purpose this application note show user interface Am188TMEM microcontroller DSLACand QSLACdevices using Synchronous Serial Interface (SSI). These techniques restricted Am188EM microcontroller; other members Am186microcontroller family with ports interfaced similar fashion.
BACKGROUND
Traditionally, line cards they processor all) used simple, inexpensive 8-bit microcontroller. However, number lines card increases, 16-bit controllers like Am188TMEM microcontroller become more attractive several reasons: Over time 16-bit controller costs have decreased More peripheral functions integrated, reducing external components counts Newer, smaller packaging options available 16-bit controllers generally offer larger address spaces These reasons, combined with availability superior, low-cost development tools like Microsoft Borland educ e-to term maintenance costs. SLACdevice connects host processor through 3-pin serial interface. While this interface used primarily initialize SLAC device, several critical functions SLICdevice monitored through serial interface; therefore, necessary make interface fast possible. Using port Am188EM microcontroller reduces software overhead making interface much faster. serial Microprocessor Interface (MPI) DSLACand QSLACdevices pre-dates most-if all-of today's industry standard serial interfaces ports, including Synchronous Serial Interface (SSI) port Am188EM microcontroller. Because these serial interfaces (MPI SSI) were designed compatible, takes little effort make them work together. This application note attempts show that worth effort explains most line-card designs, only cost effective alternative interface processor's PIOs manipulate signal lines directly from software. While this perfectly acceptable approach-even
desirable some cases-the port greatly reduce software overhead code space.
FURTHER REFERENCES
remainder this application note assumes least passing familiarity with chips involved; Am188EM microcontroller, Am79C02 DSLAC family, Am79Q02 QSLAC family. additional details needed, following literature available from AMD:
Am186TMEM/EMLV Am188TMEM/EMLV Microcontrollers Data Sheet, order #19168 Am186TMEM Am188TMEM Microcontrollers User's Manual, order #19713 Am79C02/03/031(A) DSLACDevice Data Sheet, order #18503 Am79Q02/021/031 QSLACDevice Data Sheet, Available through your local sales office
AMD's complete line line card devices found Linecard Products Public Infrastructure Market Data Book, Publication #18503.
HARDWARE OVERVIEW
QSLAC DSLAC devices have very similar MPIs; both serial, master/slave-type interfaces. Differences between devices described following paragraphs. system line card microprocessor master interface designed that multiple slaves (i.e. SLAC devices) attached single master's bus. signals, like most digital buses, consist three types signals: Clock/Control Address Data data line (DIO) bidirectional, three-state serial bus. Am79C02 separate data (Din) data (Dout) pins that strapped together look
Publication# 21728 Rev: Amendment/0 Issue Date: 1997
This document contains information product under development Advanced Micro Devices. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice.
like other SLAC device's single pin. data this line consists eight-bit bytes transmitted most significant (MSB, first, regardless direction. master initiates transfers sending command byte SLAC device. Each command predetermined length (number bytes) direction (read write). example, master microprocessor sends command number (read filter coefficients) DSLAC device, DSLAC device knows transmit bytes. Because command determines what transmitting, master slave; important make sure software drivers correct prevent contention, which could damage devices. Also, case read, SLAC device will accept command until finished (i.e. data clocked out). Software verification critical. clock signal (DCLK) free active only during data transfers input SLAC device. DCLK maximum frequency 4.096 both SLAC devices. Data clocked into SLAC device rising edge DCLK, data sent falling edge DCLK. This common technique makes easier satisfy setup hold time requirements. DCLK stopped indefinitely either High state chip select input held High. Each individual SLAC devices addressed (i.e. selected) pulling chip select inputs Low. QSLAC device single chip select four channels while DSLAC device separate chip select each channel (CS1 CS2). rising edge chip select marks frames each byte; therefore, chip select line must High least minimum period before next byte read written. DSLAC device's minimum period while QSLAC device's minimum Finally, QSLAC device does have interrupt part microprocessor interface. description this available Am79Q02/03/031 QSLACDevice Data Sheet.
pin-count interface application-specific integrated circuits (ASICs). Fortunately, although design, similar SLAC device's MPI. Like MPI, synchronous, master/slave serial protocol that allows multiple slaves bus. maximum clock rate high MHz. consists four signals: SCLK SDATA SDEN0 SDEN1 Each these signals separate pin. pins shared (i.e. multiplexed) with Am188EM microcontroller's PIOs. This allows pins used PIOs their normal function needed. SDATA pin, like DIO, bidirectional, three-state serial bus. Unlike DIO, weak pull-up pull-down resistor keeps last value systems that cannot tolerate three-state inputs. data this consists eight-bit bytes transmitted least significant (LSB, first. master/slave protocol controlled entirely with software. clock signal (SCLK) only active during byte transfers output. frequency derived from processor's internal clock dividing case 40-MHz device, this allows speeds mentioned above. Like SLAC device, data clocked falling edge clocked rising edge. enable pins (SDEN0 SDEN1) outputs unlike chip selects MPI, they highlevel active. While state SDEN pins controlled software somewhat like PIO, must high interface transmit receive.
COMPARING
Table summarizes similarities differences between interfaces.
HARDWARE OVERVIEW
Synchronous Serial Interface (SSI) Am188EM microcontroller designed provide
Interfacing Am188TMEM Controller DSLACTM/QSLACDevices Using
Table Comparison
Feature Word size order Master/Slave frequency Transmit clock edge Receive clock edge Clock inactive state Synchronous framed Enable state first 4.096 falling rising either first falling rising high high order reversed Yes, with software SDEN wrong polarity Comment
SOLVING REVERSED-BIT-ORDER PROBLEM
reversed-bit-order problem severe might seem. Generally, there types data sent over serial interface: coefficients flags. oeffic ients gener ated AmSLACsoftware stored values table microprocessor's non-volatile storage. should difficult rearrange order prior placing them table, preventing need microprocessor flags used monitor state SLAC devices' pins real time, because flags independent, host microprocessor's code only needs know where they byte. Order important. reversal should significant taken into account software. both cases, should necessary reversal microprocessor while use.
SDEN0 SDEN1 were used. However, because their pins used, they programmed PIOs used drive chip selects. pins wasted. Using software drive SLAC devices' chip selects through PIOs also provides solution polarity problem framing issue. Because software controlling state PIOs directly, trivial invert sense PIOs relative SDEN0 SDEN1. Correctly controlling chip selects further requires that high after each byte transmitted received. multiple writes reads illustrated Am186TMEM Am188TMEM Microcontrollers User's Manual figures 11-5 11-6 allowed. Figure shows resulting connections DSLAC device. QSLAC device similar, only chip select. Am188EM(tqfp) SDATA (pin SCLK (pin PIO22 (pin PIO23 (pin Figure Am79C03(plcc) (pin DCLK (pin (pin (pin
SOLVING ENABLE-POLARITY PROBLEM
obvious solution inverters SDEN outputs, with little extra software, possible without glue logic. Because DSLAC device requires chip selects QSLAC device requires chip select, inverters used, this technique only handle DSLAC device QSLAC devices. more SLAC devices required, easiest solution general PIOs Am188EM microcontroller drive chip selects SLAC devices. alternate solution Am188EM microcontroller's pins instead SDEN drive chip selects. discussed above, multiple SLAC devices more than chip selects needed, PIOs required anyway. Always using pins maintains consistency better solution. Software will still need control bits
Interface Connections
TIMING CONSIDERATIONS
following tables compare timing requirements worst case. each case table, worst case determined looking most stringent requirement other interface meet requirement. There only speed grade DSLAC device QSLAC device, there multiple speed grades Am188EM microcontroller, each case been looked with worst possibility mind. example, Table date setup time case where Am188EM microcontroller driving
Interfacing Am188TMEM Controller DSLACTM/QSLACDevices Using
data DSLAC device calculated described following paragraph. DSLAC device requirement read directly from data sheet parameter (tIDS Input Data Setup Time). This value both DSLAC QSLAC devices. Determining what Am188EM microcontroller provides takes little calculation. First, decide what minimum period SCLK. This really determined DSLAC device, where minimum DCLK period determined parameter (tDCL Data Clock Pulse Width), which SDATA guaranteed stable more than after falling edge SCLK parameter (tSLDV SCLK Data Valid) slowest processor MHz). Subtracting from leaves worst-case setup time before rising edge DCLK. previous example assumes worst-case duty cycle DCLK. fastest clock allowed period clock perfectly symmetric, either High period short rather than half clock rate (122 ns). case Am188EM microcontroller this probably over-design. Because SCLK's frequency related half CLKOUTA, should always close duty cycle. this case, data setup time provided Am188EM microcontroller closer
tables illustrate, there generous margins even worst case. case data hold time Table there specification given Am188EM microcontroller data sheet quickly SDATA change after clock goes Low. assumed that worst case that SDATA will instantaneously change soon SCLK goes Low. This means that hold time provided Am188EM microcontroller same minimum SCLK High period specified DSLAC device setup hold time times given case where SDEN driven from inverters discussed above. Even though SDEN driven interface, still controlled software writing zero bits synchronous serial control (SSC) register. Because they controlled software, actual delays will much longer than specified. same will hold true PIOs used drive SLAC device chip selects. Table gives usable options each available speed grades resultant data transfer rate. achieve maximum DCLK rate MHz, Am188EM microcontroller's internal frequency must (÷2,
Table Microprocessor Output (Data Write)
DSLAC Device Requires (ns, min) Data setup time Data hold time setup time hold time Am188EM Microcontroller Comments Provides (ns, min)
Table
Microprocessor Input (Data Read)
DSLAC Device Provides (ns, min)
Am188EM Microcontroller Requires (ns, min) Data setup time Data hold time
Comments
SOFTWARE CONSIDERATIONS
basics using port from software illustrated with subroutines; first subroutine writes byte SLAC device second reads single byte. These subroutines, along with initialization, form core necessary drivers. port appears five registers Am188EM microcontroller peripheral control block. This 256-byte block located either memory
space location pointed Peripheral Control Block Relocation Register. Because base location block moved, location individual registers specified offset from Peripheral Control Block Relocation Register rather than absolute address. ports control registers also located this block addresses. reset, block located 0FF00h space.
Interfacing Am188TMEM Controller DSLACTM/QSLACDevices Using
Table Port Registers
Offset from Register Mnemonic Register Name SSD1 SSD0 Synchronous Serial Status Synchronous Serial Control Synchronous Serial Transmit Synchronous Serial Transmit Synchronous Serial Receive
After waiting receive data: Enable CS1, [PDATA1 Enable receive, high [SSC Start reception [read SSR] Wait [SSS Disable receive, [SSC Disable CS1, high [PDATA1 Read revision number [read SSR] Appendix provides listings general purpose read write routines. They have been coded assembly language maximize speed. most cases natural flow software will guarantee that there least between bytes. listing given, print commands between writes reads take much longer than this case, either software delay Am188EM microcontroller's timer could provide necessary wait.
bit-level definitions from Port registers from Table shown Figure
SCLKDIV
SSD1
TRANSMIT REGISTER
SSD0
TRANSMIT REGISTER
RECEIVE REGISTER
Figure Bit-Level Definition Port Registers Port Busy (PB) status register goes High when transmit receive operation progress. SDEN enables (DE0 DE1) control state SDEN enable transmission reception. write transmit register read receive register initiates transfer. more complete functional description these registers, including features used here, refer Am186TMEM Am188TMEM Microcontrollers User's Manual. Assuming connections Figure following steps required execute Read Revision Code Number Command (#23) DSLAC device. Send command: Enable CS1, [PDATA1 Enable transmit, high [SSC Write command, reversed [SSD0 0CEh] Wait [SSS Disable transmit, [SSC Disable CS1, high [PDATA1
INITIALIZATION
There parts initialization process. First, on-board peripheral Am188EM microcontroller (PIO ports) must proper operation. This includes setting mode direction pins well setting itself known state. Second, that interface operational, SLAC device itself should initialized. Each SLAC devices have recommended power-up sequence that found data sheet. example, DSLAC device's recommended sequence follows: Select MCLK (command #6), Software reset (command #2), Program coefficients parameters, Activate (command Am188EM microcontroller's port should initialized soon possible after reset ensure output pins correct state, needed after power stable before commands sent SLAC device. Because Am188EM microcontroller also requires lock (parameter LOCK most systems have external power-up-reset monitor that provides this delay. not, systems have separate power supplies, software must wait before sending first command. QSLAC device power interruption flag (P1, command that should checked after delay.
Interfacing Am188TMEM Controller DSLACTM/QSLACDevices Using
SOFTWARE LISTING
software listing Appendix written compiled with Microsoft's C/C++ compiler. This example code illustrates read DSLAC device's filter coefficients. software tested several evaluation boards available from AMD. ASLACInterface Board (ACIF) used load known coefficients into DSLAC Device Noise Board. SD186EM demonstration board then connected place ACIF Board read back coefficients. main body program first initializes various ports, then sends "read filter" command.
noted previously, command must reversed. "for" loop then reads back bytes filter coefficients. subroutines SSI_read SSI_write written assembly language speed clarity. They implement code required send receive single byte. Once again, bytes coming back from DSLAC device reversed.
SUMMARY
While serial interfaces were designed used together, they surprisingly compatible. simple fixes required make them work together worth effort save code space speed operation.
Interfacing Am188TMEM Controller DSLACTM/QSLACDevices Using
Appendix
Software Listing
#include <stdio.h> #include "sys\types.h" #include "sd186em.h" defines register addresses function prototypes
void void
SSI_init(void); SSI_write(int);
Uint8 SSI_read(void);
useful constants #define #define #define #define #define #define READ_Z P22_LOW P22_HI DE0_LOW DE0_HI PB_HI 0xA1 0xFFBF 0x0040 0xFFFE 0x0001 0x0001 read z-filter (bit reversed) mask high mask mask high mask high mask
void main()
Uint8
buf[256];
printf("Start Program\n");
SSI_init(); printf("Finish SSI_init\n");
(i=0; i<256; i++) buf[i] printf("Finish buffer initialization\n");
SSI_write(READ_Z); printf("Command Sent\n");
(i=0; i<14; i++) buf[i] SSI_read(); printf("byte \n",i,buf[i]); loop
exit(0); MAIN *******************************
void SSI_init(void) _asm{
dx,PIOMODE1 ax,dx ax,0x00C0 dx,ax
point mode register read register space) bits make output) write register space)
dx,PDIR1 ax,dx ax,0xFF3F dx,ax
point PIO1 DIRECTION register read direction output) write
dx,PDATA1 ax,dx ax,0x00C0 dx,ax
point PIO1 DATA register read data bits make them high) write
dx,SSC ax,0x0030 dx,ax
point sync serial control register divisor enables (inactive) write
_asm
//============================ SSI_INIT =============================
Uint8 SSI_read(void)
_asm{
dx,PDATA1 ax,dx ax,P22_LOW dx,ax
STEP (PIO
dx,SSC ax,dx ax,DE0_HI dx,ax
STEP enable reception (i.e.
dx,SSR ax,dx
STEP start reception (with dummy read SSR)
dx,SSS ax,dx ax,PB_HI
STEP wait data (done when
dx,SSC ax,dx ax,DE0_LOW dx,ax
STEP disable reception (set low)
dx,PDATA1 ax,dx ax,P22_HI dx,ax
STEP high (PIO
dx,SSR ax,dx
STEP read data
i,ax
move data output variable
_asm
return(i);
//============================ SSI_READ =============================
static void SSI_write(i)
_asm{
dx,PDATA1 ax,dx ax,P22_LOW dx,ax
STEP (PIO
dx,SSC ax,dx ax,DE0_HI dx,ax
STEP enable transmission (i.e.
dx,SSD0 ax,i dx,ax
STEP transmit byte
dx,SSS ax,dx ax,PB_HI
STEP wait completion (done when
dx,SSC ax,dx ax,DE0_LOW dx,ax
STEP disable transmission (set low)
dx,PDATA1 ax,dx ax,P22_HI dx,ax
STEP high (PIO
_asm
//========================== SSI_WRITE ==============================
Trademarks AMD, logo, combinations thereof trademarks Advanced Micro Devices, Inc. Am186, Am188, AmSLAC, DSLAC, QSLAC, SLAC, SLIC trademarks Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.

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