July 2001, ver. Functional Specification Flexible interface

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July 2001, ver. Functional Specification Flexible interface

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Atlantic Interface
July 2001, ver.
Functional Specification
Flexible interface packet-oriented data arbitrary length Interfaces Altera® cell packet MegaCore® functions Synchronous point-to-point connection High throughput with flexible flow control Master source/slave sink master sink/slave source relationships Scalable clock frequency data path width Fixed start packet (SOP) alignment simplifies packet handling
Topology
Figure shows block diagram Atlanticinterface, including control signals.
Figure Block Diagram
Atlantic Interface Master (Source) Atlantic Interface Slave (Sink)
Atlantic Interface Master (Sink) Atlantic Interface Slave (Source)
Altera Corporation
A-FS-13-2.0
Atlantic Interface Functional Specification
Functional Description
direction data flow Atlantic interface either from master slave (master source) slave master (slave source). Figure shows example data packet either master source slave source. assumption that continuously asserted.
Figure Example Data Packet
Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
Notes:
marks start data packet. marks data packet, indicates number invalid bytes.
Master Source
slave sink interface responds write commands from master source interface. master asserts drives data dat. following rising edge clk, slave observes ena. asserted, slave accepts processes data; not, discards dat. required this direction because indicates when contains new, valid data. deasserted, undefined. slave sink cycle-by-cycle flow control; uses request master stop data transfer. However, master take several clock cycles stop transferring data, depending application. master source, there delay after asserted deasserted dataflow (and associated data interface signals) starts stops. Figure shows timing Atlantic interface with master source.
Altera Corporation
Atlantic Interface Functional Specification
Figure Atlantic Interface Timing-Master Source Slave Sink
Valid Valid Valid Valid Valid Valid Valid Valid
Notes:
Slave sink indicates space threshold words. master source begins writing data slave sink. Slave sink indicates longer space threshold words. Master source continue send data, must ensure that slave sink does overflow. Master source stops sending data. Slave sink indicates space threshold words. Master source begins writing data slave sink. Slave sink indicates still space, master source data. Master source identifies error, asserts err. Master source identifies data error, asserts holds until deasserted.
Slave Source
master sink interface generates read commands slave source interface. master asserts when ready data. following rising edge, slave observes asserted. slave immediately either drives data asserts val, deasserts val. following rising edge, master observes state samples dat. asserted, master uses value from dat; not, undefined master discards contents dat. indicates that slave accept significant amount data. amount data application dependent. master continues assert extended period time after deasserted, slave overflow. Figure shows general slave source flow control.
Altera Corporation
Atlantic Interface Functional Specification
Figure Slave Source Flow Control
Valid Valid Valid
Notes:
Master asserts request data. Slave drives asserts response request. Slave holds because master requesting additional data. master sample data point since being held. Master reasserts request next piece data. Slave data deasserts val. Slave data. Slave drives asserts val. Slave data. Slave drives asserts val.
master assert continuously. slave then issue data will, using indicate contains data. Figure shows slave source with slave flow control.
Figure Slave Source With Slave Flow Control
Valid Valid Valid
Notes:
Slave data. Slave drives asserts val. Slave data; becomes undefined. Slave deasserts val. Slave data. Slave drives asserts val. Slave data; becomes undefined. Slave deasserts val.
Altera Corporation
Atlantic Interface Functional Specification
general, master only accepts data observes asserted current rising edge asserted previous rising edge clk. However, deasserted, slave holds constant value. master then sample time until edge following reassertion ena. Figure shows slave source with master flow control.
Figure Slave Source With Master Flow Control
Valid Valid Valid Valid
Notes:
Master requests data asserting ena. Slave drives data dat. Slave observes deasserted holds their current value. Master sample these edges.
slave source master sink there one-cycle delay after asserted deasserted dataflow (and associated data interface signals) starts stops. When master asserts ena, data available data until after following rising edge clk. Similarly, when master deasserts ena, will have values following rising edge hold their values until deasserted. However, interface pipelined, delay does affect throughput interface. indicates that slave significant amount data available. However, master assert negated. slave does have data available when asserted, deasserts val. Figure shows timing Atlantic interface with master sink.
Altera Corporation
Atlantic Interface Functional Specification
Figure Atlantic Interface Timing-Slave Source Master Sink
Valid Valid Valid Valid Valid
Notes:
Slave source indicates that data available (either threshold words available, EOP). Master sink begins reading data. Master sink decides stop reading data clock cycle. remains asserted data, sop, hold their current values. Slave source indicates that less than threshold words available. master sink continue read data until detects deasserted. Master sink continues read data, validates data with val. Slave source cannot supply more data, deasserts val. Master sink goes idle until reasserted. Slave source identifies error, asserts err. Slave source identifies data error, asserts until deasserted.
Compatibility
ensure that individual implementations Atlantic interface compatible they must have:
same data width Compatible data directions (data source connecting data sink) Compatible control interfaces (master interface connecting slave interface) Compatible threshold levels (slave sink overflow, slave source operate inefficiently thresholds incorrectly set) support multiple Atlantic interfaces same module, user should differentiate each interface prefixing signal names: <prefix>_<signal name>.
Signals
Altera Corporation
Atlantic Interface Functional Specification
Table describes Atlantic interface global signals.
Table Global Signals
Name
reset_n
Direction
Input Input
Description
Clock, rising edge active. Atlantic interface uses single-edge clocking. signals synchronous clk, master slave same clock domain. Asynchronous reset, active low. asserted asynchronously, must deasserted synchronously clk.
Table describes Atlantic interface control signals.
Table Control Signals
Name
Direction
Master slave
Description
Data transfer enable signal. driven interface master used control flow data across interface. master source, behaves write enable from master slave. master asserts simultaneously. When slave observes asserted rising edge immediately captures Atlantic data interface signals. slave source, behaves read enable from master slave. When slave observes asserted rising edge drives, following rising edge, Atlantic data interface signals asserts val. master captures data interface signals following rising edge. slave unable provide data, deasserts more clock cycles until prepared drive valid data interface signals.
Slave master
Data valid signal. Present only slave source master sink interface. indicates validity data signals. updated every clock edge where sampled asserted, holds current value along with where sampled deasserted. When asserted, Atlantic data interface signals valid. When deasserted, Atlantic data interface signals invalid must disregarded. determine whether data been received, master must qualify signal with previous state signal. Data available signal. When slave master direction, high, slave least threshold words available read, data read packet without risk underflow. When master slave direction, high, slave enough space threshold words written.
Slave master
Note:
threshold implementation dependent, typically corresponds FIFO buffer almost full/empty levels.
Altera Corporation
Atlantic Interface Functional Specification
Table describes Atlantic interface data signals.
Table Data Signals (Part
Name Sink Direction
Input
Description
Start packet signal. used delineate packet boundaries bus. When high, start packet present aligned most significant byte. asserted first transfer every packet. packet signal. used delineate packet boundaries bus. When high, packet present bus. indicates number invalid bytes last word composed when asserted. asserted last transfer every packet. Error indicator signal. used indicate that current packet aborted should discarded. asserted time during current packet, when asserted only deasserted clock cycle after asserted. Conditions that cause limited header error correction (HEC) frame check (FCS) error, FIFO buffer overflow, parity error, abort sequence detection. Word empty bytes. indicates number invalid (empty) bytes data dat. should always zero, except during last transfer packet dat. When asserted, number invalid packet data bytes specified mty. definition compatible with signal POS-PHY level specifications. This table example mty[2:0]. values dependent field values. `000', bytes valid `001', dat[7:0] invalid `010', dat[15:0] invalid `011', dat[23:0] invalid `100', dat[31:0] invalid `101', dat[39:0] invalid `110', dat[47:0] invalid `111', dat[55:0] invalid 8-bit does have signal 16-bit requires mty[0] signal (m=1) 32-bit requires mty[1:0] signal(m=2) 64-bit requires mty[2:0] signal (m=3) requires mty[m-1:0] signal only non-zero when asserted.
Input
Input
mty[m-1:0] (m=0, mty) (m=1,2,3,.)
Input
adr[n:0] (n=0,1,2,3,.)
Input Input
Parity signal (optional). signal indicates parity calculated over bus. even parity supported. Address (optional). defined extension bus. carries associated address information each packet multi-port implementations. must valid same time remain constant throughout complete packet.
Altera Corporation
Atlantic Interface Functional Specification
Table Data Signals (Part
Name Sink Direction
Input
Description
dat[8 (m=0,1,2,3.)
Data bus. This carries packet octets that transferred across interface. data transmitted big-endian order dat. determines size, example: m=2, [31:0]; m=3, [63:0].
Note:
direction reversed source interfaces.
Timing
clock frequency application dependent.
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Copyright 2001 Altera Corporation. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
Altera Corporation

July 2001, ver. Functional Specification Flexible interface

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