File Number 3042.2 Radiation Hardened CMOS High Performance

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File Number 3042.2 Radiation Hardened CMOS High Performance

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HS-82C37ARH
File Number
3042.2
Radiation Hardened CMOS High Performance Programmable Controller
Intersil HS-82C37ARH enhanced, radiation hardened CMOS version industry standard 8237A Direct Memory Access (DMA) controller, fabricated using Intersil hardened field, self-aligned silicon gate CMOS process. HS-82C37ARH offers increased functionality, improved performance, dramatically reduced power consumption radiation environment. high speed, radiation hardness, industry standard configuration HS-82C37ARH make compatible with radiation hardened microprocessors such HS-80C85RH HS-80C86RH. HS-82C37ARH improve system performance allowing external devices transfer data directly from system memory. Memory-to-memory transfer capability also provided, along with memory block initialization feature. requests generated either hardware software, each channel independently programmable with variety features flexible operation. Static CMOS circuit design insures operating power allows gated clock operation even further reduction power. Multimode programmability allows user select from three basic types services, reconfiguration under program control possible even with clock controller stopped. Each channel full address word count range, programmed autoinitialize these registers following termination (end process). Intersil hardened field CMOS process results performance equal greater than existing radiation resistant products fraction power. Specifications Hard devices controlled Defense Supply Center Columbus (DSCC). numbers listed here must used when ordering. Detailed Electrical Specifications these devices contained 5962-95821. "hot-link" provided homepage downloading.
Features
Electrically Screened 5962-95821 Qualified MIL-PRF-38535 Requirements Radiation Performance Total Dose. krad(Si) (Max) Transient Upset .>108 rad(Si)/s Latch Free EPI-CMOS Power Consumption IDDSB. 50µA (Max) IDDOP 4.0mA/MHz (Max) Compatible with NMOS 8237A Intersil 82C37A High Speed Data Transfers 2.5MBPS With 5MHz Clock Four Independent Maskable Channels with Autoinitialization Capability Expandable Number Channels Memory-to-Memory Transfer Capability CMOS Compatible Hardened Field, Self-Aligned, Junction Isolated CMOS Process Single Supply Military Temperature Range -55oC 125oC
Ordering Information
ORDERING NUMBER 5962R9582101QQC 5962R9582101QXC 5962R9582101VQC 5962R9582101VXC INTERNAL MKT. NUMBER HS1-82C37ARH-8 HS9-82C37ARH-8 HS1-82C37ARH-Q HS9-82C37ARH-Q TEMP. RANGE (oC)
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil Design trademark Intersil Corporation. Copyright Intersil Corporation 2000
HS-82C37ARH Pinouts
LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T40 VIEW
MEMR MEMW READY HLDA ADSTB DACK0 DACK1 MEMR MEMW READY HLDA ADSTB RESET DACK2 DACK3 DREQ3 DREQ2 DREQ1 DREQ0 DACK0 DACK1
LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) INTERSIL OUTLINE K42.A VIEW
RESET DACK2 DACK3 DREQ3 DREQ2 DREQ1 DREQ0 (GND)
Functional Diagram
DECREMENTOR RESET READY CLOCK ADSTB MEMR MEMW WRITE BUFFER DREQ0DREQ3 HLDA DACK0DACK3 PRIORITY ENCODER ROTATING PRIORITY LOGIC COMMAND INTERNAL DATA BUFFER READ BUFFER D0-D1 TIMING CONTROL BASE ADDRESS (16) READ BUFFER BASE WORD COUNT (16) BASE ADDRESS (16) BASE WORD COUNT (16) TEMP WORD COUNT (16) 16-BIT 16-BIT OUTPUT BUFFER A4-A7 DECREMENTOR TEMP ADDRESS (16) BUFFER A0-A3
A8-A15
COMMAND CONTROL
DB0-DB7
MASK STATUS TEMPORARY
REQUEST
MODE
HS-82C37ARH Descriptions
SYMBOL NUMBER TYPE DESCRIPTION VDD: power supply pin. 0.1µF capacitor between pins recommended decoupling. Ground CLOCK INPUT: Clock Input used generate timing signals which control HS-82C37ARH operations. This input driven from 5MHz stopped either high state standby operation. CHIP SELECT: Chip Select active input used enable controller onto data communications. RESET: This active high input which clears Command, Status, Request Temporary Registers, First/Last Flip-Flop, Mode Register Counter. Mask Register ignore requests. Following Reset, controller idle cycle. READY: This signal sued extend memory read write pulses from HS-82C37ARH accommodate slow memories devices. Ready must make transitions during specified set-up hold times. Ready ignored Verify Transfer mode. HOLD ACKNOWLEDGE: active high Hold Acknowledge from indicates that relinquished control system busses. REQUEST: Request (DREQ) lines individual asynchronous channel request inputs used peripheral circuits obtain service. Fixed Priority, DREQ0 highest priority DREQ3 lowest priority. request generated activating DREQ line channel. DACK will acknowledge recognition DREQ signal. Polarity DREQ programmable. Reset initializes these lines active. DREQ will recognized while clock stopped. Unused DREQ inputs should pulled High (inactive) corresponding mask set. DATA BUS: Data lines bidirectional three-state signals connected system data bus. outputs enabled Program Condition during Read output contents register CPU. outputs disabled inputs read during Write cycle when programming HS-82C37ARH Control Registers. During cycles, most significant bits address output onto data strobed into external latch ADSTB. Memory-to-Memory operations, data from memory enters HS-82C37ARH data during read-from-memory transfer, then during write-to-memory transfer, data outputs write data into memory location. READ: Read bidirectional active three-state line. Idle cycle, input control signal used read internal registers. Active cycle, output control signal used HS-82C37ARH access data from peripheral during Write transfer. WRITE: Write bidirectional active three-state line. Idle cycle, input control signal used load information into HS-82C37ARH. Active cycle, output control signal used HS-82C37ARH load data peripheral during Read transfer. PROCESS: Process (EOP) active bidirectional signal. Information concerning completion services available bidirectional pin. HS-82C37ARH allows external signal terminate active service pulling low. pulse generated HS-82C37ARH when terminal count (TC) channel reached, except channel Memory-to-Memory mode. During Memory-to-Memory transfers, will output when channel occurs. driven open drain transistor on-chip, requires external pull-up resistor. When pulse occurs, whether internally externally generated, HS-82C37ARH will terminate service, Autoinitialize enabled, base registers will written current registers that channel. mask Status Register will currently active channel unless channel programmed Autoinitialize. that case, mask remains clear. Address: four least significant address lines bidirectional three-state signals. Idle cycle, they inputs used HS-80C86RH address internal registers loaded read. Active cycle, they outputs provide lower bits output address. Address: four most significant address lines three-state outputs provide bits address. These lines enabled only during Active cycle.
RESET
READY
HLDA DREQ0DREQ3
16-19
DB0-DB7
21-23 26-30
A0-A3
32-35
A4-A7
37-40
HS-82C37ARH Descriptions (Continued)
SYMBOL NUMBER TYPE DESCRIPTION Hold Request: Hold Request (HRQ) output used request control system bus. When DREQ occurs corresponding mask clear, software request made, HS-82C37ARH issues HRQ. HLDA signal then informs controller when access system busses permitted. stand-alone operation where HS-82C37ARH always controls busses, tied HLDA. This will result state before transfer. Acknowledge: acknowledge used notify individual peripherals when been granted cycle. sense these lines programmable. Reset initializes them active low. Address Enable: Address Enable enables 8-bit latch containing upper address bits onto system address bus. also used disable other system drivers during transfers. active HIGH. Address Strobe: This active high signal used control latching upper address byte. will drive directly strobe input external transparent octal latches, such 82C82. During block operations, ADSTB will only issued when upper address byte must updated, thus speeding operation through elimination states. (See Note Memory Read: Memory Read signal active three-state output used access data from selected memory location during Read Memory-to-Memory transfer. Memory Write: Memory Write active three-state output used write data selected memory location during Write Memory-to-Memory transfer. connect. open should tested continuity.
DACK0DACK3
14,15,
ADSTB
MEMR MEMW
Test Circuit
Testing Input, Output Waveforms
-1.5V INPUT -0.4V 1.5V OUTPUT
OUTPUT FROM DEVICE UNDER TEST
TEST POINT OUTPUT 2.0V 0.8V 0.45V 0.45
Includes Stray Capacitance
TEST CONDITION DEFINITION TABLE PINS Output Except 1.7V 1.6k 100pF 50pF
HS-82C37ARH Waveforms
TIWHAX TIWLIWH TAVIWL A0-A3 INPUT VALID TIWHDX TDVIWH DB0-DB7 INPUT VALID TIWHAX
FIGURE SLAVE MODE TIMING NOTE: Host system must allow least TCLCL recovery time between successive write accesses.
A0-A3 TAVIRL
ADDRESS MUST VALID TIRHAX TIRLIRH
TIRLDV DB0-DB7 TIRHDZ
DATA VALID
FIGURE SLAVE MODE READ NOTE: Host system must allow least TCLCL recovery time between successive write accesses.
TCHRH
TCHRWL READ TCHRWL TCHRWL
TCHWH
WRITE
EXTENDED WRITE
TCLRYX TRYVCL
TCLRYX TRYVCL
READY
FIGURE READY
READ refers both MEMR outputs. WRITE refers both MEMW outputs.
HS-82C37ARH Waveforms
TDQVCL DREQ TCHRQV TRAVCH HLDA TCLAEH TCLSH TSHSL ADSTB TDVSL TCHDV DB0-DB7 TCHAV A0-A7 A8-A15 TCHAV TCHDZ ADDRESS VALID TCLDAV DACK TCHRWV READ TCHWH TCHRWL WRITE TWLWH1 (FOR EXTENDED WRITE) TEPLEPH TCHIPL TCHRWL TCHIPH TCHWH TWLWH2 TCHRWL TCHRH TWHAX ADDRESS VALID TRHAX TCHRWL TCHRH TWHRH TRLRH1 TCHRWZ TRHAZ TCHAZ TWHAZ TSLDZ TCLDAV TEPLCL TCLSL TCHAEL TDQVCL TCLCL TCLCH TCHRQV TCHCL
(Continued)
FIGURE TRANSFER
READ refers both MEMR outputs. WRITE refers both MEMW outputs.
HS-82C37ARH Waveforms
TCLSH TCLSL ADSTB TSLDZ TCHAV ADDRESS VALID TCHDZ TCHDV TCHRH TMRHDX MEMR TDVMRH TCHWH TCHRVW TCHRWL TCHRWL TCHDV TCHAV TSLDZ
(Continued)
TCLSH
TCLSL
TCHAZ
ADDRESS VALID
TCHRWL
TDVMWH TMWHDZ
TCHRWZ EXTENDED WRITE TCHIPL TCHIPH
TEPLCL TEPLEPH
FIGURE MEMORY-TO-MEMORY TRANSFER
TPHRSL TRSHRSL
RESET TRSLIRWL
FIGURE RESET
HS-82C37ARH Waveforms
(Continued)
TCHAV
TCHAV
VALID TCHRH TCHRWL TRLRH2 TCHRWL
VALID
TCHRH
READ
TCHWH TCHWH
WRITE TCLRYX TRYVCL TCLRYX TRYVCL
READY
FIGURE COMPRESSED TRANSFER
READ refers both MEMR outputs. WRITE refers both MEMW outputs.
HS-82C37ARH Burn-In Circuits
HS-82C37ARH LEAD SBDIP
LOAD LOAD LOAD LOAD LOAD LOAD LOAD LOAD LOAD
HS-82C37ARH LEAD SBDIP
LOAD LOAD LOAD LOAD
STATIC CONFIGURATION NOTES: +6.0V Part Static Sensitive 125oC MinimumVoltage Must Ramped Resistors: ±10% (Pins 11-13, 2.7k (Pins 21-23, 28-32, 34-39)
LOAD
2.7k
2.7k
START-UP TIMING NOTES: duty cycle square wave pulse burst. 1.0kHz 100kHzF0 left High after pulse burst cycles Pulse Burst 1.0s Single pulse with width equal cycles left after pulse burst pulse occurs after start ends before Input levels: 0.9VDD VDD, -0.3V 0.7V NOTES:
DYNAMIC CONFIGURATION 6.5V (Burn-In) 6.0V (Life Test) 125oC Minimum Part Static Sensitive, Voltage Must Ramped Resistors: ±10% (Pins 11-13, 2.7k ±10% (Pins 22-24, 28-32, 34-37, LOADS)
HS-82C37ARH Burn-In Circuits
(Continued) HS-82C37ARH LEAD CERAMIC FLATPACK
LOAD LOAD OPEN LOAD LOAD LOAD LOAD LOAD OPEN OPEN LOAD LOAD LOAD LOAD LOAD LOAD
HS-82C37ARH LEAD CERAMIC FLATPACK
STATIC CONFIGURATION
2.7k
NOTES: +6.0V ±5%Part Static Sensitive 125oC MinimumVoltage Must Ramped Resistors: ±10% (Pins 11-13, 16-19) 2.7k (Pins 21-23, 26-30, 32-36)
LOAD 2.7k
START-UP TIMING NOTES: duty cycle square wave pulse burst. 1.0kHz 100kHzF0 left High after pulse burst cycles Pulse Burst 1.0s Single pulse with width equal cycles left after pulse burst pulse occurs after start ends before Input levels: 0.9VDD VDD, -0.3V 0.7V NOTES:
DYNAMIC CONFIGURATION 6.5V (Burn-In) 6.0V (Life Test) 125oC Minimum Part Static Sensitive, Voltage Must Ramped Resistors: ±10% (Pins 11-13, 16-19) 2.7k ±10% (Pins 21-23, 26-30, 32-36, LOADS)
HS-82C37ARH Irradiation Circuit
LOAD LOAD LOAD LOAD LOAD TOGGLE CLOCK RESET TOGGLE LOAD LOAD LOAD LOAD LOAD LOAD LOAD LOAD LOAD LOAD LOAD LOAD 2.7k LOAD 5.5V 2.7k LOAD LOAD 2.7k LOAD LOAD LOAD
NOTES: Pins with Load: 37-40 Pins with Load2: 21-30 Pins Brought Out: (Clock), (Reset) 5.5V ±0.5V
Functional Description
HS-82C37ARH Direct Memory Access Controller designed improve data transfer rate systems which must transfer data from device memory, move block memory device. will also perform memory-to-memory block moves, fill block memory with data from single location. Operating modes provided handle single byte transfers well discontinuous data streams, which allows HS-82C37ARH control data movement with software transparency. controller state-driven address control signal generator, which permits data transferred directly from device memory vice versa without ever being stored temporary register. This greatly increase data transfer rate sequential operations, compared with processor moves repeated string instructions. Memory-to-Memory operations require temporary internal storage data byte between generation source destination addresses, Memory-to-Memory transfers take place less than half rate operations, still much faster than with central processor techniques. maximum data transfer rate obtainable with HS-82C37ARH approximately Mbytes/second, operation using compressed timing option 5MHz clock. block diagram HS-82C37ARH shown page Timing Control Block, Priority Block, internal registers main components. Figure lists name size internal registers. Timing Control Block derives internal timing from CLOCK input, generates external control signals. Priority Encoder Block resolves priority contention between channels requesting service simultaneously.
HS-82C37ARH
NAME Base Address Registers Base Word Count Registers Current Address Registers Current Word Count Registers Temporary Address Register Temporary Word Count Register Status Register Command Register Temporary Register Mode Registers Mask Registers Request Register SIZE bits bits bits bits bits bits bits bits bits bits bits bits NUMBER
controller operates major cycles, Active Idle. After being programmed, controller normally Idle until request occurs unmasked channel, software request given. HS-82C37ARH will then request control system busses enter Active cycle. Active cycle composed several internal states, depending what options have been selected what type operation been requested. HS-82C37ARH assume seven separate states, each composed full clock period. State (SI) Idle state. entered when HS-82C37ARH valid requests pending, transfer sequence, when Reset Master Clear occurred. While controller inactive Program Condition (being programmed processor.) State (S0) first state service. HS-82C37ARH requested hold processor returned acknowledge. HS-82C37ARH still programmed until received HLDA from CPU. acknowledge from will signal that transfers begin. working states service. more time needed complete transfer than available with normal timing, wait states (SW) inserted between Ready line HS-82C37ARH. Note that data transferred directly from device memory vice versa) with MEMW MEMR IOW) being active same time. data read into driven HS-82C37ARH I/O-to-memory memory-to-I/O transfers. Memory-to-Memory transfers require read-from write-to-memory complete each transfer. states, which resemble normal working states, two-digit numbers identification. Eight states required single transfer. first four states (S11, S12, S13, S14) used read-from-memory half last four states (S21, S22, S23, S24) write-to-memory half transfer.
FIGURE HS-82C37ARH INTERNAL REGISTERS
Operation
system, HS-82C37ARH address control outputs data pins basically connected parallel with system busses. external latch required upper address byte. While inactive, controller's outputs high impedance state. When activated request control relinquished host, HS-82C37ARH drives busses generates control signals perform data transfer. operation performed activating four request inputs previously been programmed into controller Command, Mode, Address, Word Count Registers. example, block data transferred from device, starting address data loaded into HS-82C37ARH Current Base Address Registers particular channel, length block loaded into that channel's Word Count Register. corresponding Mode Register programmed Memory-to-I/O operation (read transfer), various options selected Command Register other Mode Register bits. channel's mask cleared enable recognition request (DREQ). DREQ either hardware signal software command. Once initiated, block transfer will proceed controller outputs data address, simultaneous MEMR pulses, selects device acknowledge (DACK) outputs. data byte flows directly from device. After each byte transferred, address automatically incremented decremented) word count decremented. operation then repeated next byte. controller stops transferring data when Word Count Register underflows, external applied. further understand HS-82C37ARH operation, states generated each clock cycle must considered.
Idle Cycle
When channel requesting service, HS-82C37ARH will enter Idle cycle perform "SI" states. this cycle, HS-82C37ARH will sample DREQ lines falling edge every clock cycle determine channel requesting service. Note that standby operation where clock been stopped, requests will ignored. device will respond (chip select), case attempt microprocessor write read internal registers HS-82C37ARH. When HLDA low, HS-82C37ARH enters Program Condition. establish, change inspect internal definition part reading from writing internal registers.
HS-82C37ARH
HS-82C37ARH programmed with clock stopped, provided that HLDA least rising clock edge occurred after HLDA driven low, controller state. Address lines A0-A3 inputs device select which registers will read written. lines used select time read write operations. number size internal registers, internal flip-flop used generate additional address. used determine upper lower byte 16-bit Address Word Count Registers. flip-flop reset Master Clear Reset. Separate software commands also reset this flip-flop. Special software commands executed HS-82C37ARH Program Condition. These commands decoded sets addresses with IOR, IOW. commands make data bus. Instructions include Clear First/Last Flip-Flop, Master Clear, Clear Mode Register Counter, Clear Mask Register. Demand Transfer Mode Demand Transfer Mode device continues making transfers until external encountered, until DREQ goes inactive. Thus, transfers continue until device exhaust edits data capacity. After device chance catch service reestablished means DREQ. During time between services when micro-processor allowed operate, intermediate values address word count stored HS-82C37ARH Current Address Current Word Count Registers. Higher priority channels intervene demand process, once DREQ gone inactive. Only cause Autoinitialization service. generated either external signal. Cascade Mode This mode used cascade more than HS-82C37ARH simple system expansion. HLDA signals from additional HS-82C37ARH connected DREQ DACK signals respectively channel initial HS-82C37ARH. This allows requests additional device propagate through priority network circuitry preceding device. priority chain preserved device must wait turn acknowledge requests. Since cascade channel initial HS-82C37ARH used only prioritizing additional device, does output address control signals that there conflict with cascaded device. HS-82C37ARH will respond DREQ generate DACK other outputs except will disabled. external will ignored initial device, will have usual effect added device. Figure shows additional devices cascaded with initial device using previous channels. This forms two-level system. More HS-82C37ARHs could added second level using remaining channels first level. Additional devices also added cascading into channels second level devices, forming third level.
Active Cycle
When HS-82C37ARH Idle cycle, software request unmasked channel requests service, device will output microprocessor enter Active cycle. this cycle that service will take place, four modes: Single Transfer Mode Single Transfer mode, device programmed make transfer only. word count will decremented address decremented incremented following each transfer. When word count "rolls over" from zero FFFFH, terminal count (TC) Status Register set, pulse generated, channel will Autoinitialize this option been selected. programmed Autoinitialize, mask will set, along with pulse. DREQ must held active until DACK becomes active. DREQ held active throughout single transfer (there-by triggering second transfer), will still inactive release system. Then will again active and, upon receipt HLDA, another single transfer will performed, unless higher priority channel takes over. HS-80C85RH HS-80C86RH systems, this will ensure full machine cycle execution between transfers. Details timing between HS-82C37ARH other control protocols will depend upon characteristics microprocessor involved. Block Transfer Mode Block Transfer Mode, device activated DREQ software request continues making transfers during service until caused word count going FFFFH, external Process (EOP) encountered. DREQ need only beheld active until DACK becomes active. Again, Autoinitialization will occur service channel been programmed that option.
HS-82C37ARH
LEVEL
HS-80C86RH MICROPROCESSOR
HS-82C37ARH LEVEL HLDA DREQ DACK HLDA
Memory-to-Memory perform block moves data from memory address space another with minimum program effort time, HS-82C37ARH includes Memory-to-Memory transfer feature. Programming Command Register selects channels operate Memory-to-Memory transfer channels. transfer initiated setting software hardware DREQ channel HS-82C37ARH requests service normal manner. After HLDA true, device, using four-state transfers Block Transfer Mode, reads data from memory. channel Current Address Register source address used decremented incremented normal manner. data byte read from memory stored HS-82C37ARH internal Temporary Register. Another four-state transfer moves data memory using address channel Current Address Register incrementing decrementing normal manner. channel Current Word Count Register decremented. When word count channel goes FFFFH, generated causing output terminating service. Channel word count decrementing FFFFH will channel Status Register generate this mode. will cause Autoinitialization channel that option been selected. full Autoinitialization Memory-to-Memory operation desired, channel channel word counts must equal before transfer begins. Otherwise, channel underflows before channel will Autoinitialize data source address back beginning block. channel word count underflows before channel Memory-to-Memory service will terminate, channel will Autoinitialize channel will not. Memory-to-Memory Mode, Channel programmed retain same address transfers. This allows single byte written block memory. This channel address hold feature selected Command Register. HS-82C37ARH will respond external signals during Memory-to-Memory transfers, will only relinquish system busses after transfer complete (i.e., after state). Data comparators block search schemes this input terminate service when match found. timing Memory-to-Memory transfers found Figure Memory-to-Memory operations detected active with DACK outputs. Priority HS-82C37ARH types priority encoding available software selectable options. first Fixed Priority which fixes channels priority order based upon descending value their numbers. channel with lowest priority followed highest priority channel, After recognition channel service, other channels prevented from interfering with service until completed.
HS-82C37ARH
DREQ DACK INITIAL DEVICE
HLDA HS-82C37ARH
ADDITIONAL DEVICES
FIGURE CASCADED HS-82C37ARHs
When programming cascaded controllers, start with first level (closest microprocessor). After RESET, DACK outputs programmed active held high state. they used drive HLDA directly, second level device(s) cannot programmed until DACK polarity selected active high initial device. Also, initial device's mask bits function normally cascaded channels, they used inhibit second-level services.
Transfer Types
Each three active transfer modes perform three different types transfers. These Read, Write Verify. Write transfers move data from device memory activating MEMW IOR. Read transfers move data from memory device activating MEMR IOW. Verify transfers pseudo-transfers. HS-82C37ARH operates Read Write transfers generating addresses responding EOP, etc., however memory control lines remain inactive. Verify mode permitted Memory-to-Memory operation. Ready ignored during Verify transfers. Autoinitialize programming Mode Register, channel Autoinitialize channel. During Autoinitialization, original values Current Address Current Word Count Registers automatically restored from Base Address Base Word Count Registers that channel following EOP. base registers loaded simultaneously with current registers microprocessor remain unchanged throughout service. mask when channel Autoinitialize. Following Autoinitialization, channel ready perform another service, without intervention, soon valid DREQ detected, software request made.
HS-82C37ARH
second scheme Rotating Priority. last channel service becomes lowest priority channel with others rotating accordingly. next lower channel from channel serviced highest priority following request: Priority rotates every time control system busses returned processor. change when carry borrow from takes place normal sequence addresses. save time speed transfers, HS-82C37ARH executes states only when updating A8-A15 latch necessary. This means long services, states Address Strobes occur only once every transfers, savings clock cycles each transfers.
Rotating Priority
SERVICE HIGHEST LOWEST SERVICE SERVICE SERVICE REQUEST SERVICE SERVICE
Programming
HS-82C37ARH will accept programming from host processor anytime that HLDA inactive, least rising clock edge occurred after HLDA went low. responsibility host assure that programming HLDA mutually exclusive. Note that problem occur request occurs unmasked channel while HS-82C37ARH being programmed. instance, starting reprogram byte Address Register channel when channel receives request. HS-82C37ARH enabled (bit command register channel unmasked, service will occur after only byte Address Register been reprogrammed. This condition avoided disabling controller (setting Command Register) masking channel before programming registers. Once programming complete, controller enabled/unmasked. After power-up suggested that internal locations loaded with some known value, even some channels unused. This will debugging.
With Rotating Priority single chip system, device requesting service guaranteed recognized after more than three higher priority services have occurred. This prevents channel from monopolizing system. Regardless which priority scheme chosen, priority evaluated every time HLDA returned HS-82C37ARH. Compressed Timing order achieve even greater throughput where system characteristics permit, HS-82C37ARH compress transfer time clock cycles. From Figure seen that state used extend access time read pulse. removing state read pulse width made equal write pulse width transfer consists only state change address state perform read/write. states will still occur when A8-A15 need updating (see Address Generation). Timing compressed transfers found Figure will output compressed timing selected. Compressed Timing allowed Memory-to-Memory transfers. Address Generation order reduce count, HS-82C37ARH multiplexes eight higher order address bits data lines. State used output higher order address bits external latch from which they placed address bus. falling edge Address Strobe (ADSTB) used load these bits from data lines latch. Address Enable (AEN) used enable bits onto address through three-state enable. lower order address bits output HS-82C37ARH directly. Lines A0-A7 should connected address bus. Figure shows time relationships between CLK, AEN, ADSTB, DB0-DB7 A0-A7. During Block Demand Transfer Mode service, which include multiple transfers, addresses generated will sequential. many transfers data held external address latch will remain same. This data need only
Register Description
Current Address Register Each channel 16-bit Current Address Register. This register holds value address used during transfers. address automatically incremented decremented after each transfer values address stored Current Address Register during transfer. This register written read microprocessor successive 8-bit bytes. also reinitialized Autoinitialize back original value. Autoinitialize takes place only after EOP. Memory-to-Memory Mode, channel Current Address Register prevented from incrementing decrementing setting address hold Command Register. Current Word Register Each channel 16-Bit Current Word Count Register. This register determines number transfers performed. actual number transfers will more than number programmed Current Word Count Register (i.e., programming count will result transfers). word count decremented after each transfer. When value register goes from zero FFFFH, will generated. This register loaded read successive 8-bit bytes
HS-82C37ARH
microprocessor Program Condition. Following service also reinitialized Autoinitialization back original value. Autoinitialization occur only when occurs. Autoinitialized, this register will have count FFFFH after Base Address Base Word Count Registers Each channel pair Base Address Base Word Count Registers. These 16-bit registers store original value their associated current registers. During Autoinitialization, these values used restore current registers their original values. base registers written simultaneously with their corresponding current register 8-bit bytes Program Condition microprocessor. These registers cannot read microprocessor. Mask Register Each channel associated with mask which disable incoming DREQ. Each mask when associated channel produces channel programmed Autoinitialize. Each 4-bit Mask Register also cleared separately simultaneously under soft-ware control. entire register also Reset Master Clear. This disables hardware requests until clear Mask Register instruction allows them occur. instruction separately clear mask bits similar form that used with Request Register. Refer following table Figure details. When reading Mask Register, bits will always read logical ones, bits will display mask bits channel 0-3, respectively. bits Mask Register cleared simultaneously using Clear Mask Register command (see software commands section). Mask Register
NUMBER SELECT CHANNEL MASK SELECT CHANNEL MASK SELECT CHANNEL MASK SELECT CHANNEL MASK CLEAR MASK MASK
Mode Register Each channel 6-bit Mode Register associated with When register being written microprocessor Program Condition, bits determine which channel Mode Register written. When processor reads Mode Register, bits will both ones. adjacent table Figure Mode Register functions addresses. Mode Register
NUMBER
CHANNEL SELECT CHANNEL SELECTT CHANNEL SELECT CHANNEL SELECT READBACK VERIFY TRANSFER WRITE TRANSFER READ TRANSFER ILLEGAL BITS AUTOINITIALIZATION DISABLE AUTOINITIALIZATION ENABLE ADDRESS INCREMENT SELECT ADDRESS DECREMENT SELECT DEMAND MODE SELECT SINGLE MODE SELECT BLOCK MODE SELECT CASCADE MODE SELECT
DON'T CARE
Request Register HS-82C37ARH respond requests service which initiated software well DREQ. Each channel request associated with 4-bit Request Register. These non-maskable subject prioritization Priority Encoder network. Each register reset separately under software control. entire register cleared Reset. reset bit, software loads proper form data word. Figure register address coding, following table Request Register format. software request operation made Block Single Modes. Memory-to-Memory transfers, software request channel should set. When reading Request Register, bits will always read ones, bits will display request bits channels respectively. Request Register
NUMBER SELECT CHANNEL SELECT CHANNEL SELECT CHANNEL SELECT CHANNEL RESET REQUEST REQUEST
four bits Mask Register also written with single command.
NUMBER CLEAR CHANNEL MASK CHANNEL MASK CLEAR CHANNEL MASK CHANNEL MASK CLEAR CHANNEL MASK CHANNEL MASK CLEAR CHANNEL MASK CHANNEL MASK
DON'T CARE, WRITE ONES, READ
DON'T CARE, WRITE BITS ONES, READ
Command Register This 8-bit register controls operation HS-82C37ARH. programmed microprocessor cleared Reset Master Clear
HS-82C37ARH
instruction. adjacent table lists function command bits. Figure Read Write addresses. Command Register
NUMBER MEM-TO-MEM DISABLE MEM-TO-MEM ENABLE ADDR. HOLD DISABLE ADDR. HOLD ENABLE CONTROLLER ENABLE CONTROLLER DISABLE NORMAL TIMING COMPRESSED TIMING FIXED PRIORITY ROTATING PRIORITY LATE WRITE SELECTION EXTENDED WRITE SEL. DREQ SENSE ACTIVE HIGH DREQ SENSE ACTIVE DACK SENSE ACTIVE DACK SENSE ACTIVE HIGH
These bits cleared upon Reset, Master Clear, each Status Read. Bits whenever their corresponding channel requesting service, regardless mask state. mask bits set, software poll Status Register determine which channels have DREQs, selectively clear mask bit, thus allowing user defined service priority. Status bits updated while clock high, latched falling edge. Status Bits cleared upon Reset Master Clear. Status Register
NUMBER CHANNEL REACHED CHANNEL REACHED CHANNEL REACHED CHANNEL REACHED CHANNEL REQUEST CHANNEL REQUEST CHANNEL REQUEST CHANNEL REQUEST
Status Register Status Register contains information about present status HS-82C37ARH read microprocessor. This information includes which channels have reached terminal count which channels have pending requests. Bits every time reached that channel external applied.
Temporary Register Temporary Register used hold data during Memory-to-Memory transfers. Following completion transfer, last word moved read microprocessor accessing this register. Temporary Register always contains last byte transferred previous Memory-to-Memory operation, unless cleared Reset Master Clear.
OPERATION Read Status Register Write Command Register Read Request Register Write Request Register Read Command Register Write Single Mask Read Mode Register Write Mode Register Byte Pointer Clear Byte Pointer Read Temporary Register Master Clear Clear Mode Reg. Counter Clear Mask Register Read Mask Bits Write Mask Bits
FIGURE SOFTWARE COMMAND CODES REGISTER CODES
HS-82C37ARH Software Commands
There special software commands which executed reading writing HS-82C37ARH. These commands depend specific data pattern data bus, activated operation itself. read type commands, data value guaranteed. These commands are: Clear First/Last Flip-Flop: This command executed prior writing reading address word count information HS-82C37ARH. This initializes flip-flop known state that subsequent accesses register contents microprocessor will address upper lower bytes correct sequence. First/Last Flip-Flop: This command will flip-flop select high byte first read write operations Address Word Count registers. Master Clear: This software instruction same effect hardware Reset. Command, Status, Request, Temporary Registers, Internal First/Last Flip-Flop Mode Register Counter cleared Mask Register set. HS-82C37ARH will enter Idle cycle. Clear Mask Register: This command clears mask bits four channels, enabling them accept requests. Clear Mode Register Counter: Since only address location available reading Mode Registers, internal two-bit counter been included select Mode Registers during read operations. read Mode Registers, first execute Clear Mode Register Counter command, then consecutive reads until desired channel read. Read order channel first, channel last. lower bits Mode Registers will read ones.
External Operation
bidirectional, open drain which driven external signals terminate operation. Because open drain external pull-up resistor required. value external pull-up resistor used should guarantee rise time less than 125ns. important note that HS-82C37ARH will accept external signals when (Idle)state. controller must active latch EOP. Once latched, will acted upon during next state, unless HS82C37ARH enters Idle state first. latter case latched cleared. External pulses occurring between active transfers demand mode will recognized, since HS-82C37ARH state.
HS-82C37ARH
SIGNALS CHANNEL REGISTER Base Current Address Current Address Base Current Word Count Current Word Count Base Current Address Current Address Base Current Word Count Current Word Count Base Current Address Current Address Base Current Word Count Current Word Count Base Current Address Current Address Base Current Word Count Current Word Count OPERATION Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read INTERNAL FLIP-FLOP DATA DB0-DB7 A0-A7 A8-A15 A0-A7 A8-A15 W0-W7 W8-W15 W0-W7 W8-W15 A0-A7 A8-A15 A0-A7 A8-A15 W0-W7 W8-W15 W0-W7 W8-W15 A0-A7 A8-A15 A0-A7 A8-A15 W0-W7 W8-W15 W0-W7 W8-W15 A0-A7 A8-A15 A0-A7 A8-A15 W0-W7 W8-W15 W0-W7 W8-W15
FIGURE WORD COUNT ADDRESS REGISTER COMMAND CODES
Application Information
Figure shows application system utilizing HS-82C37ARH controller HS-80C86RH Microprocessor. this application, HS-82C37ARH controller used improve system performance allowing device transfer data directly from system memory.
inverter used generate signal using output HS-82C37ARH. Hold Acknowledge (HLDA) Address Enable (AEN) "ORed" together used deactivate microprocessors 82C82 transceiver insure that controller does have contention with microprocessor.
Operation
request (DREQ) generated device. After receiving request, controller will issue Hold Request (HRQ) processor. system busses released controller until Hold Acknowledge (HLDA) signal returned controller from HS-80C86RH processor. After Hold Acknowledge been received, addresses control signals generated controller accomplish transfers. Data transferred directly from device memory vice versa) with MEMW MEMR IOW) being active. Note that data read into driven controller I/O-to-Memory Memory-to-I/O data transfers.
Components
system clock generated HS-82C85RH clock controllers generator inverted meet clock high times required HS-82C37ARH controller. four gates used support HS-80C86RH Microprocessor minimum mode producing control signals used processor access memory I/O. decoder used generate chip select controller memory. HS-82C37ARH multiplexes most significant bits address data outputs (DB0 82C82 octal latch used demultiplex address. three-state
HS-82C37ARH
MEMCS HLDA DECODER HS-82C37ARH HS-82C85RH HLDA ADSTB HLDA AD15 M/10 MN/MX 82C82 DATA 82C82 A0-7 DB0-7 MEMR MEMW DREQ0 DACK0
ADDRESS
HS-80C86RH MEMR MEMW MEMCS MEMR MEMW MEMORY DATA ADDRESS DEVICE DREQ
FIGURE APPLICATION SYSTEM
HS-82C37ARH Characteristics
DIMENSIONS: 215mils 232mils 19mils ±1mil INTERFACE MATERIALS: Glassivation: Thickness: Metallization: Type: Al/Si Thickness: ADDITIONAL INFORMATION: Worst Case Current Density: A/cm2
Metallization Mask Layout
HS-82C37ARH
READY MEMW MEMR (36)
(40)
(39)
(38)
(37)
HLDA (34) ADSTB
(35)
(33)
(32)
(10)
(31)
(11)
(30)
(29) (12) (28) RESET (13) DACK2 (14) (27)
(26)
DACK3 (15)
(21)
(22)
(23)
DACK1 (24)
DREQ3 (16)
DREQ2 (17)
DREQ1 (18)
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DREQ0 (19)
DACK0 (25)
(20)

File Number 3042.2 Radiation Hardened CMOS High Performance

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