Configuring PLDs with Flash Memory Altera® introduces higher-dens

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Configuring PLDs with Flash Memory Altera® introduces higher-dens

Datasheet Thumbnail

Top Searches for this datasheet

Configuring PLDs with Flash Memory
Altera® introduces higher-density programmable logic devices (PLDs) market, size configuration streams also increases. using standard flash memory device, these high-density devices configured. MAX® 3000 device used stream data from flash memory into large PLD. This configuration technique allows faster configuration times. Since fixed-frequency oscillator available clock system) used generate clock configuration, clock frequency high (the maximum APEX20KE device). Flash memory type nonvolatile memory that used data storage device. Flash memory erased reprogrammed units memory called blocks. This white paper describes configure with flash memory. using 3000 device configure higher density PLDs, flash memory store configuration data 3000 device serialize transmit data PLD. This configuration technique used with APEX, ACEXTM, FLEX® devices.
Configuring PLDs
Figure shows device that uses EPM3128A device flash memory configure PLDs. Figure Device Configuration Using Flash Memory EPM3128A Device
Oscillator EPM3128A Device
APEX, ACEX, FLEX
MSEL0 nSTATUS INIT_DONE CONF_DONE DCLK DATA0 nCONFIG nCEO MSEL1
Flash Memory
DATA[] ADDR[] RESTART nSTATUS ADDR[] RESTART INIT_DONE CONF_DONE DCLK DATA0 nCONFIG
APEX, ACEX, FLEX
MSEL0 nSTATUS INIT_DONE CONF_DONE DCLK DATA0 nCONFIG nCEO MSEL1
Notes: FLEX 6000 devices have single MSEL pin, which tied ground. Additionally, DATA0 renamed DATA. nCEO left unconnected last device chain. Pull-up resistors except APEX 20KE devices. APEX 20KE devices, pull resistors nSTATUS, CONF_DONE, INIT_DONE pins open-drain APEX, ACEX, FLEX devices. corresponding pins EPM3128A should also open_drain.
M-WP-M3KPLD-01
October 2000, ver.
Altera Corporation
Configuring PLDs with FLASH Memory
VHDL design file called MAXconfig, shown "Configuration Design File" section, allows EPM3128A device control configuration process. MAXconfig design configures using configuration data stored attached flash memory. MAXconfig design contains sequencer address generator, which drives correct data PLD's programming pins. MAXconfig design file available Altera site When MAXconfig design reset, MAXconfig design reads data from flash memory, byte time. MAXconfig design then serializes sends data APEX, ACEX, FLEX device. serialized data sent using passive serial interface pins such DCLK, DATA, nSTATUS, INIT_DONE, nCONFIG. Since passive serial mode used, flash pins directly connected APEX, ACEX, FLEX device. Flash memory programmed prior being onto board with standard programming equipment programmed in-system processor test equipment. Since different flash memories have different algorithms, consult flash memory data sheet programming information. Figure shows configuration timing waveform EPM3128A device downloading data APEX, ACEX, FLEX device. Figure Configuration Timing Waveform
nSTATUS nCONFIG DCLK DATA0 D[7.0] ADDR[15.0] CONF_DONE RESTART INIT_DONE DATA
Configuration Design File
This section shows MAXconfig design file that controls configuration process APEX, ACEX, FLEX devices:
library ieee; ieee.std_logic_1164.all; ieee.std_logic_unsigned.all; entity MAXconfig port clock init_done nStatus restart Conf_Done Data0 Dclk nConfig
std_logic; std_logic; std_logic; std_logic_vector(7 downto std_logic; std_logic; std_logic; std_logic; std_logic;
buffer
Altera Corporation
Configuring PLDs with Flash Memory
increase size memory, change size std_logic_vector ADDR output -std_logic_vector signal inc: ADDR std_logic_vector(15 downto std_logic); polarity signal determined type Flash device end; architecture MAXconfig -The following encoding done such that represents nConfig signal: constant constant constant constant constant constant start wait_nCfg_8us status wait_40us config init :std_logic_vector(2 :std_logic_vector(2 :std_logic_vector(2 :std_logic_vector(2 :std_logic_vector(2 :std_logic_vector(2 downto downto downto downto downto downto "000"; "100"; "001"; "101"; "011"; "111";
signal :std_logic_vector(2 downto signal count :std_logic_vector(2 downto signal data0_int, dclk_int :std_logic; signal :std_logic_vector(15 downto signal :std_logic_vector(2 downto signal waitd :std_logic_vector(11 downto -The width signal `waitd' determined frequency. (APEX 20KE devices), -`waitd' bits. (FLEX 10KE ACEX devices) `waitd' bits. calculate -the width `waitd' signal fordifferent frequencies, calculate following: -(multiply tcf2ck clock frequency)+ -Then convert this value binary obtain width. -For example, (FLEX 10KE ACEX devices), converting 1360 ((40us 33MHz)+40=1360) binary code, `waitd' 11-bit signal. signal `waitd' will -signal waitd :std_logic_vector(10 downto begin -The following process used divide CLOCK: PROCESS (clock,restart) begin restart then (others '0'); else (clock'EVENT clock '1') THEN PROCESS; PROCESS (clock,restart) begin restart then pp<=start; count (others '0'); (others '0'); waitd (others '0'); else clock'event clock='1' then -The following test used divide CLOCK. value compared must such that -condition true maximum rate (tclk 17.5 min) APEX 20KE devices -and maximum rate (tclk=30ns min) FLEX 10KE ACEX devices. (div then case when start count (others '0'); (others '0'); waitd (others '0');
Altera Corporation
Configuring PLDs with FLASH Memory
wait_nCfg_8us; -This state used order verify tcfg timing (nCONFIG pulse width). -Tcfg min= clock cycle clock (APEX 20KE devices). different -clocks, multiply clock frequency. example, 33MHz (FLEX 10KE ACEX devices) this -value 8*33=264. This clock CLOCK divided divider -div-. when wait_nCfg_8us count (others '0'); (others '0'); waitd waitd waitd then -For FLEX 10KE ACEX devices this line waitd then status; -This state used have nCONFIG high. when status count (others '0'); (others '0'); waitd (others '0'); wait_40us; -This state used generate tcf2ck timing (nCONFIG high first rising edge DCLK). -Tcf2ck 40µs 2280 clock cycles 57MHz (APEX 20KE) clock. This clock CLOCK -divide divider -div-Tcf2ck 40µs 1320 clock cycles 33MHz (FLEX 10KE/ACEX) clock. This clock CLOCK -divided divider -div-) -For other clock frequency, multiply tcf2ck clock frequency. when wait_40us count (others '0'); (others '0'); waitd waitd waitd 2280 then -For (FLEX 10KE ACEX devices), this line waitd 1320 then config; -This state used increment memory address. same state when -the Conf_Done high clock cycles added order have initialization completed. when config count count Conf_Done='1' then waitd waitd count=7 then waitd 2320 then -Modification: clock cycles. APEX 20KE devices, 2280+40=2320 -For FLEX 10KE ACEX devices, 1320+40=1360. This line becomes: waitd= 1360 then pp<= init; when init count (others '0'); (others '0'); waitd (others '0'); nStatus then start; else init; when others start;
Altera Corporation
Configuring PLDs with FLASH Memory
case; else inc; count count; PROCESS; dclk_int div(2) when pp=config else '0'; -The following process used serialize data byte PROCESS (count,D,pp) begin pp=config then case count when "000" data0_int D(0); when "001" data0_int D(1); when "010" data0_int D(2); when "011" data0_int D(3); when "100" data0_int D(4); when "101" data0_int D(5); when "110" data0_int D(6); when "111" data0_int D(7); when others null; case; else data0_int '0'; PROCESS; nConfig pp(0); nconfig; Dclk when pp(1)='0' else dclk_int; Data0 when pp(1)='0' else data0_int; ADDR inc; end;
Conclusion
Altera provides high-density PLDs that require larger configuration files. using flash memory device EPM3128A device design, quickly configured.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
Copyright 2000 Altera Corporation. Altera, ACEX, APEX, FLEX, MAX, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.

Configuring PLDs with Flash Memory Altera® introduces higher-dens

Top Searches for this datasheet

Other recent searches