author: Peter Narvaez 1991 April Article reprint Extended ba
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Extended baud rates SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 SCC2698B
author: Peter Narvaez 1991 April
Article reprint
Extended baud rates SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 SCC2698B
Author: Peter Narvaez
AFFECT `RESERVED REGISTERS' BAUD RATES
Philips Semiconductors UART chips (EXCEPTING SC26C94) have test modes which accessed READ reserved registers address Each time read either address performed, flip-flop that address will toggle. Software must keep track state these flop-flops since there internal indication sate these flop-flops. They reset non-test condition hardware reset chip. Other methods resetting described below. test mode address useful user requiring higher speed baud rates. gives rates 115.2Kb mode. test mode dividers baud rate generator changed. Test mode will, therefore, effect UARTs chip. Please note table below that some more common baud rates change when test mode Test also changes RTSN outputs transmitter clock. since there four choices action only them will correct. course hardware reset will always reset both test modes. Since hardware reset often equivalent system restart, following methods presented regain control test mode. risk belaboring subject should mentioned that several approaches several versions each could applied practicality each being dependent hardware use. These characterized typed follows: Internal transmit loop send test condition send Counter/Timer (C/T) generate time period which byte start sent. stop upon completion transmission. value then directly represents speed unknown data clock. inverse Sending data receiving data from known good device evaluating error status that data. discussion below will convenient represent state test flip-flops binary bits being normal) thus: choose baud rate which different four conditions test bits. 7200 baud rate these. configuration test bits except will increase baud rate factor eight more. (Specifically 128x). time 7200 baud about 138µs half that 69µs.
Table Baud Rates
Test Test Baud Rate 38,400 19,200 9,600 7,200 4,800 2,400 2,000 1,800 1,200 1,050 134.5 Test Test Baud Rate 38,400 19,200 9,600 57,600 4,800 57,600 2,000 14,400 115,200 1,050 57,600 28,800 19,200 14,400 1,076 7,200 4,800 Test Test Baud Rate 614,400 307,200 153,600 921,600 76,800 921,600 32,000 230,400 1,843,200 16,800 921,600 460,800 307,200 230,400 17,216 14,080 115,200 76,800 Test Test Baud Rate 614,400 307,200 153,600 115,200 76,800 38,400 32,000 28,800 19,200 16,800 9,600 4,800 3,200 2,400 2,152 1,760 1,200
Table Baud Rates
Flip-Flop Test inactive inactive active active Test inactive active inactive active 7200 Baud Rate 7200 (normal) 57,600 115,200 921,000
Type
This method will features internal UART determine reset normal mode. will counter/timer known time reference then read value TxEMT TxRDY bits status register this time. normal operation 7200 baud time will require clocks input. know that test mode will increase 7200 baud rate least time then requires `X1' clocks. Reset receiver transmitter then transmitter local loop back 7200 baud. counter timer counter mode, preset value (0030 hex), clock input. This setting will cause time approximately three-fourths time. (The precise time important frequency). Interrupt ready poll (Interrupt Status Register) ready bit. control register setup follows. (Hex values) OPCR IPCR CTUR CTLR test loop will look TxRDY TxMT status bits condition when times out. This will mean that start transmitted character completed. Since test modes will, general, make data clocks faster least factor eight, data clock slower than will cause above bits state time out. flow would then Rev. March 1994
baud rate 115,200 would selected first reading address then setting (Clock Select Register) 1200 baud rate. test mode address changes receivers transmitters mode operation. also connects some output pins various internal signals (mostly baud rate clocks). This mode very useful unless mode desired channels output port pins used. test mode will violate specified speed parameters. normal mode operation not, however, specifically verified productions testing. mentioned previously, returning from test mode normal operation only requires another read address appropriate. some reason software aware which test mode use, painful properly reset test modes 1991 April
Article reprint
Extended baud rates SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 SCC2698B
BEGIN Toggle Test TEST ROUTINE: Enable Transmitter Load Transmit holding register Start Counter/timer Wait time Stop TEST Read status register, TxEMT TxRDY then quit Reset Transmitter Toggle Test Call Test Routine Read status register, TxEMT TxRDY then quit Toggle Test Assuming test flop-flops were state begin with, above will always return test flip-flops before second toggle Test above predicated upon knowing system test condition which one. therefore valid guess Test just blindly toggle that flip-flop first step.
Type
Here value used determine active test mode. Preset (0030 hex). interrupt TxRDY. UART control register settings follow. OPCR IPCR CTUR CTLR Enable Transmitter Load Transmit holding register Start Counter/timer Wait TxRDY time Stop Read upper lower registers
Table
Counter Value Indicates Test State (CTU
Type
Similar above without TEST ROUTINE TEST. this method value will used determine approximate rate from that determine which flip-flops need toggled order return normal operation. Since dealing with large baud rate changes that test modes bring about necessary make exact measurements. UART above Enable Transmitter Load Transmit holding register Start Counter/timer Wait time Stop Read status register. Depending test mode active would expect TxEMT TxRDY bits follows:
above numbers based time required start sent. Other time intervals course used. exact values also depend fast control processor service interrupts long pooling loop could just well full character time instead start time.
Type
This test will send character known good receiver. suggested send eight `00' character with even parity 1800 baud. test mode will increase 1800 baud rate 14400, 230400, 28800. UART control register settings follow. OPCR IPCR CTUR CTLR receiver 9600 baud. Depending active test mode asynchronous timing receiver will `see' character follows:
Table
Test Mode Character Received data received. Byte time shorter than start bit.
Table
Test Mode TxEMT TxRDY
Toggle test mode bits according indication transmitter status bits.
above, course, very practical when status receiver available local processor. These have verified above hardware. However, idea what desired shown. Actual applications will doubt vary from above hardware system timing dictate
1991 April
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