FIGURE RECOMMENDED HARDWARE CONFIGURATION System Level Design Con

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

FIGURE RECOMMENDED HARDWARE CONFIGURATION System Level Design Con

Datasheet Thumbnail

Top Searches for this datasheet

AN709
FIGURE RECOMMENDED HARDWARE CONFIGURATION
System Level Design Considerations When Using I2CSerial EEPROM Devices
Rick Stoneking Microchip Technology Inc.
INTRODUCTION
Developing systems that implement protocol communicating with serial EEPROM devices requires that certain factors considered during hardware software development phase system achieve maximum compatibility robustness. This application note discusses these factors, both hardware software, help insure that optimal system design achieved. This application note limited single master systems therefore does specifically address unique requirements multimaster system. However, concepts presented this application note apply equally well those systems.
EEPROM
INSURING `BUS-FREE' DURING POWER-UP
order insure that internal state machine serial EEPROM correctly initialized power crucial guarantee that device sees `bus-free' condition (defined both being high) until VDDmin been reached. ideal guarantee this through pull-up resistors both lines. addition, these pull-ups should tied same voltage source device. other words device supplied from main positive supply rail then pull-ups should connected that same supply rail opposed being connected microcontroller pin, example). Figure example recommended hardware configuration. reasoning behind doing this same both adding pull-up line utilizing same supply pull-ups. anyone experience with CMOS logic already knows, necessary ensure that inputs tied either high low, since allowing CMOS input float lead number problems. line does have pull-up, pull-ups tied supply rail, then conditions occur, however briefly, where SCL/SDA inputs floating with respect supply voltage. When possible this condition should avoided.
CONDITIONS CONSIDERED
bi-directional nature data devices operate both transmit receive modes various times. order make this bi-directional operation possible protocol must define specific times which given device transmit receive, well define specific points protocol where functions swapped (i.e. transmitter becomes receiver receiver becomes transmitter). There number events which could potentially cause this sender/receiver `synchronization' lost, which result situations where: Both master slave send mode. Both master slave receive mode. `bit count' more bits between master slave. These events, which include microcontroller being reset during communication, brown-out conditions, excessive noise clock data lines, improper input levels during power effectively neutralized through combination hardware software techniques.
trademark Philips Semiconductors
1999 Microchip Technology Inc.
DS00709B-page
AN709
When possible pullup resistor line (i.e. hardware design already been finalized) then firmware should configured either: drive line high during power float input during power these options, first recommended method, despite typical concerns regarding latch-up, because does negatively impact battery life battery powered applications. Microchip Technology's serial EEPROM devices, like CMOS devices, susceptible latch-up, however latch-up does occur until currents excess 100mA injected into pin. Typical microcontrollers capable supply currents this magnitude, therefore risk latch-up extremely low. second option also acceptable does lead brief increase current draw device during time period which floating with respect VDD. This increase significant comparison normal standby current device have detrimental affect battery life power sensitive applications. cases important that lines actively held while EEPROM device powered This have indeterminable effect internal state machine and, some cases, state machine fail correctly initialize EEPROM will power incorrect state. Another improper practice which should pointed driving line high microcontroller rather than tri-stating allowing requisite pullup resistor pull high state. While this practice would appear harmless enough, indeed long microcontroller EEPROM device never sync, there potential high current situation occur. event that microcontroller EEPROM should sync, EEPROM outputting `low' (i.e. sending driving data `0') while microcontroller driving high then impedance path between created excessive current will flow microcontroller into EEPROM pin. amount current that flows limited only specification microcontoller's pin. This high current state obviously have very detrimental effect battery life, well potentially present long term reliability problems associated with excess current flow. START Clock nine bits START STOP
first START will cause device reset from state which expecting receive data from microcontroller. this mode device monitoring data receive mode detect START which forces internal reset. nine bits used force reset those devices that could reset previous START bit. This occurs only device mode where either driving acknowledge (low), output mode driving data bus. both these cases previous START (defined going while high) could generated device holding low. sending nine bits guaranteed that device will NACK (microcontroller does drive acknowledge data sent EEPROM) which also forces internal reset. second START sent guard against rare possibility erroneous write that could occur microcontroller reset while sending write command EEPROM, and, EEPROM driving when first START sent. this special case this second START sent, instead STOP sent, device could initiate write cycle. This potential erroneous write occurs only event microcontroller being reset while sending write command EEPROM. final STOP terminates activity puts EEPROM standby mode. This sequence does effect other devices which they will simply disregard invalid command.
SUMMARY
This application note presented ideas that fundamental nature, always obvious, utilization serial EEPROM devices. Ideally hardware/software engineer(s) takes these ideas into consideration during system development design accordingly. recommended that software reset sequence detailed this application note added system initilization code system that utilizes serial EEPROM device.
FORCING INTERNAL RESET SOFTWARE
designs recommended that software reset sequence sent EEPROM part microcontrollers power sequence. This sequence guarantees that EEPROM correct known state. Assuming that EEPROM powered into incorrect state that reset occurred microcontroller during communication), following sequence (which further explained below) should sent order guarantee that serial EEPROM device properly reset:
DS00709B-page
REFERENCES
`I2C-Bus Specification', Philips Semiconductors, January 1992 `The I2C-Bus It', Philips Semiconductors, April 1995
1999 Microchip Technology Inc.
AN709
NOTES:
1999 Microchip Technology Inc.
DS00709B-page
WORLDWIDE SALES SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Address: http://www.microchip.com
AMERICAS (continued)
Toronto
Microchip Technology Inc. 5925 Airport Road, Suite Mississauga, Ontario 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Singapore Ltd. Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific Unit 2101, Tower Metroplaza Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431
Taiwan, R.O.C
Microchip Technology Taiwan 10F-1C Tung North Road Taipei, Taiwan, Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Atlanta
Microchip Technology Inc. Sugar Mill Road, Suite 200B Atlanta, 30350 Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc. Mount Royal Avenue Marlborough, 01752 Tel: 508-480-9990 Fax: 508-480-8575
EUROPE
United Kingdom
Arizona Microchip Technology Ltd. Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 Tel: 5858 Fax: 44-118 921-5835
Beijing
Microchip Technology, Beijing Unit 915, Chaoyangmen Dajie Dong Erhuan Road, Dongcheng District China Hong Kong Manhattan Building Beijing 100027 Tel: 86-10-85282100 Fax: 86-10-85282104
Chicago
Microchip Technology Inc. Pierce Road, Suite Itasca, 60143 Tel: 630-285-0071 Fax: 630-285-0075
India
Microchip Technology Inc. India Liaison Office Legacy, Convent Road Bangalore 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062
Denmark
Microchip Technology Denmark Regus Business Centre Lautrup Ballerup DK-2750 Denmark Tel: 4420 9895 Fax: 4420 9910
Dallas
Microchip Technology Inc. 4570 Westgrove Drive, Suite Addison, 75248 Tel: 972-818-7423 Fax: 972-818-2924
Japan
Microchip Technology Intl. Inc. Benex 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
France
Arizona Microchip Technology SARL Parc d'Activite Moulin Massy Saule Trapu Batiment Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Dayton
Microchip Technology Inc. Prestige Place, Suite Miamisburg, 45342 Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc. Tri-Atria Office Building 32255 Northwestern Highway, Suite Farmington Hills, 48334 Tel: 248-538-2250 Fax: 248-538-2260
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934
Germany
Arizona Microchip Technology GmbH Gustav-Heinemann-Ring D-81739 Germany Tel: 49-89-627-144 Fax: 49-89-627-144-44
Angeles
Microchip Technology Inc. 18201 Karman, Suite 1090 Irvine, 92612 Tel: 949-263-1888 Fax: 949-263-1338
Italy
Arizona Microchip Technology Centro Direzionale Colleoni Palazzo Taurus Colleoni 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
11/15/99
Shanghai
Microchip Technology Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hong Qiao District Shanghai, 200335 Tel: 86-21-6275-5700 Fax: 21-6275-5060
York
Microchip Technology Inc. Motor Parkway, Suite Hauppauge, 11788 Tel: 631-273-5305 Fax: 631-273-5335
Jose
Microchip Technology Inc. 2107 North First Street, Suite Jose, 95131 Tel: 408-436-7950 Fax: 408-436-7955
Microchip received QS-9000 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona July 1999. Company's quality system processes procedures QS-9000 compliant PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs microperipheral products. addition, Microchip's quality system design manufacture development systems 9001 certified.
rights reserved. 1999 Microchip Technology Incorporated. Printed USA. 11/99
Printed recycled paper.
Information contained this publication regarding device applications like intended suggestion only superseded updates. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights. Microchip logo name registered trademarks Microchip Technology Inc. U.S.A. other countries. rights reserved. other trademarks mentioned herein property their respective companies.
1999 Microchip Technology Inc.

FIGURE RECOMMENDED HARDWARE CONFIGURATION System Level Design Con

Top Searches for this datasheet

Other recent searches