Quad 2-Input Exclusive Gate MC74HC7266A identical pinout LS266 HC

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Quad 2-Input Exclusive Gate MC74HC7266A identical pinout LS266 HC

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Quad 2-Input Exclusive Gate
MC74HC7266A identical pinout LS266 HC266. HC7266 standard CMOS outputs instead open-drain outputs. device inputs compatible with standard CMOS outputs; with pullup resistors, they compatible with LSTTL outputs. Output Drive Capability: LSTTL Loads Outputs Directly Interface CMOS, NMOS, Operating Voltage Range: Input Current: High Noise Immunity Characteristic CMOS Devices Compliance with Requirements Defined JEDEC Standard Chip Complexity: FETs Equivalent Gates
MC74HC7266A
SUFFIX PLASTIC PACKAGE CASE 646-06
SUFFIX SOIC PACKAGE CASE 751A-03
SUFFIX TSSOP PACKAGE CASE 948G-01
ORDERING INFORMATION MC74HCXXXXAN MC74HCXXXXAD MC74HCXXXXADT Plastic SOIC TSSOP
LOGIC DIAGRAM
ASSIGNMENT
FUNCTION TABLE
Inputs Output
3/97
Motorola, Inc. 1997
MC74HC7266A
MAXIMUM RATINGS*
Symbol Parameter Value Unit Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Vout Output Voltage (Referenced GND) Input Current, Iout Output Current, Supply Current, Pins Power Dissipation Still Plastic SOIC Package TSSOP Package Tstg Storage Temperature
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either VCC). Unused outputs must left open.
Lead Temperature, from Case Seconds (Plastic DIP, SOIC TSSOP Package)
Maximum Ratings those values beyond which damage device occur. Functional operation should restricted Recommended Operating Conditions. Derating Plastic DIP: mW/_C from 125_C SOIC Package: mW/_C from 125_C TSSOP Package: mW/_C from 125_C high frequency heavy load considerations, Chapter Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Unit
Supply Voltage (Referenced GND)
Vin, Vout
Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Figure
1000
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
25_C 3.15 1.35
85_C 125_C
3.15 1.35 3.15 1.35
Unit
Minimum High-Level Input Voltage
Vout |Iout|
Maximum Low-Level Input Voltage
Vout |Iout|
Minimum High-Level Output Voltage
|Iout|
|Iout| |Iout| |Iout|
2.48 3.98 5.48
2.34 3.84 5.34
2.20 3.70 5.20
High-Speed CMOS Logic Data DL129
MC74HC7266A
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
Guaranteed Limit Symbol Parameter Test Conditions 25_C
85_C 125_C
0.33 0.33 0.33 0.40 0.40 0.40
Unit
Maximum Low-Level Output Voltage
|Iout|
|Iout| |Iout| |Iout| Iout
0.26 0.26 0.26
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
NOTE: Information typical parametric values found Chapter Motorola High-Speed CMOS Data Book (DL129/D).
ELECTRICAL CHARACTERISTICS Input
Guaranteed Limit Symbol tPLH, tPHL Parameter 25_C
85_C 125_C
Unit
Maximum Propagation Delay, Input Output (Figures
tTLH, tTHL
Maximum Output Transition Time, Output (Figures
Maximum Input Capacitance
NOTES: propagation delays with loads other than Chapter Motorola High-Speed CMOS Data Book (DL129/D). Information typical parametric values found Chapter Motorola High-Speed CMOS Data Book (DL129/D). Typical 25°C, Power Dissipation Capacitance (Per Gate)*
Used determine no-load dynamic power consumption: load considerations, Chapter Motorola High-Speed CMOS Data Book (DL129/D).
TEST POINT tPHL DEVICE UNDER TEST OUTPUT
INPUT tPLH
OUTPUT tTLH tTHL
Includes probe capacitance
Figure Switching Waveforms
Figure Test Circuit
High-Speed CMOS Logic Data DL129
MC74HC7266A
LOGIC DETAIL (1/4 Device)
APPLICATION INFORMATION
defined biphase-level code. Also known Manchester Code, this technique utilizes binary phase shift keying (PSK). output shown Figure carries both data synchronization information; therefore, separate data clock lines required transfer information. positive-going transition middle interval indicates logic zero; negative-going transition indicates logic (see Figure NRZ-L shown Figure non-return-to-zero level code. This simply serial data shift register, such HC597. signal must phase coherent (i.e., glitches). Therefore, NRZ-L clock transitions must coincident.
HC7266A NRZ-L CLOCK
Figure Biphase-Level Encoder (Manchester Encoder)
NRZ-L
CLOCK
POSITIVE LOGIC DATA
INTERVAL
Figure Timing Diagram
High-Speed CMOS Logic Data DL129
MC74HC7266A
OUTLINE DIMENSIONS
SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE
NOTES: LEADS WITHIN 0.13 (0.005) RADIUS TRUE POSITION SEATING PLANE MAXIMUM MATERIAL CONDITION. DIMENSION CENTER LEADS WHEN FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH. ROUNDED CORNERS OPTIONAL. INCHES 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 0.052 0.095 0.008 0.015 0.115 0.135 0.300 0.015 0.039 MILLIMETERS 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 1.32 2.41 0.20 0.38 2.92 3.43 7.62 0.39 1.01
SEATING PLANE
SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION.
0.25 (0.010)
SEATING PLANE
0.25 (0.010)
MILLIMETERS 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 0.25 0.19 0.25 0.10 5.80 6.20 0.25 0.50
INCHES 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.228 0.244 0.010 0.019
High-Speed CMOS Logic Data DL129
MC74HC7266A
OUTLINE DIMENSIONS
SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS 4.90 5.10 4.30 4.50 1.20 0.05 0.15 0.50 0.75 0.65 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 INCHES 0.193 0.200 0.169 0.177 0.047 0.002 0.006 0.020 0.030 0.026 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252
0.10 (0.004) 0.15 (0.006)
0.25 (0.010)
IDENT.
DETAIL
0.15 (0.006)
SECTION
0.10 (0.004) SEATING
PLANE
DETAIL
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MC74HC7266A/D High-Speed CMOS Logic Data DL129

Quad 2-Input Exclusive Gate MC74HC7266A identical pinout LS266 HC

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