MC74HC174A identical pinout LS174. device inputs compatible with stand
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MC74HC174A Flip-Flop with Common Clock Reset
MC74HC174A identical pinout LS174. device inputs compatible with standard CMOS outputs; with pullup resistors, they compatible with LSTTL outputs. This device consists flip-flops with common Clock Reset inputs. Each flip-flop loaded with low-to-high transition Clock input. Reset asynchronous active-low.
Output Drive Capability: LSTTL Loads NMOS Compatible Input Levels Outputs Directly Interface CMOS, NMOS, Operating Voltage Range: Input Current: Compliance with Requirements Defined JEDEC Standard Chip Complexity: FETs 40.5 Equivalent Gates
LOGIC DIAGRAM
DATA INPUTS CLOCK RESET
PDIP-16 SUFFIX CASE
MC74HC174AN AWLYYWW
SO-16 SUFFIX CASE 751B
HC174A AWLYWW
Assembly Location Wafer Year Work Week
NONINVERTING OUTPUTS
ASSIGNMENT
RESET CLOCK
FUNCTION TABLE
Inputs Reset Clock Output Change Change Value 40.5 Units
ORDERING INFORMATION
Device MC74HC174AN MC74HC174AD MC74HC174ADR2 Package PDIP-16 SOIC-16 SOIC-16 Shipping 2000 Rail 2500 Reel
Semiconductor Components Industries, LLC, 2000
March, 2000 Rev.
Design Criteria Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product .0075 *Equivalent two-input NAND gate.
Publication Order Number: MC74HC174A/D
MC74HC174A
MAXIMUM RATINGS*
Symbol Parameter Value Unit Supply Voltage (Referenced GND) Input Voltage (Referenced GND) -0.5 Vout Output Voltage (Referenced GND) Input Current, Iout Output Current, Supply Current, Pins Power Dissipation Still Air, Storage Temperature Plastic SOIC Package Tstg
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either VCC). Unused outputs must left open.
Lead Temperature, from Case Seconds (Plastic SOIC Package)
*Maximum Ratings those values beyond which damage device occur. Functional operation should restricted Recommended Operating Conditions. Derating Plastic DIP: mW/_C from 125_C SOIC Package: mW/_C from 125_C high frequency heavy load considerations, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter
Unit
Supply Voltage (Referenced GND)
Vin, Vout
Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Figure
1000
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
25_C 3.15 1.35
85_C 125_C
3.15 1.35 3.15 1.35
Unit
Minimum High-Level Input Voltage
Vout |Iout|
Maximum Low-Level Input Voltage
Vout |Iout|
Minimum High-Level Output Voltage
|Iout|
|Iout| |Iout| |Iout| |Iout| |Iout|
3.98 5.48
3.84 5.34
Maximum Low-Level Output Voltage
0.26 0.26
0.33 0.33
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Used determine no-load dynamic power consumption: load considerations, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). NOTE: propagation delays with loads other than information typical parametric values, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
NOTES: Information typical parametric values along with high frequency heavy load considerations, found Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). Total Supply Current SICC.
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
Symbol Maximum Quiescent Supply Current (per Package) Maximum Input Leakage Current Parameter Iout Test Conditions
ELECTRICAL CHARACTERISTICS Input
TIMING REQUIREMENTS Input
Symbol
Symbol
trec
tPLH tPHL
tPLH tPHL
tTLH tTHL
fmax
Maximum Input Rise Fall Times
Minimum Pulse Width, Reset
Minimum Pulse Width, Clock
Minimum Recovery Time, Reset Inactive Clock
Minimum Hold Time, Clock Data
Minimum Setup Time, Data Clock
Power Dissipation Capacitance (Per Enabled Output)*
Maximum Input Capacitance
Maximum Output Transition Time, Output (Figures
Maximum Propagation Delay, Reset (Figures
Maximum Propagation Delay, Clock (Figures
Maximum Clock Frequency (50% Duty Cycle) (Figures
Parameter
Parameter
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Fig.
MC74HC174A
25_C
1000
25_C
25_C
Guaranteed Limit
Typical 25°C,
85_C
Guaranteed Limit
Guaranteed Limit
1000
85_C 125_C
85_C 125_C
125_C
1000
Unit
Unit
Unit
MC74HC174A
EXPANDED LOGIC DIAGRAM
CLOCK RESET
SWITCHING WAVEFORMS
1/fmax tPLH tTLH tTHL tPHL trec CLOCK
RESET tPHL
CLOCK
Figure
Figure
TEST POINT VALID DATA CLOCK *Includes probe capacitance DEVICE UNDER TEST OUTPUT
Figure
Figure Test Circuit
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MC74HC174A
PACKAGE DIMENSIONS
PDIP-16 SUFFIX CASE 648-08 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. DIMENSION CENTER LEADS WHEN FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS 0.740 0.770 18.80 19.55 0.250 0.270 6.85 6.35 0.145 0.175 4.44 3.69 0.015 0.021 0.53 0.39 0.040 0.070 1.77 1.02 0.100 2.54 0.050 1.27 0.008 0.015 0.38 0.21 0.110 0.130 3.30 2.80 0.295 0.305 7.74 7.50 0.020 0.040 1.01 0.51
0.25 (0.010)
SEATING PLANE
SOIC-16 SUFFIX CASE 751B-05 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. MILLIMETERS 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 0.25 0.19 0.25 0.10 6.20 5.80 0.50 0.25 INCHES 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.229 0.244 0.010 0.019
0.25 (0.010)
SEATING
PLANE
0.25 (0.010)
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MC74HC174A
Notes
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MC74HC174A
Notes
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MC74HC174A
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MC74HC174A/D
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