MC33410 Dual CVSD/PLL Cordless Phone System MC33410 Dual CVS

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MC33410 Dual CVSD/PLL Cordless Phone System MC33410 Dual CVS

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MC33410
Dual CVSD/PLL Cordless Phone System
MC33410 Dual CVSD/Cordless Phone system designed requirements digital cordless telephone system. device Modulator/Demodulator) Encoder digitize speech transmission, CVSD Decoder reconstruct received digital speech from receiver. Provisions made transmit receive data well. Included three PLLs (Phase-Locked Loops). intended with external VCOs 64/65 128/129 dual modulus prescalers, control transmit receive (LO1) frequencies communication. third configured local oscillator (LO2), functional MHz. Also included muting, audio gain adjust (internal external), battery/carrier detect, wide range reference frequency. power supply range data only (non-voice) mode also included.
DUAL CVSD/PLL CORDLESS PHONE SYSTEM
SEMICONDUCTOR TECHNICAL DATA
Complete CVSD Sections Full Duplex Operation PLLs Suitable System Adjustable Detection Battery Carrier Signal (RSSI) Minimal External Components Encode Path Includes Adjustable Gain Amplifiers, Filters, Mute, CVSD Encoder, Data Insert, Scrambler Decoder Path Contains Data Slicer, Clock Recovery, Descrambler, Data Detect, CVSD Decoder, Filters, Mute Power Amplifier Data Transmitted During Voice Conversation with Minimal Noticeable Audio Disruption Idle Channel Noise Control Independent Power Amplifier with Differential Outputs, Mute Selectable Frequency Switched Capacitor Filters, CVSD Function, PLLs, Reference Frequency Source Crystal System Clock Serial Port Control Gain, Mute, Frequency Selection, Phase Detector Gain, Power Down Modes, Idle Channel Control, Scrambler Operation, Battery Detect, Others Mode Available Data Only Transmission (non-voice) Ambient Temperature Range: 85_C Power Supply Range: Power Down Modes Power Conservation LQFP with Lead Pitch
SUFFIX PLASTIC PACKAGE CASE (LQFP-48)
ORDERING INFORMATION
Device XC33410FTA Operating Temperature -40° +85°C Package LQFP-48
This document contains information product under development. Motorola reserves right change discontinue this product without notice.
Motorola, Inc. 1998
MOTOROLA RF/IF DEVICE DATA
MC33410
Simplified Block Diagram
Analog Speech Gain Adj. Filter CVSD Decoder Anti-Alias Gain Adj. Analog Speech Mute Mute Filter Programmable Counters Interface Batt Dec. Clock Encode Clock Data Det. Register Idle Channel
Mute
CVSD Encoder
Data Register
Scrambler Idle Channel
Digital Speech/ Data Data
Descrambler
Clock Recovery Data Slicer
Digital Speech/ Data Dec. Clock Status Battery/
Power
Ref. Freq.
VCO+ 64/65 PreScaler
VCO+ 64/65 PreScaler
Tank
PRELIMINARY SPECIFICATIONS (Subject change)
Parameter Supply Voltage Supply Current (All sections active) Remote Gain Adjust Range Receive Path Gain Control Range Output Current Capability (PAO+, PAO-) Max. frequency Phase Detector Charge Pump Output Current High Digital Input Signal Amplitude Data Slicer Operating Ambient Temperature
NOTE: Above specs represent design objectives, subject change.
Symbol
28.5 ±400 ±100 >200
Units
mVpp
MOTOROLA RF/IF DEVICE DATA
MC33410
Figure Typical Applications Circuit
Battery
Dec. Battery Dig. Input
Audio
Audio Mute
PAO- PAO+ Dec. CVSD Encoder Rem. Gain Adjust SMTH Mute Audio Enc. Battery 1010 Generator Ref. Ctr. Enc. Ctr. Ctr. Ref. Serial Interface Fref Enc. Audio Input
AALPF
Gain Adjust
Mute
Data Slicer Data Clock Recovery 1010 Generator Status Clk. CVSD Decoder
Clk. Idle Channel Detect
Battery LO2+
Data Detect Descrambler Data Register
Ref.
Battery Carr. Det.
Idle Chan Control
CVSD Encoder
LO2-
Idle Chan Ctrl Idle Chan Ctr.
Scrambler Data Register
Enc.
Battery/CD
Phase Detector
Ctr. Ref. Freq.
LO2PD
Fref
Phase Detector
Phase Detector
Status
Data
Battery 64/65
Battery 64/65
Microprocessor
NOTE:
numbers firm used design-in purposes.
MOTOROLA RF/IF DEVICE DATA
MC33410
RECOMMENDED OPERATING CONDITIONS (Subject change)
Parameter Supply Voltage CVSD Clock Rate Encoder Signal Level (max) Peak Output Current PAO+, PAO- Reference Frequency Amplitude (Fref Digital Input Signal Amplitude Crystal Reference Frequency Max. Input Frequency FRx, Control Voltage (Pin Max. Frequency Reference Counter Range (Note Counter Range (Note Counter Range (Note with 64/65 Modulus Prescaler with 128/129 Modulus Prescaler Counter Range (Note Counters (for Encode Clock) (Note Receive Path Gain Control Code Range (Note Operating Ambient Temperature
NOTES: Values specified pure numbers base Above specs represent design objectives, subject change.
Symbol
>200 0.20 18.25 4095 8191 16383
Units mVpp
FUNCTION DESCRIPTION
Name Description Modulus Control Output 64/65 128/129 dual modulus prescaler. Input PLL. Data Status Supply section. Allowable range Phase detector charge pump output PLL. Ground sections. Phase detector charge pump output PLL. Supply section Serial Interface section. Allowable range Input PLL. Modulus Control Output 64/65 128/129 dual modulus prescaler. Enable input port. This signal latches register address data. Clock input port. Maximum frequency MHz. Bi-directional data line port. Data Modem mode, this provides recovered clock. Logic output which indicates that predetermined 24-bit code word been detected Data Detect register, following data word been loaded into register Data Modem mode, this provides Transmit Data clock. crystal, range 18.25 connected these pins provide reference frequency. external reference source used, capacitively coupled Fref
NOTE:
Fref Fref
pins must within ±0.5 each other.
MOTOROLA RF/IF DEVICE DATA
FUNCTION DESCRIPTION (continued)
Description Name Battery/CD Audio Ground PAO+, PAO- Audio Output Audio open collector output. When low, indicates either supply voltage (VCC) low, carrier level above threshold. This output when disabled. digital output scrambler, which passes data from CVSD encoder, Data register, 1010 Generator. Source selection done through port. Supply input audio sections, filters, CVSD blocks. Allowable range Internally connected Pins analog input CVSD encoder. Max. input level Vpp. Output transmit speech processing section. Ground audio sections, filters, CVSD blocks. Internally connected Pins Output microphone amplifier, input filters. This output rail-to-rail capability. Inverting input microphone amplifier. Gain frequency response with external resistors capacitors. This capacitor sets time constant CVSD encoder. This sensitive leakage. Analog ground audio section CVSD encoder decoder. capacitor sets time constant CVSD decoder. This sensitive leakage. Supply input audio sections, filters, CVSD blocks. Allowable range Internally connected Pins Differential outputs power amplifier stage driving earpiece hybrid network. gain frequency response with external resistors capacitors. Ground audio sections, filters, CVSD blocks. Internally connected Pins Input power amplifier stage. This summing node. Output receive speech processing section. capacitor filters internal reference voltage. adjusted, monitored this pin. Max. load current Input receive speech processing section. analog output CVSD decoder. output, provides recovered data, Data Detect output, data slicer output. high impedance input (600 carrier detect input signal. Selection done through port. Table Supply input audio sections, filters, CVSD blocks. Allowable range Internally connected Pins digital stream from receiver applied data slicer this pin. Minimum amplitude mVpp. Hysteresis output, this provides recovered clock from Clock Recovery block. input, CVSD decoder clock applied this pin. this disabled state. Selection done through port. Table Data Modem mode, data transmitted input this pin. Ground audio sections, filters, CVSD blocks. Internally connected Pins Buffered output frequency. pullup resistor required. Supply Allowable range tank circuit connected these pins varactor control Ground section. Phase detector charge pump output PLL. Ground section. Digital Input
NOTE:
MC33410
LO2+, LO2-
pins must within ±0.5 each other.
MOTOROLA RF/IF DEVICE DATA
MC33410
Note: following descriptions, control bits Serial Interface various functions will identified register number number. example, 3/19 indicates register Bits 5/14-11 indicates register bits through Please refer Figure Transmit Speech Processing Section This section made externally adjustable microphone amplifier (Pins 23), internally adjustable gain stage, pass filters, mute switch. gain microphone amplifier with external resistors receive audio from microphone handset), from hybrid base unit), from other audio source. output rail-to-rail capability, bias level (1.5 adjustable gain stage, referred Remote Gain Adjust, provides levels gain increments. controlled with bits 6/15-11 shown Table
Table Remote Gain Adjust
Register
Bits 15-11 00001 00010 00100 01000 10000
Gain
-8.0 -4.0
+4.0 +8.0
CVSD Encoder/Idle Channel/Tx Data Register analog signals digitized input CVSD Encoder. output encoder will digital equivalent audio, selected clock rate. Based reference frequency, bits 4/23-18 used Encoder Counter, conjunction with subsequent divider, CVSD Encoder frequency kHz. Bits 3/16-15 will CVSD proper operation selected frequency, according Table
Table CVSD Clock/Data Rates
Register
Clock/Data Rate
Encoder's minimum step size selected using bits 2/22-21, according Table
Other combinations bits invalid. Pass Filter after gain stage switched capacitor filter with corner frequency kHz. subsequent smoothing pass filter corner frequency kHz, designed filter high frequency clock noise from previously mentioned switched capacitor filter. mute switch will mute minimum controls mute.
Table Minimum Step Size
Decoder Register Bits Encoder Register Bits Step Size minimum 22.4
FUNCTIONAL DESCRIPTION
1010 Generator, when selected, provides alternating "1-0" pattern square wave half CVSD clock rate) scrambler. This represents lowest amplitude analog signal, used when desired send quiet signal. Selection this block occur either automatically, intentionally, follows: automatic selection occurs when Idle Channel Detector senses average audio signal below threshold which with bits 5/17-15 (See Table Bits 5/14-11 select time delay automatic threshold detection occur. minimum delay zero, with these bits 0000. Changing bits provides delay increments clock cycles CVSD Encoder clock). maximum delay clock cycles, (7.5 kHz). When average audio signal increases above threshold, 1010 Generator will deselected with delay. This automatic switchover feature disabled with 7/2. 5/21 indicates when idle channel condition been detected. This output will functional even when idle channel detector disabled with 7/2. 5/18 will power down Idle Channel Detect Circuit power saving measure. used intentionally select 1010 Generator time. Table Idle Channel Detection Threshold
Register
Register
Bits 17-15
Threshold -52.5 -57.5
Bits 17-15
Threshold -62.5 -67.5
Data Register used transmission data between handset base units. procedure follows: receiving unit: code word bits, with 7/11) identifying that data transmission occurring must loaded into Data Register loading register This used detect when code word sent from transmitting unit. transmitting unit: same code word above loaded into register automatically loaded into Data Register. data word bits, with 7/12) then loaded into register
MOTOROLA RF/IF DEVICE DATA
MC33410
Upon loading register MC33410 automatically sends code word, followed data word, CVSD clock rate. When data word completely sent out, MC33410 will then return previous source digital information (CVSD Encoder 1010 Generator). Scrambler/Digital Output scrambler receives digital data from CVSD Encoder, 1010 Generator, Data Register, output output level VCC. scrambler bypassed with 7/1. scrambler, better known randomizer, provides only level communication security, also helps ensure digital output will contain abnormally long string which adversely affect CVSD Decoder operation, well section. scrambler maximal-length shift register sequence generator. length shift register selectable eight values with bits 7/10-8 (the descrambler receiving unit must same). Table lists polynomial associated with each selection.
Data Slicer/Clock Recovery data slicer will receive level digital signal from receiver section input signal data slicer must >200 mVpp. Hysteresis internally provided. output data slicer will same waveform, with amplitude VCC, observed (MP1) bits 7/5-4 output inverted setting 5/19 clock recovery block will generate phase locked clock, equal CVSD data rate, from incoming data, long Encoder Counter (bits 4/23-18) that data rate. recovered clock observed (MP2) bits 7/7-6 data from clock recovery block observed bits 7/5-4 clock recovery block bypassed setting With this setting data slicer output will directly descrambler, encoder clock will replace Clock Recovery Clock. Tables summarize options available (Pins 39). Table Options (Pin
Register
Function
Data from clock recovery block Data Detect Output Data Slicer Output Hi-Z/ Input
MOTOROLA RF/IF DEVICE DATA
Table Scrambler/Descrambler Selection
Register Shift Register Length Shif Polynomial z-10
Table Options (Pin
Register
Function
Output recovered clock
Input CVSD Decoder clock Disabled (Hi-Z)
When Hi-Z condition, input (Carrier Detect) function, with input impedance section entitled Battery/Carrier Detect explanation this function. Descrambler descrambler receives scrambled data from clock recovery block data slicer descrambles original data long selected taps same those transmitting scrambler (see Table descrambler block same configuration scrambler, self-synchronizing. descrambler bypassed with 7/1. Data Detect Register/Status Output/Rx Data Register Data Detect register will continuously compare descrambled data receives with 24-bit code word stored Data Register (loaded through register Upon detecting match, after code word passes through shift register, following 24-bit) data word will stored into Data Register, then loaded into register Interface. this time Status
output 5/22, will high. external microprocessor then retrieve data word reading register which time Status will low. Upon detection code word described above, CVSD Decoder will provided with 48-bits 1010 pattern (idle channel) minimize disturbances audio. After data word loaded into register CVSD Decoder resumes receiving data from descrambler. audio therefore interrupted with level signal maximum clock cycles (0.75 mSec kHz). Data Detect register bypassed setting CVSD Decoder/Decoder Clock/Idle Channel CVSD Decoder will provide analog equivalent, digital data receives from descrambler, from 1010 generator (idle channel generator). There single pole filter Decoder output reduce clock noise normally present CVSD analog output. CVSD Decoder self synchronizing long decoder clock matches data rate, Decoder been with bits 3/16-15 according Table Decoder clock provided from Clock Recovery block setting bits 7/7-6 clock internally provided Decoder, available Alternately, Decoder clock provided from external source setting 7/7-6 (see Table 1010 Generator provides alternating pattern square wave half CVSD clock rate) CVSD Decoder, resulting lowest amplitude analog signal 1010 Generator automatically selected whenever data detected received Data Detection Circuit, described above. Additionally, 1010 Generator selected with time. Decoder's minimum step size selected using bits 1/22-21, according Table Receive Audio Path Receive Audio Path (Pins consists anti-aliasing filter, pass filter, gain adjust stage, mute switch. Since analog output CVSD Decoder (typically input will contain noise CVSD clock rate, anti-aliasing filter, with corner frequency kHz, provided prevent aliasing that clock noise with subsequent switched capacitor filter. switched capacitor pass filter pole filter, with corner frequency kHz. This designed remove clock noise from CVSD Decoder output signal, well provide bandwidth limiting audio range. gain stage provides 28.5 gain adjustment steps (1.5 each), measured from Bits 6/10-6 used gain according Table mute switch controlled 6/1, will mute minimum
Table Receive Gain Adjustment
Register Bits 10.6 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 Register Bits 10.6 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Gain Gain -13.5 -12.0 -10.5 -9.0 -7.5 -6.0 -4.5 -3.0 -1.5 +1.5 +3.0 +4.5 +6.0 +7.5 +9.0 +10.5 +12.0 +13.5 +15.0
MC33410
Power Amplifiers power amplifiers (Pins designed drive earpiece handset, telephone line hybrid circuit base unit. Each output (PAO+ PAO-) source sink swing each. gain amplifiers with feedback resistor from input resistor differential gain resistor ratio. Capacitors used frequency shaping. pins' level (1.5 Mute switch, controlled with 6/0, will provide muting with feedback resistor. amount muting will depend value feedback resistor. Reference Clock reference clock provides frequency basis three PLLs, switched capacitor filters, CVSD Encoder section. source reference clock crystal range 18.25 connected Pins external source connected Fref (Pin 14). reference frequency directed programmable 12-bit counter provide reference frequency three PLLs. 12-bit counter such that, conjunction with programmable counters within each PLL, proper frequencies produced each VCO. programmable 6-bit counter, followed stage, frequency switched capacitor filters kHz, close that possible. programmable 6-bit counter which provides clock Clock Recovery block. This followed stage which provides CVSD Encoder clock. This followed stage, programmable 4-bit counter which sets delay Idle Channel Detect circuit. Transmit Receive (LO1) Sections transmit receive PLLs (Pins respectively) designed part system.
MOTOROLA RF/IF DEVICE DATA
MC33410
typical application Transmit section will generate transmit frequency, Receive section will generate frequency. sections identical, function independently. External requirements each include pass filter, VCO, 64/65 128/129 dual modulus prescaler. frequency output reduced dual modulus prescaler, then input MC33410 That frequency then further reduced programmable 13-bit counter (bits 1/19-7 2/19-7), provided side Phase Detector, where compared with reference frequency. output phase detector bi-directional charge pump which drives through pass filter. Bits 1/20 2/20 gain each charge pumps either 100/2 µA/Radian 400/2 µA/Radian. polarity phase detector outputs with bits 7/22 7/23. bit=0, appropriate configured operate with non-inverting pass filter/VCO combination. pass filter/VCO combination inverting, polarity should 7-bit counters (bits 1/6-0 2/6-0) drive Modulus Control input 64/65 128/129 dual modulus prescalers. Modulus Control outputs (Pins either voltage mode current mode with 7/13. calculate settings registers, following procedure used: Equation must integer) Bits 7/20-18 used select internal capacitor, with value range parallel varactor diodes tank's external capacitor. This permits certain amount fine tuning oscillator's performance. Table buffered output provided drive, e.g., mixer. frequency with programmable 14-bit counter (bits 3/13-0) conjunction with reference frequency. example, reference frequency kHz, frequency 63.3 MHz, 14-bit counter needs 1266d 0100 1111 0010). output level dependent value impedance partly determined external pullup resistor. output phase detector bi-directional charge pump which drives varactor diodes through external pass filter. 3/14 sets gain charge pump either 100/2 µA/Radian 400/2 µA/Radian. 7/21 sets polarity configured operate with non-inverting pass filter/VCO combination. pass filter/VCO combination inverting, polarity should Table Capacitor Selection
Capacitor Value Register
Equation
Remainder Equation Equation (decimal part where: fVCO frequency fPLL Reference Frequency within MC33410 smaller divisor dual modulus prescaler 64/65 prescaler) whole number portion setting counter within MC33410 setting counter within MC33410 example, provide MHz, internal reference frequency kHz, then equations yield:
18,64 284.375
0.375 register setting 284d 0001 0001 1100), register setting (001 1000). (LO2) This designed Local Oscillator typical system, designed frequencies MHz. varactor diodes included, used with external tank circuit (Pins 45).
MOTOROLA RF/IF DEVICE DATA
Register Bits 20-18 Bits 20-18 Capacitor Value
Reference Voltage voltage (1.5 available will have production tolerance ±6%, adjusted over range using bits 3/20-17. adjustment steps will 1.2% each. used bias external circuitry, long load current this does exceed Battery/Carrier Detect This circuit will provide indication either Battery voltage, carrier signal applied (MP1) from RSSI circuit. desired mode selected with 6/5. Battery Mode (Bit supply voltage applied comparator through internal resistor divider, compared internal reference (1.5 comparator hysteresis, measured VCC. resistor divider adjustable using bits 3/23-21. Battery threshold voltage will then equal voltage multiplied factor listed Table example, bits 3/23-21 011, threshold will 3.21 Carrier Detect Mode (Bit (MP1) must Hi-Z/CD Input mode setting bits 7/5-4 will then input with input impedance referenced analog signal applied will applied comparator through internal adjustable gain stage (adjustable using bits 3/23-21), compared internal reference comparator 18.0 hysteresis, measured threshold voltage will then equal voltage multiplied factor listed Table
MC33410
example, bits 3/23-21 011, threshold will 0.576 Internally there data registers, bits each, addressed with four bits ranging from Register bits 23-21 register contain data read microprocessor, while other register bits written microprocessor. contents registers read time. bits written read out, clock's positive transition. write read operations follows: Write Operation: write data MC33410, following sequence required (see Figure Enable line taken high. Five bits entered: first must indicate Write operation. next four bits identify register address (0001-1010). entered first. After clock pulse low, Enable line taken low. this transition, address latched decoded. Enable line maintained while data bits clocked entered first, last. bits written register which less than active bits (e.g., register unassigned bits After last entered, Enable line taken high then low. falling edge this pulse latches just entered data. clock line logic high low, must transition either direction during this Enable pulse. Enable line must then kept until next communication. Note: less than bits written data register, necessary enter full bits, long they lower order bits. example, bits register updated, they entered bits with clock cycles step above. However, this procedure used, minimum bits, with clock pulses, must entered.
Table LB/CD Threshold Adjustment Factor
Battery Mode 1.96 2.02 2.08 2.14 2.19 2.25 2.30 2.37 Register Bits 23-21 Carrier Detect Mode 0.574 0.524 0.453 0.384 0.314 0.247 0.177 0.110
comparator output 5/23, (open collector output). outputs high monitored voltage above threshold, Carrier signal below threshold. requires external pullup resistor. When this circuit disabled (bit 5/10 5/23 will high. Serial Interface Serial Interface 3-wire interface, consisting Clock line, Enable line, bi-directional Data line. interface always active, i.e. cannot powered down other sections MC33410 disabled enabled through this interface. clock must supplied MC33410 write read data, frequency MHz. clock need present when data being transferred. Enable line must when data being transferred.
Figure Writing Data MC33410
Clock Data
4-Bit Address
24-Bit Data from Latch Address
Latch Data
Enable
Figure Reading Data from MC33410
Sets Data Output
Clock Data
4-Bit Address
24-Bit Data from MC33410 Latch Address Load Data into Shift Register
Sets Data Input
Enable
MOTOROLA RF/IF DEVICE DATA
MC33410
Read Operation: read output bits (bits 5/23-21, register 10), contents register, following sequence required (see Figure Enable line taken high. Five bits entered: first must indicate Read operation. next four bits identify register address (0001-1010). entered first. After clock taken low, Enable line taken low. this transition, address latched decoded, contents selected register loaded into 24-bit output shift register. this point, Data line (Pin still input. While maintaining Enable line low, data read out. first clock rising edge will change Data line output, will present this line. full contents register then read (MSB first, last) with total clock rising edges, including step above. recommended that read bits clock's falling edge. only register read, this done with one, two, three clock rising edges, respectively. After last clock pulse, Enable line taken high then low. falling edge this pulse returns Data input. clock line logic high low, must transition either direction during this Enable pulse. Enable line must then kept until next communication. Data Modem Mode applications where MC33410 used wireless system transmitting data only (non-voice), mode which bypasses speech digitizing sections. resulting configuration makes those sections associated with data only, i.e., scrambler, descrambler, clock recovery section. Also functional three PLLs, audio receive path (Pins 28), transmit audio path (Pins 20), Battery circuit (but Carrier Detect mode). this mode, MC33410 will provide transmit data clock from crystal, conjunction with internal 6-bit counter (bits 4/23-18) block associated with that counter. transmit data clock available used synchronize external data source. data input passes through scrambler, outputs demodulated data from receiver input applied data slicer, clock recovery block. recovered clock output data passes through descrambler, output Figure diagram data paths through MC33410. procedure entering Data Modem mode Table
Figure Data Modem Mode Configuration
Data Input
Scrambler
Crystal Data Slicer Data Input Clock Recovery
Prog. 6-bit Counter
MC33410
Descrambler
MOTOROLA RF/IF DEVICE DATA
Table Entering Data Modem Mode
Function Bits Value Desired Desired Clock desired frequency Fcrystal/(16 Counter). Scrambler Descrambler setting (Bit Bypass Data Detect. Data Detect Output. Test Mode bits connect Encode Clock Status (Pin 13). Data Modem Mode (MP2 scrambler Input). Write Register shown Figure configure 4/23 7/10 7/17 5/20
above sequence critical, except that last steps must setting 5/20, writing register Writing register shown Figure
Data Clock Data Recovered Clock
MC33410
Figure Entering/Exiting Data Modem Mode
Clock Data
Address 1011 Sets Data Output Recovered Clock Output Sets Data Input
Enable
After address clocked Enable falling edge will cause (Data) switch output, providing recovered clock. microprocessor's data must changed input prior this falling edge. This sequence effective only 5/20 During time that recovered clock available microprocessor port unavailable control functions. exit Data Modem mode, Enable line taken high (the clock stable during this active high pulse). falling edge will input, allowing normal microprocessor port. next step 5/20 Other register bits then needed. prevent inadvertent incorrect operation microprocessor port, 5/20 must always when Data Modem mode use. Power Supply/Power Saving Modes power supply voltage, applied pins, range from pins must within ±0.5 each other, each must bypassed. recommended ground plane used, leads MC33410 short direct possible. supply ground pins distributed follows: Pins internally connected together, provide power audio amplifiers, filters, CVSD encoder decoder, frequency (CVSD rate) logic circuits. Pins ground pins these sections. provides power section. ground pin. provides power section, interface. ground pin. provides power section. Pins ground pins. conserve power, various sections individually disabled, using bits 5/10-0 (setting disables section).
Reference Oscillator Disable (bit 5/0) reference oscillator Pins disabled, thereby denying clock three PLLs, CVSD Encoder, switched capacitor filters. Disable (bit 5/1) 13-bit 7-bit counters, input buffer, phase detector, modulus control blocks disabled. charge pump output will Hi-Z state. Disable (bit 5/2) 13-bit 7-bit counters, input buffer, phase detector, modulus control blocks disabled. charge pump output will Hi-Z state. Disable (bit 5/3) VCO, 14-bit counter, output buffer, phase detector disabled. charge pump output will Hi-Z state. Data Path Disable (bit 5/4) data slicer, clock recovery block, descrambler, data detect register, status output circuit disabled. state status line (Pin 5/22) will change upon disabling this section. CVSD Decoder Disable (bit 5/5) CVSD Decoder 1010 Generator disabled. Audio Path Disable (bit 5/6) anti-aliasing filter, pass filter, variable gain stage disabled. Power Amplifier Disable (bit 5/7) power amplifiers disabled. Their outputs will Hi-Z state. Audio Path Disable (bit 5/8) Disables microphone amplifier, pass filter, smoothing filter. CVSD Encoder Disable (bit 5/9) CVSD Encoder, Idle Channel detect circuit, 1010 Generator, Data register, scrambler disabled. Battery/Carrier Detect Disable (bit 5/10) LB/CD circuit disabled. output, 5/23 will logic high. Idle Channel Detect Disable (bit 5/18) Powers down Idle Channel Detect circuit. Note: 12-bit reference counter disabled three PLLs disabled (bits 5/1-3
MOTOROLA RF/IF DEVICE DATA
Table Control Listing Register Number)
Register Power Default 1000000 10.0 Function (when appropriate) bits total) Sets 7-bit counter PLL. Sets 13-bit counter PLL. Sets phase detector charge pump output current. ±100 ±400 Sets CVSD Decoder minimum step size Table Sets 7-bit counter PLL. Sets 13-bit counter PLL. Sets phase detector charge pump output current. ±100 ±400 Sets CVSD Encoder minimum step size Table Sets 14-bit counter Sets phase detector charge pump output current. ±100 ±400 CVSD encoder/decoder selected clock rate. (Table Adjusts reference voltage (1.5 improve battery detection accuracy. Total adjustment range ±9%. Selects threshold Battery Detection Carrier Signal Detection. Table Sets 12-bit counter Reference Clock. Sets 6-bit counter Switched Capacitor Filter clock. Sets 6-bit counter CVSD Encoder clock rate. Power down Reference Oscillator Power down PLL. Power down PLL. Power down PLL. Power down Data Path. Includes Data Slicer, Clock Recovery, Descrambler, Data Detect, Status circuits. Power down CVSD Decoder. Power down Audio path (Pin 30). Includes AALPF, LPF, Gain Adjust circuits. Power down Power Amplifiers (Pins Power down Audio Path (Pin 22). Includes micro-phone amplifier, LPF, Smoothing circuits. Power down CVSD Encoder, Idle Channel Detector, 1010 Generator, Data Register, Scrambler circuits. Power down Battery/Carrier Detect Circuit. Sets 4-bit counter response delay idle channel detect circuit. Sets idle channel detect threshold level. Table Power down Idle Channel Detect Circuit. Inverts Data Slicer output. Sets Data Modem mode operation. Indicates idle channel condition been detected (Output). This output unaffected 7/2. Status Output (same read from this bit. output Battery/Carrier Detect Circuit read from this bit. bits total) bits total) bits total) bits total) 1000000 10.0 10.0 0111 $800 100000 100000 0111
MC33410
MOTOROLA RF/IF DEVICE DATA
Table Control Listing Register Number) (continued)
Power Default 01111 00100 $000000 $000000 $000000 Register bits total) Function (when appropriate) bits total) Mutes power amplifiers (Pins 29). Mutes receive speech processing path (Pin 30). Mutes transmit speech processing path (Pin 22). Selects 1010 Generator CVSD decoder. Selects 1010 Generator scrambler. Sets Carrier Detect Mode Battery mode. Provides steps, each (28.5 range), gain adjust receive speech audio path (Pins 30). Table Provides steps each, remote gain adjust transmit speech audio path (Pins 20). Bypass Clock Recovery Block (Data slicer output goes directly descrambler). Bypass scrambler descrambler. Disables automatic idle channel detect CVSD encoder. 5/21 still active. Bypass Data Detect block (Descrambler output goes directly CVSD Decoder). Determines function (MP1). Table Determines function (MP2). Table Selects programmable taps scrambler descrambler. Table Sets code word size sent Data Register bits. this code word size bits. Sets data word size sent Data Register bits. this data word size bits. Sets output level from ground VCC. this output level ±100 Disables CVSD charge compensation circuit. Test modes production testing only. Selects value internal capacitor between Pins fine tune tank circuit. Table Sets polarity phase detector charge pump output inverting pass filter/VCO combination. Sets polarity phase detector charge pump output inverting pass filter/VCO combination. Sets polarity phase detector charge pump output inverting pass filter/VCO combination. Code word Data Register entered into this register. Data word Data Register entered into this register. data word received into Data Register read port from this register.
MC33410
MOTOROLA RF/IF DEVICE DATA
Table Control Listing Function) Controls
Register Power Default 1000000 10.0 Function (when appropriate) Sets 7-bit counter PLL. Sets 13-bit counter PLL. Sets 7-bit counter PLL. 1000000 10.0 10.0 $800 Sets 13-bit counter PLL. Sets 14-bit counter Sets 12-bit counter Reference Clock. Sets output level from ground VCC. this output level ±100
MC33410
Phase Detectors
Register Power Default Function (when appropriate) Sets phase detector charge pump output current. ±100 ±400 Sets phase detector charge pump output current. ±100 ±400 Sets phase detector charge pump output current. ±100 ±400 Selects value internal capacitor between Pins fine tune tank circuit. Table Sets polarity phase detector charge pump output inverting pass filter/VCO combination. Sets polarity phase detector charge pump output inverting pass filter/VCO combination. Sets polarity phase detector charge pump output inverting pass filter/VCO combination.
CVSD Controls
Register Power Default Function (when appropriate) Sets CVSD Decoder minimum step size Table Sets CVSD Encoder minimum step size Table CVSD encoder/decoder selected clock rate. (Table Sets 6-bit counter CVSD Encoder clock rate. Selects 1010 Generator CVSD decoder. Selects 1010 Generator scrambler. Disables CVSD charge compensation circuit, which affects idle channel performance. 100000
Idle Channel Detector
Register Power Default 0111 Function (when appropriate) Sets 4-bit idle channel counter response delay idle channel detect circuit. Sets idle channel detect threshold level. Table Indicates idle channel condition been detected (Output). This output unaffected 7/2. Disables automatic idle channel detect CVSD encoder. 5/21 still active.
MOTOROLA RF/IF DEVICE DATA
Table Control Listing Function) (continued) Data Transmission/Reception
Register Power Default Function (when appropriate) Inverts Data Slicer output. Sets Data Modem mode. $000000 $000000 $000000 Status Output (same read from this bit. logic indicates Data Detect register detected code word. Bypass Clock Recovery Block (Data slicer output goes directly descrambler). Bypass Data Detect block (Descrambler output goes directly CVSD Decoder). Sets code word size sent Data Register bits. this code word size bits. Sets data word size sent Data Register bits. this data word size bits. Code word Data Register entered into this register. Data word Data Register entered into this register. data word received into Data Register read port from this register.
MC33410
Scrambler/Descrambler
Register Power Default Function (when appropriate) Bypass scrambler descrambler. Selects programmable taps scrambler descrambler. Table
Multi Purpose Control
Register
Power Default
Function (when appropriate)
Determines function (MP1). Table Determines function (MP2). Table
Audio Paths
Register
Power Default 100000 01111 00100
Function (when appropriate)
Sets 6-bit counter Switched Capacitor Filter clock. Mutes power amplifiers (Pins 29).
Mutes receive speech processing path (Pin 30).
Mutes transmit speech processing path (Pin 22). Provides steps, each (28.5 range), gain adjust receive speech audio path (Pins 30). Table Provides steps each, gain adjust transmit speech audio path (Pins 20).
Battery/Carrier Detection
Register Power Default 0111 Function (when appropriate) Adjusts reference voltage (1.5 improve battery detection accuracy. Total adjustment range ±9%. Selects threshold Battery Detection Carrier Signal Detection. Table output Battery/Carrier Detect Circuit read from this bit. Sets Carrier Detect Mode Battery Mode
MOTOROLA RF/IF DEVICE DATA
Table Control Listing Function) (continued) Power Down Control
Register Power Default Function (when appropriate) Power down Reference Oscillator Power down PLL. Power down PLL. Power down PLL. Power down Data Path. Includes Data Slicer, Clock Recovery, Descrambler, Data Detect, Status circuits. Power down CVSD Decoder. Power down Audio path (Pin 30). Includes AALPF, LPF, Gain Adjust circuits. Power down Power Amplifiers (Pins Power down Audio Path (Pin 22). Includes micro-phone amplifier, LPF, Smoothing circuits. Power down CVSD Encoder, Idle Channel Detector, 1010 Generator, Data Register, Scrambler circuits. Power down Battery/Carrier Detect Circuit. Power down Idle Channel Detection Circuit.
MC33410
MOTOROLA RF/IF DEVICE DATA
Table Register
Counter Divide Value (Bits Counter Divide Value (Bits Adjust Reference Voltage CVSD selected Clock Rate Curr. Sel. Counter Divide Value (Bits PhDet. Curr. Sel. PhDet. Curr. Sel. CVSD Decoder Minimum Step Size CVSD Encoder Minimum Step Size Sets Battery/Carrier Detect Threshold Encode Clock Counter Divide Value LB/CD Det. Sets Idle Channel Threshold Level Status Output Idle Chan. Output Data Modem Mode Invert Data Slicer Idle Channel Disable Switched Capacitor Filter Counter Divide Value Idle Channel Counter Delay Value (Bits Remote Gain Adjust (Bits Phase Detector Polarity Detector Polarity Capacitor Select Code Word Data Register (Bits Data Word Data Register (Bits Data Word Output from Data Register (Bits Phase Detector Polarity Production Test Modes Data Modem Mode Idle Charge Disable FTxMC/ FRxMC Level Data Word Size (16/24 bit) Counter Divide Value (Bits Counter Divide Value (Bits Counter Divide Value (Bits Reference Counter Divide Value Idle Channel Ctr. Value LB/CD Detect Disable CVSD Encoder Disable Audio Path Disable Remote Gain Adj. Code Word Size (16/24 bit) Scrambler/Descrambler Selection Power Amplifier Disable Audio Path Disable CVSD Decoder Disable Mode Mode (See Table Data Path Disable 1010 Generator Mode (See Table Code Word Data Register (Bits Data Word Data Register (Bits Data Word Output from Data Register (Bits Disable 1010 Generator Bypass Data Detect Disable Mute Audio Disable Idle Chnl. Detection Disable Mute Audio Bypass Scrambler/ Descrambler Ref. Osc. Disable Mute Pwr. Amps Bypass Clock Recovery Counter Divide Value Counter Divide Value Audio Path Gain Adjust (28.5 range)
Register Address
Register Number
0001
0010
0011
0100
0101
0110
0111
1000
1001
MC33410
1010
Register Address
Register Number
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
MOTOROLA RF/IF DEVICE DATA
Note: Shaded areas represent output bits read out.
MC33410
OUTLINE DIMENSIONS
SUFFIX PLASTIC PACKAGE CASE (LQFP-48) ISSUE 0.200 (0.008)
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DATUM PLANE -AB- LOCATED BOTTOM LEAD COINCIDENT WITH LEAD WHERE LEAD EXITS PLASTIC BODY BOTTOM PARTING LINE. DATUMS -T-, -U-, DETERMINED DATUM PLANE -AB-. DIMENSIONS DETERMINED SEATING PLANE -AC-. DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.250 (0.010) SIDE. DIMENSIONS INCLUDE MOLD MISMATCH DETERMINED DATUM PLANE -AB-. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL CAUSE DIMENSION EXCEED 0.350 (0.014). MINIMUM SOLDER PLATE THICKNESS SHALL 0.0076 (0.0003). EXACT SHAPE EACH CORNER OPTIONAL. MILLIMETERS 7.000 3.500 7.000 3.500 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BASIC 0.050 0.150 0.090 0.200 0.500 0.700 _REF 0.090 0.160 0.250 BASIC 0.150 0.250 9.000 4.500 9.000 4.500 0.200 1.000 INCHES 0.276 0.138 0.276 0.138 0.055 0.063 0.007 0.011 0.053 0.057 0.007 0.009 0.020 BASIC 0.002 0.006 0.004 0.008 0.020 0.028 _REF 0.004 0.006 0.010 BASIC 0.006 0.010 0.354 0.177 0.354 0.177 0.008 0.039
DETAIL
-T-, -U-,
DETAIL 0.200 (0.008)
-AB- -AC-
BASE METAL
0.080 (0.003)
BOTTOM
GAUGE PLANE
0.080 (0.003)
SECTION AE-AE
MOTOROLA RF/IF DEVICE DATA
0.250 (0.010)
DETAIL
MC33410
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MC33410/D MOTOROLA RF/IF DEVICE DATA

MC33410 Dual CVSD/PLL Cordless Phone System MC33410 Dual CVS

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