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Programmable Delay Chip
MC10E/100E195 programmable delay chip (PDC) designed primarily clock de-skewing timing adjustment. provides variable delay differential input transition. delay section consists chain gates organized shown logic symbol. first delay elements feature gates that have been modified have delays 1.25 times basic gate delay approximately These elements provide E195 with digitally-selectable resolution approximately required device delay selected seven address inputs D[0:6], which latched chip high signal latch enable (LEN) control. Because delay programmability E195 achieved purely differential gate delays device will operate frequencies >1.0 while maintaining over output swing. E195 thus offers very fine resolution, very high frequencies, that selectable entirely from digital input allowing very accurate system clock timing. eighth latched input, provided cascading multiple PDC's increased programmable range. cascade logic allows full control multiple PDC's, expense only single added line data each additional PDC, without need external gating.
MC10E195 MC100E195
PROGRAMMABLE DELAY CHIP
SUFFIX PLASTIC PACKAGE CASE 776-02
2.0ns Worst Case Delay Range 20ps/Delay Step Resolution >1.0GHz Bandwidth Chip Cascade Circuitry Extended 100E Range -4.2 -5.46V Input Pulldown Resistors
NAMES
IN/IN D[0:7] CASCADE Signal Input Input Enable Select Inputs Signal Output Latch Enable Delay Delay Cascade Signal Function
Pinout: 28-Lead PLCC (Top View)
VCCO VCCO
CASCADE
CASCADE
CASCADE CASCADE
LOGIC DIAGRAM SIMPLIFIED
1.25
GATES
GATES
GATES
CASCADE
LATCH LATCH
DELAYS LONGER THAN STANDARD (STANDARD
04/99
Motorola, Inc. 1999
MC10E195 MC100E195
CHARACTERISTICS (VEE VEE(min) VEE(max); VCCO GND)
Symbol Characteristic Input HIGH Current Power Supply Current 100E 25°C 85°C Unit Condition
CHARACTERISTICS (VEE VEE(min) VEE(max); VCCO GND)
Symbol tPLH tPHL Characteristic Propagation Delay CASCADE Programmable Range (max) (min) Step Delay High High High High High High High Linearity Duty Cycle Skew tPHL-tPLH Setup Time Hold Time Release Time Jitter Output Rise/Fall Time 20-80% 20-80% (CASCADE) <5.0 1210 3200 1250 2000 1360 3570 1450 2175 1088 <5.0 1510 3970 1650 1240 3270 1275 2050 25°C 1390 3630 1475 2240 17.5 1120 <5.0 1540 4030 1675 1440 3885 1350 2375 85°C 1590 4270 1650 2580 1344 1765 4710 1950 Unit Notes
tRANGE
1000
1190
1030
1220
1240
1450
tSKEW
tjit
Duty cycle skew guaranteed only differential operation measured from cross point input cross point output. This setup time defines amount time prior input signal delay device must set. This setup time minimum time that must asserted prior next transition IN/IN prevent output response greater than that IN/IN transition. This hold time minimum time that must remain asserted after negative going positive going prevent output response greater than that IN/IN transition. This release time minimum time that must deasserted prior next IN/IN transition ensure output response that meets specified propagation delay transition times. Specification limits represent amount delay added with assertion each individual delay control pin. various combinations asserted delay control inputs will typically realize resolution steps across specified programmable range. linearity specification guarantees which delay control input programmable steps will monotonic (i.e. increasing delay steps increasing binary counts control inputs Dn). Typically device will monotonic input, however under worst case conditions process variation, delays could decrease slightly with increasing binary counts when input LSB. With input device guaranteed monotonic over specified environmental conditions process variation. jitter device less than what measured without resorting very tedious specialized measurement techniques.
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MC10E195 MC100E195
ADDRESS (A0-A6)
VCCO CASCADE CASCADE VCCO OUTPUT
Reset Reset
INPUT CASCADE CASCADE
E195 Chip
VCCO VCCO
E195 Chip
Figure Cascading Interconnect Architecture
Cascading Multiple E195's increase programmable range E195 internal cascade circuitry been included. This circuitry allows cascading multiple E195's without need external gating. Furthermore this capability requires only more address line added E195. Obviously cascading multiple PDC's will result larger programmable range however this increase expense longer minimum delay. Figure illustrates interconnect scheme cascading E195's. seen, this scheme easily expanded larger E195 chains. input E195 cascade control pin. With interconnect scheme Figure when asserted signals need larger programmable range than achievable with single device. expansion latch section block diagram pictured below. this diagram will simplify explanation cascade circuitry works. When chip above cascade output will also while cascade output will logical high. this condition chip will asserted thus latches chip will reset device will minimum delay. Since RESET inputs latches overriding changes A0-A6 address will affect operation chip
SELECT MULTIPLEXERS
Chip other hand will have both de-asserted that delay will controlled entirely address A0-A6. delay needed greater than achieved with 31.75 gate delays (1111111 A0-A6 address bus) will asserted signal need cascade delay next E195 device. When asserted chip will de-asserted delay will controlled A0-A6 address bus. Chip other hand will have asserted resulting device delay independent A0-A6 address bus. When chip asserted latches will reset while rest latches will set. addition, maintain monotonicity additional gate delay selected cascade circuitry. result when chip asserted delay increases from 31.75 gates gates. gate delay maximum delay setting E195. expand this cascading scheme more devices simply needs connect input CASCADE outputs current most significant E195 most significant E195 same manner pictured Figure only addition logic increase line address cascade control second PDC.
Reset Reset
Reset Reset
Reset Reset
CASCADE Reset Reset CASCADE
Reset Reset
Reset Reset
Reset Reset
Figure Expansion Latch Section E195 Block Diagram
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MC10E195 MC100E195
OUTLINE DIMENSIONS
SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE
0.007 (0.180)
0.007 (0.180)
-L-M-
VIEW 0.010 (0.250)
0.007 (0.180) 0.007 (0.180)
0.007 (0.180)
0.010 (0.250)
0.004 (0.100) -TSEATING PLANE
VIEW 0.007 (0.180)
VIEW
NOTES: DATUMS -L-, -M-, DETERMINED WHERE LEAD SHOULDER EXITS PLASTIC BODY MOLD PARTING LINE. TRUE POSITION MEASURED DATUM -T-, SEATING PLANE. INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH 0.010 (0.250) SIDE. DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. PACKAGE SMALLER THAN PACKAGE BOTTOM 0.012 (0.300). DIMENSIONS DETERMINED OUTERMOST EXTREMES PLASTIC BODY EXCLUSIVE MOLD FLASH, BURRS, GATE BURRS INTERLEAD FLASH, INCLUDING MISMATCH BETWEEN BOTTOM PLASTIC BODY. DIMENSION DOES INCLUDE DAMBAR PROTRUSION INTRUSION. DAMBAR PROTRUSION(S) SHALL CAUSE DIMENSION GREATER THAN 0.037 (0.940). DAMBAR INTRUSION(S) SHALL CAUSE DIMENSION SMALLER THAN 0.025 (0.635).
INCHES 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 0.026 0.032 0.020 0.025 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 0.020 0.410 0.430 0.040
MILLIMETERS 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 0.66 0.81 0.51 0.64 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 0.50 10.42 10.92 1.02
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MC10E195 MC100E195
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. Mfax trademark Motorola, Inc. reach EUROPE Locations Listed: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217. 1-303-675-2140 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, Motorola Back System Canada ONLY 1-800-774-1848 King Street, Industrial Estate, N.T., Hong Kong. http://sps.motorola.com/mfax/ 852-26629298 HOME PAGE: http://motorola.com/sps/ JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488
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MC10E195/D

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