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SH7622

Hardware Manual

Hitachi SuperH RISC engine
SH7622
Hardware Manual
ADE-602-212A Rev. 2.0 9 / 19 / 01 Hitachi, Ltd.
Cautions
Preface
Manual Title SH7622 Hardware Manual SH-1, SH-2, SH-DSP Programming Manual ADE No. This manual ADE-602-085
Users manuals for development tools:
Application Note:
Manual Title C / C++ Complier ADE No. ADE-502-046
Contents
Section 1 Overview and Pin Functions .....................................
1.1 1.2 1.3 1 SH7622 Features ........................................................ 1 Block Diagram.......................................................... 6 Pin Description .......................................................... 7 1.3.1 Pin Arrangement .................................................. 7 1.3.2 Pin Functions..................................................... 10
Section 2 CPU ............................................................ 19
2.1 Register Configuration .................................................... 2.1.1 General Registers ................................................. 2.1.2 Control Registers.................................................. Features of CPU Instructions............................................... 2.2.1 Fetching and Decoding............................................. 2.2.2 Integer Unit ...................................................... 2.2.3 System Registers .................................................. 2.2.4 DSP Registers.................................................... Data Format............................................................ 2.3.1 Data Format in Registers (Non-DSP Type) ............................. 2.3.2 DSP-Type Data Format ............................................. 2.3.3 Data Format in Memory............................................ 19 19 21 24 24 24 25 25 30 30 30 32
Section 3 DSP Operation .................................................. 33
3.1 Data Operations of DSP Unit ............................................... 3.1.1 ALU Fixed-Point Operations ........................................ 3.1.2 ALU Integer Operations............................................ 3.1.3 ALU Logical Operations ............................................ 3.1.4 Fixed-Point Multiply Operation...................................... 3.1.5 Shift Operations .................................................. 3.1.6 Most Significant Bit Detection Operation .............................. 3.1.7 Rounding Operation ............................................... 3.1.8 Overflow Protection ............................................... 3.1.9 Data Transfer Operation............................................ 3.1.10 Local Data Move Operation......................................... 3.1.11 Operand Conflict .................................................. DSP Addressing......................................................... 3.2.1 DSP Loop Control................................................. 3.2.2 DSP Data Addressing.............................................. 33 33 38 40 41 43 47 50 52 52 57 58 59 59 66
Section 4 Instruction Set ................................................... 75
4.1 4.2 4.3 Basic Concept of SH7622 Instruction Set..................................... 75 SH-1, SH-2 Compatible Instruction Set ....................................... 75 4.2.1 Instruction Set by Classification ...................................... 75 Instructions for DSP Extension ............................................. 88 4.3.1 Introduction ...................................................... 88 4.3.2 Additional System Control Instruction for CPU .......................... 94 4.3.3 Single- and Double-Data Transfer for DSP Instructions ................... 96 4.3.4 Parallel Operation for the DSP Unit................................... 100
Section 5 Exception Handling .............................................. 113
5.1 5.2 5.3 Overview .............................................................. 113 5.1.1 Types of Exception Handling and Priority Order ......................... 113 Exception Handling Operations ............................................. 115 5.2.1 Exception Vector Table ............................................ 116 Resets................................................................. 118 5.3.1 Types of Resets ................................................... 118 5.3.2 Power-On Reset .................................................. 118 5.3.3 Manual Reset..................................................... 119 Address Errors.......................................................... 119 5.4.1 Sources of Address Errors........................................... 119 5.4.2 Address Error Exception Handling .................................... 119 Interrupts .............................................................. 120 5.5.1 Interrupt Sources .................................................. 120 5.5.2 Interrupt Priority Levels............................................ 121 5.5.3 Interrupt Exception Handling........................................ 121 Exceptions Triggered by Instructions ........................................ 122 5.6.1 Instruction-Triggered Exception Types ................................ 122 5.6.2 Trap Instructions .................................................. 122 5.6.3 Illegal Slot Instructions ............................................. 122 5.6.4 General Illegal Instructions .......................................... 123 When Exception Sources are Not Accepted ................................... 124 5.7.1 Immediately after a Delayed Branch Instruction ......................... 124 5.7.2 Immediately after an Interrupt-Disabled Instruction....................... 124 5.7.3 Instructions in Repeat Loops......................................... 125 Stack Status after Exception Handling ........................................ 126 Usage Notes............................................................ 126 5.9.1 Value of Stack Pointer (SP) ......................................... 126 5.9.2 Value of Vector Base Register (VBR) ................................. 126 5.9.3 Manual Reset during Register Access.................................. 126
Section 6 Cache ........................................................... 127
Overview .............................................................. 127
6.1.1 Features ......................................................... 127 6.1.2 Cache Structure ................................................... 128 6.1.3 Register Configuration ............................................. 129 Register Description ...................................................... 129 6.2.1 Cache Control Register (CCR)....................................... 129 Cache Operation ......................................................... 130 6.3.1 Searching the Cache............................................... 130 6.3.2 Read Access ..................................................... 132 6.3.3 Write Access ..................................................... 132 6.3.4 Write-Back Buffer................................................. 132 6.3.5 Coherency of Cache and External Memory ............................. 133 Memory-Mapped Cache................................................... 133 6.4.1 Address Array .................................................... 133 6.4.2 Data Array ....................................................... 134 Usage Examples ......................................................... 136 6.5.1 Invalidating Specific Entries ......................................... 136 6.5.2 Reading the Data of a Specific Entry.................................. 136 6.5.3 Usage Notes ..................................................... 136
Section 7 X / Y Memory .................................................... 139
7.1 7.2 7.3 7.4 7.5 Overview .............................................................. 139 7.1.1 Features ......................................................... 139 X- / Y-Memory Access from the CPU ......................................... 140 X- / Y-Memory Access from the DSP ......................................... 141 X- / Y-Memory Access from the DMAC....................................... 141 Usage Note ............................................................. 141
Section 8 Interrupt Controller (INTC) ...................................... 143
8.1 Overview .............................................................. 143 8.1.1 Features ......................................................... 143 8.1.2 Pin Configuration ................................................. 144 8.1.3 Register Configuration ............................................. 144 Interrupt Sources ........................................................ 145 8.2.1 NMI Interrupt .................................................... 145 8.2.2 User Break Interrupt............................................... 145 8.2.3 H-UDI Interrupt .................................................. 145 8.2.4 IRQ Interrupts .................................................... 145 8.2.5 On-Chip Peripheral Module Interrupts ................................. 146 8.2.6 Interrupt Exception Vectors and Priority Order.......................... 147 INTC Registers.......................................................... 149 8.3.1 Interrupt Priority Registers A to H (IPRA-IPRH)........................ 149 8.3.2 Interrupt Control Register 0 (ICR0)................................... 150 8.3.3 Interrupt Control Register 1 (ICR1)................................... 151
8.3.4 Interrupt Request Register (IRR) ..................................... 152 Interrupt Operation ....................................................... 153 8.4.1 Interrupt Sequence ................................................ 153
Section 9 User Break Controller ........................................... 155
9.1 Overview .............................................................. 155 9.1.1 Features ......................................................... 155 9.1.2 Block Diagram ................................................... 156 9.1.3 Register Configuration ............................................. 157 Register Descriptions..................................................... 158 9.2.1 Break Address Register A (BARA) ................................... 158 9.2.2 Break Address Mask Register A (BAMRA)............................. 159 9.2.3 Break Bus Cycle Register A (BBRA) .................................. 160 9.2.4 Break Address Register B (BARB) ................................... 162 9.2.5 Break Address Mask Register B (BAMRB) ............................. 163 9.2.6 Break Data Register B (BDRB) ...................................... 164 9.2.7 Break Data Mask Register B (BDMRB)................................ 165 9.2.8 Break Bus Cycle Register B (BBRB) .................................. 166 9.2.9 Break Control Register (BRCR) ...................................... 168 9.2.10 Execution Times Break Register (BETR) ............................... 171 9.2.11 Branch Source Register (BRSR) ...................................... 172 9.2.12 Branch Destination Register (BRDR) .................................. 173 Operation Description .................................................... 175 9.3.1 Flow of the User Break Operation .................................... 175 9.3.2 Break on Instruction Fetch Cycle..................................... 175 9.3.3 Break by Data Access Cycle ......................................... 176 9.3.4 Break on X- / Y-Memory Bus Cycle ................................... 177 9.3.5 Sequential Break .................................................. 177 9.3.6 Value of Saved Program Counter..................................... 177 9.3.7 PC Trace........................................................ 178 9.3.8 Usage Examples .................................................. 180 9.3.9 Notes........................................................... 185
Section 10 Power-Down Modes ............................................ 187
10.1 Overview .............................................................. 187 10.1.1 Power-Down Modes............................................... 187 10.1.2 Pin Configuration ................................................. 188 10.1.3 Register Configuration ............................................. 188 10.2 Register Description ...................................................... 188 10.2.1 Standby Control Register (STBCR)................................... 188 10.2.2 Standby Control Register 2 (STBCR2)................................. 189 10.2.3 Standby Control Register 3 (STBCR3)................................. 190 10.3 Standby Mode .......................................................... 192
10.3.1 Transition to Standby Mode......................................... 192 10.3.2 Canceling Standby Mode ........................................... 193 10.3.3 Usage Note ...................................................... 193 10.4 Module Standby Function ................................................. 195 10.4.1 Transition to Module Standby Function................................ 195 10.4.2 Clearing the Module Standby Function ................................ 195 10.5 Timing of STATUS Pin Changes............................................ 196 10.5.1 Timing for Resets................................................. 196 10.5.2 Timing for Canceling Standbys ...................................... 197
Section 11 On-Chip Oscillator Circuit ...................................... 199
11.1 Overview .............................................................. 199 11.1.1 Features ......................................................... 199 11.2 Overview of the CPG ..................................................... 200 11.2.1 CPG Block Diagram............................................... 200 11.2.2 CPG Pin Configuration ............................................. 202 11.2.3 CPG Register Configuration ......................................... 202 11.3 Clock Operating Modes................................................... 203 11.4 Register Descriptions..................................................... 207 11.4.1 Frequency Control Register (FRQCR)................................. 207 11.5 Changing the Frequency................................................... 209 11.5.1 Changing the Multiplication Rate ..................................... 209 11.5.2 Changing the Division Ratio ......................................... 209 11.6 Overview of the WDT.................................................... 210 11.6.1 Block Diagram of the WDT......................................... 210 11.6.2 Register Configurations ............................................ 210 11.7 WDT Registers .......................................................... 211 11.7.1 Watchdog Timer Counter (WTCNT).................................. 211 11.7.2 Watchdog Timer Control / Status Register (WTCSR)...................... 211 11.7.3 Notes on Register Access........................................... 213 11.8 Using the WDT ......................................................... 214 11.8.1 Canceling Standbys ................................................ 214 11.8.2 Changing the Frequency............................................ 214 11.8.3 Using Watchdog Timer Mode........................................ 215 11.8.4 Using Interval Timer Mode.......................................... 215 11.9 Notes on Board Design ................................................... 216 11.10 Usage Notes............................................................ 217
Section 12 Extend Clock Pulse Generator for USB (EXCPG) ............... 219
12.1 Overview of EXCPG..................................................... 219 12.1.1 EXCPG Features .................................................. 219 12.1.2 EXCPG Configuration ............................................. 219 12.1.3 Register Configuration ............................................. 220
12.2 Register Descriptions..................................................... 220 12.2.1 USB Clock Control Register (USBCLKCR) ............................ 220 12.3 Usage Notes............................................................ 221
Section 13 Bus State Controller (BSC) ..................................... 223
13.1 Overview .............................................................. 223 13.1.1 Features ......................................................... 223 13.1.2 Block Diagram ................................................... 225 13.1.3 Pin Configuration ................................................. 226 13.1.4 Register Configuration ............................................. 227 13.1.5 Area Overview ................................................... 228 13.2 BSC Registers .......................................................... 231 13.2.1 Bus Control Register 1 (BCR1) ...................................... 231 13.2.2 Bus Control Register 2 (BCR2) ...................................... 233 13.2.3 Wait Control Register 1 (WCR1)..................................... 234 13.2.4 Wait Control Register 2 (WCR2)..................................... 235 13.2.5 Individual Memory Control Register (MCR)............................ 239 13.2.6 Synchronous DRAM Mode Register (SDMR) ........................... 243 13.2.7 Refresh Timer Control / Status Register (RTCSR)......................... 244 13.2.8 Refresh Timer Counter (RTCNT) ..................................... 246 13.2.9 Refresh Time Constant Register (RTCOR) ............................. 247 13.2.10 Refresh Count Register (RFCR) ...................................... 247 13.2.11 Cautions on Accessing Refresh Control Related Registers ................. 248 13.3 BSC Operation.......................................................... 249 13.3.1 Access Size and Data Alignment ..................................... 249 13.3.2 Description of Areas............................................... 252 13.3.3 Basic Interface.................................................... 254 13.3.4 Synchronous DRAM Interface....................................... 262 13.3.5 Burst ROM Interface ............................................... 291 13.3.6 Waits between Access Cycles ........................................ 294 13.3.7 Bus Arbitration................................................... 295
Section 14 Direct Memory Access Controller (DMAC) ..................... 297
14.1 Overview .............................................................. 297 14.1.1 Features ......................................................... 297 14.1.2 Block Diagram ................................................... 299 14.1.3 Pin Configuration ................................................. 300 14.1.4 Register Configuration ............................................. 301 14.2 Register Descriptions..................................................... 302 14.2.1 DMA Source Address Registers 0-3 (SAR0-SAR3) ...................... 302 14.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3) ................. 303 14.2.3 DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3) ............. 304 14.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3).................. 305
14.2.5 DMA Channel Expansion Request Registers 0 and 1 (CHCRA0, CHCRA1)... 311 14.2.6 DMA Operation Register (DMAOR).................................. 313 Operation .............................................................. 315 14.3.1 DMA Transfer Flow............................................... 315 14.3.2 DMA Transfer Requests............................................ 317 14.3.3 Channel Priority .................................................. 320 14.3.4 DMA Transfer Types .............................................. 323 14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing .............. 336 14.3.6 Source Address Reload Function ..................................... 345 14.3.7 DMA Transfer Ending Conditions.................................... 347 Compare Match Timer 0 (CMT0) ........................................... 349 14.4.1 Overview ........................................................ 349 14.4.2 Register Descriptions .............................................. 350 14.4.3 Operation ........................................................ 353 14.4.4 Compare Match ................................................... 354 Examples of Use......................................................... 356 14.5.1 Example of DMA Transfer between On-Chip SCIF0 and External Memory ... 356 14.5.2 Example of DMA Transfer between A / D Converter and External Memory (Address Reload on)............................................... 357 Cautions............................................................... 359
Section 15 Timer (TMU) .................................................. 361
15.1 Overview .............................................................. 361 15.1.1 Features ......................................................... 361 15.1.2 Block Diagram ................................................... 362 15.1.3 Pin Configuration................................................. 363 15.1.4 Register Configuration ............................................. 363 15.2 TMU Registers .......................................................... 364 15.2.1 Timer Start Register (TSTR)......................................... 364 15.2.2 Timer Control Register (TCR) ....................................... 365 15.2.3 Timer Constant Register (TCOR) ..................................... 368 15.2.4 Timer Counters (TCNT)............................................ 369 15.2.5 Input Capture Register (TCPR2)...................................... 370 15.3 TMU Operation ......................................................... 371 15.3.1 Overview ........................................................ 371 15.3.2 Basic Functions ................................................... 371 15.4 Interrupts .............................................................. 375 15.4.1 Status Flag Set Timing ............................................. 375 15.4.2 Status Flag Clear Timing ........................................... 376 15.4.3 Interrupt Sources and Priorities....................................... 376 15.5 Usage Notes............................................................ 377 15.5.1 Writing to Registers ............................................... 377 15.5.2 Reading Registers................................................. 377
Section 16 Serial Communication Interface with FIFO (SCIF0) .............. 379
16.1 Overview .............................................................. 379 16.1.1 Features ......................................................... 379 16.1.2 Block Diagram ................................................... 380 16.1.3 Pin Configuration ................................................. 381 16.1.4 Register Configuration ............................................. 381 16.2 Register Descriptions..................................................... 382 16.2.1 Receive Shift Register (SCRSR0)..................................... 382 16.2.2 Receive FIFO Data Register (SCFRDR0) .............................. 382 16.2.3 Transmit Shift Register (SCTSR0) .................................... 383 16.2.4 Transmit FIFO Data Register (SCFTDR0) .............................. 383 16.2.5 Serial Mode Register (SCSMR0)..................................... 384 16.2.6 Serial Control Register (SCSCR0).................................... 385 16.2.7 Serial Status Register (SCSSR0)...................................... 387 16.2.8 Bit Rate Register (SCBRR0)......................................... 389 16.2.9 FIFO Control Register (SCFCR0) .................................... 390 16.2.10 Receive FIFO Data Count Register (SCRFDR0)......................... 391 16.2.11 Transmit FIFO Data Count Register (SCTFDR0) ........................ 391 16.2.12 Line Status Register (SCLSR0) ...................................... 392 16.3 Operation .............................................................. 394 16.3.1 Overview ........................................................ 394 16.3.2 Serial Operation .................................................. 394 16.4 SCIF0 Interrupt Sources and the DMAC ...................................... 407 16.5 Timing of TDFST, RDFST, and TEND Bit Setting.............................. 408 16.6 Usage Notes............................................................ 408
Section 17 Serial Communication Interface with FIFO (SCIF1) .............. 411
17.1 Overview .............................................................. 411 17.1.1 Features ......................................................... 411 17.1.2 Block Diagram ................................................... 412 17.1.3 Pin Configuration ................................................. 413 17.1.4 Register Configuration ............................................. 413 17.2 Register Descriptions..................................................... 414 17.2.1 Receive Shift Register (SCRSR1)..................................... 414 17.2.2 Receive FIFO Data Register (SCFRDR1) .............................. 414 17.2.3 Transmit Shift Register (SCTSR1) .................................... 415 17.2.4 Transmit FIFO Data Register (SCFTDR1) .............................. 415 17.2.5 Serial Mode Register (SCSMR1)..................................... 416 17.2.6 Serial Control Register (SCSCR1).................................... 417 17.2.7 Serial Status Register (SCSSR1)...................................... 419 17.2.8 Bit Rate Register (SCBRR1)......................................... 421 17.2.9 FIFO Control Register (SCFCR1) .................................... 422 17.2.10 FIFO Data Count Register (SCFDR1) ................................. 423
17.2.11 Line Status Register (SCLSR1) ...................................... 424 17.3 Operation .............................................................. 426 17.3.1 Overview ........................................................ 426 17.3.2 Serial Operation .................................................. 426 17.4 SCIF1 Interrupt Sources and the DMAC ...................................... 438 17.5 Timing of TDFST, RDFST, and TEND Bit Setting ............................. 439 17.6 Usage Notes............................................................ 439
Section 18 Serial Communication Interface with FIFO (SCIF2) .............. 441
18.1 Overview .............................................................. 441 18.1.1 Features ......................................................... 441 18.1.2 Block Diagrams................................................... 443 18.1.3 Pin Configuration ................................................. 444 18.1.4 Register Configuration ............................................. 444 18.2 Register Descriptions..................................................... 445 18.2.1 Receive Shift Register (SCRSR2)..................................... 445 18.2.2 Receive FIFO Data Register (SCFRDR2) .............................. 445 18.2.3 Transmit Shift Register (SCTSR2) .................................... 446 18.2.4 Transmit FIFO Data Register (SCFTDR2) .............................. 446 18.2.5 Serial Mode Register (SCSMR2)..................................... 447 18.2.6 Serial Control Register (SCSCR2).................................... 449 18.2.7 Serial Status Register (SCSSR2)...................................... 451 18.2.8 Bit Rate Register (SCBRR2)......................................... 456 18.2.9 FIFO Control Register (SCFCR2) .................................... 464 18.2.10 FIFO Data Count Register (SCFDR2) ................................. 466 18.3 Operation .............................................................. 467 18.3.1 Overview ........................................................ 467 18.3.2 Asynchronous Mode ............................................... 467 18.3.3 Serial Operation in Asynchronous Mode............................... 469 18.3.4 Synchronous Mode................................................ 478 18.3.5 Serial Operation in Synchronous Mode ................................ 479 18.4 SCIF2 Interrupt Sources and the DMAC ...................................... 489 18.5 Usage Notes............................................................ 490
Section 19 USB Function Module .......................................... 495
19.1 19.2 19.3 19.4 19.5 Features ............................................................... 495 Block Diagram.......................................................... 496 Pin Configuration ........................................................ 496 Register Configuration .................................................... 497 Register Descriptions..................................................... 498 19.5.1 USBEP0i Data Register (USBEPDR0I) ................................ 498 19.5.2 USBEP0o Data Register (USBEPDR0O) ............................... 498 19.5.3 USBEP0s Data Register (USBEPDR0S) ............................... 498
19.5.4 USBEP1 Data Register (USBEPDR1)................................. 498 19.5.5 USBEP2 Data Register (USBEPDR2)................................. 499 19.5.6 USBEP3 Data Register (USBEPDR3)................................. 499 19.5.7 USB Interrupt Flag Register 0 (USBIFR0) .............................. 499 19.5.8 USB Interrupt Flag Register 1 (USBIFR1) .............................. 500 19.5.9 USB Trigger Register (USBTRG) .................................... 501 19.5.10 USBFIFO Clear Register (USBFCLR) ................................. 502 19.5.11 USBEP0o Receive Data Size Register (USBEPSZ0O) .................... 502 19.5.12 USB Data Status Register (USBDASTS) ............................... 503 19.5.13 USB Endpoint Stall Register (USBEPSTL)............................. 503 19.5.14 USB Interrupt Enable Register 0 (USBIER0)............................ 504 19.5.15 USB Interrupt Enable Register 1 (USBIER1)............................ 504 19.5.16 USBEP1 Receive Data Size Register (USBEPSZ1) ....................... 504 19.5.17 USB Interrupt Select Register 0 (USBISR0) ............................ 505 19.5.18 USB Interrupt Select Register 1 (USBISR1) ............................ 505 19.5.19 USBDMA Setting Register (USBDMAR).............................. 506 Operation .............................................................. 508 19.6.1 Cable Connection ................................................. 508 19.6.2 Cable Disconnection ............................................... 509 19.6.3 Control Transfer .................................................. 510 19.6.4 EP1 Bulk-Out Transfer (Dual FIFOs) .................................. 517 19.6.5 EP2 Bulk-In Transfer (Dual FIFOs)................................... 518 19.6.6 EP3 Interrupt-In Transfer........................................... 520 Processing of USB Standard Commands and Class / Vendor Commands ............. 521 19.7.1 Processing of Commands Transmitted by Control Transfer ................. 521 Stall Operations ......................................................... 522 19.8.1 Overview ........................................................ 522 19.8.2 Forcible Stall by Application ........................................ 522 19.8.3 Automatic Stall by USB Function Module .............................. 524 Example of USB External Circuitry.......................................... 526 Usage Notes............................................................ 528
Section 20 Compare Match Timer 1 (CMT1) ............................... 529
20.1 Overview .............................................................. 529 20.1.1 Features ......................................................... 529 20.1.2 Block Diagram ................................................... 530 20.1.3 Register Configuration ............................................. 530 20.2 Register Descriptions..................................................... 531 20.2.1 Compare Match Timer Start Register 1 (CMSTR1) ....................... 531 20.2.2 Compare Match Timer Control / Status Register 1 (CMCSR1) ............... 532 20.2.3 Compare Match Counter 1 (CMCNT1) ................................ 533 20.2.4 Compare Match Constant Register 1 (CMCOR1) ........................ 534 20.3 Operation .............................................................. 535
20.3.1 Interval Count Operation ........................................... 535 20.3.2 CMCNT Count Timing ............................................. 535 20.4 Compare Matches........................................................ 536 20.4.1 Timing of Compare Match Flag Setting ................................ 536 20.4.2 DMA Transfer Requests and Interrupt Requests ......................... 536 20.4.3 Timing of Compare Match Flag Clearing ............................... 536
Section 21 Pin Function Controller (PFC) .................................. 537
21.1 Overview .............................................................. 537 21.2 Register Configuration .................................................... 541 21.3 Register Descriptions..................................................... 542 21.3.1 Port A Control Register (PACR) ..................................... 542 21.3.2 Port B Control Register (PBCR) ...................................... 543 21.3.3 Port C Control Register (PCCR) ...................................... 544 21.3.4 Port D Control Register (PDCR) ..................................... 545 21.3.5 Port E Control Register (PECR)...................................... 547 21.3.6 Port F Control Register (PFCR)...................................... 548 21.3.7 Port G Control Register (PGCR) ..................................... 550 21.3.8 Port H Control Register (PHCR) ..................................... 551 21.3.9 Port J Control Register (PJCR) ....................................... 553 21.3.10 Port K Control Register (PKCR) ..................................... 554 21.3.11 Port L Control Register (PLCR)...................................... 555 21.3.12 SC Port Control Register (SCPCR) ................................... 557
Section 22 I / O Ports ....................................................... 561
22.1 Overview .............................................................. 561 22.2 Port A................................................................. 561 22.2.1 Register Description............................................... 561 22.2.2 Port A Data Register (PADR) ........................................ 562 22.3 Port B................................................................. 563 22.3.1 Register Description............................................... 563 22.3.2 Port B Data Register (PBDR)........................................ 564 22.4 Port C................................................................. 565 22.4.1 Register Description............................................... 565 22.4.2 Port C Data Register (PCDR)........................................ 565 22.5 Port D................................................................. 567 22.5.1 Register Description............................................... 567 22.5.2 Port D Data Register (PDDR) ........................................ 567 22.6 Port E................................................................. 569 22.6.1 Register Description............................................... 569 22.6.2 Port E Data Register (PEDR)........................................ 569 22.7 Port F ................................................................. 571 22.7.1 Register Description............................................... 571
22.7.2 Port F Data Register (PFDR) ........................................ 572 22.8 Port G................................................................. 573 22.8.1 Register Description............................................... 573 22.8.2 Port G Data Register (PGDR) ........................................ 574 22.9 Port H................................................................. 575 22.9.1 Register Description............................................... 575 22.9.2 Port H Data Register (PHDR) ........................................ 575 22.10 Port J.................................................................. 577 22.10.1 Register Description............................................... 577 22.10.2 Port J Data Register (PJDR)......................................... 578 22.11 Port K................................................................. 579 22.11.1 Register Description............................................... 579 22.11.2 Port K Data Register (PKDR) ........................................ 580 22.12 Port L................................................................. 581 22.12.1 Register Description............................................... 581 22.12.2 Port L Data Register (PLDR)........................................ 582 22.13 SC Port................................................................ 583 22.13.1 Register Description............................................... 583 22.13.2 SC Port Data Register (SCPDR) ...................................... 584
Section 23 A / D Converter ................................................. 587
Section 24 Hitachi User Debug Interface (H-UDI) .......................... 607
24.1 Overview .............................................................. 607 24.2 Hitachi User Debug Interface (H-UDI)....................................... 607 24.2.1 Pin Description................................................... 607 24.2.2 Block Diagram ................................................... 608 24.3 Register Descriptions..................................................... 608 24.3.1 Bypass Register (SDBPR) .......................................... 609 24.3.2 Instruction Register (SDIR) ......................................... 609 24.3.3 Boundary Scan Register (SDBSR).................................... 610 24.4 H-UDI Operations ....................................................... 617 24.4.1 TAP Controller................................................... 617 24.4.2 Reset Configuration ............................................... 618 24.4.3 H-UDI Reset..................................................... 618 24.4.4 H-UDI Interrupt .................................................. 619 24.4.5 Bypass .......................................................... 619 24.5 Boundary Scan.......................................................... 619 24.5.1 Supported Instructions ............................................. 619 24.5.2 Notes on Use ..................................................... 620 24.6 Notes on Use ........................................................... 621 24.7 Advanced User Debugger (AUD) ........................................... 621
Section 25 Electrical Characteristics (80 MHz) ............................. 623
25.1 Absolute Maximum Ratings................................................ 623 25.2 DC Characteristics....................................................... 625 25.3 AC Characteristics....................................................... 628 25.3.1 Clock Timing .................................................... 629 25.3.2 Control Signal Timing ............................................. 633 25.3.3 AC Bus Timing ................................................... 636 25.3.4 Basic Timing ..................................................... 637 25.3.5 Burst ROM Timing ................................................ 641 25.3.6 Synchronous DRAM Timing ........................................ 644 25.3.7 Peripheral Module Signal Timing ..................................... 662 25.3.8 USB Module Signal Timing......................................... 666 25.3.9 H-UDI-Related Pin Timing .......................................... 668 25.3.10 A / D Converter Timing ............................................. 670 25.3.11 AC Characteristics Measurement Conditions ............................ 672 25.3.12 Delay Time Variation Due to Load Capacitance (Reference Values) ......... 673 25.4 A / D Converter Characteristics .............................................. 674
Section 26 Electrical Characteristics (100 MHz) ............................ 675
26.1 Absolute Maximum Ratings................................................ 675 26.2 DC Characteristics....................................................... 677 26.3 AC Characteristics....................................................... 680
26.3.1 Clock Timing .................................................... 681 26.3.2 Control Signal Timing ............................................. 685 26.3.3 AC Bus Timing ................................................... 688 26.3.4 Basic Timing ..................................................... 689 26.3.5 Burst ROM Timing ................................................ 693 26.3.6 Synchronous DRAM Timing ........................................ 696 26.3.7 Peripheral Module Signal Timing ..................................... 714 26.3.8 USB Module Signal Timing......................................... 718 26.3.9 H-UDI-Related Pin Timing .......................................... 720 26.3.10 A / D Converter Timing ............................................. 722 26.3.11 AC Characteristics Measurement Conditions ............................ 724 26.3.12 Delay Time Variation Due to Load Capacitance (Reference Values) ......... 725 26.4 A / D Converter Characteristics .............................................. 726
Appendix A On-Chip Peripheral Module Registers ......................... 727
A.1 Address List............................................................ 727
Appendix B Pin Functions ................................................ 741
B.1 Pin States .............................................................. 741
Appendix C Notes on Consecutive Execution of Multiply-Accumulate / Multiplication are DSP Instructions ........................... 745 Appendix D Product Lineup ............................................... 747 Appendix E Package Dimensions .......................................... 748
Section 1 Overview and Pin Functions
1.1 SH7622 Features
The SH7622 is a RISC microprocessor with a 32-bit RISC type SuperH architecture CPU plus digital signal processing (DSP) extended functions as its core, and also including cache memory, on-chip X / Y memory, and an interrupt controller necessary for system configuration. High-speed data transfer is provided by the on-chip DMAC (direct memory access controller), and external memory access support functions allow direct connection to various kinds of memory. The SH7622 also provided with powerful on-chip peripheral functions ideal for system configuration, including a USB function module and serial communication interface with largecapacity built-in FIFOs. Powerful on-chip power management functions enable power consumption to be reduced even during high-speed operation. The SH7622 is ideally suited to electronic devices and other applications requiring high-speed operation together with low power consumption. The features of the SH7622 are summarized in table 1.1. Table 1.1
Item CPU
SH7622 Features
Features · · · · Original Hitachi SuperH architecture Object code level upward compatibility with SH-1, SH-2, SH-DSP 32-bit internal data bus General register file Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers · RISC-type instruction set Fixed 16-bit instruction length for excellent code efficiently Load-store architecture Delayed branch instructions C-based instruction set · · · Instruction execution time: Basic instructions execute in one cycle Address space: 4 Gbytes Five-stage pipeline
Table 1.1
Item DSP
SH7622 Features (cont)
Clock pulse generator (CPG)
Cache memory
Table 1.1
Item X / Y memory
SH7622 Features (cont)
Features · Three independent read / write ports 8- / 16- / 32-bit access from CPU Maximum of two 16-bit accesses from DSP · 8-kbyte on-chip RAM for X and Y memory Nine external interrupt pins (NMI, IRQ7 to IRQ0) On-chip peripheral module interrupts: Priority level can be set for each module Auto vector mode supported (no external vector mode) Fixed vector numbers Two break channels Address, data value, access type, and data size can all be set as break conditions Supports sequential break function External memory space divided into six areas (area 0 and areas 2 to 6), each of up to 64 Mbytes, with the following parameters settable for each area: Bus size (8, 16, or 32 bits) Number of wait cycles (hardware wait function also supported) Direct connection of SRAM, synchronous DRAM, and burst ROM possible by designating memory to be connected to each area Chip select signals (CS0, CS2 to CS6) output for relevant areas · Synchronous DRAM refresh functions Programmable refresh interval Supports auto-refresh and self-refresh modes · Synchronous DRAM burst access function E10A emulator support Pin arrangement conforming to JTAG specification Realtime branch trace 1-kbyte on-chip RAM for high-speed emulation program execution 3-channel auto-reload 32-bit timer Input capture function (channel 2 only) Choice of six counter input clocks
Interrupt controller (INTC)
User break controller (UBC)
Bus state controller · (BSC)
User debug interface (H-UDI)
Timer unit (TMU)
Table 1.1
SH7622 Features (cont)
Features · · · · · · · 16-bit counter Choice of four counter input clocks CPU interrupt request or DMAC transfer request generated by compare match Synchronous mode Simultaneous transmission / reception (full-duplex) capability, clock pin used for both transmission and reception DMA transfer capability 128-byte transmit FIFO, 384-byte receive FIFO Synchronous mode Simultaneous transmission / reception (full-duplex) capability, clock pin used for both transmission and reception DMAC transfer capability 128-byte transmit and receive FIFOs Choice of synchronous mode or asynchronous mode 16-byte transmit and receive FIFOs DMA transfer capability Four channels Burst mode and cycle steal mode External request capability (channels 0 and 1 only) Dual-function input / output ports can be switched between input and output bit by bit
Compare match timer 1 (CMT1)
Serial communication interface 0 (SCIF0)
Serial communication interface 1 (SCIF1)
Serial communication interface 2 (SCIF2) DMA controller (DMAC)
Table 1.1
Item USB function module
SH7622 Features (cont)
· · · · · · A / D converter · · Power supply voltage Product lineup ·
Product Operating Name Voltage Frequency SH7622 3.3 V 80 MHz
Product Code HD6417622FL80
Package 216-pin plastic LQFP (FP-216)
HD6417622BP80 208-pin TFBGA (TBP-208A) HD6417622F80 100 MHz 208-pin plastic QFP (FP-208C)
HD6417622FL100 216-pin plastic LQFP (FP-216) HD6417622BP100 208-pin TFBGA (TBP-208A) HD6417622F80 208-pin plastic QFP (FP-208C)
Block Diagram
Figure 1.1 shows an internal block diagram of the SH7622.
Y-bus
X-bus
XYCNT
SH-DSP CPU
XYMEM L-bus
UBC Peripheral bus 1
AUD CCN CACHE
I-bus
ASERAM
BSC H-UDI SCIF0
SCIF1 DMAC Peripheral bus 2
CPG / WDT CMT0
SCIF2
USB External bus interface I / O ports
ADC: ASERAM: AUD: BSC: CACHE: CCN: CMT0: CMT1:
A / D converter ASE memory Advanced user debugger Bus state controller Cache memory Cache memory controller Compare match timer 0 Compare match timer 1
CPG / WDT: CPU: DMAC: INTC: SCIF: TMU: UBC: H-UDI:
Clock pulse generator / watchdog timer Central processing unit Direct memory access controller Interrupt controller Serial communication interface (with FIFO) Timer unit User break controller Hitachi user debug interface
Figure 1.1 Block Diagram of SH7622
Pin Description
Pin Arrangement
NC1 EXTAL XTAL Vcc Vss Vss AUDCK / PTH6 Vcc-PLL22 CAP2 Vss-PLL22 Vss-PLL12 CAP1 Vcc-PLL12 MD0 TXDMNS / PTF0 TXDPLS / PTF1 DPLS / PTF2 DMNS / PTF3 TCK / PTF4 TDI / PTF5 TMS / PTF6 TRST / PTF7 AUDATA0 / PTG0 Vcc AUDATA1 / PTG1 Vss AUDATA2 / PTG2 AUDATA3 / PTG3 UCLK / PTG4 ASEBRKAK / PTG5 ASEMD0 / PTG6 PTG7 ADTRG / PTH5 RESE WAIT BREQ BACK TDO / PTE0 PTE1 RAS3U / PTE2 PTE3 PTE6 DACK1 / PTD7 DACK0 / PTD5 NF / PTJ5 NF / PTJ4 VccQ CASU / PTJ3 VssQ CASL / PTJ2 NF / PTJ1 RAS3L / PTJ0 CKE / PTK5 NC1
NC1 STATUS0 / PTJ6 STATUS1 / PTJ7 TCLK / PTH7 IRQOUT VssQ CKIO VccQ TxD0 / SCPT0 SCK0 / SCPT1 TxD1 / SCPT2 SCK1 / SCPT3 TxD2 / SCPT4 SCK2 / SCPT5 SCPT6 RxD0 / SCPT0 RxD1 / SCPT2 Vss RxD2 / SCPT4 Vcc IRQ5 / SCPT7 IRQ6 / PTC7 IRQ7 / PTC6 XVDATA / PTC5 TXENL / PTC4 VssQ VBUS / PTD3 VccQ SUSPND / PTD2 NF / PTC3 NF / PTC2 NF / PTC1 PTC0 DRAK0 / PTD1 DRAK1 / PTD0 DREQ0 / PTD4 DREQ1 / PTD6 RESETP VccQ MD3 MD4 Vss AVss AN0 / PTL0 AN1 / PTL1 AN2 / PTL2 AN3 / PTL3 PTL4 PTL5 AVcc PTL6 PTL7 AVss NC1
SH7622 FP-216 (Top View)
INDEX
NC1 PTE5 PTE4 CS6 CS5 / PTK3 CS4 / PTK2 CS3 / PTK1 CS2 / PTK0 VccQ CS0 VssQ AUDSYNC / PTE7 RD / WR WE3 / DQMUU / PTK7 WE2 / DQMUL / PTK6 WE1 / DQMLU WE0 / DQMLL RD BS / PTK4 A25 VccQ A24 VssQ A23 Vcc A22 Vss A21 A20 A19 A18 A17 A16 A15 VccQ A14 VssQ A13 A12 A11 A10 A9 A8 A7 A6 A5 VccQ A4 VssQ A3 A2 A1 A0 NC1
Notes: 1 NC pins must be connected to ground, except for the No.5 NC pin, which should be left open. 2 Must be connected to the power supply when the on-chip PLL is not used.
NC1 MD1 MD2 Vcc NC1 Vcc Vss NMI IRQ0 / PTH0 IRQ1 / PTH1 IRQ2 / PTH2 IRQ3 / PTH3 IRQ4 / PTH4 D31 / PTB7 D30 / PTB6 D29 / PTB5 D28 / PTB4 D27 / PTB3 D26 / PTB2 VssQ D25 / PTB1 VccQ D24 / PTB0 D23 / PTA7 D22 / PTA6 D21 / PTA5 D20 / PTA4 Vss D19 / PTA3 Vcc D18 / PTA2 D17 / PTA1 D16 / PTA0 VssQ D15 VccQ D14 D13 D12 D11 D10 D9 D8 D7 D6 VssQ D5 VccQ D4 D3 D2 D1 D0 NC1
Figure 1.2 Pin Arrangement (FP-216)
SH7622 TBP-208A (Top View)
A B C D E F G H J K L M N P R T U Note: The area within dotted lines shows a cutaway view of the pins.
Figure 1.3 Pin Arrangement (TBP-208A)
STATUS0 / PTJ6 STATUS1 / PTJ7 TCLK / PTH7 IRQOUT VssQ CKIO VccQ TXD0 / SCPT0 SCK0 / SCPT1 TXD1 / SCPT2 SCK1 / SCPT3 TXD2 / SCPT4 SCK2 / SCPT5 SCPT6 RXD0 / SCPT0 RXD1 / SCPT2 Vss RXD2 / SCPT4 Vcc IRQ5 / SCPT7 IRQ6 / PTC7 IRQ7 / PTC6 XVDATA / PTC5 TXENL / PTC4 VssQ VBUS / PTD3 VccQ SUSPND / PTD2 NF / PTC3 NF / PTC2 NF / PTC1 PTC0 DRAK0 / PTD1 DRAK1 / PTD0 DREQ0 / PTD4 DREQ1 / PTD6 RESETP VccQ MD3 MD4 Vss AVss AN0 / PTL0 AN1 / PTL1 AN2 / PTL2 AN3 / PTL3 PTL4 PTL5 AVcc PTL6 PTL7 AVss
EXTAL XTAL Vcc Vss Vss AUDCK / PTH6 Vcc-PLL22 CAP2 Vss-PLL22 Vss-PLL12 CAP1 Vcc-PLL12 MD0 TXDMNS / PTF0 TXDPLS / PTF1 DPLS / PTF2 DMNS / PTF3 TCK / PTF4 TDI / PTF5 TMS / PTF6 TRST / PTF7 AUDATA0 / PTG0 Vcc AUDATA1 / PTG1 Vss AUDATA2 / PTG2 AUDATA3 / PTG3 UCLK / PTG4 ASEBRKAK / PTG5 ASEMD0 / PTG6 PTG7 PTH5 / ADTRG RESE WAIT BREQ BACK TDO / PTE0 PTE1 RAS3U / PTE2 PTE3 PTE6 DACK1 / PTD7 DACK0 / PTD5 NF / PTJ5 NF / PTJ4 VccQ CASU / PTJ3 VssQ CASL / PTJ2 NF / PTJ1 RAS3L / PTJ0 CKE / PTK5
SH7622 FP-208C (Top View)
INDEX
PTE5 PTE4 CS6 CS5 / PTK3 CS4 / PTK2 CS3 / PTK1 CS2 / PTK0 VccQ CS0 VssQ AUDSYNC / PTE7 RD / WR WE3 / DQMUU / PTK7 WE2 / DQMUL / PTK6 WE1 / DQMLU WE0 / DQMLL RD BS / PTK4 A25 VccQ A24 VssQ A23 Vcc A22 Vss A21 A20 A19 A18 A17 A16 A15 VccQ A14 VssQ A13 A12 A11 A10 A9 A8 A7 A6 A5 VccQ A4 VssQ A3 A2 A1 A0
Notes: 1 No. 4 NC pin should be left open. 2 Must be connected to the power supply when the on-chip PLL is not used.
MD1 MD2 Vcc NC1 Vcc Vss NMI IRQ0 / PTH0 IRQ1 / PTH1 IRQ2 / PTH2 IRQ3 / PTH3 IRQ4 / PTH4 D31 / PTB7 D30 / PTB6 D29 / PTB5 D28 / PTB4 D27 / PTB3 D26 / PTB2 VssQ D25 / PTB1 VccQ D24 / PTB0 D23 / PTA7 D22 / PTA6 D21 / PTA5 D20 / PTA4 Vss D19 / PTA3 Vcc D18 / PTA2 D17 / PTA1 D16 / PTA0 VssQ D15 VccQ D14 D13 D12 D11 D10 D9 D8 D7 D6 VssQ D5 VccQ D4 D3 D2 D1 D0
Figure 1.4 Pin Arrangement (FP-208C)
Pin Functions
Table 1.2 summarizes the pin functions. Table 1.2 SH7622 Pin Functions
Pin No. FP-208C - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 FP-216 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 TBP-208A - A1 B1 C3 C2 C1 D3 D2 D1 E4 E3 E2 E1 F4 F3 F2 F1 G4 G3 G2 G1 H4 H3 H2 H1 J4 J2 Pin Name NC1, 4 MD1 MD2 Vcc3 NC1, 4 Vcc Vss NMI IRQ0 / PTH0 IRQ1 / PTH1 IRQ2 / PTH2 IRQ3 / PTH3 IRQ4 / PTH4 D31 / PTB7 D30 / PTB6 D29 / PTB5 D28 / PTB4 D27 / PTB3 D26 / PTB2 VssQ3 D25 / PTB1 VccQ3 D24 / PTB0 D23 / PTA7 D22 / PTA6 D21 / PTA5 D20 / PTA4 I / O - I I - O - - I I I I I I IO IO IO IO IO IO - IO - IO IO IO IO IO Description - Clock mode setting Clock mode setting Power supply (1.9 V) - Power supply (1.9 V) Power supply (0 V) Nonmaskable interrupt request External interrupt request / input port H External interrupt request / input port H External interrupt request / input port H External interrupt request / input port H External interrupt request / input port H Data bus / input / output port B Data bus / input / output port B Data bus / input / output port B Data bus / input / output port B Data bus / input / output port B Data bus / input / output port B Input / output power supply (0 V) Data bus / input / output port B Input / output power supply (3.3 V) Data bus / input / output port B Data bus / input / output port A Data bus / input / output port A Data bus / input / output port A Data bus / input / output port A
Table 1.2
SH7622 Pin Functions (cont)
Pin No.
FP-208C 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 - - 53 54
FP-216 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
TBP-208A J1 J3 K1 K2 K3 K4 L1 L2 L3 L4 M1 M2 M3 M4 N1 N2 N3 N4 P1 P2 P3 R1 R2 R4 T1 T2 - - U1 U2
Pin Name Vss3 D19 / PTA3 Vcc3 D18 / PTA2 D17 / PTA1 D16 / PTA0 VssQ3 D15 VccQ3 D14 D13 D12 D11 D10 D9 D8 D7 D6 VssQ3 D5 VccQ3 D4 D3 D2 D1 D0 NC1, 4 NC1, 4 A0 A1
Description Power supply (0 V) Data bus / input / output port A Power supply (1.9 V) Data bus / input / output port A Data bus / input / output port A Data bus / input / output port A Input / output power supply (0 V) Data bus Input / output power supply (3.3 V) Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Input / output power supply (0 V) Data bus Input / output power supply (3.3 V) Data bus Data bus Data bus Data bus Data bus - - Address bus Address bus
Table 1.2
SH7622 Pin Functions (cont)
Pin No.
FP-208C 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
FP-216 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87
TBP-208A R3 T3 U3 R4 T4 U4 P5 R5 T5 U5 P6 R6 T6 U6 P7 R7 T7 U7 P8 R8 T8 U8 P9 T9 U9 R9 U10 T10 R10 P10
Pin Name A2 A3 VssQ3 A4 VccQ3 A5 A6 A7 A8 A9 A10 A11 A12 A13 VssQ3 A14 VccQ3 A15 A16 A17 A18 A19 A20 A21 Vss3 A22 Vcc3 A23 VssQ3 A24
Description Address bus Address bus Input / output power supply (0 V) Address bus Input / output power supply (3.3 V) Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Input / output power supply (0 V) Address bus Input / output power supply (3.3 V) Address bus Address bus Address bus Address bus Address bus Address bus Address bus Power supply (0 V) Address bus Power supply (1.9 V) Address bus Input / output power supply (0 V) Address bus
Table 1.2
SH7622 Pin Functions (cont)
Pin No.
FP-208C 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 - - 105 106 107 108 109
FP-216 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114
TBP-208A U11 T11 R11 P11 U12 T12 R12 P12 U13 T13 R13 P13 U14 T14 R14 U15 T15 P14 U16 T16 - - U17 T17 R15 R16 R17
Pin Name VccQ3 A25 BS / PTK4 RD WE0 / DQMLL WE1 / DQMLU WE2 / DQMUL / PTK6 WE3 / DQMUU / PTK7 RD / WR AUDSYNC / PTE7 VssQ CS0 VccQ
Description Input / output power supply (3.3 V) Address bus Bus cycle start signal / input / output port K Read strobe D7-D0 select signal / DQM (SDRAM) D15-D8 select signal / DQM (SDRAM) D23-D16 select signal / DQM (SDRAM) / input / output port K D31-D24 select signal / DQM (SDRAM) / input / output port K Read / write AUD synchronization / input / output port E Input / output power supply (0 V) Chip select 0 Input / output power supply (3.3 V) Chip select 2 / input / output port K Chip select 3 / input / output port K Chip select 4 / input / output port K Chip select 5 / input / output port K Chip select 6 Input / output port E Input / output port E - - CK enable (SDRAM) / input / output port K Lower 32 MB address (SDRAM) RAS / input / output port J No function / output port J Lower 32 MB address (SDRAM) CAS / input / output port J Input / output power supply (0 V)
CS2 / PTK0 CS3 / PTK1 CS4 / PTK2 CS5 / PTK3 CS6 PTE4 PTE5 NC NC
CKE / PTK5 RAS3L / PTJ0 NF6 / PTJ1 CASL / PTJ2 VssQ3
Table 1.2
SH7622 Pin Functions (cont)
Pin No.
FP-208C 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137
FP-216 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142
TBP-208A P15 P16 P17 N14 N15 N16 N17 M14 M15 M16 M17 L14 L15 L16 L17 K14 K15 K16 K17 J14 J16 J17 J15 H17 H16 H15 H14 G17
Pin Name CASU / PTJ3 VccQ3 NF / PTJ4 NF / PTJ5 DACK0 / PTD5 DACK1 / PTD7 PTE6 PTE3 RAS3U / PTE2 PTE1 TDO / PTE0 BACK BREQ WAIT RESE ADTRG / PTH5 PTG7 ASEMD0 / PTG6 ASEBRKAK / PTG5 UCLK / PTG4 AUDATA3 / PTG3 AUDATA2 / PTG2 Vss
Description Upper 32 MB address (SDRAM) CAS / input / output port J Input / output power supply (3.3 V) No function / output port J No function / output port J DMA acknowledge 0 / input / output port D DMA acknowledge 1 / input / output port D Input / output port E Input / output port E Upper 32 MB address (area 3 DRAM, SDRAM) RAS / input / output port E Input / output port E Test data output / input / output port E Bus acknowledge Bus request Hardware wait request Manual reset request Analog trigger / input port H Input port G ASE mode / input port G ASE break acknowledge / input port G USB external input clock / input port G AUD data / input port G AUD data / input port G Power supply (0 V) AUD data / input port G Power supply (1.9 V) AUD data / input port G Test reset / input port F Test mode switch / input port F
AUDATA1 / PTG1 Vcc
AUDATA0 / PTG0 TRST / PTF7 TMS / PTF6
Table 1.2
SH7622 Pin Functions (cont)
Pin No.
FP-208C 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 - - 157 158 159 160 161 162 163 164
FP-216 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171
TBP-208A G16 G15 G14 F17 F16 F15 F14 E17 E16 E15 E14 D17 D16 D15 C17 C16 D14 B17 B16 - - A17 A16 C15 B15 A15 C14 B14 A14
Pin Name TDI / PTF5 TCK / PTF4 DMNS / PTF3 DPLS / PTF2 TXDPLS / PTF1 TXDMNS / PTF0 MD0 Vcc-PLL12 CAP1 Vss-PLL12 Vss-PLL22 CAP2 Vcc-PLL22 AUDCK / PTH6 Vss3 Vss3 Vcc3 XTAL EXTAL NC1, 4 NC1, 4 STATUS0 / PTJ6 STATUS1 / PTJ7 TCLK / PTH7 IRQOUT VssQ CKIO VccQ
Description Test data input / input port F Test clock / input port F D- input from USB receiver / input port F D+ input from USB receiver / input port F USB D+ transmit output / input port F USB D- transmit output / input port F Clock mode setting PLL1 power supply (1.9 V) PLL1 external capacitance pin PLL1 power supply (0 V) PLL2 power supply (0 V) PLL2 external capacitance pin PLL2 power supply (1.9 V) AUD clock / input port H Power supply (0 V) Power supply (0 V) Power supply (1.9 V) Clock pulse generator pin External clock / crystal oscillator pin - - Processor status / input / output port J Processor status / input / output port J TMU or RTC clock input / output / input / output port H Interrupt request notification Input / output power supply (0 V) System clock output Input / output power supply (3.3 V) Transmit data 0 / SCI output port
TxD0 / SCPT0
Table 1.2
SH7622 Pin Functions (cont)
Pin No.
FP-208C 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190
FP-216 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197
TBP-208A D13 C13 B13 A13 D12 C12 B12 A12 D11 C11 B11 A11 D10 C10 B10 A10 D9 B9 A9 C9 A8 B8 C8 D8 A7 B7
Pin Name SCK0 / SCPT1 TxD1 / SCPT2 SCK1 / SCPT3 TxD2 / SCPT4 SCK2 / SCPT5 SCPT6 RxD0 / SCPT0 RxD1 / SCPT2 Vss3 RxD2 / SCPT4 Vcc3 IRQ5 / SCPT7 IRQ6 / PTC7 IRQ7 / PTC6 XVDATA / PTC5 TXENL / PTC4 VssQ
Description Serial clock 0 / SCI input / output port Transmit data 1 / SCI output port Serial clock 1 / SCI input / output port Transmit data 2 / SCI output port Serial clock 2 / SCI input / output port SCI input / output port Receive data 0 / SCI input port Receive data 1 / SCI input port Power supply (0 V) Receive data 2 / SCI input port Power supply (1.9 V) External interrupt request / SCI input port External interrupt request / input / output port C External interrupt request / input / output port C USB differential receive signal input / input / output port C USB output enable / input / output port C Input / output power supply (0 V) USB power supply detection / input / output port D Input / output power supply (3.3 V) USB suspend / input / output port D No function / output port C No function / output port C No function / input port C Output port C DMA request acknowledge / input / output port D DMA request acknowledge / input / output port D
VBUS / PTD3 VccQ3 SUSPND / PTD2 NF6 / PTC3 NF6 / PTC2 NF6 / PTC1 PTC0 DRAK0 / PTD1 DRAK1 / PTD0
Table 1.2
SH7622 Pin Functions (cont)
Pin No.
FP-208C 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 -
FP-216 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216
TBP-208A C7 D7 A6 B6 C6 D6 A5 B5 C5 D5 A4 B4 C4 A3 B3 D4 A2 B2 -
Pin Name DREQ0 / PTD4 DREQ1 / PTD6 RESETP VccQ3 MD3 MD4 Vss3 AVss3 AN0 / PTL0 AN1 / PTL1 AN2 / PTL2 AN3 / PTL3 PTL4 PTL5 AVcc3 PTL6 PTL7 AVss3 NC1, 4
Description DMA request / input / output port D DMA request / input / output port D Power-on reset request Input / output power supply (3.3 V) Area 0 bus width setting Area 0 bus width setting Power supply (0 V) Analog power supply (0 V) A / D converter input / input port L A / D converter input / input port L A / D converter input / input port L A / D converter input / input port L Input port L Input port L Analog power supply (3.3 V) Input port L Input port L Analog power supply (0 V) -
Notes: 1 NC pins must be connected to ground, except for the No. 5 (FP-216) and No. 4 (FP208C), which should be left open. 2 Must be connected to the power supply when the on-chip PLL is not used. 3 All Vcc / Vss / VccQ / VssQ / AVcc / Avss pins must be connected to the system power supply (Power must be supplied constantly). 4 Except for pin No.5 on the FP-216, NC pins are not connected internally. 5 The system design must ensure that noise is not introduced onto the Vss and VssQ pins. 6 NF pins should be left open when not used as output ports. An exception is the PTC1 NF pin, for which a pull-down connection should be made.
Section 2 CPU
2.1 Register Configuration
The register set consists of sixteen 32-bit general registers, six 32-bit control registers and ten 32bit system registers. The SH7622 is upwardly compatible with the SH-1, SH-2 on the object code level. For this reason, several registers have been added to the previous SuperH microcontroller registers. The added registers are the three control registers: repeat start register (RS), repeat end register (RE), and modulo register (MOD) and the eight system registers: DSP status register (DSR), and A0, A1, X0, X1, Y0, and Y1 among the DSP data registers. The general registers are used in the same manner as the SH-1, SH-2 with regard to SuperH microcontroller-type instructions. With regard to DSP type instructions, they are used as address and index registers for accessing memory. 2.1.1 General Registers
There are 16 general registers (Rn) numbered R0-R15, which are 32 bits in length. General registers are used for data processing and address calculation. With SuperH microcomputer type instructions, R0 is also used as an index register. Several instructions are limited to use of R0 only. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15. With DSP type instructions, eight of the 16 general registers are used for the addressing of X, Y data memory and data memory (single data) using the L bus. R4, R5 are used as an X address register (Ax) for X memory accesses, and R8 is used as an X index register (Ix). R6, R7 are used as a Y address register (Ay) for Y memory accesses, and R9 is used as a Y index register (Iy). R2, R3, R4, R5 are used as a single data address register (As) for accessing single data using the L bus, and R8 is used as a single data index register (Is). DSP type instructions can simultaneously access X and Y data memory. There are two groups of address pointers for designating X and Y data memory addresses. Figure 2.1 shows the general registers.
31 R01 R1 R2, As3 R3, As3 R4, As, Ax3 R5, As, Ax3 R6, Ay3 R7, Ay3 R8, Ix, Is3 R9, Iy3 R10 R11 R12 R13 R14 R15, SP2 Notes:
1 R0 also functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, only the R0 functions as a source register or destination register. 2 R15 functions as a hardware stack pointer (SP) during exception processing. 3 Used as memory address registers, memory index registers with DSP type instructions.
Figure 2.1 General Register Configuration With the assembler, symbol names are used for R2, R3 .. R9. If it is wished to use a name that makes clear the role of a register for DSP type instructions, a different register name (alias) can be used. This is written in the following manner for the assembler.
Ix: .REG (R8)
The name Ix is an alias for R8. The other aliases are assigned as follows:
Ax0: Ax1: Ix: Ay0: Ay1: Iy: As0: As1: As2: As3: Is: .REG (R4) .REG (R5) .REG (R8) .REG (R6) .REG (R7) .REG (R9) .REG (R4) .REG (R5) .REG (R2) .REG (R3) .REG (R8) defined when an alias is required for single data transfer defined when an alias is required for single data transfer defined when an alias is required for single data transfer defined when an alias is required for single data transfer defined when an alias is required for single data transfer
Control Registers
The six 32-bit control registers consist of the status register (SR), repeat start register (RS), repeat end register (RE), global base register (GBR), vector base register (VBR), and modulo register (MOD). The SR register indicates processing states. The GBR register functions as a base address for the indirect GBR addressing mode, and is used for such as on-chip peripheral module register data transfers. The VBR register functions as the base address of the exception processing vector area (including interrupts). The RS and RE registers are used for program repeat (loop) control. The repeat count is designated in the SR register repeat counter (RC), the repeat start address in the RS register, and the repeat end address in the RE register. However, note that the address values stored in the RS and RE registers are not necessarily always the same as the physical start and end address values of the repeat. The MOD register is used for modulo addressing to buffer the repeat data. The modulo addressing designation is made by DMX or DMY, the modulo end address (ME) is designated in the upper 16 bits of the MOD register, and the modulo start address (MS) is designated in the lower 16 bits. Note that the DMX and DMY bits cannot simultaneously designate modulo addressing. Modulo addressing is possible with X and Y data transfer instructions (MOVX, MOVY). It is not possible with single data transfer instructions (MOVS).
Figure 2.2 shows the control registers. Table 2.1 indicates the SR register bits.
Status register (SR) 31 28 27 16 15 12 11 10 9 8 7 4 3 2 1 0 0000 RC 0000 DMY DMX M Q I3 I2 I1 I0 RF1 RF0 S T Repeat start register (RS) 31 RS Repeat end register (RE) 31 RE Global base register (GBR) 31 GBR Vector base register (VBR) 31 VBR Modulo register (MOD) 31 ME ME: Modulo end address MS: Modulo start address
Figure 2.2 Control Register Configuration
Table 2.1
Bit 27-16 11
SR Register Bits
Saturation arithmetic bit (S)
Used with MAC instructions and DSP instructions 1: Designates saturation arithmetic (prevents overflows) For MOVT, CMP / cond, TAS, TST, BT, BT / S, BF, BF / S, SETT, CLRT and DT instructions, 0: represents false 1: represents true For ADDV / ADDC, SUBV / SUBC, DIV0U / DIV0S, DIV1, NEGC, SHAR / SHAL, SHLR / SHLL, ROTR / ROTL and ROTCR / ROTCL instructions, 1: represents occurrence of carry, borrow, overflow or underflow
0: 0 is always read out write a 0
There are dedicated load / store instructions for accessing the RS, RE and MOD registers. For example, the RS register is accessed as follows.
LDC LDC.L STC STC.L Rm, RS @Rm+, RS RS, Rn RS, @-Rn RmRS (Rm)RS, Rm+4Rm RSRn Rn-4Rn, RS(Rn)
The following instructions set addresses in the RS, RE registers for zero overhead repeat control:
Features of CPU Instructions
Fetching and Decoding
The SH7622 supports a series of mixed 16-bit and 32-bit instructions. There are no restrictions on the order of instructions within a series of mixed 16-bit and 32-bit instructions. 2.2.2 Integer Unit
· Zero-overhead loop control: The integer unit supports zero-overhead program loops, in which loop counter incrementing and judgment of completion of the loop are performed automatically. These loops are important for high-speed DSP applications. To set up such a loop, special registers are used to specify the number of repetitions of the instruction loop, and the loop start address and end address. The processor then automatically executes the loop the specified number of times. 2.2.3 System Registers
SH7622 has four system registers, MACL, MACH, PR and PC (figure 2.3).
31 MACH MACL 31 PR 31 PC
0 Multiply and accumulate high and low registers (MACH / L) Store the results of multiplicationand accumulation operations. 0 Procedure register (PR) Stores the sbroutine procedure return address. 0 Program counter (PC) Indicates the starting address of the current instruction.
Figure 2.3 System Registers DSR, A0, X0, X1, Y0 and Y1 registers are also treated as system registers. So, data transfer instructions between general registers and system registers are supported for them. 2.2.4 DSP Registers
The SH7622 has eight data registers and one control register (figure 2.4). The data registers are 32-bit width with the exception of registers A0 and A1. Registers A0 and A1 include 8 guard bits (fields A0G and A1G), giving them a total width of 40 bits. Three types of operations access the DSP data registers. First one is the DSP data. When a DSP fixed-point data operation uses A0 or A1 for source register, it uses the guard bits (bits 39-32). When it uses A0 or A1 for destination register, bits 39-32 in the guard bit is valid. When a DSP fixed-point data operation uses the DSP registers other than A0 and A1 for source register, it signextends the source value to bits 39-32. When it uses them for destination register, the bits 39-32 of the result is discard. Second one is X and Y data transfer operation, "MOVX.W MOVY.W". This operation accesses the X and Y memories through 16-bit X and Y data buses (figure 2.8). Registers to be loaded or stored by this operation are always upper 16 bits (bits 31-16). X0 and X1 can be destination of the
X memory load and Y0 and Y1 can be destination of Y memory load, but other register cannot be destination register of this operation. When data is read into the upper 16 bits of a register (bits 31-16), the lower 16 bits of the register (bits 15-0) are automatically cleared. A0 and A1 can be stored to the X or Y memory by this operation, but other registers cannot be stored. Third one is single-data transfer instruction, "MOVS.W" and "MOVS.L". This instruction accesses any memory location through LDB (figure 2.5). All DSP registers connect to the LDB and be able to be source and destination register of the data transfer. It has word and longword access modes. In the word mode, registers to be loaded or stored by this instruction are upper 16 bits (bits 31-16) for the DSP registers except A0G and A1G. When data is loaded into a register other than A0G and A1G in the word mode, lower half of the register is cleared. When it is A0 or A1, the data is sign-extended to bits 39-32 and lower half