Hardware Manual ADE-602-212A Rev. 9/19/01 Hitachi, Ltd. Caut
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SH7622
Hardware Manual
ADE-602-212A Rev. 9/19/01 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
SH7622 microprocessor that integrates peripheral functions necessary system configuration with 32-bit internal architecture SH2-DSP core. SH7622's on-chip peripheral functions include DSP, cache memory, internal memory, interrupt controller, timers, three serial communication interfaces, function module, user break controller (UBC), state controller (BSC), ports, making ideal microcomputer electronic devices that require high speed together with power consumption. Intended Readership: This manual intended users undertaking design application system using SH7622. Readers using this manual require basic knowledge electrical circuits, logic circuits, microcomputers. Purpose: purpose this manual give users understanding hardware functions electrical characteristics SH7622. Details execution instructions found SH-1, SH-2, SH-DSP Programming Manual, which should read conjunction with present manual.
Using this Manual: overall understanding SH7622's functions Follow Table Contents. This manual broadly divided into sections CPU, system control functions, peripheral functions, electrical characteristics. detailed understanding functions Refer separate publication SH-1, SH-2, SH-DSP Programming Manual. Note notation: Bits shown high-to-low order from left right. Related Material: latest information available Site. Please make sure that have most up-to-date information available.
User's Manuals SH7622:
Manual Title SH7622 Hardware Manual SH-1, SH-2, SH-DSP Programming Manual This manual ADE-602-085
Users manuals development tools:
Manual Title C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual Simulator Debugger Users Manual Hitachi Embedded Workshop Users Manual ADE-702-304 ADE-702-266 ADE-702-275
Application Note:
Manual Title C/C++ Complier ADE-502-046
Contents
Section Overview Functions
SH7622 Features Block Diagram. Description 1.3.1 Arrangement 1.3.2 Functions.
Section
Register Configuration 2.1.1 General Registers 2.1.2 Control Registers. Features Instructions. 2.2.1 Fetching Decoding. 2.2.2 Integer Unit 2.2.3 System Registers 2.2.4 Registers. Data Format. 2.3.1 Data Format Registers (Non-DSP Type) 2.3.2 DSP-Type Data Format 2.3.3 Data Format Memory.
Section Operation
Data Operations Unit 3.1.1 Fixed-Point Operations 3.1.2 Integer Operations. 3.1.3 Logical Operations 3.1.4 Fixed-Point Multiply Operation. 3.1.5 Shift Operations 3.1.6 Most Significant Detection Operation 3.1.7 Rounding Operation 3.1.8 Overflow Protection 3.1.9 Data Transfer Operation. 3.1.10 Local Data Move Operation. 3.1.11 Operand Conflict Addressing. 3.2.1 Loop Control. 3.2.2 Data Addressing.
Section Instruction
Basic Concept SH7622 Instruction Set. SH-1, SH-2 Compatible Instruction 4.2.1 Instruction Classification Instructions Extension 4.3.1 Introduction 4.3.2 Additional System Control Instruction 4.3.3 Single- Double-Data Transfer Instructions 4.3.4 Parallel Operation Unit.
Section Exception Handling
Overview 5.1.1 Types Exception Handling Priority Order Exception Handling Operations 5.2.1 Exception Vector Table Resets. 5.3.1 Types Resets 5.3.2 Power-On Reset 5.3.3 Manual Reset. Address Errors. 5.4.1 Sources Address Errors. 5.4.2 Address Error Exception Handling Interrupts 5.5.1 Interrupt Sources 5.5.2 Interrupt Priority Levels. 5.5.3 Interrupt Exception Handling. Exceptions Triggered Instructions 5.6.1 Instruction-Triggered Exception Types 5.6.2 Trap Instructions 5.6.3 Illegal Slot Instructions 5.6.4 General Illegal Instructions When Exception Sources Accepted 5.7.1 Immediately after Delayed Branch Instruction 5.7.2 Immediately after Interrupt-Disabled Instruction. 5.7.3 Instructions Repeat Loops. Stack Status after Exception Handling Usage Notes. 5.9.1 Value Stack Pointer (SP) 5.9.2 Value Vector Base Register (VBR) 5.9.3 Manual Reset during Register Access.
Section Cache
Overview
6.1.1 Features 6.1.2 Cache Structure 6.1.3 Register Configuration Register Description 6.2.1 Cache Control Register (CCR). Cache Operation 6.3.1 Searching Cache. 6.3.2 Read Access 6.3.3 Write Access 6.3.4 Write-Back Buffer. 6.3.5 Coherency Cache External Memory Memory-Mapped Cache. 6.4.1 Address Array 6.4.2 Data Array Usage Examples 6.5.1 Invalidating Specific Entries 6.5.2 Reading Data Specific Entry. 6.5.3 Usage Notes
Section Memory
Overview 7.1.1 Features X-/Y-Memory Access from X-/Y-Memory Access from X-/Y-Memory Access from DMAC. Usage Note
Section Interrupt Controller (INTC)
Overview 8.1.1 Features 8.1.2 Configuration 8.1.3 Register Configuration Interrupt Sources 8.2.1 Interrupt 8.2.2 User Break Interrupt. 8.2.3 H-UDI Interrupt 8.2.4 Interrupts 8.2.5 On-Chip Peripheral Module Interrupts 8.2.6 Interrupt Exception Vectors Priority Order. INTC Registers. 8.3.1 Interrupt Priority Registers (IPRA-IPRH). 8.3.2 Interrupt Control Register (ICR0). 8.3.3 Interrupt Control Register (ICR1).
8.3.4 Interrupt Request Register (IRR) Interrupt Operation 8.4.1 Interrupt Sequence
Section User Break Controller
Overview 9.1.1 Features 9.1.2 Block Diagram 9.1.3 Register Configuration Register Descriptions. 9.2.1 Break Address Register (BARA) 9.2.2 Break Address Mask Register (BAMRA). 9.2.3 Break Cycle Register (BBRA) 9.2.4 Break Address Register (BARB) 9.2.5 Break Address Mask Register (BAMRB) 9.2.6 Break Data Register (BDRB) 9.2.7 Break Data Mask Register (BDMRB). 9.2.8 Break Cycle Register (BBRB) 9.2.9 Break Control Register (BRCR) 9.2.10 Execution Times Break Register (BETR) 9.2.11 Branch Source Register (BRSR) 9.2.12 Branch Destination Register (BRDR) Operation Description 9.3.1 Flow User Break Operation 9.3.2 Break Instruction Fetch Cycle. 9.3.3 Break Data Access Cycle 9.3.4 Break X-/Y-Memory Cycle 9.3.5 Sequential Break 9.3.6 Value Saved Program Counter. 9.3.7 Trace. 9.3.8 Usage Examples 9.3.9 Notes.
Section Power-Down Modes
10.1 Overview 10.1.1 Power-Down Modes. 10.1.2 Configuration 10.1.3 Register Configuration 10.2 Register Description 10.2.1 Standby Control Register (STBCR). 10.2.2 Standby Control Register (STBCR2). 10.2.3 Standby Control Register (STBCR3). 10.3 Standby Mode
10.3.1 Transition Standby Mode. 10.3.2 Canceling Standby Mode 10.3.3 Usage Note 10.4 Module Standby Function 10.4.1 Transition Module Standby Function. 10.4.2 Clearing Module Standby Function 10.5 Timing STATUS Changes. 10.5.1 Timing Resets. 10.5.2 Timing Canceling Standbys
Section On-Chip Oscillator Circuit
11.1 Overview 11.1.1 Features 11.2 Overview 11.2.1 Block Diagram. 11.2.2 Configuration 11.2.3 Register Configuration 11.3 Clock Operating Modes. 11.4 Register Descriptions. 11.4.1 Frequency Control Register (FRQCR). 11.5 Changing Frequency. 11.5.1 Changing Multiplication Rate 11.5.2 Changing Division Ratio 11.6 Overview WDT. 11.6.1 Block Diagram WDT. 11.6.2 Register Configurations 11.7 Registers 11.7.1 Watchdog Timer Counter (WTCNT). 11.7.2 Watchdog Timer Control/Status Register (WTCSR). 11.7.3 Notes Register Access. 11.8 Using 11.8.1 Canceling Standbys 11.8.2 Changing Frequency. 11.8.3 Using Watchdog Timer Mode. 11.8.4 Using Interval Timer Mode. 11.9 Notes Board Design 11.10 Usage Notes.
Section Extend Clock Pulse Generator (EXCPG)
12.1 Overview EXCPG. 12.1.1 EXCPG Features 12.1.2 EXCPG Configuration 12.1.3 Register Configuration
12.2 Register Descriptions. 12.2.1 Clock Control Register (USBCLKCR) 12.3 Usage Notes.
Section State Controller (BSC)
13.1 Overview 13.1.1 Features 13.1.2 Block Diagram 13.1.3 Configuration 13.1.4 Register Configuration 13.1.5 Area Overview 13.2 Registers 13.2.1 Control Register (BCR1) 13.2.2 Control Register (BCR2) 13.2.3 Wait Control Register (WCR1). 13.2.4 Wait Control Register (WCR2). 13.2.5 Individual Memory Control Register (MCR). 13.2.6 Synchronous DRAM Mode Register (SDMR) 13.2.7 Refresh Timer Control/Status Register (RTCSR). 13.2.8 Refresh Timer Counter (RTCNT) 13.2.9 Refresh Time Constant Register (RTCOR) 13.2.10 Refresh Count Register (RFCR) 13.2.11 Cautions Accessing Refresh Control Related Registers 13.3 Operation. 13.3.1 Access Size Data Alignment 13.3.2 Description Areas. 13.3.3 Basic Interface. 13.3.4 Synchronous DRAM Interface. 13.3.5 Burst Interface 13.3.6 Waits between Access Cycles 13.3.7 Arbitration.
Section Direct Memory Access Controller (DMAC)
14.1 Overview 14.1.1 Features 14.1.2 Block Diagram 14.1.3 Configuration 14.1.4 Register Configuration 14.2 Register Descriptions. 14.2.1 Source Address Registers (SAR0-SAR3) 14.2.2 Destination Address Registers (DAR0-DAR3) 14.2.3 Transfer Count Registers (DMATCR0-DMATCR3) 14.2.4 Channel Control Registers (CHCR0-CHCR3).
14.3
14.4
14.5
14.6
14.2.5 Channel Expansion Request Registers (CHCRA0, CHCRA1). 14.2.6 Operation Register (DMAOR). Operation 14.3.1 Transfer Flow. 14.3.2 Transfer Requests. 14.3.3 Channel Priority 14.3.4 Transfer Types 14.3.5 Number Cycle States DREQ Sampling Timing 14.3.6 Source Address Reload Function 14.3.7 Transfer Ending Conditions. Compare Match Timer (CMT0) 14.4.1 Overview 14.4.2 Register Descriptions 14.4.3 Operation 14.4.4 Compare Match Examples Use. 14.5.1 Example Transfer between On-Chip SCIF0 External Memory 14.5.2 Example Transfer between Converter External Memory (Address Reload on). Cautions.
Section Timer (TMU)
15.1 Overview 15.1.1 Features 15.1.2 Block Diagram 15.1.3 Configuration. 15.1.4 Register Configuration 15.2 Registers 15.2.1 Timer Start Register (TSTR). 15.2.2 Timer Control Register (TCR) 15.2.3 Timer Constant Register (TCOR) 15.2.4 Timer Counters (TCNT). 15.2.5 Input Capture Register (TCPR2). 15.3 Operation 15.3.1 Overview 15.3.2 Basic Functions 15.4 Interrupts 15.4.1 Status Flag Timing 15.4.2 Status Flag Clear Timing 15.4.3 Interrupt Sources Priorities. 15.5 Usage Notes. 15.5.1 Writing Registers 15.5.2 Reading Registers.
Section Serial Communication Interface with FIFO (SCIF0)
16.1 Overview 16.1.1 Features 16.1.2 Block Diagram 16.1.3 Configuration 16.1.4 Register Configuration 16.2 Register Descriptions. 16.2.1 Receive Shift Register (SCRSR0). 16.2.2 Receive FIFO Data Register (SCFRDR0) 16.2.3 Transmit Shift Register (SCTSR0) 16.2.4 Transmit FIFO Data Register (SCFTDR0) 16.2.5 Serial Mode Register (SCSMR0). 16.2.6 Serial Control Register (SCSCR0). 16.2.7 Serial Status Register (SCSSR0). 16.2.8 Rate Register (SCBRR0). 16.2.9 FIFO Control Register (SCFCR0) 16.2.10 Receive FIFO Data Count Register (SCRFDR0). 16.2.11 Transmit FIFO Data Count Register (SCTFDR0) 16.2.12 Line Status Register (SCLSR0) 16.3 Operation 16.3.1 Overview 16.3.2 Serial Operation 16.4 SCIF0 Interrupt Sources DMAC 16.5 Timing TDFST, RDFST, TEND Setting. 16.6 Usage Notes.
Section Serial Communication Interface with FIFO (SCIF1)
17.1 Overview 17.1.1 Features 17.1.2 Block Diagram 17.1.3 Configuration 17.1.4 Register Configuration 17.2 Register Descriptions. 17.2.1 Receive Shift Register (SCRSR1). 17.2.2 Receive FIFO Data Register (SCFRDR1) 17.2.3 Transmit Shift Register (SCTSR1) 17.2.4 Transmit FIFO Data Register (SCFTDR1) 17.2.5 Serial Mode Register (SCSMR1). 17.2.6 Serial Control Register (SCSCR1). 17.2.7 Serial Status Register (SCSSR1). 17.2.8 Rate Register (SCBRR1). 17.2.9 FIFO Control Register (SCFCR1) 17.2.10 FIFO Data Count Register (SCFDR1)
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17.2.11 Line Status Register (SCLSR1) 17.3 Operation 17.3.1 Overview 17.3.2 Serial Operation 17.4 SCIF1 Interrupt Sources DMAC 17.5 Timing TDFST, RDFST, TEND Setting 17.6 Usage Notes.
Section Serial Communication Interface with FIFO (SCIF2)
18.1 Overview 18.1.1 Features 18.1.2 Block Diagrams. 18.1.3 Configuration 18.1.4 Register Configuration 18.2 Register Descriptions. 18.2.1 Receive Shift Register (SCRSR2). 18.2.2 Receive FIFO Data Register (SCFRDR2) 18.2.3 Transmit Shift Register (SCTSR2) 18.2.4 Transmit FIFO Data Register (SCFTDR2) 18.2.5 Serial Mode Register (SCSMR2). 18.2.6 Serial Control Register (SCSCR2). 18.2.7 Serial Status Register (SCSSR2). 18.2.8 Rate Register (SCBRR2). 18.2.9 FIFO Control Register (SCFCR2) 18.2.10 FIFO Data Count Register (SCFDR2) 18.3 Operation 18.3.1 Overview 18.3.2 Asynchronous Mode 18.3.3 Serial Operation Asynchronous Mode. 18.3.4 Synchronous Mode. 18.3.5 Serial Operation Synchronous Mode 18.4 SCIF2 Interrupt Sources DMAC 18.5 Usage Notes.
Section Function Module
19.1 19.2 19.3 19.4 19.5 Features Block Diagram. Configuration Register Configuration Register Descriptions. 19.5.1 USBEP0i Data Register (USBEPDR0I) 19.5.2 USBEP0o Data Register (USBEPDR0O) 19.5.3 USBEP0s Data Register (USBEPDR0S)
19.6
19.7 19.8
19.9 19.10
19.5.4 USBEP1 Data Register (USBEPDR1). 19.5.5 USBEP2 Data Register (USBEPDR2). 19.5.6 USBEP3 Data Register (USBEPDR3). 19.5.7 Interrupt Flag Register (USBIFR0) 19.5.8 Interrupt Flag Register (USBIFR1) 19.5.9 Trigger Register (USBTRG) 19.5.10 USBFIFO Clear Register (USBFCLR) 19.5.11 USBEP0o Receive Data Size Register (USBEPSZ0O) 19.5.12 Data Status Register (USBDASTS) 19.5.13 Endpoint Stall Register (USBEPSTL). 19.5.14 Interrupt Enable Register (USBIER0). 19.5.15 Interrupt Enable Register (USBIER1). 19.5.16 USBEP1 Receive Data Size Register (USBEPSZ1) 19.5.17 Interrupt Select Register (USBISR0) 19.5.18 Interrupt Select Register (USBISR1) 19.5.19 USBDMA Setting Register (USBDMAR). Operation 19.6.1 Cable Connection 19.6.2 Cable Disconnection 19.6.3 Control Transfer 19.6.4 Bulk-Out Transfer (Dual FIFOs) 19.6.5 Bulk-In Transfer (Dual FIFOs). 19.6.6 Interrupt-In Transfer. Processing Standard Commands Class/Vendor Commands 19.7.1 Processing Commands Transmitted Control Transfer Stall Operations 19.8.1 Overview 19.8.2 Forcible Stall Application 19.8.3 Automatic Stall Function Module Example External Circuitry. Usage Notes.
Section Compare Match Timer (CMT1)
20.1 Overview 20.1.1 Features 20.1.2 Block Diagram 20.1.3 Register Configuration 20.2 Register Descriptions. 20.2.1 Compare Match Timer Start Register (CMSTR1) 20.2.2 Compare Match Timer Control/Status Register (CMCSR1) 20.2.3 Compare Match Counter (CMCNT1) 20.2.4 Compare Match Constant Register (CMCOR1) 20.3 Operation
20.3.1 Interval Count Operation 20.3.2 CMCNT Count Timing 20.4 Compare Matches. 20.4.1 Timing Compare Match Flag Setting 20.4.2 Transfer Requests Interrupt Requests 20.4.3 Timing Compare Match Flag Clearing
Section Function Controller (PFC)
21.1 Overview 21.2 Register Configuration 21.3 Register Descriptions. 21.3.1 Port Control Register (PACR) 21.3.2 Port Control Register (PBCR) 21.3.3 Port Control Register (PCCR) 21.3.4 Port Control Register (PDCR) 21.3.5 Port Control Register (PECR). 21.3.6 Port Control Register (PFCR). 21.3.7 Port Control Register (PGCR) 21.3.8 Port Control Register (PHCR) 21.3.9 Port Control Register (PJCR) 21.3.10 Port Control Register (PKCR) 21.3.11 Port Control Register (PLCR). 21.3.12 Port Control Register (SCPCR)
Section Ports
22.1 Overview 22.2 Port 22.2.1 Register Description. 22.2.2 Port Data Register (PADR) 22.3 Port 22.3.1 Register Description. 22.3.2 Port Data Register (PBDR). 22.4 Port 22.4.1 Register Description. 22.4.2 Port Data Register (PCDR). 22.5 Port 22.5.1 Register Description. 22.5.2 Port Data Register (PDDR) 22.6 Port 22.6.1 Register Description. 22.6.2 Port Data Register (PEDR). 22.7 Port 22.7.1 Register Description.
22.7.2 Port Data Register (PFDR) 22.8 Port 22.8.1 Register Description. 22.8.2 Port Data Register (PGDR) 22.9 Port 22.9.1 Register Description. 22.9.2 Port Data Register (PHDR) 22.10 Port 22.10.1 Register Description. 22.10.2 Port Data Register (PJDR). 22.11 Port 22.11.1 Register Description. 22.11.2 Port Data Register (PKDR) 22.12 Port 22.12.1 Register Description. 22.12.2 Port Data Register (PLDR). 22.13 Port. 22.13.1 Register Description. 22.13.2 Port Data Register (SCPDR)
Section Converter
23.1 Overview 23.1.1 Features 23.1.2 Block Diagram 23.1.3 Input Pins 23.1.4 Register Configuration 23.2 Register Descriptions. 23.2.1 Data Registers (ADDRA ADDRD) 23.2.2 Control/Status Register (ADCSR) 23.2.3 Control Register (ADCR). 23.3 Master Interface 23.4 Operation 23.4.1 Single Mode (MULTI 23.4.2 Multi Mode (MULTI 23.4.3 Scan Mode (MULTI 23.4.4 Input Sampling Conversion Time 23.4.5 External Trigger Input Timing 23.5 Interrupts 23.6 Definitions Conversion Accuracy 23.7 Converter Usage Notes. 23.7.1 Setting Analog Input Voltage. 23.7.2 Processing Analog Input Pins 23.7.3 Access Size Read Data
Section Hitachi User Debug Interface (H-UDI)
24.1 Overview 24.2 Hitachi User Debug Interface (H-UDI). 24.2.1 Description. 24.2.2 Block Diagram 24.3 Register Descriptions. 24.3.1 Bypass Register (SDBPR) 24.3.2 Instruction Register (SDIR) 24.3.3 Boundary Scan Register (SDBSR). 24.4 H-UDI Operations 24.4.1 Controller. 24.4.2 Reset Configuration 24.4.3 H-UDI Reset. 24.4.4 H-UDI Interrupt 24.4.5 Bypass 24.5 Boundary Scan. 24.5.1 Supported Instructions 24.5.2 Notes 24.6 Notes 24.7 Advanced User Debugger (AUD)
Section Electrical Characteristics MHz)
25.1 Absolute Maximum Ratings. 25.2 Characteristics. 25.3 Characteristics. 25.3.1 Clock Timing 25.3.2 Control Signal Timing 25.3.3 Timing 25.3.4 Basic Timing 25.3.5 Burst Timing 25.3.6 Synchronous DRAM Timing 25.3.7 Peripheral Module Signal Timing 25.3.8 Module Signal Timing. 25.3.9 H-UDI-Related Timing 25.3.10 Converter Timing 25.3.11 Characteristics Measurement Conditions 25.3.12 Delay Time Variation Load Capacitance (Reference Values) 25.4 Converter Characteristics
Section Electrical Characteristics (100 MHz)
26.1 Absolute Maximum Ratings. 26.2 Characteristics. 26.3 Characteristics.
xiii
26.3.1 Clock Timing 26.3.2 Control Signal Timing 26.3.3 Timing 26.3.4 Basic Timing 26.3.5 Burst Timing 26.3.6 Synchronous DRAM Timing 26.3.7 Peripheral Module Signal Timing 26.3.8 Module Signal Timing. 26.3.9 H-UDI-Related Timing 26.3.10 Converter Timing 26.3.11 Characteristics Measurement Conditions 26.3.12 Delay Time Variation Load Capacitance (Reference Values) 26.4 Converter Characteristics
Appendix On-Chip Peripheral Module Registers
Address List.
Appendix Functions
States
Appendix Notes Consecutive Execution Multiply-Accumulate/ Multiplication Instructions Appendix Product Lineup Appendix Package Dimensions
Section Overview Functions
SH7622 Features
SH7622 RISC microprocessor with 32-bit RISC type SuperH architecture plus digital signal processing (DSP) extended functions core, also including cache memory, on-chip memory, interrupt controller necessary system configuration. High-speed data transfer provided on-chip DMAC (direct memory access controller), external memory access support functions allow direct connection various kinds memory. SH7622 also provided with powerful on-chip peripheral functions ideal system configuration, including function module serial communication interface with largecapacity built-in FIFOs. Powerful on-chip power management functions enable power consumption reduced even during high-speed operation. SH7622 ideally suited electronic devices other applications requiring high-speed operation together with power consumption. features SH7622 summarized table 1.1. Table
Item
SH7622 Features
Features Original Hitachi SuperH architecture Object code level upward compatibility with SH-1, SH-2, SH-DSP 32-bit internal data General register file Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers RISC-type instruction Fixed 16-bit instruction length excellent code efficiently Load-store architecture Delayed branch instructions C-based instruction Instruction execution time: Basic instructions execute cycle Address space: Gbytes Five-stage pipeline
Table
Item
SH7622 Features (cont)
Features 16-bit 32-bit instructions 32-/40-bit internal data Multiplier, ALU, barrel shifter, register file 16-bit 16-bit 32-bit 1-cycle multiplier Large-capacity data register file 32-bit data registers 40-bit data registers Extended Harvard architecture data buses data buses instruction Maximum parallel operations: ALU, multiply, load/store address units generating addresses memory accesses data addressing modes: Increment/decrement Zero-overhead repeat loop control Conditional execution instructions Clock modes: Choice external clock (EXTAL CKIO) crystal resonator input clock Three kinds clock generated clock clock Peripheral clock Power-down modes Standby mode Module standby mode Single-channel watchdog timer 8-kbyte cache, mixed instructions/data entries, 4-way set-associative, 16-byte block length Write-back, write-through, replacement algorithm Single-stage write-back buffer
Clock pulse generator (CPG)
Cache memory
Table
Item memory
SH7622 Features (cont)
Features Three independent read/write ports 8-/16-/32-bit access from Maximum 16-bit accesses from 8-kbyte on-chip memory Nine external interrupt pins (NMI, IRQ7 IRQ0) On-chip peripheral module interrupts: Priority level each module Auto vector mode supported external vector mode) Fixed vector numbers break channels Address, data value, access type, data size break conditions Supports sequential break function External memory space divided into areas (area areas each Mbytes, with following parameters settable each area: size bits) Number wait cycles (hardware wait function also supported) Direct connection SRAM, synchronous DRAM, burst possible designating memory connected each area Chip select signals (CS0, CS6) output relevant areas Synchronous DRAM refresh functions Programmable refresh interval Supports auto-refresh self-refresh modes Synchronous DRAM burst access function E10A emulator support arrangement conforming JTAG specification Realtime branch trace 1-kbyte on-chip high-speed emulation program execution 3-channel auto-reload 32-bit timer Input capture function (channel only) Choice counter input clocks
Interrupt controller (INTC)
User break controller (UBC)
state controller (BSC)
User debug interface (H-UDI)
Timer unit (TMU)
Table
Item
SH7622 Features (cont)
Features 16-bit counter Choice four counter input clocks interrupt request DMAC transfer request generated compare match Synchronous mode Simultaneous transmission/reception (full-duplex) capability, clock used both transmission reception transfer capability 128-byte transmit FIFO, 384-byte receive FIFO Synchronous mode Simultaneous transmission/reception (full-duplex) capability, clock used both transmission reception DMAC transfer capability 128-byte transmit receive FIFOs Choice synchronous mode asynchronous mode 16-byte transmit receive FIFOs transfer capability Four channels Burst mode cycle steal mode External request capability (channels only) Dual-function input/output ports switched between input output
Compare match timer (CMT1)
Serial communication interface (SCIF0)
Serial communication interface (SCIF1)
Serial communication interface (SCIF2) controller (DMAC)
ports
Table
Item function module
SH7622 Features (cont)
Features Conforms (Can connected Philips PDIUSBP11 Series transceiver compatible product (when using compatible product, carry evaluation investigation with manufacturer supplying transceiver beforehand), Supports Mbps full-speed transfer Supports control (endpoint bulk transfer (endpoints interrupt transfer (endpoint standard commands supported; class vendor commands processed software Built-in endpoint FIFO buffers (128 bytes endpoint) Supports transfer on-chip DMAC Module internal clock: bits LSB, four channels Input range: AVcc (max. I/O: internal: 1.75 2.05
converter Power supply voltage Product lineup
Product Operating Name Voltage Frequency SH7622
Product Code HD6417622FL80
Package 216-pin plastic LQFP (FP-216)
HD6417622BP80 208-pin TFBGA (TBP-208A) HD6417622F80 208-pin plastic (FP-208C)
HD6417622FL100 216-pin plastic LQFP (FP-216) HD6417622BP100 208-pin TFBGA (TBP-208A) HD6417622F80 208-pin plastic (FP-208C)
Block Diagram
Figure shows internal block diagram SH7622.
Y-bus
X-bus
XYCNT
SH-DSP
XYMEM L-bus
Peripheral
CACHE
I-bus
ASERAM
H-UDI SCIF0
SCIF1 DMAC Peripheral
CPG/WDT CMT0
SCIF2
CMT1
External interface ports
INTC
ADC: ASERAM: AUD: BSC: CACHE: CCN: CMT0: CMT1:
converter memory Advanced user debugger state controller Cache memory Cache memory controller Compare match timer Compare match timer
CPG/WDT: CPU: DMAC: INTC: SCIF: TMU: UBC: H-UDI:
Clock pulse generator/watchdog timer Central processing unit Direct memory access controller Interrupt controller Serial communication interface (with FIFO) Timer unit User break controller Hitachi user debug interface
Figure Block Diagram SH7622
1.3.1
Description
Arrangement
NC*1 EXTAL XTAL AUDCK/PTH[6] Vcc-PLL2*2 CAP2 Vss-PLL2*2 Vss-PLL1*2 CAP1 Vcc-PLL1*2 TXDMNS/PTF[0] TXDPLS/PTF[1] DPLS/PTF[2] DMNS/PTF[3] TCK/PTF[4] TDI/PTF[5] TMS/PTF[6] TRST/PTF[7] AUDATA[0]/PTG[0] AUDATA[1]/PTG[1] AUDATA[2]/PTG[2] AUDATA[3]/PTG[3] UCLK/PTG[4] ASEBRKAK/PTG[5] ASEMD0/PTG[6] PTG[7] ADTRG/PTH[5] RESEWAIT BREQ BACK TDO/PTE[0] PTE[1] RAS3U/PTE[2] PTE[3] PTE[6] DACK1/PTD[7] DACK0/PTD[5] NF/PTJ[5] NF/PTJ[4] VccQ CASU/PTJ[3] VssQ CASL/PTJ[2] NF/PTJ[1] RAS3L/PTJ[0] CKE/PTK[5] NC*1
NC*1 STATUS0/PTJ[6] STATUS1/PTJ[7] TCLK/PTH[7] IRQOUT VssQ CKIO VccQ TxD0/SCPT[0] SCK0/SCPT[1] TxD1/SCPT[2] SCK1/SCPT[3] TxD2/SCPT[4] SCK2/SCPT[5] SCPT[6] RxD0/SCPT[0] RxD1/SCPT[2] RxD2/SCPT[4] IRQ5/SCPT[7] IRQ6/PTC[7] IRQ7/PTC[6] XVDATA/PTC[5] TXENL/PTC[4] VssQ VBUS/PTD[3] VccQ SUSPND/PTD[2] NF/PTC[3] NF/PTC[2] NF/PTC[1] PTC[0] DRAK0/PTD[1] DRAK1/PTD[0] DREQ0/PTD[4] DREQ1/PTD[6] RESETP VccQ AVss AN[0]/PTL[0] AN[1]/PTL[1] AN[2]/PTL[2] AN[3]/PTL[3] PTL[4] PTL[5] AVcc PTL[6] PTL[7] AVss NC*1
SH7622 FP-216 (Top View)
INDEX
NC*1 PTE[5] PTE[4] CS5/PTK[3] CS4/PTK[2] CS3/PTK[1] CS2/PTK[0] VccQ VssQ AUDSYNC/PTE[7] RD/WR WE3/DQMUU/PTK[7] WE2/DQMUL/PTK[6] WE1/DQMLU WE0/DQMLL BS/PTK[4] VccQ VssQ VccQ VssQ VccQ VssQ NC*1
Notes: pins must connected ground, except No.5 pin, which should left open. Must connected power supply when on-chip used.
NC*1 NC*1 IRQ0/PTH[0] IRQ1/PTH[1] IRQ2/PTH[2] IRQ3/PTH[3] IRQ4/PTH[4] D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] VssQ D25/PTB[1] VccQ D24/PTB[0] D23/PTA[7] D22/PTA[6] D21/PTA[5] D20/PTA[4] D19/PTA[3] D18/PTA[2] D17/PTA[1] D16/PTA[0] VssQ VccQ VssQ VccQ NC*1
Figure Arrangement (FP-216)
SH7622 TBP-208A (Top View)
Note: area within dotted lines shows cutaway view pins.
Figure Arrangement (TBP-208A)
STATUS0/PTJ[6] STATUS1/PTJ[7] TCLK/PTH[7] IRQOUT VssQ CKIO VccQ TXD0/SCPT[0] SCK0/SCPT[1] TXD1/SCPT[2] SCK1/SCPT[3] TXD2/SCPT[4] SCK2/SCPT[5] SCPT[6] RXD0/SCPT[0] RXD1/SCPT[2] RXD2/SCPT[4] IRQ5/SCPT[7] IRQ6/PTC[7] IRQ7/PTC[6] XVDATA/PTC[5] TXENL/PTC[4] VssQ VBUS/PTD[3] VccQ SUSPND/PTD[2] NF/PTC[3] NF/PTC[2] NF/PTC[1] PTC[0] DRAK0/PTD[1] DRAK1/PTD[0] DREQ0/PTD[4] DREQ1/PTD[6] RESETP VccQ AVss AN[0]/PTL[0] AN[1]/PTL[1] AN[2]/PTL[2] AN[3]/PTL[3] PTL[4] PTL[5] AVcc PTL[6] PTL[7] AVss
EXTAL XTAL AUDCK/PTH[6] Vcc-PLL2*2 CAP2 Vss-PLL2*2 Vss-PLL1*2 CAP1 Vcc-PLL1*2 TXDMNS/PTF[0] TXDPLS/PTF[1] DPLS/PTF[2] DMNS/PTF[3] TCK/PTF[4] TDI/PTF[5] TMS/PTF[6] TRST/PTF[7] AUDATA[0]/PTG[0] AUDATA[1]/PTG[1] AUDATA[2]/PTG[2] AUDATA[3]/PTG[3] UCLK/PTG[4] ASEBRKAK/PTG[5] ASEMD0/PTG[6] PTG[7] PTH[5]/ADTRG RESEWAIT BREQ BACK TDO/PTE[0] PTE[1] RAS3U/PTE[2] PTE[3] PTE[6] DACK1/PTD[7] DACK0/PTD[5] NF/PTJ[5] NF/PTJ[4] VccQ CASU/PTJ[3] VssQ CASL/PTJ[2] NF/PTJ[1] RAS3L/PTJ[0] CKE/PTK[5]
SH7622 FP-208C (Top View)
INDEX
PTE[5] PTE[4] CS5/PTK[3] CS4/PTK[2] CS3/PTK[1] CS2/PTK[0] VccQ VssQ AUDSYNC/PTE[7] RD/WR WE3/DQMUU/PTK[7] WE2/DQMUL/PTK[6] WE1/DQMLU WE0/DQMLL BS/PTK[4] VccQ VssQ VccQ VssQ VccQ VssQ
Notes: should left open. Must connected power supply when on-chip used.
NC*1 IRQ0/PTH[0] IRQ1/PTH[1] IRQ2/PTH[2] IRQ3/PTH[3] IRQ4/PTH[4] D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] VssQ D25/PTB[1] VccQ D24/PTB[0] D23/PTA[7] D22/PTA[6] D21/PTA[5] D20/PTA[4] D19/PTA[3] D18/PTA[2] D17/PTA[1] D16/PTA[0] VssQ VccQ VssQ VccQ
Figure Arrangement (FP-208C)
1.3.2
Functions
Table summarizes functions. Table SH7622 Functions
FP-208C FP-216 TBP-208A Name NC*1, Vcc*3 NC*1, IRQ0/PTH[0] IRQ1/PTH[1] IRQ2/PTH[2] IRQ3/PTH[3] IRQ4/PTH[4] D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] VssQ*3 D25/PTB[1] VccQ*3 D24/PTB[0] D23/PTA[7] D22/PTA[6] D21/PTA[5] D20/PTA[4] Description Clock mode setting Clock mode setting Power supply (1.9 Power supply (1.9 Power supply Nonmaskable interrupt request External interrupt request/input port External interrupt request/input port External interrupt request/input port External interrupt request/input port External interrupt request/input port Data input/output port Data input/output port Data input/output port Data input/output port Data input/output port Data input/output port Input/output power supply Data input/output port Input/output power supply (3.3 Data input/output port Data input/output port Data input/output port Data input/output port Data input/output port
Table
SH7622 Functions (cont)
FP-208C
FP-216
TBP-208A
Name Vss*3 D19/PTA[3] Vcc*3 D18/PTA[2] D17/PTA[1] D16/PTA[0] VssQ*3 VccQ*3 VssQ*3 VccQ*3 NC*1, NC*1,
Description Power supply Data input/output port Power supply (1.9 Data input/output port Data input/output port Data input/output port Input/output power supply Data Input/output power supply (3.3 Data Data Data Data Data Data Data Data Data Input/output power supply Data Input/output power supply (3.3 Data Data Data Data Data Address Address
Table
SH7622 Functions (cont)
FP-208C
FP-216
TBP-208A
Name VssQ*3 VccQ*3 VssQ*3 VccQ*3 Vss*3 Vcc*3 VssQ*3
Description Address Address Input/output power supply Address Input/output power supply (3.3 Address Address Address Address Address Address Address Address Address Input/output power supply Address Input/output power supply (3.3 Address Address Address Address Address Address Address Power supply Address Power supply (1.9 Address Input/output power supply Address
Table
SH7622 Functions (cont)
FP-208C
FP-216
TBP-208A
Name VccQ*3 BS/PTK[4] WE0/DQMLL WE1/DQMLU WE2/DQMUL/ PTK[6] WE3/DQMUU/ PTK[7] RD/WR AUDSYNC/PTE[7] VssQ* VccQ*
O/IO O/IO O/IO O/IO O/IO O/IO O/IO O/IO
Description Input/output power supply (3.3 Address cycle start signal input/output port Read strobe D7-D0 select signal (SDRAM) D15-D8 select signal (SDRAM) D23-D16 select signal (SDRAM) input/output port D31-D24 select signal (SDRAM) input/output port Read/write synchronization input/output port Input/output power supply Chip select Input/output power supply (3.3 Chip select input/output port Chip select input/output port Chip select input/output port Chip select input/output port Chip select Input/output port Input/output port enable (SDRAM) input/output port Lower address (SDRAM) input/output port function/output port Lower address (SDRAM) input/output port Input/output power supply
CS2/PTK[0] CS3/PTK[1] CS4/PTK[2] CS5/PTK[3] PTE[4] PTE[5]
O/IO O/IO O/IO
CKE/PTK[5] RAS3L/PTJ[0] NF*6/PTJ[1] CASL/PTJ[2] VssQ*3
Table
SH7622 Functions (cont)
FP-208C
FP-216
TBP-208A
Name CASU/PTJ[3] VccQ*3 /PTJ[4] /PTJ[5] DACK0/PTD[5] DACK1/PTD[7] PTE[6] PTE[3] RAS3U/PTE[2] PTE[1] TDO/PTE[0] BACK BREQ WAIT RESEADTRG/PTH[5] PTG[7] ASEMD0/PTG[6] ASEBRKAK/PTG[5] UCLK/PTG[4] AUDATA[3]/PTG[3] AUDATA[2]/PTG[2] Vss*
O/IO O/IO O/IO O/IO
Description Upper address (SDRAM) input/output port Input/output power supply (3.3 function/output port function/output port acknowledge input/output port acknowledge input/output port Input/output port Input/output port Upper address (area DRAM, SDRAM) input/output port Input/output port Test data output input/output port acknowledge request Hardware wait request Manual reset request Analog trigger input port Input port mode input port break acknowledge input port external input clock input port data input port data input port Power supply data input port Power supply (1.9 data input port Test reset input port Test mode switch/ input port
AUDATA[1]/PTG[1] Vcc*
AUDATA[0]/PTG[0] TRST/PTF[7] TMS/PTF[6]
Table
SH7622 Functions (cont)
FP-208C
FP-216
TBP-208A
Name TDI/PTF[5] TCK/PTF[4] DMNS/ PTF[3] DPLS/ PTF[2] TXDPLS/ PTF[1] TXDMNS/ PTF[0] Vcc-PLL1*2 CAP1 Vss-PLL1*2 Vss-PLL2*2 CAP2 Vcc-PLL2*2 AUDCK/PTH[6] Vss*3 Vss*3 Vcc*3 XTAL EXTAL NC*1, NC*1, STATUS0/PTJ[6] STATUS1/PTJ[7] TCLK/PTH[7] IRQOUT VssQ* CKIO VccQ*
O/IO O/IO
Description Test data input/ input port Test clock/ input port input from receiver input port input from receiver input port transmit output input port transmit output input port Clock mode setting PLL1 power supply (1.9 PLL1 external capacitance PLL1 power supply PLL2 power supply PLL2 external capacitance PLL2 power supply (1.9 clock input port Power supply Power supply Power supply (1.9 Clock pulse generator External clock crystal oscillator Processor status input/output port Processor status input/output port clock input/output input/output port Interrupt request notification Input/output power supply System clock output Input/output power supply (3.3 Transmit data output port
TxD0/SCPT[0]
Table
SH7622 Functions (cont)
FP-208C
FP-216
TBP-208A
Name SCK0/SCPT[1] TxD1/SCPT[2] SCK1/SCPT[3] TxD2/SCPT[4] SCK2/SCPT[5] SCPT[6] RxD0/SCPT[0] RxD1/SCPT[2] Vss*3 RxD2/SCPT[4] Vcc*3 IRQ5/SCPT[7] IRQ6/PTC[7] IRQ7/PTC[6] XVDATA/PTC[5] TXENL/PTC[4] VssQ*
I/IO I/IO I/IO O/IO I/IO O/IO O/IO O/IO
Description Serial clock input/output port Transmit data output port Serial clock input/output port Transmit data output port Serial clock input/output port input/output port Receive data input port Receive data input port Power supply Receive data input port Power supply (1.9 External interrupt request input port External interrupt request input/output port External interrupt request input/output port differential receive signal input input/output port output enable input/output port Input/output power supply power supply detection input/output port Input/output power supply (3.3 suspend input/output port function output port function output port function input port Output port request acknowledge input/output port request acknowledge input/output port
VBUS/PTD[3] VccQ*3 SUSPND/PTD[2] NF*6/PTC[3] NF*6/PTC[2] NF*6/PTC[1] PTC[0] DRAK0/PTD[1] DRAK1/PTD[0]
Table
SH7622 Functions (cont)
FP-208C
FP-216
TBP-208A
Name DREQ0/PTD[4] DREQ1/PTD[6] RESETP VccQ*3 Vss*3 AVss*3 AN[0]/PTL[0] AN[1]/PTL[1] AN[2]/PTL[2] AN[3]/PTL[3] PTL[4] PTL[5] AVcc*3 PTL[6] PTL[7] AVss*3 NC*1,*4
Description request input/output port request input/output port Power-on reset request Input/output power supply (3.3 Area width setting Area width setting Power supply Analog power supply converter input input port converter input input port converter input input port converter input input port Input port Input port Analog power supply (3.3 Input port Input port Analog power supply
Notes: pins must connected ground, except (FP-216) (FP208C), which should left open. Must connected power supply when on-chip used. Vcc/Vss/VccQ/VssQ/AVcc/Avss pins must connected system power supply (Power must supplied constantly). Except No.5 FP-216, pins connected internally. system design must ensure that noise introduced onto VssQ pins. pins should left open when used output ports. exception PTC[1] pin, which pull-down connection should made.
Section
Register Configuration
register consists sixteen 32-bit general registers, 32-bit control registers 32bit system registers. SH7622 upwardly compatible with SH-1, SH-2 object code level. this reason, several registers have been added previous SuperH microcontroller registers. added registers three control registers: repeat start register (RS), repeat register (RE), modulo register (MOD) eight system registers: status register (DSR), among data registers. general registers used same manner SH-1, SH-2 with regard SuperH microcontroller-type instructions. With regard type instructions, they used address index registers accessing memory. 2.1.1 General Registers
There general registers (Rn) numbered R0-R15, which bits length. General registers used data processing address calculation. With SuperH microcomputer type instructions, also used index register. Several instructions limited only. used hardware stack pointer (SP). Saving recovering status register (SR) program counter (PC) exception processing accomplished referencing stack using R15. With type instructions, eight general registers used addressing data memory data memory (single data) using bus. used address register (Ax) memory accesses, used index register (Ix). used address register (Ay) memory accesses, used index register (Iy). used single data address register (As) accessing single data using bus, used single data index register (Is). type instructions simultaneously access data memory. There groups address pointers designating data memory addresses. Figure shows general registers.
R0*1 [As]*3 [As]*3 [As, Ax]*3 [As, Ax]*3 [Ay]*3 [Ay]*3 [Ix, Is]*3 [Iy]*3 R15, SP*2 Notes:
also functions index register indirect indexed register addressing mode indirect indexed addressing mode. some instructions, only functions source register destination register. functions hardware stack pointer (SP) during exception processing. Used memory address registers, memory index registers with type instructions.
Figure General Register Configuration With assembler, symbol names used wished name that makes clear role register type instructions, different register name (alias) used. This written following manner assembler.
.REG (R8)
name alias other aliases assigned follows:
Ax0: Ax1: Ay0: Ay1: As0: As1: As2: As3: .REG (R4) .REG (R5) .REG (R8) .REG (R6) .REG (R7) .REG (R9) .REG (R4) .REG (R5) .REG (R2) .REG (R3) .REG (R8) defined when alias required single data transfer defined when alias required single data transfer defined when alias required single data transfer defined when alias required single data transfer defined when alias required single data transfer
2.1.2
Control Registers
32-bit control registers consist status register (SR), repeat start register (RS), repeat register (RE), global base register (GBR), vector base register (VBR), modulo register (MOD). register indicates processing states. register functions base address indirect addressing mode, used such on-chip peripheral module register data transfers. register functions base address exception processing vector area (including interrupts). registers used program repeat (loop) control. repeat count designated register repeat counter (RC), repeat start address register, repeat address register. However, note that address values stored registers necessarily always same physical start address values repeat. register used modulo addressing buffer repeat data. modulo addressing designation made DMY, modulo address (ME) designated upper bits register, modulo start address (MS) designated lower bits. Note that bits cannot simultaneously designate modulo addressing. Modulo addressing possible with data transfer instructions (MOVX, MOVY). possible with single data transfer instructions (MOVS).
Figure shows control registers. Table indicates register bits.
Status register (SR) 0000 0000 Repeat start register (RS) Repeat register (RE) Global base register (GBR) Vector base register (VBR) Modulo register (MOD) Modulo address Modulo start address
Figure Control Register Configuration
Table
27-16
Register Bits
Name (Abbreviation) Repeat counter (RC) pointer usage modulo addressing designation (DMY) pointer usage modulo addressing designation (DMX) Interrupt request mask (I3-I0) Repeat flags (RF1, RF0) Function Designate repeat count (2-4095) repeat (loop) control modulo addressing mode becomes valid memory address pointer, (R6, modulo addressing mode becomes valid memory address pointer, (R4, Used DIV0S/U, DIV1 instructions Used DIV0S/U, DIV1 instructions Indicate receive level interrupt request Used zero overhead repeat (loop) control. below SETRC instruction step repeat RE-RS=-4 step repeat RE-RS=-2 step repeat RE-RS=0 steps more RE-RS>0
Saturation arithmetic
Used with instructions instructions Designates saturation arithmetic (prevents overflows) MOVT, CMP/cond, TAS, TST, BT/S, BF/S, SETT, CLRT instructions, represents false represents true ADDV/ADDC, SUBV/SUBC, DIV0U/DIV0S, DIV1, NEGC, SHAR/SHAL, SHLR/SHLL, ROTR/ROTL ROTCR/ROTCL instructions, represents occurrence carry, borrow, overflow underflow
31-28 15-12
always read out; write
There dedicated load/store instructions accessing registers. example, register accessed follows.
LDC.L STC.L Rm,RS; @Rm+,RS; RS,Rn; RS,@-Rn; RmRS (Rm)RS,Rm+4Rm RSRn Rn-4Rn,RS(Rn)
following instructions addresses registers zero overhead repeat control:
LDRS LDRE @(disp,PC); @(disp,PC); PCRS PCRE
2.2.1
Features Instructions
Fetching Decoding
SH7622 supports series mixed 16-bit 32-bit instructions. There restrictions order instructions within series mixed 16-bit 32-bit instructions. 2.2.2 Integer Unit
SH7622's integer unit extended SH-2 core functions supports operations. integer unit execute SH-1 SH-2 object code, upward-compatible with SH-3 object code. integer unit following features addition those SH-2 core. Dual addressing function: on-chip memories accessed simultaneously using main integer unit memory address calculation, separate 16-bit called pointer arithmetic unit (PAU) memory address calculation. Indexed addressing with pointer update function: addressing mechanism supports indexed addressing with automatic address pointer update function. address pointer automatically incremented decremented when consecutive words longwords accessed memory. addition, address pointer incremented specified index amount after each memory access. Modulo addressing: Modulo addressing useful implementing circular buffer. start modulo addresses specified control register. When address register incremented address value, automatically reset first address.
Zero-overhead loop control: integer unit supports zero-overhead program loops, which loop counter incrementing judgment completion loop performed automatically. These loops important high-speed applications. such loop, special registers used specify number repetitions instruction loop, loop start address address. processor then automatically executes loop specified number times. 2.2.3 System Registers
SH7622 four system registers, MACL, MACH, (figure 2.3).
MACH MACL
Multiply accumulate high registers (MACH/L) Store results multiplicationand accumulation operations. Procedure register (PR) Stores sbroutine procedure return address. Program counter (PC) Indicates starting address current instruction.
Figure System Registers DSR, registers also treated system registers. data transfer instructions between general registers system registers supported them. 2.2.4 Registers
SH7622 eight data registers control register (figure 2.4). data registers 32-bit width with exception registers Registers include guard bits (fields A1G), giving them total width bits. Three types operations access data registers. First data. When fixed-point data operation uses source register, uses guard bits (bits 39-32). When uses destination register, bits 39-32 guard valid. When fixed-point data operation uses registers other than source register, signextends source value bits 39-32. When uses them destination register, bits 39-32 result discard. Second data transfer operation, "MOVX.W MOVY.W". This operation accesses memories through 16-bit data buses (figure 2.8). Registers loaded stored this operation always upper bits (bits 31-16). destination
memory load destination memory load, other register cannot destination register this operation. When data read into upper bits register (bits 31-16), lower bits register (bits 15-0) automatically cleared. stored memory this operation, other registers cannot stored. Third single-data transfer instruction, "MOVS.W" "MOVS.L". This instruction accesses memory location through (figure 2.5). registers connect able source destination register data transfer. word longword access modes. word mode, registers loaded stored this instruction upper bits (bits 31-16) registers except A1G. When data loaded into register other than word mode, lower half register cleared. When data sign-extended bits 39-32 lower half cleared. When destination register word mode, data loaded into 8-bit register, cleared. longword mode, when destination register sign-extended bits 39-32. Tables show data type registers used instructions. Some instructions cannot some registers shown tables because instruction code limitation. example, PMULS source registers, cannot These tables ignore details register selectability. Table Destination Register Instructions
Guard Bits Registers data instruction Instructions Fixed-point, PSHA, PMULS Integer, PDMSB Logical, PSHL Data transfer MOVS.W MOVS.L A0G, Data transfer data instruction MOVS.W MOVS.L Fixed-point, PSHA, PMULS Integer, logical, PDMSB, PSHL Data transfer MOVX/Y.W, MOVS.W MOVS.L Register Bits
Sign-extended 40-bit result Sign-extended 24-bit result Cleared 16-bit result Cleared Cleared Cleared
Sign-extended 16-bit data Sign-extended 32-bit data Data Data update update 32-bit result 16-bit result 16-bit result 32-bit data
Cleared Cleared
Table
Source Register Operations
Guard Bits Register Bits
Registers data instruction
Instructions Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data transfer MOVX/Y.W, MOVS.W MOVS.L MOVS.W MOVS.L Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data transfer MOVS.W MOVS.L
40-bit data 24-bit data 16-bit data 16-bit data 32-bit data Data Data Sign* Sign* 32-bit data 16-bit data 16-bit data 16-bit data 32-bit data
A0G,
Data transfer data instruction
Note: Sign-extend data feed ALU.
Data Registers
[2:0] Status Register (DSR)
Reset status DSR: zeros Others: Undefined
Figure Registers
Table
31-8
Register Bits
Name (Abbreviation) Reserved bits Signed greater than (GT) Function Always read out; always write value Indicates that operation result positive (excepting that operand greater than operand Operation result positive, operand greater
Zero
Indicates that operation result zero (0), that operand equal operand Operation result zero (0), equivalence
Negative
Indicates that operation result negative, that operand smaller than operand Operation result negative, operand smaller
Overflow
Indicates that operation result overflowed Operation result overflowed
Status selection bits (CS) Designate mode selecting operation result status either 000: Carry/borrow mode 001: Negative value mode 010: Zero mode 011: Overflow mode 100: Signed greater mode 101: Signed above mode
status (DC)
Sets status operation result mode designated bits Designated mode status realized (unrealized) Designated mode status realized
MOVY.W MOVX.W MOVS.W, MOVS.L
MOVS.W, MOVS.L
Figure Connections Registers Buses unit control register Status Register (DSR). conditions data operation result (zero, negative, which similar CPU. indicates conditional flags. data processing instruction controls execution based bit. This control affects only operations unit; controls update registers only. cannot control operations CPU, such address register updating load/store operations. control CS[2:0] specifies condition reflect (table 2.5). unconditional type data operations, except PMULS, MOVX, MOVY MOVS, update conditional flags bit, instructions, including instructions, update bit. conditional type instructions update either. Table
[2:0]
Mode
Mode Carry borrow Negative Zero Overflow Signed greater than Signed greater than equal
assigned system register load/store instructions prepared follows:
DSR,Rn; STS.L DSR,@-Rn; Rn,DSR; LDS.L @Rn+,DSR;
When read instructions, upper bits (bit
2.3.1
Data Format
Data Format Registers (Non-DSP Type)
Register operands always longwords bits) (figure 2.6). When memory operand only byte bits) word bits), sign-extended into longword when loaded into register.
Longword
Figure Longword Operand 2.3.2 DSP-Type Data Format
SH7622 several different data formats that depend operations. This section explains data formats type instructions. Figure shows three DSP-type data formats with different binary point positions. CPU-type data format with binary point right also shown reference. DSP-type fixed point data format binary point between DSPtype integer format binary point between DSP-type logical format does have binary point. valid data lengths data formats depend operations registers.
type fixed point With guard bits Without guard bits Multiplier input 2-15 2-31 2-31
type integer With guard bits Without guard bits Shift amount arithmetic shift (PSHA) Shift amount logical shift (PSHL) -215 +215 -223 +223
type logical
type integer Longword
-231 +231
Sign
Binary point
Does affect operations
Figure Data Format Shift amount arithmetic shift (PSHA) instruction 7-bit filed that could represent +63, however valid number operation. Also shift amount logical shift operation 6-bit field, however valid number instruction.
2.3.3
Data Format Memory
Memory data formats classified into bytes, words, longwords. Byte data accessed from address, address error will occur word data starting from address other than longword data starting from address other than accessed. such cases, data accessed cannot guaranteed (figure 2.8).
Address Address Address Address Address Byte Byte Address
Address Byte Byte
Word Longword
Word
Big-endian mode
Figure Byte, Word, Longword Alignment
Section Operation
3.1.1
Data Operations Unit
Fixed-Point Operations
Figure shows arithmetic operation flow. Table shows variation this type operation table shows flexibility each operand.
Guard Source
Guard Source
Destination Guard
Figure Fixed-Point Arithmetic Operation Flow Note: fixed-point arithmetic operations basically 40-bit operation; bits base precision bits guard-bit parts. signed copied guard-bit parts when register providing guard-bit parts specified source operand. When register providing guard-bit parts destination operand, lower bits operation result input into destination register. fixed-point operations executed between registers. Each source destination operand selected independently from registers. When register providing guard bits specified operand, guard bits activated this type operation. These operations executed final stage pipeline sequence, named stage, shown figure 3.2.
Table
Mnemonic PADD PSUB PADDC PSUBC PCMP PCOPY
Variation Fixed-Point Operation
Function Addition Subtraction Addition with carry Subtraction with borrow Comparison Data copy Source Source Destination (Du) (Du)
PABS
Absolute
PNEG
Negation
PCLR
Clear
Table
Register
Operand Flexibility
shown figure 3.2, loaded data from memory stage, which programmed same line operation, used source operand this operation, even though destination operand memory read operation identical source operand operation. this case, previous operation results used source operands operation then, updated destination operand data load operation.
PADD Slot Stage
MOVX.W @(R4, R8), MOVX.W @R4+, MOVX MOVX MOVX MOVX Addressing Addressing MOVX MOVX Previous cycle result used.
Figure Operation Sequence Example Every time arithmetic operation executed, bits register basically updated accordance with operation result. However, case conditional operation, they updated even though specified condition true operation executed. case unconditional operation, they always updated accordance with operation result. definition selected CS0-2 (condition selection) bits register. result follows: Carry Borrow Mode: [2:0] 000: indicates that carry borrow generated from most significant operation result, except guard-bit parts. Some examples shown figure 3.3. This mode default condition. Negative Value Mode: [2:0] 001: flag indicates same state operation result. When result negative number, shows When positive number, shows always executes 40-bit arithmetic operation, sign detect whether positive negative always from operation result regardless destination operand. Some examples shown figure 3.4.
Example Guard bits 0000 0000 1111111111111111 0000 0000 0000 0000 0000 0001 0000 0001 0000 0000 0000 0000 Carry detecting point Carry detected.
Example Guard bits 111111110111 0000 0000 0000 0011 11110001 0000 0000 0000 0011 11101000 0000 0000 0000 Carry detecting point Carry detected.
Example Guard bits 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0001 1100 0000 0000 0000 0000 0001 Borrow detecting point Borrow detected.
Example Guard bits 0000 0000 0001 0000 0000 0001 0000 0000 0001 0000 0000 0010 111111111111111111111111 Borrow detecting point Borrow detected.
Figure Generation Examples Carry Borrow Mode
Example Guard bits 1100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1100 0000 0000 0000 0000 0001 Sign Negative value Example Guard bits 0011 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0001 0011 0000 1000 0000 0000 0001 Sign Positive value
Figure Generation Examples Negative Value Mode Zero Value Mode: [2:0] 010: flag indicates whether operation result not. When result shows When shows Overflow Mode: [2:0] 011: indicates whether overflow occurs result. When operation yields result beyond range destination register, except guard-bit parts, set. Even though guard bits provided, always indicates result guard bits provided case. always guard-bit parts used large number representation. Some flag detection examples shown figure 3.5.
Example Guard bits 1111 1111 1111 1111 1111 1111 1111 1111 1000 0000 0000 0000 1111 1111 0111 1111 1111 1111 Overflow detecting field Overflow case
Example Guard bits 1111 1111 1111 1111 1111 1111 1111 1111 1000 0000 0000 0001 1111 1111 1000 0000 0000 0000 Overflow detecting field overflow case
Figure Generation Examples Overflow Mode Signed Greater Than Mode: [2:0] 100: indicates whether source data (signed) greater than source data (signed) result compare operation PCMP. `PCMP' operation should executed advance when conditional operation executed under this condition mode. This mode similar Negative Value Mode described before, because result compare operation usually positive value source data greater than source data. However, signed result shows negative value compare operation yields result beyond range destination operand, including guard-bit parts (called "Over-range"), even though source data greater than source data. updated concerning this type special case this condition mode. equation below shows definition getting this condition:
{(Negative Over-range) Zero}
When PCMP operation executed under this condition mode, result same result PCMP/GT operation core instruction. Signed Greater Than Equal Mode: [2:0] 101: indicates whether source data (signed) greater than equal source data (signed) result compare operation. `PCMP' operation should executed advance when conditional operation executed under this condition mode. This mode similar Signed Greater Than Mode described before equal case also included this mode. equation below shows definition getting this condition:
(Negative Over-range)
When PCMP operation executed under this condition mode, result same result PCMP/GE operation core instruction. always indicates same state which CS[2:0] bits negative value mode. negative value mode part above. always indicates same state which CS[2:0] bits zero value mode. zero value mode part above. always indicates same state which CS[2:0] bits overflow mode. overflow mode part above. always indicates same state
which CS[2:0] bits signed greater than mode. signed greater than mode part above. Note: always updated carry flag `PADDC' always updated borrow flag `PSUBC' regardless CS[2:0] state. Overflow Protection: register effective fixed-point arithmetic operations unit. section 3.1.8, Overflow Protection, details. 3.1.2 Integer Operations
Figure shows integer arithmetic operation flow. Table shows variation this type operation. flexibility each operand same fixed-point operations shown table 3.2.
Guard Source Guard Source
Ignored Cleared
Destination Guard
Figure Integer Arithmetic Operation Flow
Table
Mnemonic PINC
Variation Integer Operation
Function Increment Source Source Destination
PDEC
Decrement
Note: integer operations basically 24-bit operation, upper bits base precision bits guard-bits parts. signed copied guard-bit parts when register providing guard-bit parts specified source operand. When register providing guard-bit parts destination operand, lower bits operation result input into destination register.
integer arithmetic operations, lower word source operand ignored lower word destination operand automatically cleared. guard-bit parts effective integer arithmetic operations they supported. Others basically same operation fixed-point arithmetic operations. shown table 3.3, however, this type operation provides kinds instructions only, that second operand actually either When word data loaded into unit's registers, input upper word data. reasonable increment decrement operations execute using upper word unit. When register providing guard bits specified operand, guard bits also activated. These operations executed final stage pipeline sequence, named stage, shown figure 3.2, well fixed-point operations. Every time arithmetic operation executed, bits register basically updated accordance with operation result. This same fixedpoint operations lower word each source destination operand used order generate them. section 3.1.1, Fixed-Point Operations, details. case conditional operation, they updated even though specified condition true operation executed. case unconditional operation, they always updated accordance with operation result. section 3.1.1, Fixed-Point Operations, details. Overflow Protection: register effective integer arithmetic operations unit. section 3.1.8, Overflow Protection, details.
3.1.3
Logical Operations
Figure shows logical operation flow. Table shows variation this type operation. flexibility each operand same fixed-point operations shown table 3.2. note section 3.1.1, Fixed-Point Operations. Logical operations also executed between registers. Each source destination operand selected independently from registers. shown figure 3.7, this type operation uses upper word each operand only. Lower word guard-bit parts ignored source operand those destination operand automatically cleared. These operations also executed final stage pipeline sequence, named stage, shown figure 3.2.
Guard Soruce Guard Source
Ignored Cleared
Destination Guard
Figure Logical Operation Flow Table
Mnemonic PAND PXOR
Variation Logical Operation
Function Logical Logical Logical exclusive Source Source Destination
Every time logical operation executed, bits register basically updated accordance with operation result. case conditional operation, they updated even though specified condition true operation executed. case unconditional operation, they always updated accordance with operation result. definition selected CS0-2 (condition selection) bits register. result Carry Borrow Mode: [2:0] always cleared. Negative Value Mode: [2:0] 31st operation result loaded into bit. Zero Value Mode: [2:0] when operation result zeros, otherwise cleared. Overflow Mode: [2:0] always cleared. Signed Greater Than Mode: [2:0] always cleared. Signed Greater Than Equal Mode: [2:0] always cleared. always indicates same state which CS[2:0] bits negative value mode. negative value mode part above. always indicates same state which CS[2:0] bits zero value mode. zero value mode part above. always indicates same state which CS[2:0] bits overflow mode. overflow mode part above. always indicates same state which CS[2:0] bits signed greater than mode. signed greater than mode part above. following restriction applies PXOR instruction. PXOR both upper word upper word equal, zero flag DSR) will set. zero mode this time (DSR.CS[2:0] 010), will set. 3.1.4 Fixed-Point Multiply Operation
Figure shows multiply operation flow. Table shows variation this type operation table shows flexibility each operand. multiply operation unit single-word signed single-precision multiplication. double-precision multiply operation needed, possible make SH-2's standard double-word multiply instructions.
Guard Source
Guard Source
Ignored
Guard
Destination
Figure Fixed-Point Multiply Operation Flow Table
Mnemonic PMULS
Variation Fixed-Point Multiply Operation
Function Signed multiplication Source Source Destination
Table
Register
Operand Flexibility
Note: multiply operations basically generates bits operation result. when register providing guard-bit parts specified destination operand, guard-bit parts will copy 32nd (MSB) operation result.
multiply operation unit side integer fixed-point arithmetic. upper words each multiplier multiplicand input into unit shown figure 3.8. SH's standard multiply operations, lower words both source operands input into unit. operation result also different from SH's case. SH's multiply operation result aligned destination, fixed-point multiply operation result aligned MSB, that fixed-point multiply operation result always This fixed-point multiply operation executed cycle using bits 8-bit unit. other SH's multiply operations executed SH-2's are. Multiply operation doesn't affect condition code bits, register. Overflow Protection: register effective this multiply operation unit. section 3.1.8, Overflow Protection, details. `0', there only case occur overflow when H'8000*H'8000, (-1.0)*(-1.0), operation executed signed signed fixed-point multiply. result H'8000 0000 means (+1.0) (-1.0). `1', protects overflow result H'00 7FFF FFFF. 3.1.5 Shift Operations
Shift operations either register immediate value shift amount operand. Other source destination operands specified register. There kinds shift operations. Table shows variations this type operation. flexibility each operand, except immediate operands, same fixed-point operations shown table 3.2. section more detailed information about each instruction operand. note section 3.1.1, Fixed-Point Operations. Table
Mnemonic PSHA PSHL PSHA #Imm, PSHL #Imm,
Variation Shift Operations
Function Arithmetic shift Logical shift Arithmetic shift w/imm. Logical shift w/imm. Source Source Imm1 Imm2 Destination
Imm1 +32, Imm2
Arithmetic Shift: Figure shows arithmetic shift operation flow.
affected
Left Shift
(MSB copy)
Right Shift
Shift
Shift
Updated
Shift amount data: (Source
Imm1
Figure Shift Operation Flow Note: arithmetic shift operations basically 40-bit operation, bits base precision bits guard-bit parts. signed copied guard-bit parts when register providing guard-bit parts specified source operand. When register providing guard-bit parts destination operand, lower bits operation result input into destination register. this arithmetic shift operation, full size source destination operands activated. shift amount specified source operand integer data. source operand specified either register immediate operand. Available shift range from +32. Here, negative value means right shift, positive value means left shift. It's possible source operand specify from result unknown invalid shift value specified. case shift with immediate operand instruction, source operand must same register destination's. This operation executed final stage pipeline sequence, named stage, shown figure well fixed-point operations. Every time arithmetic shift operation executed, bits register basically updated accordance with operation result. case conditional operation, they updated even though specified condition true operation executed. case unconditional operation, they always updated accordance with operation result. definition selected CS0-2 (condition selection) bits register. result Carry Borrow Mode: [2:0] indicates last shifted data operation result. Negative Value Mode: [2:0] Same definition fixed-point arithmetic operations.
Zero Value Mode: [2:0] Same definition fixed-point arithmetic operations. Overflow Mode: [2:0] Same definition fixed-point arithmetic operations. Signed Greater Than Mode: [2:0] always cleared. Signed Greater Than Equal Mode: [2:0] always cleared. always indicates same state which [2:0] bits negative value mode. negative value mode part above. always indicates same state which [2:0] bits zero value mode. zero value mode part above. always indicates same state which [2:0] bits overflow mode. overflow mode part above. always indicates same state which [2:0] bits signed greater than mode. signed greater than mode part above. Overflow Protection: register also effective arithmetic shift operation unit. section 3.1.8, Overflow Protection, details. Logical Shift: Figure 3.10 shows logical shift operation flow.
affected
Left Shift
Right Shift
Shift
Shift
Cleared Shift amount data: (Source
Updated
Imm2
Figure 3.10 Logical Shift Operation Flow shown figure 3.10, logical shift operation uses upper word source destination operands. lower word guard-bit parts ignored source operand those destination operand automatically cleared logical operations. shift amount specified source operand integer data. source operand specified either register immediate operand. Available shift range from +16. Here, negative value means right shift, positive value means left shift. It's possible source
operand specify from result unknown invalid shift value specified. case shift with immediate operand instruction, source operand must same register destination's. These operations executed final stage pipeline sequence, named stage, shown figure 3.2. Every time logical shift operation executed, bits register basically updated with operation result bits always cleared. case conditional operation, they updated, even though specified condition true operation executed. case unconditional operation, they always updated with operation result. definition selected CS0-2 (condition selection) bits register. result Carry Borrow Mode: [2:0] indicates last shifted data operation result. Negative Value Mode: [2:0] Same definition logical operations. Zero Value Mode: [2:0] Same definition logical operations. Overflow Mode: [2:0] always cleared. Signed Greater Than Mode: [2:0] always cleared. Signed Greater Than Equal Mode: [2:0] always cleared. always indicates same state which CS[2:0] bits negative value mode. negative value mode part above. always indicates same state which CS[2:0] bits zero value mode. zero value mode part above. always indicates same state which CS[2:0] bits overflow mode always cleared this operation. bit. PSHA instruction have been after should have been, should used. Also, PSHA instruction should used overflow mode (DSR.CS[2:0] 011).
3.1.6
Most Significant Detection Operation
`PDMSB', most significant detection operation, used calculate shift amount normalization. Figure 3.12 shows `PDMSB' operation flow table shows operation definition. Table shows possible variations this type operation. flexibility each operand same fixed-point operations, shown table 3.2. note section 3.1.1, Fixed-Point Operations. Note: result priority encode operation basically bits well integer operation, upper bits base precision bits guard-bit parts. When register providing guard-bit parts destination operand, lower bits operation result input into destination register. shown figure 3.11, `PDMSB' operation uses full-size data source operand, destination operand treated integer operation result because shift amount data normalization should integer data described section 3.1.5 (Arithmetic Shift). These operations executed final stage pipeline sequence, named stage, shown figure 3.11. Every time `PDMSB' operation executed, bits register basically updated with operation result. case conditional operation, they updated, even though specified condition true, operation executed. case unconditional operation, they always updated with operation result.
Guard Source
Priority encoder
Destination Guard
Cleared
Figure 3.11 `PDMSB' Operation Flow
definition selected CS0-2 (condition selection) bits register. result Carry Borrow Mode: [2:0] always cleared. Negative Value Mode: [2:0] Same definition integer arithmetic operations. Zero Value Mode: [2:0] Same definition integer arithmetic operations. Overflow Mode: [2:0] always cleared. Signed Greater Than Mode: [2:0] Same definition integer arithmetic operations. Signed Greater Than Equal Mode: [2:0] Same definition integer arithmetic operations.
Table
Operation Definition `PDMSB'
Data Result Lower Word Guard Upper Word
Guard
Upper Word
7g-0g 31-22 Decimal
Note: Don't care.
Table
Mnemonic PDMSB
Variation `PDMSB' Operations
Function detection Source Source Destination
always indicates same state which [2:0] bits negative value mode. negative value mode part above. always indicates same state which [2:0] bits zero value mode. zero value mode part above. always indicates same state which [2:0] bits overflow mode. overflow mode part above. always indicates same state which [2:0] bits signed greater than mode. signed greater than mode part above. 3.1.7 Rounding Operation
unit provides rounding function that rounds from bits bits. case providing guard-bit parts, rounds from bits bits. When round instruction executed, H'00008000 added source operand data then, lower word cleared. Figure 3.12 shows rounding operation flow figure 3.13 shows operation definition. Table 3.10 shows variation this type operation. flexibility each operand same fixed-point operations shown table 3.2. note section 3.1.1, Fixed-Point Operations. shown figure 3.12, rounding operation uses full-size data both source destination operands. These operations executed final stage pipeline sequence, named stage shown figure 3.2. rounding operation always executed unconditionally, that bits register always updated accordance with operation result. definition selected CS0-2 (condition selection) bits register. These condition code result same ALU-fixed point arithmetic operations.
Guard Source
h'00008000
Addition
Destination Guard
Figure 3.12 Rounding Operation Flow
h'00 0002 Rounded result h'00 0001
Analog value True value
Figure 3.13 Definition Rounding Operation Table 3.10 Variation Rounding Operations
Mnemonic PRND Function Rounding Source Source Destination
Overflow Protection: register effective rounding operations unit. section 3.1.8, Overflow Protection, details.
3.1.8
Overflow Protection
register effective arithmetic operations executed unit, including conventional SH's multiply operations. register, SH's core, used overflow protection enable bit. arithmetic operation overflows when operation result exceeds range two's complement representation without guard-bit parts. Table 3.11 shows definition overflow protection fixed-point arithmetic operations, including fixed-point signed signed multiplication described section 3.1.4, Fixed-Point Multiply Operation. Table 3.12 shows definition overflow protection integer arithmetic operations. When SH's conventional multiply operation executed, function completely same current SH-2's definition. When overflow protection effective, course overflow never occurs. never also never when overflow mode selected [2:0] bits. Table 3.11 Definition Overflow Protection Fixed-Point Arithmetic
Sign Positive Negative Overflow Condition Result Result
Fixed Value
Representation 7FFF FFFF 8000 0000
Table 3.12 Definition Overflow Protection Integer Arithmetic
Sign Positive Negative Note: Don't care. Overflow Condition Result Result
Fixed Value
Representation 7FFF **** 8000 ****
3.1.9
Data Transfer Operation
SH7622 execute maximum data transfer operations between register on-chip data memory parallel unit. This results almost same performance other DSPs. SH7622 provides three types data transfer instructions unit. Parallel operation type (using YDB) Double data transfer type (using YDB) Single data transfer type (using LDB) type instructions execute both data processing data transfer operations parallel. 32-bit instruction code used this type instruction. Basically, data transfer operations specified this type instruction, they don't always have specified. data transfer memory another memory. Both these data transfer operations
cannot executed memory. Load operation memory specify either register memory specify either register destination operand. Both store operations memories specify either register source operand. This type operation treats word data only. When word data transfer operation executed, upper word register operand activated. case word data load, data loaded into upper word destination register, then lower side destination automatically cleared. When conditional operation specified data processing operation, specified condition also doesn't affect data transfer operations. Figure 3.14 shows this type data transfer operation flow. This type data transfer operation access memory only. other memory space cannot accessed.
pointer (R4,
pointer (R6,
[15:1]
[15:1]
memory (RAM, ROM)
memory (RAM, ROM)
[15:0]
[15:0]
affected store, cleared load
Cannot available
Figure 3.14 Data Transfer Operation Flow Type instructions execute just data transfer operations. 16-bit instruction code used this type instructions. Basically, operation operand flexibility same type conditional operation supported. This type data transfer operation also access memory only. other memory space cannot accessed.
Type instructions execute single data transfer operations only. 16-bit instruction code used this type instructions. pointers other extra pointers available this type operation pointers available. This type operation access memory address space, registers unit, except DSR, specified both source destination operands. guard-bit registers, A1G, also specified independent registers. this type operation, used instead XAB, XDB, save hardware, that conflict might occur between data transfer instruction fetch. This type operation treat both single-word data longword data. When word-data transfer operation executed, upper word register operand activated. case word data load, data loaded into upper word destination register, lower side destination automatically cleared signed copied into guard-bit parts, supported. case longword data load, data loaded into upper word lower word destination register signed copied into guard-bit parts, supported. case guard register store, sign copied upper bits LDB. Figures 3.15 3.16 show this type data transfer operation flows.
Pointer (R2,
[31:0]
memory areas
[15:0]
affected store, cleared load Note
Cannot available
Figure 3.15 Word Data-Transfer Operation Flow
Pointer (R2,
[31:0]
memory areas
[31:0]
Cannot available
Figure 3.16 Longword Data-Transfer Operation Flow data transfer operations executed stage pipeline data processing operations execute stage. When store instruction written following step corresponding data processing instruction, stall cycle generated order execute properly because data processing operation completed when following data store operation starts execution. instruction should inserted between data processing instruction data store instruction shown figure 3.17 order avoid such overhead cycle.
PADD
MOVX.W @R4+ MOVX.W @R5, MOVX.W @R4+ MOVX MOVX MOVX
step another operation inserted between data processing store operations. MOVX MOVX Addressing MOVX Addressing MOVX Addressing MOVX MOVX
Stage
Slot
Figure 3.17 Instruction Sequence Example Between Data Processing Store data transfer operations don't update condition code bits register. When guard-bit register, A1G, specified destination operand word data load operation, `MOVS.W', word data input into lower register. register loaded using both MOVS.L LDS(.L)/STS(.L). Both operation completely same module.
3.1.10
Local Data Move Operation
unit SH7622 provides additional independent registers, MACL MACH, order support conventional SH-2's multiply/MAC operations. They also used temporary storage registers. Local data move instruction between MACH/L other registers make this benefit. Figure 3.18 shows flow seven local data move instructions. Table 3.13 shows variation this type instruction.
MACH MACL
PSTS
PLDS
Cannot available
Figure 3.18 Local Data Move Instruction Flow Table 3.13 Variation Local Data Move Operation
Mnemonic PLDS PSTS Function Data Move from reg. MACL/H Data Move from MACL/H reg.
Operand
This instruction very similar other transfer instruction. registers specified destination operand PSTS, signed copied into corresponding guard-bit parts, A1G. other condition code bits updated based upon instruction result. This instruction operate conditionally. Note: Basically, local data move operation specified with MOVX MOVY parallel. However, MOVX this local data move operation same hardware resource, cycle overhead inserted when both specified same instruction line.
3.1.11
Operand Conflict
When identical destination operand specified with multiple parallel operations, data conflict occurs. Table 3.14 shows operand flexibility each operation. Table 3.14 Operand Flexibility
X-Side Load register Notes: Operand confliction case Available regs (for operand) Y-Side Load 6-Inst. 6-Inst. Multi 3-Inst. 3-Inst. Multi
There three cases operand conflict problems. Actual hardware will avoid conflict ignoring either even though such instruction code issued. When multiply instructions specify same destination operand Dg), instruction executed normally multiplier instruction ignored. When X-side load instructions specify same destination operand (Dx, Dz), instruction executed normally X-side load instruction ignored. When Y-side load instructions specify same destination operand (Dy, Dz), instruction executed normally Y-side load instruction ignored. these cases above, result unknown destination register specs. Note: When PLDS instruction specified parallel with X-side load instruction, kind conflict occurs. However, treated operand conflict resource conflict because both instructions have same internal module, that conflict always occurs even though specified operand different.
3.2.1
Addressing
Loop Control
SH7622 prepares special control mechanism efficient loop control. instruction `SETRC' sets repeat times into repeat counter bits), execution mode which program loop executes repetitively until equal `1'. After completion repeat instructions, contents becomes Repeat start address register keeps start address repeat loop. Repeat register keeps repeat address (There some exceptions. note, "Actual Implementation Options"). Repeat counter keeps number repeat times. order make this loop control, following steps required. Step Step Step Step loop start address into loop address into repeat counter into Start repeat control
steps instructions:
LDRS @(disp,PC); LDRE @(disp,PC);
steps instruction, SETRC. operand SETRC immediate value general-purpose registers that will specify repeat times.
SETRC #imm; SETRC #imm->RC, enable repeat control Rm->RC, enable repeat control
#imm bits while bits. Therefore, more than into sample program shown below.
LDRS LDRE SETRC RptStart; RptEnd3+4; #imm; #imm
instr0; instr1-5 executes repeatedly RptStart: RptEnd3: instr1; instr2; instr3; instr4;
RptEnd:
instr5; instr6;
this implementation, there some restrictions this repeat controls follows: There must least instruction between SETRC first instruction repeat loop. LDRS LDRE must executed before SETRC. case that repeat loop four more instructions stall cycle necessary each iteration repeat start address (address instr1 above example) longword boundary. repeat loop less than four instructions have branch instructions (BRA, BSR, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JMP), repeat control instructions (SETRC, LDRS LDRE), load instructions TRAPA these instructions written, reserved instruction code exception executed certain address value shown table 3.15 stored into SPC. Table 3.15 Address Value Stored into
Condition RC>=2 RC=1 Location Address Pushed RptStart Prog. addr. illegal inst.
repeat loop four more instructions branch instructions (BRA, BSR, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JMP), repeat control instructions (SETRC, LDRS LDRE), load instructions TRAPA must written within last three instructions from bottom repeat loop. written, reserved instruction code exception executed certain address value shown table 3.16 stored into SPC. cases repeat control instructions (SETRC, LDRS LDRE) load instructions TRAPA they cannot placed other location repeat module, either. they are, operation guaranteed. Table 3.16 Address Value Stored into
Condition RC>=2 Location instr3 instr4 instr5 RC=1 Address Pushed Prog. addr. illegal inst. RptStart RptStart Prog. addr. illegal inst.
repeat loop less than four instructions relative instructions (MOVA @(disp,PC), etc.) don't work properly except instruction repeat (instr1). repeat loop four more instructions relative instructions (MOVA @(disp,PC), etc.) don't work properly instructions from repeat bottom. repeat enable flag, however uses condition disable repeat control. Whenever matches repeat control alive. When repeat control disabled repeat loop executed once does return repeat start well case. When repeat loop executed once does return repeat start becomes after completing execution repeat loop. repeat loop more than three instructions branch instructions, including subroutine call return instructions, cannot specify instruction from "inst3" "inst5" previous example branch target address. executed, repeat control doesn't work program through following instruction also updated. When repeat loop less than four instructions repeat control doesn't work properly contents register updated branch target "RptStart" subsequent address. Interrupt acceptance restricted during repeat loop processing. figure 3.19 detail restrictions. Here, flow each case figure 3.19 shows stages. Usually interrupt starts right after instruction's stage finished. These specified figure. However, point specified "B", interrupt accepted. release start delayed until repeat loop. This prevented follows: When instructions located external memory cache memory, least four instructions loop. When instructions located memory, place instruction that does access memory address loop. there problem with having release start delayed until repeat loop, this restriction irrelevant.
Acceptable interrupts acceptable interrupts RC>=1 cases, step repeat instr0 Start(End): instr1 instr2
step repeat instr0 Start: instr1 End: instr2 instr3
Three step repeat instr0 Start: instr1 instr2 End: instr3 instr4
Four more steps repeat instr0 Start: instr1 instr instr instr End: instr instr
(When return from instr
RC=0 case, Acceptable interrupts
Figure 3.19 Restriction Interrupt Acceptance Repeat Loop
Note Actual Implementation Repeat start repeat registers, keep repeat start address repeat address. addresses that kept these registers depend number instructions repeat loop. rule follows, Repeat_Start: address instruction repeat Repeat_Start0: address instruction before instruction repeat Repeat_End3: address instruction before three instruction repeat bottom Table 3.17 Setting Rule
Number Instructions Repeat Loop Repeat_start0 Repeat_start0 Repeat_start0 Repeat_start0 Repeat_start0 Repeat_start0 Repeat_start Repeat_End3+4
Based this table, actual repeat programming various cases should described following examples: CASE Repeated Instruction
LDRS LDRE RptStart0+8; RptStart0+4;
SETRC RptCount; RptStart0: RptStart: instr0; instr1; instr2; Repeated instruction
CASE Repeated Instructions
LDRS LDRE RptStart0+6; RptStart0+4;
SETRC RptCount; RptStart0: RptStart: RptEnd: instr0; instr1; instr2; instr3; Repeated instruction Repeated instruction
CASE Repeated Instructions
LDRS LDRE RptStart0+4; RptStart0+4;
SETRC RptCount; RptStart0: RptStart: instr0; instr1; instr2; RptEnd: instr3; instr4; Repeated instruction Repeated instruction Repeated instruction
CASE more Repeated Instructions
LDRS LDRE RptStart; RptEnd3+4;
SETRC RptCount; RptStart0: RptStart: instr0; instr1; instr2; instr3; Repeated instruction Repeated instruction Repeated instruction
-RptEnd3: instrN-3; instrN-2; instrN-1; RptEnd: instrN; instrN+1; Repeated instruction Repeated instruction Repeated instruction Repeated instruction
examples above used template program this repeat loop sequences. However, easy programming, extended instruction "REPEAT" will provided handle these complex labeling offset issues. Details will described following note
Note Extended Instruction REPEAT This REPEAT extended instruction will handle delicate labeling offset processing described table 3.17 note labels used here Rptart: address instruction repeat loop RptEnd: address instruction bottom repeat loop RptCount: Repeat count immediate number This instruction used following way: Here repeat count specified immediate value #Imm register indirect value CASE Repeated Instruction
REPEAT RptStart, RptStart, RptCount; instr0; RptStart: instr1; instr2; Repeated instruction
CASE Repeated Instruction
REPEAT RptStart, RptEnd, RptCount; instr0; RptStart: RptEnd: instr1; instr2; Repeated instruction Repeated instruction
CASE Repeated Instruction
REPEAT RptStart, RptEnd, RptCount; instr0; RptStart: instr1; instr2; RptEnd: instr3; Repeated instruction Repeated instruction Repeated instruction
CASE more Repeated Instructions
REPEAT RptStart, RptEnd, RptCount; instr0;
RptStart
instr1; instr2; instr3;
Repeated instruction Repeated instruction Repeated instruction
-instrN-3; instrN-2; instrN-1; RptEnd instrN; instrN+1; Repeated instruction Repeated instruction Repeated instruction Repeated instruction
expanded results each case corresponds same case numbers note 3.2.2 Data Addressing
SH7622 types memory access instructions: data transfer instruction" (MOVX.W MOVY.W), other "single data transfer instruction" (MOVS.W MOVS.L). Data addressing these types instruction different. Table 3.18 shows summary data transfer instructions. Table 3.18 Summary Data Transfer Instructions
Data Transfer Operation (MOVX.W MOVY.W) Address registers Index register(s) Addressing operations Nop/Inc (+2)/Add-index-reg: Post-update Single Data Transfer Operation (MOVS.W, MOVS.L) Nop/Inc (+2, +4)/Add-index-reg: Post-update (-2, -4): Pre-update Modulo addressing Data Data length conflict Memory Source registers (word) data memories bit/32 (word/longword) Possible (same memory space A0/1, M0/1, X0/1, Y0/1, A0G, A0/1, M0/1, X0/1, Y0/1, A0G,
Destination registers X0/1, Y0/1
Addressing Instructions MOVX.W MOV.W: SH7622 access data memories simultaneously (MOVX.W MOVY.W). instructions have address pointers that simultaneously access data memories. instruction only pointeraddressing does have immediate-addressing). Address registers divided into sets, R4,5 (Ax: Address register memory) R6,7 (Ay: Address register memory). There three data addressing operations data transfer instruction. Not-update address register Add-index register Increment address register Each address pointer index register, R8[Ix] R9[Iy] Address instructions CPU, address instructions additional address unit (figure 3.20).
[Ix] (INC) (Not update)
[Ax] [Ax] (INC) (Not update) Additional adder addressing
[Iy]
[Ay] [Ay]
Three address operation types, Increment Add-index-register (Ix/Iy) update operations post-update type. decrement address pointer, index register.
Figure 3.20 Addressing Instructions MOVX.W MOVY.W Addressing data transfer operation always word mode; that access data memories 16-bit data width. Therefore, increment operation adds address register. realize decrement, `-2' index register add-index-register operation. Addressing Instructions MOVS: SH7622 single-data transfer instruction (MOVS.W MOVS.L) load/store data registers. this instruction, R2-5 (As: Address register single-data transfer) used address pointer. There four data addressing instructions single data transfer operation. Not-update address register Add-index register (post-update) Increment address register (post-update)
Decrement address register (pre-update) address pointer has, index register R8[Is] (figure 3.21).
[As] [As] [Is] -2/-4 (DEC) +2/+4 (INC) update)
[As] [As]
Four address operation types, update Add-index-register (Is) Increment Decrement
Post-update Pre-update
Figure 3.21 Addressing Instructions MOVS Modulo Addressing: SH7622 provides modulo addressing mode, which common DSPs. modulo addressing mode, address register updated explained above. When address pointer reaches pre-defined address (the modulo-end address), goes modulo start address. Modulo addressing available data transfer instruction (MOVX MOVY), single-data transfer instruction (MOVS). register used modulo addressing control. then modulo addressing mode effective memory address pointer R5). then effective memory address pointer R7). Modulo addressing available address registers time. simultaneously. this done, only setting will valid. specify start addresses modulo address area, register, which includes (modulo start) (modulo end) prepared. Following example shows register.
MOV.L ModAddr,Rn; Rn,MOD; ModAddr: .DATA.W .DATA.W mEnd; mStart; Rn=ModEnd, ModStart ME=ModEnd, MS=ModStart Lower bits ModEnd Lower bits ModStart
ModStart:
.DATA
ModEnd:
.DATA
specify start addresses, then `1.' content address register compared matches start address restored address register. Bits 1-15 address register compared register holds also used. maximum modulo size exceed memory size data memory through). Figure 3.22 shows block diagram modulo addressing.
Instr (MOVX/Y) [Ix] 1615 [Ax] [Ax]
CONT
1615 [Ay] [Ay]
[Iy]
Figure 3.22 Modulo Addressing example shown bellow.
MS=H'F000; ME=H'F004; R4=H'0800F000; DMX=1; DMY=0 (modulo addressing address register Ax(R4,5)) H'0800F000 MOVX.W @R4+,Dx MOVX.W @R4+,Dx MOVX.W @R4+,Dx MOVX.W @R4+,Dx H'0800F002 H'0800F004 H'0800F000 H'0800F002
upper bits modulo start addresses must same. Because modulo start address replaces only bits address register.
When add-index register instruction used data addressing, address pointer might exceed instead matching this case, address pointer does return modulo start address. Addressing Instruction Execution Stage: Address instructions, including modulo addressing, executed execution stage pipeline. Behavior data addressing execution stage
Operation MOVX.W MOVY.W ABx=Ax; ABy=Ay; Memory access cycle uses ABy. addresses used have been updated.
R4,5 DMX==0 DMX==1 DMY==1 Ax+(+2 R8[Ix] +0); Inc,Index,Not-Update else not-update) Ax=modulo( R8[Ix])
R6,7 DMY==0 Ay=Ay+(+2 R9[Iy] +0); Inc,Index,Not-Update else not-update) Ay=modulo( R9[Iy]) else Operation MOVS.W MOVS.L Addressing Nop, Inc, Add-index-reg MAB=As; Memory access cycle uses MAB. address used been updated.
R2-5 As+(+2 R8[Is] +0); Inc,Index,Not-Update else Decrement, Pre-update R2-5 As=As+(-2 -4); MAB=As; Memory access cycle uses MAB. address used been updated. value added address register depends addressing instructions.
example, R8[Ix] means that instruction increment
R8[Ix]: instruction add-index-register instruction not-update
function modulo AddrReg, Index AddrReg[15:1]==ME[15:1] AddrReg[15:1]==MS[15:1]; else AddrReg=AddrReg+Index; return AddrReg;
Data Transfer Instruction (MOVX.W MOVY.W): This type instruction uses access data memories (They cannot access other memory space). These buses separate from instruction bus, therefore, there access conflict between data memory access instruction memory access. Figure 3.23 shows load/store control data transfer instruction. memory accesses word mode accesses.
Instruction code data transfer operation data register X0/1, A0/1 Input/output control Control [Ax] [Ax]
[Ay] [Ay]
Instruction code data transfer operation data register Y0/1, A0/1 Input/output control
Control
X_MEM
Y_MEM data kbytes
data kbytes
X_MEM, _MEM: Select data memory
Figure 3.23 Load/Store Control Data-Transfer Instruction
Control
!Nop X_MEM=1; XAB=ABx; load operation Dx[31:16]=XDB; Dx[15:0]=0x0000; else Dx[31:16]; else X_MEM=0; XAB=0x000;
conditional execution based flag cannot control MOVX/MOVY instructions. Single-Data Transfer Instruction (MOVS.W MOVS.L): SH7622 single load/store instruction registers. similar load/store instruction system register. transfers data between memory data registers using LDB. There access conflict between data access instruction fetch. single-data transfer instruction word longword access modes. Figure 3.24 shows block diagram single-data transfer. Control memory address buffer (MAB) memory select uses existing SH-CPU core design.
[As] [As] [As] [As] Memory Control core Control data register Input/output control Instruction code single data transfer operation
Figure 3.24 Load/Store Control Single-Data Transfer Instruction
Control
LAB=MAB; Ms!=NLS word access MOVS.W (LS==load) (Ds!=A0G Ds!=A1G) Ds[31:16]=LDB[15:0]; Ds[15:0]=0x0000; (Ds==A0) A0G[7:0]=sign-extension LDB; (Ds==A1) A1G[7:0]=sign-extension LDB; else Ds[7:0]=LDB[7:0]; else Store (Ds!=A0G Ds!=A1G) LDB[15:0]=Ds[31:16]; else LDB[15:0]=Ds[7:0] with 8bit sign-extension; else MA!=NLS long-word access MOVS.L (LS==load) (Ds!=A0G Ds!=A1G) Ds[31:0]=LDB[31:0]; (Ds==A0) A0G[7:0]=sign-extension LDB; (Ds==A1) A1G[7:0]=sign-extension LDB; else Ds[7:0]=LDB[7:0]; else Store (Ds!=A0G Ds!=A1G) LDB[31:0]=Ds[31:0]; else LDB[31:0]=Ds[7:0] with 24bit sign-extension;
Section Instruction
Basic Concept SH7622 Instruction
order improve digital signal processing performance, type instructions added form SH7622's ISA. relationship with rest SuperH family Object-code level upward compatible with SH-1 SH-2. Instructions extension object-code level compatible with extension SHDSP. This section organized parts: section 4.2, SH-1, SH-2 Compatible Instruction section 4.3, Instructions Extension. Instructions described section 16-bit length compatible SH-1 SH-2. Extension instructions divided into groups: Additional system control instructions unit, e.g. setting repeat loop control modulo addressing Single- double-data transfer between memory registers unit Parallel instruction unit Groups 16-bit length, while 32-bit instructions which specify four parallel instructions (two load/store, Multiply) same time.
4.2.1
SH-1, SH-2 Compatible Instruction
Instruction Classification
SH-1 SH-2 instruction include basic instruction types, divided into seven functional classifications, listed table 4.1. Tables summarize instruction notation, machine mode, execution time, function.
Table
Classification Instructions
Types Operation Code Function Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer Effective address transfer T-bit transfer Swap upper lower bytes Extraction middle registers connected Binary addition Binary addition with carry Binary addition with overflow check Comparison Division Initialization signed division Initialization unsigned division Signed double-length multiplication Unsigned double-length multiplication Decrement test Sign extension Zero extension Multiply/accumulate, double-length multiply/accumulate operation Double-length multiplication bits) Signed multiplication bits) Unsigned multiplication bits) Negation Negation with borrow Binary subtraction Binary subtraction with carry Binary subtraction with underflow check Number Instructions
Classification Data transfer
MOVA MOVT SWAP XTRCT Arithmetic operations ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU EXTS EXTU MULS MULU NEGC SUBC SUBV
Table
Classification Instructions (cont)
Types Operation Code Function Logical inversion Logical Memory test Logical T-bit Exclusive One-bit left rotation One-bit right rotation One-bit left rotation with One-bit right rotation with One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Conditional branch, conditional branch with delay Conditional branch, conditional branch with delay Unconditional branch Unconditional branch Branch subroutine procedure Branch subroutine procedure Unconditional branch Branch subroutine procedure Return from subroutine procedure Number Instructions
Classification Logic operations
Shift
ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn
Branch
BRAF BSRF
Table
Classification Instructions (cont)
Types Operation Code CLRT CLRMAC SETT SLEEP TRAPA Function T-bit clear register clear Load control register Load system register operation Return from exception processing T-bit Shift into power-down mode Storing control register data Storing system register data Trap exception handling Number Instructions
Classification System control
Total:
Instruction codes, instruction, execution states listed table classification. Tables through list minimum number clock cycles required execution. practice, number execution cycles increases when instruction fetch contention with data access when destination register load instruction (memory register) same register used next instruction.
Table
Item Instruction mnemonic
Instruction Code Format
Format Explanation SRC: DEST: imm: disp: Operation code Size Source Destination Source register Destination register Immediate data Displacement
OP.Sz SRC,DEST
Instruction code
mmmm: Source register nnnn: Destination register 0000: 0001: 1111: iiii: Immediate data dddd: Displacement Direction transfer Memory operand Flag bits Logical each Logical each Exclusive each Logical each n-bit shift Value when wait states inserted execution cycles listed table minimums. actual number cycles increased: When contention occurs between instruction fetches data access, When destination register load instruction (memory register) register used next instruction same.
Operation summary
(xx) M/Q/T <<n,
Execution cycle Instruction execution cycles
Value after instruction executed change
Note: Instruction execution cycles: execution cycles listed table minimums. actual number cycles increased when contention occurs between instruction fetches data access, when destination register load instruction (memory register) register used next instruction same.
Table
Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W
Data Transfer Instructions
Operation (disp Sign extension (disp (Rn) (Rn) (Rn) Code Cycles
#imm,Rn @(disp,PC),Rn @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0 @(disp,Rm),R0 @(disp,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn
#imm Sign extension 1110nnnniiiiiiii 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010
(Rm) Sign extension 0110nnnnmmmm0000 (Rm) Sign extension 0110nnnnmmmm0001 (Rm) Rn-1 (Rn) Rn-2 (Rn) Rn-4 (Rn) 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110
(Rm) Sign extension 0110nnnnmmmm0100 (Rm) Sign extension 0110nnnnmmmm0101 (Rm) (disp (disp (disp (disp Sign extension (disp Sign extension (disp Sign extension Sign extension 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101
Table
Instruction MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT
Data Transfer Instructions (cont)
Operation (disp GBR) (disp GBR) (disp GBR) (disp GBR) Sign extension (disp GBR) Sign extension (disp GBR) disp Swap bottom bytes Swap consecutive words Middle bits Code 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd 11000101dddddddd 11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101 Cycles
@(R0,Rm),Rn R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) @(disp,GBR),R0 @(disp,GBR),R0 @(disp,GBR),R0 @(disp,PC),R0
SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn
Table
Instruction ADDC ADDV
Arithmetic Instructions
Operation Carry Overflow imm, Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 Cycles 2-5*
Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result
Rm,Rn #imm,Rn Rm,Rn Rm,Rn
CMP/EQ #imm,R0 CMP/EQ Rm,Rn CMP/HS Rm,Rn CMP/GE Rm,Rn CMP/HI Rm,Rn CMP/GT Rm,Rn CMP/PZ CMP/PL CMP/STR Rm,Rn DIV1 DIV0S DIV0U DMULS.L Rm,Rn Rm,Rn Rm,Rn
with unsigned 0011nnnnmmmm0010 data, with signed data, with unsigned data, with signed data, have equivalent byte, Single-step division (Rn/Rm) M/Q/T Signed operation MACH, MACL bits Unsigned operation MACH, MACL bits else 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010001 0100nnnn00010101 0010nnnnmmmm1100 0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 0011nnnnmmmm1101
DMULU.L Rm,Rn
0011nnnnmmmm0101
2-5*
0100nnnn00010000
Comparison result
Table
Instruction
Arithmetic Instructions (cont)
Operation byte signextended word signextended byte zeroextended word zeroextended Signed operation (Rn) (Rm) Signed operation (Rn) (Rm) bits MACL bits Signed operation bits Unsigned operation bits 0-Rm 0-Rm-T Borrow Rn-Rm Rn-Rm-T Borrow Rn-Rm Underflow Code 0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111 0100nnnnmmmm1111 Cycles 2-5* 2-5*
EXTS.B Rm,Rn EXTS.W Rm,Rn EXTU.B Rm,Rn EXTU.W Rm,Rn MAC.L @Rn+ MAC.W @Rn+ MUL.L @Rm+, @Rm+,
Rm,Rn
0000nnnnmmmm0111 0010nnnnmmmm1111
2-5* 1-3*
MULS.W Rm,Rn
MULU.W Rm,Rn
0010nnnnmmmm1110
1-3*
NEGC SUBC SUBV
Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn
0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011
Borrow Borrow Underflow
Notes: normal minimum number execution cycles cycles required when results operation read from register immediately after instruction. normal minimum number execution cycles cycles required when results operation read from register immediately after instruction.
Table
Instruction AND.B OR.B TAS.B TST.B XOR.B
Logic Operation Instructions
Operation GBR) GBR) GBR) GBR) (Rn) (Rn) result Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 0010nnnnmmmm1000 Cycles Test result Test result Test result Test result
Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn #imm,R0 #imm,@(R0,GBR)
imm; result 11001000iiiiiiii GBR) imm; result GBR) GBR) 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii
Table
Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8
Shift Instructions
Operation Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 Cycles
SHLL16 SHLR16
Table
Instruction
Branch Instructions
Operation Code Cycles 3/1*
label
disp 10001011dddddddd (where label disp Delayed branch, disp disp Delayed branch, disp Delayed branch, disp Delayed branch, disp Delayed branch, Delayed branch, Delayed branch, 10001111dddddddd 10001001dddddddd 10001101dddddddd
BF/S BT/S
label label label
2/1* 3/1* 2/1*
BRAF BSRF
label label
1010dddddddddddd 0000nnnn00100011 1011dddddddddddd 0000nnnn00000011 0100nnnn00101011 0100nnnn00001011 0000000000001011
Note: state when does branch
Table
Instruction CLRMAC CLRT LDC.L LDC.L LDC.L LDS.L LDS.L LDS.L SETT SLEEP STC.L STC.L STC.L
System Control Instructions
Operation MACH, MACL (Rm) (Rm) GBR, (Rm) VBR, MACH MACL (Rm) MACH, (Rm) operation Delayed branch, SSR/SPC SR/PC Sleep Rn-4 (Rn) Rn-4 (Rn) Rn-4 (Rn) MACH MACL Code 0000000000101000 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 Cycles
Rm,SR Rm,GBR Rm,VBR @Rm+,SR @Rm+,GBR @Rm+,VBR Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR
(Rm) MACL, 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000000000101011 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010
SR,Rn GBR,Rn VBR,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn
Table
Instruction STS.L STS.L STS.L TRAPA
System Control Instructions (cont)
Operation Rn-4 MACH (Rn) Rn-4 MACL (Rn) Rn-4 (Rn) PC/SR stack area, (imm Code 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Cycles
MACH,@-Rn MACL,@-Rn PR,@-Rn #imm
Note: number execution states before chip enters standby state. This table lists minimum execution cycles. practice, number execution cycles increases when instruction fetch contention with data access when destination register load instruction (memory register) same register used next instruction.
4.3.1
Instructions Extension
Introduction
instructions provided classified following three groups: A
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