SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SC
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M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
DESCRIPTION
M37281MAH-XXXSP, M37281MFH-XXXSP M37281MKHXXXSP single-chip microcomputers designed with CMOS silicon gate technology. They have function data slicer function, useful channel selection system with closed caption decoder. feautures M37281EKSP similar those M37281MKH-XXXSP except that chip built-in PROM which written electrically. difference between M37281MAH- XXXSP, M37281MKH-XXXSP M37281MFH-XXXSP size size. Accordingly, following descriptions will M37281MKH-XXXSP.
FEATURES
qNumber basic instructions qMemory size bytes (M37281MAH-XXXSP) bytes (M37281MFH-XXXSP) bytes (M37281MKH-XXXSP, M37281EKSP) 1088 bytes (M37281MAH-XXXSP, M37281MFH-XXXSP) 1536 bytes (M37281MKH-XXXSP, M37281EKSP) (*ROM correction memory included) qMinimum instruction execution time oscillation frequency) qPower source voltage qSubroutine nesting levels (Max.) qInterrupts types, vectors q8-bit timers qProgrammable ports (Ports P30, P31) qInput ports (Ports P40-P46, P63, P64, P70-P72) qOutput ports (Ports P52-P55) qLED drive ports qSerial 8-bit channel qMulti-master I2C-BUS interface systems) qA-D converter (8-bit resolution) channels qPWM output circuit 8-bit qPower dissipation high-speed mode 5.5V, oscillation frequency, Data slicer low-speed mode 0.33 5.5V, oscillation frequency)
qROM correction function vectors qClosed caption data slicer qOSD function Display characters characters lines font character) (CC/OSD mode)(CDOSD mode)(RAM font) Kinds characters kinds kinds kind (Coloring unit) character) dot) dot) Triple layer function layers selected from CC/CDOSD/OSD mode font layer Character display area CC/CDOSD mode: dots mode/RAM font: dots Kinds character sizes mode/RAM font: kinds OSD/CDOSD mode: kinds Kinds character colors colors adjustment levels each Coloring unit dot, character, character background, raster Blanking output OUT1, OUT2 Display position Horizontal: levels Vertical :1024 levels (RAM font independently) Attribute mode: smooth italic, underline, flash, automatic solid space mode: border, shadow Window/Blank function
APPLICATION
with closed caption decoder
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
TABLE CONTENTS
DESCRIPTION FEATURES APPLICATION CONFIGURATION FUNCTIONAL BLOCK DIAGRAM PERFORMANCE OVERVIEW DESCRIPTION FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) MEMORY INTERRUPTS TIMERS SERIAL MULTI-MASTER I2C-BUS INTERFACE OUTPUT CIRCUIT CONVERTER CORRECTION FUNCTION 8.10 DATA SLICER 8.11 FUNCTIONS 8.11.1 Triple Layer 8.11.2 Display Position 8.11.3 Size 8.11.4 Clock 8.11.5 Field Determination Display 8.11.6 Memory 8.11.7 Character Color 8.11.8 Character Background Color 8.11.9 OUT1, OUT2 Signals 8.11.10 Attribute 8.11.11 Automatic Solid Space Function 8.11.12 Multiline Display 8.11.13 SPRITE Function 8.11.14 Window Function 8.11.15 Blank Function 8.11.16 Raster Coloring Function 8.11.17 Scan Mode 8.11.18 Output Control 8.12. SOFTWARE RUNAWAY DETECT FUNC-TION 8.13. RESET CIRCUIT 8.14 CLOCK GENERATING CIRCUIT 8.15. DISPLAY OSCILLATION CIRCUIT 8.16. AUTO-CLEAR CIRCUIT 8.17. ADDRESSING MODE 8.18. MACHINE INSTRUCTIONS PROGRAMMING NOTES ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRIC CHARACTERISTICS ANALOG OUTPUT CHARACTERISTICS CONVERTER CHARACTERISTICS MULTI-MASTER I2C-BUS LINE CHARACTERISTICS PROM PROGRAMMING METHOD DATA REQUIRED MASK ORDERS APPENDIX PACKAGE OUTLINE
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
CONFIGURATION
HSYNC VSYNC P40/AD4 P41/INT2 P42/TIM2 P43/TIM3 P24/AD3 P25/AD2 P26/AD1 P27/AD5 P00/PWM4 P01/PWM5 P02/PWM6 P17/SIN/R0 P44/INT1 P45/SOUT P46/SCLK ).M37281EKSP (AVCC HLF/AD6 P72/(SIN) P71/VHOLD P70/CVIN CNVSS XOUT
P52/R/R1 P53/G/G1 P54/B/B1 P55/OUT1 P04/PWM0 P05/PWM1 P06/PWM2 P07/PWM3 P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/G0 P16/INT3/B0 P03/PWM7 P30/AD7 P31/AD8 RESET P64/OSC2/X COUT P63/OSC1/X
Note: Only 18th M37281MAH/ MFH/MKH-XXXSP. This AVcc M37281EKSP. M37281MAH/MFH/MKH-XXXSP connect apply Vcc.
M37281MAH-XXXSP, M37281MFH-XXXSP, M37281MKH-XXXSP, M37281EKSP
Outline 52P4B
Fig. Configuration (Top View)
Rev.
SCLK SOUT
SDA2 SDA1 SCL2 SCL1
PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
INT1 INT2
I2C-BUS interface
INT3
OUT1
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
ports P30, port
port
port
Input ports P40-P46
Output port P52-P55
Sync signal input
VSYNC HSYNC
Input ports P63, M37281EKSP Clock input OSD/ sub-clock input Clock output OSD/ sub-clock output OSC2/XOUT
Input ports
Clock input Clock output CNVSS
XOUT
Reset input RESET OSC1/XCIN
Pins data slicer CVIN VHOLD
SI/O Data slicer circuit P6(2) converter circuit
Clock generating circuit TIM2 TIM3
Program counter
Fig. Functional Block Diagram M37281
Timer count source selection circuit Timer Timer Timer Timer Control signal
Index register Index register
FUNCTIONAL BLOCK DIAGRAM
Data
Progam counter
Address
8-bit arithmetic logical unit Stack pointer Timer Timer Instruction decoder Instruction register
Accumulator
Processor status register
circuit
Multi-master
converter SI/O
8-bit circuit
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
PERFORMANCE OVERVIEW
Table Performance Overview Parameter Number basic instructions Instruction execution time Clock frequency Memory size Functions (the minimum instruction execution time, oscillation frequency) (maximum) bytes bytes bytes 1088 bytes (ROM correction memory included) 1536 bytes (ROM correction memory included) 20400 bytes 9672 bytes bytes 1536 bytes 7-bit (N-channel open-drain output structure, used output pins) 1-bit (CMOS input/output structure, used output pin) 4-bit (CMOS input/output structure, used output pin, input pin, serial input pin) 4-bit (N-channel open-drain output structure, used multimaster I2C-BUS interface) 8-bit (CMOS input/output structure, used input pins) 2-bit (CMOS input/output structure, used input pins) 5-bit (can used input pins, input pins, external clock input pins timer) 2-bit (N-channel open-drain output structure when serial used, used serial pins) 4-bit (CMOS output structure, used output pins) 1-bit (can used sub-clock input pin, clock input pin) 1-bit (CMOS output structure when oscillating, used sub-clock output pin, clock output pin) 3-bit (can used data slicer input/output, serial input pin) 8-bit systems) channels (8-bit resolution) 8-bit 8-bit timer vectors levels (maximum) types> external interrupt Internal timer interrupt Serial interrupt interrupt Multi-master C-BUS interface interrupt Data slicer interrupt f(XIN)/4096 interrupt SPRITE interrupt VSYNC interrupt conversion interrupt instruction interrupt Reset built-in circuits (externally connected ceramic resonator quartzcrystal oscillator) Built
M37281MAH-XXXSP M37281MFH-XXXSP M37281MKH-XXXSP, M37281EKSP M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP, M37281EKSP
Input/Output ports
(character font) (color font) (SPRITE) (character) P00-P02, P04-P07 P10, P15-P17 P11-P14 P30, P40-P44 P45, P52-P55
Input Input Output Input Input Input
P70-P72 Serial Multi-master I2C-BUS interface converter output circuit Timers correction function Subroutine nesting Interrupt
Clock generating circuit Data slicer
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Table Performance Overview Parameter Number display characters structure Functions characters lines mode: dots (Character display area: dots) mode: dots EXOSD mode: dots SPRITE display: dots CC/OSD mode: kinds CDOSD mode: kinds SPRITE display: kind mode: kinds OSD/CDOSD mode: kinds SPRITE display: kinds mode> screen kinds (per character unit) <OSD mode> screen kinds (per character unit) <CDOSD mode> screen kinds (per unit) <SPRITE display> screen kinds (per unit) Horizontal: levels, Vertical: 1024 levels <SPRITE display> Horizontal: 2048 levels, Vertical: 1024 levels typ. oscillation frequency f(XIN) MHz, fOSC MHz) typ. oscillation frequency f(XIN) MHz, fOSC 82.5 typ. oscillation frequency f(XIN) MHz) 0.33 typ. oscillation frequency f(XCIN) kHz, f(XIN) stop) 0.055 maximum CMOS silicon gate process 52-pin shrink plastic molded
function
Kinds characters
Kinds character sizes
Character font coloring
Display position Power source voltage high-speed Power mode dissipation
low-speed mode stop mode Operating temperature range Device structure Package
(Analog output) (Digital output)
Data slicer Data slicer Data slicer Data slicer
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
DESCRIPTION
Table Description VCC, (AVCC,) CNVSS RESET Name Power source Input/ Output Functions Apply voltage (typical) (AVCC VSS. .M37281EKSP Connected VSS. enter reset state, reset input must kept more (under normal conditions). more time needed quartz-crystal oscillator stabilize, this condition should maintained required time. This chip internal clock generating circuit. control generating frequency, external ceramic resonator quartz-crystal oscillator connected between pins XOUT. external clock used, clock source should connected XOUT should left open. Port 8-bit port with direction register allowing each individually programmed input output. reset, this port input mode. output structure CMOS output, that P00-P02 P04-P07 N-channel open-drain output (See note.) Pins P00-P03 P04-P07 also used 8-bit output pins PWM4-PWM7 PWM0-PWM3 respectively. output structure PWM0-PWM6 N-channel open-drain output. output structure PWM7 CMOS output. Port 8-bit port basically same functions port output structure P15-P17 CMOS output, that P11-P14 N-channel open-drain output (See note.) P10, P15-P17 also used output pins OUT2, respectively. output structure CMOS output. P11-P14 used SCL1, SCL2, SDA1 SDA2 respectively, when multi-master I2C-BUS interface used. output structure N-channel open-drain output. also used extemal interrupt input INT3. also used serial data input SIN. Port 8-bit port basically same functions port output structure CMOS output (See note.) Pins P24-P26, also used analog input pins AD3-AD1, respectively. Ports 2-bit ports have basically same functions port output structure CMOS output (See note.) Pins P30, also used analog input pins AD7, respectively. Ports P40-P46 7-bit input port. also used analog input AD4. Pins P41, also used external interrupt input pins INT2, INT1. Pins also used external clock input pins TIM2, TIM3 timer respectively. used serial data output SOUT. output structure N-channel opendrain output. used serial synchronous clock input/output SCLK. output structure N-channel open-drain output.
CNVSS Reset input Input
XOUT
Clock input Clock output
Input Output
P00/ port PWM4- P02/PWM6, P03/PWM7, P04/ 8-bit output PWM0- P07/PWM3 P10/OUT2, P11/SCL1, P12/SCL2, P13/SDA1, P14/SDA2, P15/G0, P16/INT3/ P17/SIN/R0 port
Output
output Multi-master I2C-BUS interface External interrupt input Serial data input port Analog input port Analog input Input port Analog input External interrupt input External clock input timer Serial data output Serial synchronous clock input/output
Output Input Input Input Input Input Input Input Input Output
P20-P23 P24/AD3- P26/AD1, P27/AD5 P30/AD7, P31/AD8 P40/AD4, P41/INT2, P42/TIM2, P43/TIM3, P44/INT1, P45/SOUT, P46/SCLK
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Table Description (continued) P52/R/R1, P53/G/G1, P54/B/B1, P55/OUT1 P63/OSC1/ XCIN, P64/OSC2/ XCOUT Name Output port output Input/ Output Output Output Functions Port 4-bit output port. output structure CMOS output. Pins P52-P55 also used output pins R/R1, G/G1, B/B1, OUT1 respectively. output, output structure analog output. OUT1 output, output structure CMOS output. Ports 2-bit input port. also used clock input OSC1. also used clock output OSC2. output structure CMOS output. also used sub-clock input XCIN. also used sub-clock output XCOUT. output structure CMOS output. Ports P70-P72 3-bit input port. Pins P70, also used data slicer input pins CVIN, VHOLD respectively. When using data slicer, input composite video signal through capacitor. Connect capacitor between VHOLD VSS. Pins also used serial data input SIN. When using data slicer, connect filter using capacitor resistor between VSS. This analog input This horizontal synchronous signal input OSD. This vertical synchronous signal input OSD.
P70/CVIN, P71/VHOLD, P72/(SIN)
Input port Clock input Clock output Sub-clock input Sub-clock output Input port Input data slicer Serial data input data slicer Analog input HSYNC input VSYNC input
Input Input Output Input Output Input Input
HLF/AD6
Input Input Input Input
HSYNC VSYNC
Note Port port direction register (address 00C116 zero page) which used program each input ("0") output ("1"). pins programmed direction register output pins. When pins programmed "0," they input pins. When pins programmed output pins, output data written into port latch then output. When data read from output pins, output level read data port latch read. This allows previously-output value read correctly even output voltage risen, example, because light emitting diode directly driven. input pins float, values pins read. When data written into input pin, written only into port latch, while remains floating state.
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
P03, P10, P15-P17, P30,
Direction register
CMOS output Ports P03, P10, P15-P17, P30, Note Each port also used follows PWM7 OUT2 INT3/B0 SIN/R0 P24-P26 AD3-AD1
Data
Port latch
P00-P02, P04-P07 Direction register
N-channel open-drain output Ports P00-P02, P04-P07
Data
Port latch
Note1 Each port also used follows 0-P02 PWM4-PWM6 P04-P07 PWM0-PWM3 M37281EKSP, does have
diode side with VCC.
P11-P14 Direction register
N-channel open-drain output Port P11-P14
Data
Port latch
Note Each port also used follows SCL1 SCL2 SDA1 SDA2
Fig. Block Diagram
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
SOUT, SCLK
N-channel open-drain output
Direction register
Ports P45,
Data
Note Each also used follows SOUT SCLK
HSYNC, VSYNC
Port
Schmidt input
Internal circuit
CMOS output
HSYNC, VSYNC
Internal circuit
Port Note Port also used OUT1.
Ports P40-P44
Input
Data
Ports P40-P44 Note Each port also used follows INT2 TIM2 TIM3 INT1
Ports P52-P54
Internal circuit
Output Ports P52-P54 Note Each port also used follows R/R1 G/G1 B/B1
Fig. Block Diagram
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION 8.1. CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses standard Family instruction set. Refer table Family addressing modes machine instructions SERIES <Software> User's Manual details instruction set. Machine-resident Family instructions follows: FST, instruction cannot used. MUL, DIV, instructions used.
8.1.1 Mode Register
mode register contains stack page selection internal system clock selection bit. mode register allocated address 00FB16.
Mode Register
mode register (CM) [Address 00FB16] Name Processor mode bits (CM0, CM1) Functions
After reset
Single-chip mode available
Stack page selection (CM2) (See note) these bits "1." XCOUT drivability selection (CM5)
page page
drive HIGH drive
Main Clock (XIN-XOUT) Oscillating stop Stopped (CM6) Internal system clock selection (CM7) XIN-XOUT selected (high-speed mode) XCIN-XCOUT selected (low-speed mode)
Note: This after reset release.
Fig. 8.1.1 Mode Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
MEMORY 8.2.1 Special Function Register (SFR) Area
special function register (SFR) area zero page contains control registers such ports timers.
8.2.6 Interrupt Vector Area
interrupt vector area contains reset interrupt vectors.
8.2.7 Zero Page
bytes from addresses 000016 00FF16 called zero page area. internal special function registers (SFR) allocated this area. zero page addressing mode used specify memory register addresses zero page area. Access this area with only bytes possible zero page addressing mode.
8.2.2
used data storage stack area subroutine calls interrupts.
8.2.3
M37281MAH-XXXSP 40K-byte program area M37281MFH-XXXSP 60K-byte program area. M37281MKH -XXXSP 56K-byte program area 24K-byte data-dedicated area. M37281EKSP, area (60K, 56K) swithed each other setting bank control register.
8.2.8 Special Page
bytes from addresses FF0016 FFFF16 called special page area. special page addressing mode used specify memory addresses special page area. Access this area with only bytes possible special page addressing mode.
8.2.4
display used specifying character codes colors display.
8.2.9 Correction Vector
This used program jump destination addresses correction.
8.2.5
display used storing character data.
M37281MKH-XXXSP, M37281EKSP
000016 00BF16 00C016 00FF16 010016 020016 025816 02C016 02E016 SFR2 area used correction function Vector address 02C016 Vector address 02E016 Zero page SFR1 area 1000016 used 1080016
(1536 bytes)
(Character font) (20400 bytes)
157FF16 used
(SPRITE) (120 bytes) (Note (Character) (1536 bytes) (Note
06FF16 070016 07A716 used 080016 (Color font) (9672 bytes)
1800016
0FFF16 100016 Extra area 200016
1ACFF16
used
1B00016 (60K bytes) Expansion (20K bytes) FF0016 FFDE16 FFFF16 Interrupt vector area 1C00016
Bank Bank
1D00016 1E00016
Bank Bank Bank
Special page
1F00016 1FFFF16
Notes Refer Table 8.11.6 (SPRITE). Tables 8.11.4 8.11.5 (Character).
Fig. 8.2.1 Memory (M37281MKH-XXXSP, M37281EKSP)
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
M37281MAH-XXXSP, M37281MFH-XXXSP
000016 00BF16 00C016 00FF16 010016 020016 025816 02C016 02E016 053F16 used (SPRITE) (120 bytes) (Note (Character) (1536 bytes) (Note 070016 07A716 Extra area 080016 (Color font) (9672 bytes) 1ACFF16 1800016 SFR2 area used correction function Vector address 02C016 Vector address 02E016 1000016 1080016 Zero page SFR1 area
used
M37281MAH-XXXSP, M37281MFH-XXXSP (1088 bytes)
(Character font) (20400 bytes)
157FF16 used
0FFF16 100016
M37281MFH-XXXSP (60K bytes) 600016
used
M37281MAH-XXXSP (40K bytes) FF0016 FFDE16 FFFF16 Interrupt vector area Special page
Notes Refer Table 8.11.6 (SPRITE). Tables 8.11.4 8.11.5 (Character).
Fig. 8.2.2 Memory
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.2.10 Expansion (only M37281MKHXXXSP/M37281EKSP)
M37281MKH-XXXSP/M37281EKSP 5-bank (total bytes) expansion bytes each bank) setting bank register. expansion assigned address 1B00016 1FFFF16. contents each bank expansion read setting bank register accessing addresses 100016 1FFF16. expansion programmable, data-dedicated area. When using expansion area, internal addresses 100016 1FFF16 (extra area) also programmable.
Notes When using expansion (BK7 "1"), correction function operate addresses 100016 1FFF16. When using emulator (M37281ERSS), addresses 100016 FFFF16 emulated setting bank control register "0," expansion cannot used. Addresses 200016 FFFF16 emulated setting "1." data specified area bank selection bits read accessing addresses 100016 1FFF16. When using emulator MCU, expansion extra area cannot emulated setting bank control register "1." Therefore, write data this area before using. M37281MKH-XXXSP, bank control register "1." M37281MAH-XXXSP M37281MFH-XXXSP, address 00ED16 "0016."
Bank Control Register
Bank control register (BK) [Address 00ED16]
Name
Functions
After reset
Bank Bank number selected (bank selection bits (BK0 BK3)
these bits "0." Bank control bits (BK6, BK7) Bank Address 100016 level access Read from extra area used (programmable) Read data Used from area specified bank selection bits Read from extra area Used (data-dedicated)
Fig. 8.2.3 Bank Control Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
SFR1 area (addresses C016 DF16)
<Bit allocation> <State immediately after reset>
Name
Function
immediately after reset immediately after reset Indeterminate immediately after reset
function
this write "1") this write "0") Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register
Port (P0) Port direction register (D0) Port (P1) Port direction register (D1) Port (P2) Port direction register (D2) Port (P3) Port direction register (D3) Port (P4) Port direction register (D4) Port (P5) port control register (PF) Port (P6) Port (P7) control register Horizontal position register (HP) Block control register (BC1) Block control register (BC2) Block control register (BC3) Block control register (BC4) Block control register (BC5) Block control register (BC6) Block control register (BC7) Block control register (BC8) Block control register (BC9) Block control register (BC10) Block control register (BC11) Block control register (BC12) Block control register (BC13) Block control register (BC14) Block control register (BC15) Block control register (BC16)
P6IM T3CS
allocation
State immediately after reset
OUT2OUT1
2BIT
BC16 BC15 BC14 BC13 BC12 BC11 BC10 BC26 BC25 BC24 BC23 BC22 BC21 BC20 BC36 BC35 BC34 BC33 BC32 BC31 BC30 BC46 BC45 BC44 BC43 BC42 BC41 BC40 BC56 BC55 BC54 BC53 BC52 BC51 BC50 BC66 BC65 BC64 BC63 BC62 BC61 BC60 BC76 BC75 BC74 BC73 BC72 BC71 BC70 BC86 BC85 BC84 BC83 BC82 BC81 BC80 BC96 BC95 BC94 BC93 BC92 BC91 BC90
BC106 BC105 BC104 BC103 BC102 BC101 BC100 BC116 BC115 BC114 BC113 BC112 BC111 BC110 BC126 BC125 BC124 BC123 BC122 BC121 BC120
BC136 BC135 BC13 BC133 BC132 BC131 BC130
BC156 BC155 BC154 BC153 BC152 BC151 BC150 BC166 BC165 BC164 BC163 BC162 BC161 BC160
0016 0016 0016 0016 0016 0016 0016 0016
Fig. 8.2.4 Memory Special Function Register (SFR1)
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
SFR1 area (addresses E016 FF16)
<Bit allocation> <State immediately after reset>
Name
Function
immediately after reset immediately after reset Indeterminate immediately after reset
function
this write "1") this write "0")
Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16
Register
allocation
DSC12 DSC11 DSC10
State immediately after reset
Data slicer control register (DSC1) Data slicer control register (DSC2) Caption data register (CD1) Caption data register (CD2) Caption data register (CD3) Caption data register (CD4) Caption Position register (CPS) Data slicer test register Data slicer test register
Sync signal counter register (HC) Clock run-in detect register (CRD) Data clock position register (DPS)
DSC25 DSC24 DSC23
DSC20
CDL17 CDL16 CDL15 CDL14 CDL13 CDL12 CDL11 CDL10 CDL27 CDL26 CDL25 CDL24 CDL23 CDL22 CDL21 CDL20
CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0
0016 0016
CRD7 CRD6 CRD5 CRD4 CRD3 DPS7 DPS6 DPS5 DPS4 DPS3
Bank control register (BK) conversion register (AD) control register (ADCON) Timer (T1) Timer (T2) Timer (T3) Timer (T4) Timer mode register (TM1) Timer mode register (TM2) data shift register (S0) address register (S0D) status register (S1) control register (S1D) clock control register (S2)
ADVREF ADSTR ADIN2 ADIN1 ADIN0
TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10 TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
BSEL1 BSEL0 10BIT
CCR4 CCR3 CCR2 CCR1 CCR0
FAST MODE
mode register (CM) Interrupt request register (IREQ1) VSCR OSDR TM4R TM3R TM2R
TM1R
Interrupt request register (IREQ2) Interrupt control register (ICON1) Interrupt control register (ICON2)
TM56R
IICR IN2R SIOR IN1R
VSCEOSDE TM4E TM3E TM2E TM1E
TM56S TM56E
IICE IN2E SIOE IN1E
0016 0016 0016 0016 0016 0016 0016 0016 0916 0016 FF16 0716 FF16 0716 0016 0016 0016 0016 0016 3C16 0016 0016 0016 0016
Fig. 8.2.5 Memory Special Function Register (SFR2)
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
SFR2 area (addresses 20016 21F16)
<Bit allocation> <State immediately after reset>
Name
Function
immediately after reset immediately after reset Indeterminate immediately after reset
function
this write "1") this write "0") Address 20016 20116 20216 20316 20416 20516 20516 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 21C16 21D16 21E16 21F16 Register
PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM5 register (PWM5) PWM6 register (PWM6) PWM7 register (PWM7)
allocation
State immediately after reset
mode register (PN) mode register (PW) correction address (high-order) correction address (low-order) correction address (high-order) correction address (low-order) correction enable register (RCR) Test register Interrupt input polarity register (IP) Serial mode register (SM) Serial register (SIO) control register 2(OC2) Clock control register (CS) polarity control register (PC) Raster color register (RC) control register 3(OC3) Timer (TM5) Timer (TM6) border control register (TB1) Bottom border control register (BB1) border control register (TB2) Bottom border control register (BB2)
AD/INT3
0016
RCR1 RCR0
AD/I/NN3 SELL AD/INT3
POL2 POL1
OC27 OC26 OC25 OC24 OC23 OC12 OC21 OC20
AD/INT3 AD/INT3 AD/INT3
OC37 OC36 OC35 OC34 OC33 OC22 OC11 OC30
TB17 TB16 TB15 TB14 TB13 TB12 TB11 TB10 BB17 BB16 BB15 BB14 BB13 BB12 BB11 BB10 TB21 TB20 BB21 BB20
0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 8016 0016 0016 FF16 0716
Fig. 8.2.6 Memory Special Function Register (SFR2)
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
SFR2 area (addresses 22016 23F16)
<Bit allocation> <State immediately after reset>
Name
Function
immediately after reset immediately after reset Indeterminate immediately after reset
function
this write "1") this write "0") Address 22016 22116 22216 22316 22416 22516 22616 22716 22816 22916 22A16 22B16 22C16 22D16 22E16 22F16 23016 23116 23216 23316 23416 23516 23616 23716 23816 23916 23A16 23B16 23C16 23D16 23E16 23F16 Register
Vertical position register (VP11) Vertical position register (VP12) Vertical position register (VP13) Vertical position register (VP14) Vertical position register (VP15) Vertical position register (VP16) Vertical position register (VP17) Vertical position register (VP18) Vertical position register (VP19) Vertical position register (VP110) Vertical position register (VP111) Vertical position register (VP112) Vertical position register (VP113) Vertical position register (VP114) Vertical position register (VP115) Vertical position register (VP116) Vertical position register (VP21) Vertical position register (VP22) Vertical position register (VP23) Vertical position register (VP24) Vertical position register (VP25) Vertical position register (VP26) Vertical position register (VP27) Vertical position register (VP28) Vertical position register (VP29) Vertical position register (VP210) Vertical position register (VP211) Vertical position register (VP212) Vertical position register (VP213) Vertical position register (VP214) Vertical position register (VP215) Vertical position register (VP216)
allocation
State immediately after reset
VP117 VP116 VP115 VP114 VP113 VP112 VP111 VP110 VP127 VP126 VP125 VP124 VP123 VP122 VP121 VP120 VP137 VP136 VP135 VP134 VP133 VP132 VP131 VP130 VP147 VP146 VP145 VP144 VP143 VP142 VP141 VP140 VP157 VP156 VP155 VP154 VP153 VP152 VP151 VP150 VP167 VP166 VP165 VP164 VP163 VP162 VP161 VP160 VP177 VP176 VP175 VP174 VP173 VP172 VP171 VP170 VP187 VP186 VP185 VP184 VP183 VP182 VP181 VP180 VP197 VP196 VP195 VP194 VP193 VP192 VP191 VP190
VP1107 VP1106 VP1105 VP1104 VP1103 VP1102 VP1101 VP1100 VP1117 VP1116 VP1115 VP1114 VP1113 VP1112 VP1111 VP1110 VP1127 VP1126 VP1125 VP1124 VP1123 VP1122 VP1121 VP1120 VP1137 VP1136 VP1135 VP1134 VP1133 VP1132 VP1131 VP1130 VP1147 VP1146 VP1145 VP1144 VP1143 VP1142 VP1141 VP1140 VP1157 VP1156 VP1155 VP1154 VP1153 VP1152 VP1151 VP1150 VP1167 VP1166 VP1165 VP1164 VP1163 VP1162 VP1161 VP1160 VP211 VP210 VP221 VP220 VP231 VP230 VP241 VP240 VP251 VP250 VP261 VP260 VP271 VP270 VP281 VP280 VP291 VP290 VP2101 VP2100 VP2111 VP2110 VP2121 VP2120 VP2131 VP2130 VP2141 VP2140 VP2151 VP2150 VP2161 VP2160
Fig. 8.2.7 Memory Special Function Register (SFR2)
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
SFR2 area (addresses 24016 25816)
<Bit allocation> <State immediately after reset
Name
Function
immediately after reset immediately after reset Indeterminate immediately after reset
function
this write "1") this write "0") Address 24016 24116 24216 24316 24416 24516 24616 24716 24816 24916 24A16 24B16 24C16 24D16 24E16 24F16 25016 25116 25216 25316 25416 25516 25616 25716 25816 Register
Color pallet register (CR1) Color pallet register (CR2) Color pallet register (CR3) Color pallet register (CR4) Color pallet register (CR5) Color pallet register (CR6) Color pallet register (CR7) Color pallet register (CR9) Color pallet register10 (CR10) Color pallet register (CR11) Color pallet register (CR12) Color pallet register (CR13) Color pallet register (CR14) Color pallet register (CR15) Left border control register (LB1) Left border control register (LB2) Right border control register (RB1) Right border control register (RB2)
SPRITE vertical position register (VS1) SPRITE vertical position register (VS2)
allocation
State immediately after reset
CR16 CR15 CR14 CR13 CR12 CR11 CR10 CR26 CR25 CR24 CR23 CR22 CR21 CR20 CR36 CR35 CR34 CR33 CR32 CR31 CR30 CR46 CR45 CR44 CR43 CR42 CR41 CR40 CR56 CR55 CR54 CR53 CR52 CR51 CR50 CR66 CR65 CR64 CR63 CR62 CR61 CR60 CR76 CR75 CR74 CR73 CR72 CR71 CR70 CR96 CR95 CR94 CR93 CR92 CR91 CR90
LB17 LB16 LB15 LB14 LB13 LB12 LB11 LB10 LB22 LB21 LB20 RB17 RB16 RB15 RB14 RB13 RB12 RB11 RB10 RB22 RB21 RB20 VS17 VS16 VS15 VS14 VS13 VS12 VS11 VS10 VS21 VS20
SPRITE horizontal position register (HS1) HS17 HS16 HS15 HS14 HS13 HS12 HS11 HS10 SPRITE horizontal position register (HS2)
HS22 HS21 HS20
SPRITE control register (SC)
0116 0016 FF16 0716 0016 0016
Fig. 8.2.8 Memory Special Function Register (SFR2)
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
<Bit allocation>
<State immediately after reset>
Name
Function
immediately after reset immediately after reset Indeterminate immediately after reset
function
this write "1") this write "0") Register
Processor status register (PS) Program counter (PCH) Program counter (PCL)
allocation
State immediately after reset
Contents address FFFF16 Contents address FFFE16
Fig. 8.2.9 Internal State Processor Status Register Program Counter Reset
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
INTERRUPTS
Interrupts caused different sources consisting external, internal, software, reset. Interrupts vectored interrupts with priorities shown Table 8.3.1. Reset also included table because operation similar interrupt. When interrupt accepted, contents program counter processor status register automatically stored into stack. interrupt disable flag corresponding interrupt request "0." jump destination address stored vector address enters program counter. Nothing stop reset. Other interrupts disabled when interrupt disable flag "1." interrupts except instruction interrupt have interrupt request interrupt enable bit. interrupt request bits interrupt request registers interrupt enable bits interrupt control registers Figures 8.3.2 8.3.6 show interrupt-related registers. Interrupts other than instruction interrupt reset accepted when interrupt enable "1," interrupt request "1," interrupt disable flag "0." interrupt request program, "1." interrupt enable program. Reset treated non-maskable interrupt with highest priority. Figure 8.3.1 shows interrupt control.
8.3.1 Interrupt Causes
VSYNC Interrupts VSYNC interrupt interrupt request synchronized with vertical sync signal. interrupt occurs after character block display completed. INT1, INT2 External Interrupts INT1 INT2 interrupts external interrupt inputs, system detects that level changes from HIGH from HIGH LOW, generates interrupt request. input active edge selected bits interrupt input polarity register (address 021216) when this "0," change from HIGH detected; when "1," change from HIGH detected. Note that both bits cleared reset. Timer Interrupts interrupt generated overflow timer
Table 8.3.1 Interrupt Vector Addresses Priority Priority Interrupt Source Reset interrupt INT1 external interrupt Data slicer interrupt Serial interrupt Timer interrupt f(XIN)/4096 SPRITE interrupt VSYNC interrupt Timer interrupt Timer interrupt Timer interrupt convertion INT3 external interrupt INT2 external interrupt Multi-master I2C-BUS interface interrupt Timer interrupt instruction interrupt Vector Addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF716, FFF616 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFE316, FFE216 FFDF16, FFDE16 Remarks Non-maskable Active edge selectable
Software switch software (See note)
Software switch software (See note)/ When selecting INT3 interrupt, active edge selectable. Active edge selectable Software switch software (See note) Non-maskable (software interrupt)
Note Switching source during program causes unnecessary interrupt occurs. Accordingly, source initializing program.
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Serial Interrupt This interrupt request from clock synchronous serial function. f(XIN)/4096 SPRITE Interrupt (XIN)/4096 interrupt occurs regularly with f(XIN)/4096 period. mode register "0." SPRITE interrupt occurs completion SPRITE display. Since f(XIN)/4096 interrupt SPRITE interrupt share same vector, interrupt source selected SPRITE control register (address 025816). Data Slicer Interrupt interrupt occurs when slicing data completed. Multi-master I2C-BUS Interface Interrupt This interrupt request related multi-master I2C-BUS interface. Conversion INT3 external Interrupt conversion interrupt occurs completion conversion. INT3 external input,the system detects that level changes from HIGH from HIGH LOW, generates interrupt request. input active edge selected interrupt input polarity register (address 021216) when this "0," change from HIGH detected; when "1," change from HIGH detected. Note that this cleared reset. Since conversion interrupt INT3 external interrupt share same vector, interrupt source selected interrupt interval determination control register (address 021216). Timer Interrupt interrupt generated overflow timer Their priorities same, switched software. (10) Instruction Interrupt This software interrupt least significant priority. does have corresponding interrupt enable bit, affected interrupt disable flag (non-maskable). Fig. 8.3.1 Interrupt Control
Interrupt request Interrupt enable
Interrupt disable flag
instruction Reset
Interrupt request
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Interrupt Request Register
Interrupt request register (IREQ1) [Address 00FC16] Name Timer interrupt request (TM1R) Timer interrupt request (TM2R) Timer interrupt request (TM3R) Timer interrupt request (TM4R) After reset Functions interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued
interrupt request (OSDR) VSYNC interrupt request (VSCR) conversion INT3 external interrupt request (ADR) Nothing assigned. This write disable bit. When this read out, value "0."
software, cannot set.
Fig. 8.3.2 Interrupt Request Register
Interrupt Request Register
Interrupt request register (IREQ2) [Address 00FD16]
After reset Functions interrupt request issued INT1 external interrupt request (IN1R) Interrupt request issued interrupt request issued Data slicer interrupt request (DSR) Interrupt request issued interrupt request issued Serial interrupt request (SIOR) Interrupt request issued interrupt request issued f(XIN)/4096 SPRITE interrupt request (CKR) Interrupt request issued INT2 external interrupt request interrupt request issued (IN2R) Interrupt request issued Multi-master I2C-BUS interrupt interrupt request issued request (IICR) Interrupt request issued interrupt request issued Timer interrupt request (TM56R) Interrupt request issued this "0."
Name
software, cannot set.
Fig. 8.3.3 Interrupt Request Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Interrupt Control Register
Interrupt control register (ICON1) [Address 00FE16] Functions After reset Interrupt disabled Interrupt enabled Interrupt disabled Timer interrupt enable (TM2E) Interrupt enabled Interrupt disabled Timer interrupt enable (TM3E) Interrupt enabled Interrupt disabled Timer interrupt enable (TM4E) Interrupt enabled Interrupt disabled interrupt enable (OSDE) Interrupt enabled Interrupt disabled VSYNC interrupt enable (VSCE) Interrupt enabled conversion INT3 external Interrupt disabled Interrupt enabled interrupt enable (ADE) Nothing assigned. This write disable bit. When this read out, value "0." Name Timer interrupt enable (TM1E)
Fig. 8.3.4 Interrupt Control Register
Interrupt Control Register
Interrupt control register (ICON2) [Address 00FF16] Name INT1 external interrupt enable (IN1E) Data slicer interrupt enable (DSE) Serial interrupt enable (SIOE)
After reset Functions Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Timer Timer
f(XIN)/4096 SPRITE interrupt enable (CKE) INT2 external interrupt enable (IN2E) Multi-master I2C-BUS interface interrupt enable (IICE) Timer interrupt enable (TM56E) Timer interrupt switch (TM56S)
Fig. 8.3.5 Interrupt Control Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Interrupt Input Polarity Register
Interrupt input polarity register (IP) [Address 021216]
Name Functions After reset
Nothing assigned. These bits write disable bits. When these bits read out, values "0." INT1 polarity switch (POL1) INT2 polarity switch (POL2) Positive polarity Negative polarity Positive polarity Negative polarity
Nothing assigned. This write disable bit. When this read out, value "0." INT3 polarity switch (POL3) conversion INT3 interrupt source selection (AD/INT3SEL) Positive polarity Negative polarity INT3 interrupt conversion interrupt
Fig. 8.3.6 Interrupt Input Polarity Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
TIMERS
This microcomputer timers: timer timer timer timer timer timer timers 8-bit timers with 8-bit timer latch. timer block diagram shown Figure 8.4.3. timers count down their divide ratio 1/(n+1), where value timer latch. writing count value corresponding timer latch (addresses 00F016 00F316 timers addresses 021A16 021B16 timers value also timer, simultaneously. Down counts "nn16 nn16 0116, 0016" input count source from right after setting timer. interrupt requested timer overflow next count source input which value timer becomes "0016." Each timers explained below.
8.4.4 Timer
Timer select following count sources: f(XIN)/16 f(XCIN)/16 f(XIN)/2 f(XCIN)/2 f(XCIN) Timer overflow signal count source timer selected setting bits timer mode register (address 00F516). Either f(XIN) f(XCIN) selected mode register. When timer overflow signal count source timer timer functions 8bit prescaler. Timer interrupt request occurs timer overflow.
8.4.5 Timer
Timer select following count sources: f(XIN)/16 f(XCIN)/16 Timer overflow signal Timer overflow signal count source timer selected setting timer mode register (address 00F416) timer mode register (address 00F516). When overflow timer count source timer either timer functions 8-bit prescaler. Either f(XIN) f(XCIN) selected mode register. Timer interrupt request occurs timer overflow.
8.4.1 Timer
Timer select following count sources: f(XIN)/16 f(XCIN)/16 f(XIN)/4096 f(XCIN)/4096 External clock from TIM2 count source timer selected setting bits timer mode register (address 00F416). Either f(XIN) f(XCIN) selected mode register. Timer interrupt request occurs timer overflow.
8.4.2 Timer
Timer select following count sources: f(XIN)/16 f(XCIN)/16 Timer overflow signal External clock from TIM2 count source timer selected setting bits timer mode register (address 00F416). Either f(XIN) f(XCIN) selected mode register. When timer overflow signal count source timer timer functions 8bit prescaler. Timer interrupt request occurs timer overflow.
8.4.6 Timer
Timer select following count sources: f(XIN)/16 f(XCIN)/16 Timer overflow signal count source timer selected setting timer mode register (address 00F416). Either f(XIN) f(XCIN) selected mode register. When timer overflow signal count source timer timer functions 8-bit prescaler. Timer interrupt request occurs timer overflow. reset, timers connected hardware "FF16" automatically timer "0716" timer f(XIN) selected timer count source. internal reset released timer overflow this state internal clock connected. execution instruction, timers connected hardware "FF16" automatically timer "0716" timer However, f(XIN) selected timer count source. both timer mode register (address 00F516) address 00C716 before execution instruction (f(XIN) selected timer count source). internal state released timer overflow this state internal clock connected. result above procedure, program start under stable clock. When mode register (CM7) "1," f(XIN) becomes f(XCIN). timer-related registers shown Figures 8.4.1 8.4.2.
8.4.3 Timer
Timer select following count sources: f(XIN)/16 f(XCIN)/16 f(XCIN) External clock from TIM3 count source timer selected setting timer mode register (address 00F516) address 00C716. Either f(XIN) f(XCIN) selected mode register. Timer interrupt request occurs timer overflow.
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Timer Mode Register
Timer mode register (TM1) [Address 00F416] Name Timer count source selection (TM10) Timer count source selection (TM11) Functions f(XIN)/16 f(XCIN)/16 (See note) Count source selected Count source selected External clock from TIM2 Count start Count stop Count start Count stop After reset
Timer count stop (TM12) Timer count stop (TM13)
Timer count source f(XIN)/16 f(XCIN)/16 (See note) selection (TM14) Timer overflow Timer count source selection (TM15) Timer count source selection (TM16) Timer count source selection (TM17) f(XIN)/4096 f(XCIN)/4096 (See note) External clock from TIM2 Timer overflow Timer overflow f(XIN)/16 f(XCIN)/16 (See note) Timer overflow
Note: Either f(XIN) f(XCIN) selected mode register.
Fig. 8.4.1 Timer Mode Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Timer Mode Register
Timer mode register (TM2) [Address 00F516] Name Timer count source selection (TM20) Functions address 00C716) f(XIN)/16 f(XCIN)/16 (See note) f(XCIN) External clock from TIM3 Timer overflow signal f(XIN)/16 f(XCIN)/16 (See note) f(XIN)/2 f(XCIN)/2 (See note) f(XCIN) Count start Count stop Count start Count stop Count start Count stop Count start Count stop f(XIN)/16 f(XCIN)/16 (See note) Count source selected After reset
Timer count source selection bits (TM21, TM24)
Timer count stop (TM22) Timer count stop (TM23) Timer count stop (TM25) Timer count stop (TM26) Timer count source selection (TM27)
Note: Either f(XIN) f(XCIN) selected mode register.
Fig. 8.4.2 Timer Mode Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Data
XCIN
TM15 1/4096 Timer latch
TM10 TM12 TM14
Timer
Timer interrupt request
Timer latch
TIM2 TM11 TM13
Timer
Timer interrupt request
FF16 T3CS Timer latch
Reset instruction
TIM3 TM20 TM22
Timer
Timer interrupt request
TM21
0716 Timer latch
Timer TM21 TM24 TM23 TM16 Selection gate Connected black side reset Timer mode register Timer mode register T3CS Timer count source switch (address 00C716) mode register TM27 TM25
Timer interrupt request
Timer latch
Timer
Timer interrupt request
Timer latch
Timer TM17 TM26
Timer interrupt request
Notes HIGH pulse width external clock inputs TIM2 TIM3 needs machine cycles more. When external clock source selected, timers counted rising edge input signal. stop mode wait mode, external clock inputs TIM2 TIM3 cannot used.
Fig. 8.4.3 Timer Block Diagram
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
SERIAL
This microcomputer built-in serial which either transmit receive 8-bit data serially clock synchronous mode. serial block diagram shown Figure 8.5.1. synchronous clock (SCLK), data output (SOUT) also function port data input (SIN) also functions ports serial mode register (address 021316) selects whether synchronous clock supplied internally externally (from SCLK pin). When internal clock selected, bits select whether f(XIN) f(XCIN) divided servial I/O, corresponding SCLK port direction register (address 00C916) corresponding port direction register (address 00C316) "0".
More over, corresponding SOUT port direction register (address 00C916) And, SOUT serial I/O, corresponding bits port direction register (address 00C916) "1." operation serial described below. operation serial differs depending clock source; external clock internal clock.
XCIN
Synchronous circuit
Data Frequency divider
1/16
Selection gate: Connect black side reset.
mode register Serial mode register
SCLK
Serial counter
Serial interrupt request
SOUT
(Note)
Serial shift register (Address 021416)
Note When data serial register (address 021416), register functions serial shift register.
Fig. 8.5.1 Serial Block Diagram
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Internal clock serial counter during write cycle into serial register (address 021416), transfer clock goes forcibly. each falling edge transfer clock after write cycle, serial data output from SOUT pin. Transfer direction selected serial mode register. each rising edge transfer clock, data input from data serial register shifted bit. After transfer clock counted times, serial counter becomes transfer clock stops HIGH. this time interrupt request "1."
External clock external clock selected clock source, interrupt request after transfer clock been counted counts. However, transfer operation does stop, clock should controlled externally. external clock less with duty cycle serial timing shown Figure 8.5.2. When using external clock transfer, external clock must held HIGH initializing serial counter. When switching between internal clock external clock, switch during transfer. Also, sure initialize serial counter after switching.
Notes programming, note that serial counter writing serial register with managing instructions, such CLB. When external clock used synchronous clock, write transmit data serial register when transfer clock input level HIGH.
Synchronous clock
Transfer clock Serial register write signal (Note) Serial output SOUT Serial input
Interrupt request Note When internal clock selected, SOUT high-impedance after transfer completed.
Fig. 8.5.2 Serial Timing (for first)
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Serial Mode Register
Serial mode register (SM) [Address 021316] Name Functions f(XIN)/8 f(XCIN)/8 f(XIN)/16 f(XCIN)/16 f(XIN)/32 f(XCIN)/32 f(XIN)/64 f(XCIN)/64 After reset
Internal synchronous clock selection bits (SM0, SM1)
Synchronous clock selection (SM2) Port function selection (SM3)
External clock Internal clock P11, SCL1, SDA1 P12, SCL2, SDA2 Transfer from last significant (LSB) Transfer from significant (MSB)
Port function selection (SM4) Transfer direction selection (SM5)
switch (SM6)
Nothing assigned. This write disable bit. When this read out, value "0."
Fig. 8.5.3 Serial Mode Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
MULTI-MASTER I2C-BUS INTERFACE
multi-master I2C-BUS interface serial communications circuit, conforming Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection synchronous functions, useful multi-master serial communications. Figure 8.6.1 shows block diagram multi-master I2C-BUS interface Table 8.6.1 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists address register, data shift register, clock control register, control register, status register other control circuits.
Table 8.6.1 Multi-master I2C-BUS Interface Functions Item Function conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 MHz)
Format
Communication mode
clock frequency
System clock f(XIN)/2
Note responsible third party's infringement patent rights other rights attributable control function (bits control register address 00F916) connections between I2C-BUS interface ports (SCL1, SCL2, SDA1, SDA2).
address register (S0D)
Interrupt generating circuit Interrupt request signal (IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
Address comparator Serial data
(SDA)
Noise elimination circuit
Data control circuit
data shift register
circuit
Internal data
status register (S1)
circuit
Serial clock
(SCL)
Noise elimination circuit
Clock control circuit
BSEL1 BSEL0
FAST MODE CCR4 CCR3 CCR2 CCR1 CCR0
clock control register (S2) Clock division
control register (S1D) System clock counter
Fig. 8.6.1 Block Diagram Multi-master I2C-BUS Interface
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.6.1 Data Shift Register
data shift register address 00F616) 8-bit shift register store receive data write transmit data. When transmit data written into this register, transferred outside from synchronization with clock, each time one-bit data output, data this register shifted left. When data received, input this register from synchronization with clock, each time one-bit data input, data this register shifted left. data shift register write enable status only when control register (address 00F916) "1." counter reset write instruction data shift register. When both status register (address 00F816) "1," output write instruction data shift register. Reading data from data shift register always enabled regardless value.
Note: write data into data shift register after setting (slave mode), keep interval machine cycles more.
Data Shift Register
data shift register (S0) [Address 00F616]
Name
Functions
After reset
This 8-bit shift register store Indeterminate receive data write transmit data.
Note: write data into data shift register after setting (slave mode), keep interval machine cycles more.
Fig. 8.6.2 Data Shift Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.6.2 Address Register
address register (address 00F716) consists 7-bit slave address read/write bit. addressing mode, slave address written this register compared with address data received immediately after START condition detected. Read/Write (RBW) used when comparing addresses, 7-bit addressing mode. 10-bit addressing mode, first address data received compared with contents (SAD6 SAD0 RBW) address register. cleared automatically when STOP condition detected. Bits Slave Address (SAD0-SAD6) These bits store slave addresses. Regardless 7-bit addressing mode 10-bit addressing mode, address data transmitted from master compared with contents these bits.
Address Register
address register (S0D) [Address 00F716]
Name
Read/write (RBW)
Functions
<Only 10-bit addressing slave) mode> last significant address data compared. Wait first byte slave address after START condition (read state) Wait first byte slave address after RESTART condition (write state) both modes> address data compared.
After reset
Slave address (SAD0 SAD6)
Fig. 8.6.3 Address Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.6.3 Clock Control Register
clock control register (address 00FA16) used control, mode frequency. Bits Frequency Control Bits (CCR0-CCR4) These bits control frequency. Mode Specification (FAST MODE) This specifies mode. When this "0," standard clock mode set. When "1," high-speed clock mode set. (ACK BIT) This sets status when clock generated. When this "0," return mode goes occurrence clock. When "1," non-return mode set. held HIGH status occurrence clock. However, when slave address matches address data reception address data "0," automatically made (ACK returned). there mismatch between slave address address data, automatically made HIGH (ACK returned). clock: Clock acknowledgement
Clock (ACK) This specifies mode acknowledgment which acknowledgment response data transmission. When this "0," clock mode set. this case, clock occurs after data transmission. When "1," clock mode master generates clock upon completion each 1-byte data transmission.The device transmitting address data control data releases occurrence clock (make HIGH) receives generated data receiving device.
Note: write data into clock control register during transmission. data written during transmission, clock generator reset, that data cannot transmitted normally.
Clock Control Register
clock control register (S2) [Address 00FA16]
Name
frequency control bits (CCR0 CCR4) Register value
Functions
Standard clock mode High speed clock mode
After reset
Setup disabled Setup disabled Setup disabled Setup disabled 83.3
500/CCR value
(See note)
1000/CCR value
17.2 16.6 16.1
34.5 33.3 32.3
MHz, unit kHz) mode specification (FAST MODE) (ACK BIT) clock (ACK) Standard clock mode High-speed clock mode returned. returned. clock clock
Note: high-speed clock mode, duty below period period other cases, duty below. period period
Fig. 8.6.4 Clock Control
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.6.4 Control Register
control register (address 00F916) controls data communication format. Bits Counter (BC0-BC2) These bits decide number bits next 1-byte data transmitted. interrupt request signal occurs immediately after number bits specified with these bits transmitted. When START condition received, these bits become "0002" address data always transmitted received bits. Interface Enable (ESO) This enables usage multimaster interface. When this "0," disable status provided, become high-impedance. When "1," interface enabled. When "0," following performed. "1," (they bits status register address 00F816 Writing data data shift register (address 00F616) disabled.
Data Format Selection (ALS) This decides whether recognize slave addresses. When this "0," addressing format selected, that address data recognized. When match found between slave address address data result comparison when general call (refer "8.6.5 Status Register," received, transmission processing performed. When this "1," free data format selected, that slave addresses recognized. Addressing Format Selection (10BIT SAD) This selects slave address specification format. When this "0," 7-bit addressing format selected. this case, only high-order bits (slave address) address register (address 00F716) compared with address data. When this "1," 10-bit addressing format selected, bits address register compared with address data. Bits 7:Connection Control Bits between C-BUS Interface Ports (BSEL0, BSEL1) These bits controls connection between ports ports (refer Figure 8.6.5).
BSEL0 SCL1/P11 Multi-master I2C-BUS interface BSEL1 SCL2/P12 BSEL0 SDA1/P13 BSEL1 SDA2/P14
Note: When using multi-master I2C-BUS interface, bits serial mode register (address 021316) "1." Moreover, corresponding direction register port multi-master I2C-BUS interface. Fig. 8.6.5 Connection Port Control BSEL0 BSEL1
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Control Register
control register (S1D) [Address 00F916]
Name
counter (Number transmit/recieve bits) (BC0 BC2)
Functions
After reset
I2C-BUS interface enable (ESO) Data format selection (ALS) Addressing format selection (10BIT SAD)
Disabled Enabled Addressing format Free data format 7-bit addressing format 10-bit addressing format Connection port (See note) None SCL1, SDA1 SCL2, SDA2 SCL1, SDA1, SCL2, SDA2
Connection control bits between I2C-BUS interface ports (BSEL0, BSEL1)
Fig. 8.6.6 Control Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.6.5 Status Register
status register (address 00F816) controls I2C-BUS interface status. low-order bits read-only bits highorder bits read written Last Receive (LRB) This stores last value received data also used receive confirmation. returned when clock occurs, "0." returned, this "1." Except mode, last value received data input. state this changed from executing write instruction data shift register (address 00F616). General Call Detecting Flag (AD0) This when general call whose address data received slave mode. general call master device, every slave device receives control data after general call. detecting STOP condition START condition. General call: master transmits general call address "0016" slaves. Slave Address Comparison Flag (AAS) This flag indicates comparison result address data. slave receive mode, when 7-bit addressing format selected, this following conditions. address data immediately after occurrence START condition matches slave address stored high-order bits address register (address 00F716). general call received. slave reception mode, when 10-bit addressing format selected, this with following condition. When address data compared with address register bits consists slave address RBW), first bytes match. state this changed from executing write instruction data shift register (address 00F616). Arbitration Lost detecting flag (AL) master transmission mode, when device other than microcomputer sets "L,", arbitration judged have been lost, that this "1." same time, "0," that immediately after transmission byte whose arbitration lost completed, "0." When arbitration lost during slave address transmission, reception mode set. Consequently, becomes possible receive recognize slave address transmitted another master device. Arbitration lost: status which communication master disabled.
I2C-BUS Interface Interrupt Request (PIN) This generates interrupt request signal. Each time 1-byte data transmitted, state changes from "0." same time, interrupt request signal sent CPU. synchronization with falling edge last clock (including clock) internal clock interrupt request signal occurs synchronization with falling edge bit. When "0," kept state clock generation disabled. Figure 8.6.8 shows interrupt request signal generating timing chart. following conditions. Executing write instruction data shift register (address 00F616). When reset conditions which shown below: Immediately after completion 1-byte data transmission (including when arbitration lost detected) Immediately after completion 1-byte data reception slave reception mode, with immediately after completion slave address general call address reception slave reception mode, with immediately after completion address data reception Busy Flag (BB) This indicates status system. When this "0," this system busy START condition generated. When this "1," this system busy occurrence START condition disabled START condition duplication prevention function (Note). This flag written software only master transmission mode. other modes, this detecting START condition detecting STOP condition. When control register (address 00F916) reset, flag kept state. Communication Mode Specification (transfer direction specification bit: TRX) This decides direction transfer data communication. When this "0," reception mode selected data transmitting device received. When "1," transmission mode selected address data control data output into synchronization with clock generated SCL. When control register (address 00F916) slave reception mode selected, (trans_ mit) least significant (R/W bit) address data transmit_ master "1." When "0," cleared (receive). cleared following conditions. When arbitration lost detected. When STOP condition detected. When occurence START condition disabled START condition duplication prevention function (Note). With when START condition detected. With when non-return detected. reset
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Communication Mode Specification (master/slave specification bit: MST) This used master/slave specification data communication. When this "0," slave specified, that START condition STOP condition generated master received, data communication performed synchronization with clock generated master. When this "1," master specified START condition STOP condition generated, also clocks required data communication generated SCL. cleared following conditions. Immediately after completion 1-byte data transmission when arbitration lost detected When STOP condition detected. When occurence START condition disabled START condition duplication preventing function (Note). reset
Note: START condition duplication prevention function disables START condition generation, reset counter reset, output, when following condition satisfied: START condition another master device.
Status Register
status register (S1) [Address 00F816]
Name
Last receive (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request (PIN) busy flag (BB)
Functions
Last Last (See note)
After reset
Indeterminate (See note)
general call detected General call detected (See note) Address mismatch Address match detected Detected
(See note) Interrupt request issued interrupt request issued
free busy Slave recieve mode Slave transmit mode Master recieve mode Master transmit mode
Communication mode specification bits (TRX, MST)
Note These bits flags read out, cannnot written.
Fig. 8.6.7 Status Register
IICIRQ
Fig. 8.6.8 Interrupt Request Signal Generation Timing
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.6.6 START Condition Generation Method
When control register (address 00F916) "1," execute write instruction status register (address 00F816) MST, bits "1." START condition will then generated. After that, counter becomes "0002" byte output. START condition generation timing timing different standard clock mode highspeed clock mode. Refer Figure 8.6.9 START condition generation timing diagram, Table 8.6.2 START condition/ STOP condition generation timing table. status register write signal flag Setup time Setup time Hold time time flag
Fig. 8.6.9 START Condition Generation Timing Diagram
8.6.7 STOP Condition Generation Method
When control register (address 00F916) "1," execute write instruction status register (address 00F816) setting "0". STOP condition will then generated. STOP condition generation timing flag reset timing different standard clock mode high-speed clock mode. Refer Figure 8.6.10 STOP condition generation timing diagram, Table 8.6.2 START condition/STOP condition generation timing table.
status register write signal flag Setup time Hold time Reset time flag
Fig. 8.6.10 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Timing Table Item Setup time Hold time Set/reset time flag Standard Clock Mode 4.25 cycles) cycles) cycles) High-speed Clock Mode 1.75 cycles) cycles) cycles)
Note: Absolute time MHz. value parentheses denotes number cycles.
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.6.8 START/STOP Condition Detect Conditions
START/STOP condition detect conditions shown Figure 8.6.11 Table 8.6.3. Only when conditions Table 8.6.3 satisfied, START/STOP condition detected.
Note: When STOP condition detected slave mode (MST interrupt request signal "IICIRQ" generated CPU.
8.6.9 Address Data Communication
There address data communication formats, namely, 7-bit addressing format 10-bit addressing format. respective address communication formats described below. 7-bit Addressing Format meet 7-bit addressing format, 10BIT control register (address 00F916) "0." first 7-bit address data transmitted from master compared with high-order 7-bit slave address stored address register (address 00F716). time this comparison, address comparison address register (address 00F716) made. data transmission format when 7-bit addressing format selected, refer Figure 8.6.12, (2). 10-bit Addressing Format meet 10-bit addressing format, 10BIT control register (address 00F916) "1." address comparison made between first-byte address data transmitted from master 7-bit slave address stored address register (address 00F716). time this comparison, address comparison between address register (address 00F716) which last address data transmitted from master made. 10-bit addressing mode, which last address data only specifies direction communication control data also processed address data bit. When first-byte address data matches slave address, status register (address 00F816) "1." After second-byte address data stored into data shift register (address 00F616), make address comparison between second-byte data slave address software. When address data bytes matches slave address, address register (address 00F716) software. This processing match 7-bit slave address data, which received after RESTART condition detected, with value address register (address 00F716). data transmission format when 10-bit addressing format selected, refer Figure 8.6.12, (4).
release time (START condition) (STOP condition) Setup time Setup time Hold time Hold time
Fig. 8.6.11 START Condition/STOP Condition Detect Timing Diagram
Table 8.6.3 START Condition/STOP Condition Detect Conditions Standard Clock Mode cycles) release time 3.25 cycles) Setup time 3.25 cycles) Hold time High-speed Clock Mode cycles) release time cycles) Setup time cycles) Hold time
Note: Absolute time MHz. value parentheses denotes number cycles.
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.6.10 Example Master Transmission
example master transmission standard clock mode, frequency return mode shown below. slave address high-order bits address register (address 00F716) bit. return mode setting "8516" clock control register (address 00FA16). "1016" status register (address 00F816) hold HIGH. communication enable status setting "4816" control register (address 00F916). address data destination transmission highorder bits data shift register (address 00F616) least significant bit. "F016" status register (address 00F816) generate START condition. this time, byte clock automatically occurs. transmit data data shift register (address 00F616). this time, clock automatically occurs. When transmitting control data more than byte, repeat step "D016" status register (address 00F816). After this, returned transmission ends, STOP condition will generated.
8.6.11 Example Slave Reception
example slave reception high-speed clock mode, frequency kHz, non-return mode, using addressing format, shown below. slave address high-order bits address register (address 00F716) bit. clock mode setting "2516" clock control register (address 00FA16). "1016" status register (address 00F816) hold HIGH. communication enable status setting "4816" control register (address 00F916). When START condition received, address comparison made. transmitted address are"0" (general call): status register (address 00F816) "1"and interrupt request signal occurs. transmitted addresses match address status register (address 00F816) interrupt request signal occurs. cases other than above: status register (address 00F816) interrupt request signal occurs. dummy data data shift register (address 00F616). When receiving control data more than byte, repeat step When STOP condition detected, communication ends.
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Slave address
Data
Data
bits bits bits master-transmitter transmits data slave-receiver
Slave address
Data
Data
bits bits bits master-receiver receives data from slave-transmitter Slave address bits Slave address byte
Data
Data
bits bits bits bits master-transmitter transmits data slave-receiver with 10-bit address Slave address bits Slave address byte Slave address bits
Data
Data bits
bits bits bits bits master-receiver receives data from slave-transmitter with 10-bit address START condition Restart condition STOP condition Read/Write From master slave From slave master
Fig. 8.6.12 Address Data Communication Format 8.6.12 Precautions when using multi-master I2C-BUS interface Read-modify-write instruction precautions when read-modify-write instruction such SEB, etc. executed each register multi-master I2C-BUS interface described below. data shift register (S0) When executing read-modify-write instruction this register during transfer, data become value intended. address register (S0D) When read-modify-write instruction executed this register detecting STOP condition, data become value intended. because hardware changes read/write (RBW) above timing. status register (S1) execute read-modify-write instruction this register because bits this register changed hardware. control register (S1D) When read-modify-write instruction executed this register detecting START condition completing byte transfer, data become value intended. Because hardware changes counter (BC0-BC2) above timing. clock control register (S2) read-modify-write instruction executed this register. START condition generating procedure using multi-master Procedure example (The necessary conditions generating procedure described following
5,S1,BUSBUSY BUSFREE: #$F0, BUSBUSY:
(Taking slave address value) (Interrupt disabled) flag confirming branch process) (Writing slave address value) (Trigger START condition generating) (Interrupt enabled)
(Interrupt enabled)
"STA," "STX" "STY" zero page addressing instruction writing slave address value data shift register. "LDM" instruction setting trigger START condition generating. Write slave address value above trigger START condition generating above continuously shown above procedure example. Disable interrupts during following three process steps: flag confirming Writing slave address value Trigger START condition generating When condition flag busy, enable interrupts immediately.
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
RESTART condition generating procedure
Procedure example (The necessary conditions generating procedure described following Execute following procedure when "0." #$00, #$F0, Select slave receive mode when "0." write bit. Neither specified writing bit. becomes released. released writing slave address value data shift register. "STA," "STX" "STY" zero page addressing instruction writing. "LDM" instruction setting trigger RESTART condition generating. Write slave address value above trigger RESTART condition generating above continuously shown above procedure example. Disable interrupts during following process steps: Writing slave address value Trigger RESTART condition generating
STOP condition generating procedure
Procedure example (The necessary conditions generating procedure described following
(Select slave receive mode) (Taking slave address value) (Interrupt disabled) (Writing slave address value) (Trigger RESTART condition generating) (Interrupt enabled)
#$C0, #$D0,
(Interrupt disabled) (Select master transmit mode) (Set NOP) (Trigger STOP condition generating) (Interrupt enabled)
Write when master transmit mode select. Execute "NOP" instruction after setting master transmit mode. Also, trigger STOP condition generating within cycles after selecting master trasmit mode. Disable interrupts during following process steps: Select master transmit mode Trigger STOP condition generating
Writing status register
execute instruction from instruction bits from simultaneously. because enter state that released released after about machine cycle. execute instruction bits from simultaneously when "1." because become same above.
Process after STOP condition generating
write data data shift register status register until busy flag becomes after generating STOP condition master mode. because STOP condition waveform might normally generated. Reading above registers have problem.
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
OUTPUT CIRCUIT
This microcomputer equipped with eight 8-bit PWMs (PWM0- PWM7). PWM0-PWM7 have same circuit structure 8-bit resolution with minimum resolution width repeat period 1024 (for f(XIN) MHz) Figure 8.7.1 shows block diagram. timing generating circuit applies individual control signals PWM0-PWM7 using f(XIN) divided reference signal.
8.7.1 Data Setting
When outputting PWM0-PWM7, 8-bit output data PWMi register means addresses 020016 020716).
8.7.2 Transmitting Data from Register circuit
Data transfer from register circuit executed writing data register. signal output from output corresponds contents this register.
8.7.3 Operation
following explains operation. First, mode register (address 020A16) reset, already automatically), that count source supplied. PWM0-PWM3 also used pins P04-P07, PWM4-PWM6 also used pins P00-P02, PWM7 also used respectively. corresponding bits port direction register (output mode). select each output polarity mode register (address 020A16). Then, bits mode register (PWM output). waveform output from output pins setting these registers. Figure 8.7.2 shows timing. cycle composed (28) segments. kinds pulses, relative weight each (bits output inside circuit during cycle. Refer Figure 8.7.2 (a). outputs waveform which logical (OR) pulses corresponding contents bits register. Several examples shown Figure 8.7.2 (b). kinds output (HIGH area: 0/256 255/256) selected changing contents register. length entirely HIGH cannot output, i.e. 256/256.
8.7.4 Output after Reset
reset, output port high-impedance state, contents register circuit undefined. Note that after reset, output undefined until setting register.
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Data timing generating circuit PWM0 register (Address 020016)
circuit
PWM0
PWM1
PWM1 register (Address 020116)
PWM2
PWM2 register (Address 020216)
PWM3
PWM3 register (Address 020316)
PWM4
PWM4 register (Address 020416)
PWM5
PWM5 register (Address 020516)
PWM6
PWM6 register (Address 020616)
PWM7 register (Address 020716)
Selection gate: Connected black side reset. Inside same contents with others.
mode register [address 020A16] mode register [address 020B16] Port register [address 00C016] Port direction register [address 00C116] PWM7
Fig. 8.7.1 Block Diagram
Rev.
3579
Fig. 8.7.2 Timing
Pulses showing weight each
0016
0116
1816 (24)
FF16 (255)
output 1024 f(XIN) Example 8-bit
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Mode Register
mode register (PN) [Address 020A16] Name counts source selection (PN0) Functions Count source supply Count source stop After reset
Nothing assigned. These bits write disable bits. When these bits read out, values "0." output polarity selection (PN3) P03/PWM7 output selection (PN4) Positive polarity Negative polarity output PWM7 output
Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.7.3 Mode Register
Mode Register
mode register (PW) [Address 020B16] Name Functions output PWM0 output output PWM1 output output PWM2 output output PWM3 output output PWM4 output output PWM5 output output PWM6 output
After reset
P04/PWM0 output selection (PW0) P05/PWM1 output selection (PW1) P06/PWM2 output selection (PW2) P07/PWM3 output selection (PW3)
P00/PWM4 output selection (PW4) P01/PWM5 output selection (PW5) P02/PWM6 output selection (PW6) this "0."
Fig. 8.7.4 Mode Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
CONVERTER 8.8.1 Conversion Register (AD)
conversion reigister read-only register that stores result conversion. This register should read during conversion.
8.8.3 Comparison Voltage Generator (Resistor Ladder)
voltage generator divides voltage between 256, outputs divided voltages comparator reference voltage Vref.
8.8.2 Control Register (ADCON)
control register controls conversion. Bits this register select analog input pins. When these pins used analog input pins, they used ordinary pins. conversion completion bit, conversion started writing this bit. value this remains during conversion, then changes when conversion completed. controls connection between resistor ladder VCC. When using converter, resistor ladder from internal setting this "0," accordingly providing lowpower dissipation.
8.8.4 Channel Selector
channel selector connects analog input pin, selected bits control register, comparator.
8.8.5 Comparator Control Circuit
conversion result analog input voltage reference voltage "Vref" stored conversion register. conversion completion conversion interrupt request completion conversion.
Data
control register (address 00EF16)
control circuit Comparator conversion register (address 00EE16)
conversion interrupt request
Channel selector
Switch tree
Resistor ladder
Fig. 8.8.1 Comparator Block Diagram
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Control Register
control register (ADCON) [Address 00EF16]
Name
Analog input selection bits (ADIN0 ADIN2)
Functions
After reset
conversion completion (ADSTR) connection selection (ADVREF) this "0."
Conversion progress Convertion completed
Indeterminate
Nothing assigned. This write disable bit. When this read out, value indeterminate. this "0."
Fig. 8.8.2 Control Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.8.6 Conversion Method
interrupt input polarity register (address 021216) generate interrupt request completion conversion. conversion INT3 interrupt request (even when conversion started, conversion INT3 interrupt reguest automatically). When using conversion interrupt, enable interrupts setting conversion INT3 interrupt request setting interrupt disable flag "0." connection selection connect resistor ladder. Select analog input pins analog input selection control register. conversion completion "0." This write operation starts conversion. read conversion register during conversion. Verify completion conversion state ("1") conversion completion bit, state ("1") conversion INT3 interrupt reguest bit, occurrence conversion interrupt. Read conversion register obtain conversion results.
Note When ladder resistor disconnect from VCC, connection selection between steps
8.8.7 Internal Operation
When conversion starts, following operations automatically performed. conversion register "0016." most significant conversion register becomes comparison voltage "Vref" input comparator. this point, Vref compared with analog input voltage "VIN determined comparison results follows. When Vref holds When Vref becomes With above operations, analog value converted into digital value. conversion terminates maximum machine cycles (12.5 f(XIN) MHz) after starts, conversion result stored conversion register. conversion interrupt request occurs same time conversion completion, conversion INT3 interrupt request becomes "1." conversion completion also becomes "1."
Table 8.8.1 Expression Vref VREF conversion register contents (decimal notation)
Note: VREF indicates reference voltage Vcc).
Vref VREF 0.5)
Contents conversion register conversion start
Reference voltage (Vref)
VREF VREF VREF
VREF VREF VREF VREF VREF VREF
comparison start comparison start comparison start
comparison start
VREF VREF VREF VREF VREF
conversion completion (8th comparison completion)
Digital value corresponding analog input voltage.
Value determined result
Fig. 8.8.3 Changes Conversion Register Comparison Voltage during Conversion
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.8.8 Definition Conversion Accuracy
definition conversion accuracy described below (refer Figure 8.8.4). Accuracy shown difference between measurement result output code output code which expected conversion whose specification ideal using LSB. analog input voltage accuracy measurement made middle point input voltage width LSB) which outputs code which converter with ideal characteristics identical. example, LSB's width VREF 5.12V. selected analog input voltage. conversion accuracy shown 8.8.4. That output code expected ideal converter "0516" shows that there actual conversion result with "0316" "0716" ±2LSB absolute accuracy, when analog input voltage And, zero error scale error contained absolute accuracy, quantization error contained.
Output code 0916 0816 Absolute accuracy 0716 0616 0516 0416 0316 2LSB 0216 0116 0016 Analog input voltage (mV)
Fig. 8.8.4 Definition Conversion Accuracy
2LSB Ideal conversion characteristics Limitless resolution conversion characteristics
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
CORRECTION FUNCTION
This correct program data ROM. addresses corrected, program correction stored correction vector address. correction vectors vectors. Vector address 02C016 Vector address 02E016 address data corrected into correction address register. When value counter matches data address correction vector address, main program branches correction program stored memory correction. return from correction program main program, code operand instruction (total bytes) necessary correction program. correction function controlled correction enable register.
Notes Specify first address code address) each instruction correction address. instruction (total bytes) return from correction program main program. same correction address vectors M37281MKH-XXXSP M37281EKSP, when using expansion (BK7 "1"), correction function operate used addresses 100016 to1FFF16. Note that programming.
correction address (high-order) 020C16 correction address (low-order) 020D16
correction address (high-order) 020E16 correction address (low-order) 020F16
Fig. 8.9.1 Correction Address Registers
Correction Enable Register
correction enable register (RCR) [Address 021016]
Name
Vector enable (RCR0) Vector enable (RCR1)
Functions
Disabled Enabled Disabled Enabled
After reset
these bits "0."
Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.9.2 Correction Enable Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.10 DATA SLICER
This microcomputer includes data slicer function closed caption decoder (referred CCD). This function takes caption data superimposed vertical blanking interval composite video signal. composite video signal which makes sync chip's polarity negative input CVIN pin.
When data slicer function used, data slicer circuit timing signal generating circuit setting data slicer control register (address 00E016) "0." These settings realize low-power dissipation.
Composite video signal
Sync pulse counter register (address 00E916)
CVIN
HSYNC
Synchronizing signal counter Clamping circuit Low-pass filter Sync slice circuit
Synchronizing separation circuit
Data slicer control register (address 00E116)
Data slicer control register (address 00E016) Timing signal generating circuit
Data slicer ON/OFF
Reference voltage generating 1000 circuit
VHOLD
Comparator
Clock run-in determination circuit
Data slice line specification circuit
Clock run-in defect register (address 00EA16)
Start detecting circuit
External circuit Note Make length wiring which connected VHOLD, HLF, CVIN short possible that leakage current generated when mounting resistor capacitor each pin.
Caption position register (address 00E616)
Data clock generating circuit Data clock position register (address 00EB16) 16-bit shift register Interrupt request generating circuit
high-order low-order Caption data register (address 00E216)
Data slicer interrupt request
Caption data register (address 00E316)
Caption data register (address 00E516)
Caption data register (address 00E416)
Data
Fig. 8.10.1 Data Slicer Block Diagram
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.10.1 Notes When Using Data Slicer
When data slicer control register (address 00E016) "0," terminate pins shown Figure 8.10.2.
<When data slicer circuit timing signal generating circuit state>
Apply same voltage pin.
AVCC
Apply level. Apply VHOLD level. Pull-up CVIN through resistor more.
VHOLD
CVIN
Only M37281EKSP have AVCC pin. This non-connection M37281MAH-XXXSP, M37281MFH-XXXSP, M37281MKH-XXXSP. M37281MAH-XXXSP, M37281MFH-XXXSP, M37281MKH-XXXSP connect apply Vcc.
Fig. 8.10.2 Termination Data Slicer Input/Output Pins when Data Slicer Circuit Timing Generating Circuit State
When both bits data slicer control register (address 00E016) "1," terminate pins shown Figure 8.10.3.
<When using reference clock generated timing signal generating circuit clock>
Apply same voltage pin.
AVCC
Connect same external circuit when using data slicer pin. Leave VHOLD open. Pull-up CVIN through resistor more.
200pF
Open
VHOLD
more
CVIN
Only M37281EKSP have AVCC pin. This non-connection M37281MAH-XXXSP, M37281MFH-XXXSP, M37281MKH-XXXSP. M37281MAH-XXXSP, M37281MFH-XXXSP, M37281MKH-XXXSP connect apply Vcc.
Fig. 8.10.3 Termination Data Slicer Input/Output Pins when Timing Signal Generating Circuit State
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Figures 8.10.4 8.10.5 data slicer control registers.
Data Slicer Control Register
Data slicer control register 1(DSC1) [Address 00E016] Name Functions Stopped Operating Video signal SYNC signal After reset
Data slicer timing signal generating circuit control (DSC10) Selection data slice reference voltage generating field (DSC11) Reference clock source selection (DSC12) these bits "0."
Definition fields (F1) (F2) Hsep Vsep Hsep Vsep
Fig. 8.10.4 Data Slicer Control Register
Data Slicer Control Register
Data slicer control register (DSC2) [Address 00E116]
Name Caption data latch completion flag (DSC20)
Functions Data latched clock-run-in determined. Data latched clock-run-in determined.
After reset
Indeterminate
this "0." Test Field determination flag(DSC23) Read-only
Indeterminate Indeterminate
Vertical synchronous signal Method Method (Vsep) generating method selection (DSC24) Match V-pulse shape determination flag (DSC25) Mismatch this "0." Test Read-only
Indeterminate
Indeterminate
Definition fields (F1) (F2) Hsep Vsep Hsep Vsep
Fig. 8.10.5 Data Slicer Control Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.10.2 Clamping Circuit Low-pass Filter
clamp circuit clamps sync chip part composite video signal input from CVIN pin. low-pass filter attenuates noise clamped composite video signal. CVIN which composite video signal input requires capacitor (0.1 coupling outside. Pull down CVIN with resistor hundreds kiloohms addition, recommend install externally simple lowpass filter using resistor capacitor CVIN (refer Figure 8.10.1).
Composite sync signal Measure period Timing signal
8.10.3 Sync Slice Circuit
This circuit takes composite sync signal from output signal low-pass filter.
Vsep signal
8.10.4 Synchronous Signal Separation Circuit
This circuit separates horizontal synchronous signal vertical synchronous signal from composite sync signal taken sync slice circuit. (1)Horizontal Synchronous Signal (Hsep) one-shot horizontal synchronizing signal Hsep generated falling edge composite sync signal. (2)Vertical Synchronous Signal (Vsep) Vsep signal generating method, possible select following methods using data slicer control register (address 00E116). level width composite sync signal measured. this width exceeds certain time, Vsep signal generated synchronization with rising timing signal immediately after this level. level width composite sync signal measured. this width exceeds certain time, detected whether falling composite sync signal exits level period timing signal immediately after this level. falling exists, Vsep signal generated synchronization with rising timing signal (refer Figure 8.10.6). Figure 8.10.6 shows Vsep generating timing. timing signal shown figure generated from reference clock which timing generating circuit outputs. Reading data slicer control register permits determinating shape V-pulse portion composite sync signal. shown Figure 8.10.7, when level matches level, this "0." case mismatch, "1."
Vsep signal generated rising timing signal immediately after level width composite sync signal exceeds certain time.
Fig. 8.10.6 Vsep Generating Timing (method
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.10.5 Timing Signal Generating Circuit
This circuit generates reference clock which times large horizontal synchronous signal frequency. also generates various timing signals basis reference clock, horizontal synchronous signal vertical synchronizing signal. circuit operates setting data slicer control register (address 00E016) "1." reference clock used display clock function addition data slicer. HSYNC signal used count source instead composite sync signal. However, when HSYNC signal selected, data slicer cannot used. count source reference clock selected data slicer control register (address 00E016). pins HLF, connect resistor capacitor shown Figure 8.10.1. Make length wiring which connected these pins short possible that leakage current generated.
Note: takes tens milliseconds until reference clock becomes stable after data slicer timing signal generating circuit started. this period, various timing signals, Hsep signals Vsep signals become unstable. this reason, take stabilization time into consideration when programming.
DSC2 Composite sync signal
Fig. 8.10.7 Determination V-pulse Waveform
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.10.6 Data Slice Line Specification Circuit
Specification Data Slice Line This circuit decides line which caption data superimposed. line (fixed), appropriate line period field (total line period field), both fields sliced their data. caption position register (address 00E616) used each setting (refer Table 8.10.1). counter reset falling edge Vsep incremented every Hsep pulse. When counter value matched value specified bits caption position register, this Hsep sliced. values "0016" "1F16" caption position register setting only appropriate line). Figure 8.10.8 shows signals vertical blanking interval. Figure 8.10.9 shows structure caption position register. Specification Line Slice Voltage reference voltage slicing (slice voltage) generated clock run-in pulse particular line (refer Table 8.10.1). field generate slice voltage specified data slicer control register line generate slice voltage field specified bits caption position register (refer Table 8.10.1).
Field Determination field determination flag read data slicer control register This flag charge falling edge Vsep.
Video signal
Vertical blanking interval
Composite video signal Vsep
appropriate line caption position register Line (when setting line
Hsep
Count value caption position register ("0F16" this case)
Magnified drawing
Hsep Clock run-in Start 16-bit data
Composite video signal Window deteminating clock-run-in
Start
Fig. 8.10.8 Signals Vertical Blanking Interval
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
Caption Position Register
Caption Position Register (CPS) [Address 00E616]
Name Caption position bits(CPS0 CPS4) Caption data latch completion flag (CPS5)
Functions
After reset
Data latched Indeterminate clock-run-in determined. Data latched clock-run-in determined. Refer corresponding Table (Table 8.10.1).
Slice line mode specification bits field) (CPS6, CPS7)
Fig. 8.10.9 Caption Position Register
Table 8.10.1 Specification Data Slice Line Field Line Sliced Data Both fields Line line specified bits (total lines) (See note Both fields line specified bits (total line) (See note Both fields Line (total line) Both fields Line line specified bits (total lines) (See note Field Line Generate Slice Voltage Field specified DSC1 Line (total line) Field specified DSC1 line specified bits (total line) (See note Field specified DSC1 Line (total line) Field specified DSC1 Line line specified bits (total lines) (See note
Notes DSC1 data slicer control register caption position register. "0016" "1016" bits CPS. "0016" "1F16" bits CPS.
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.10.7 Reference Voltage Generating Circuit Comparator
composite video signal clamped clamping circuit input reference voltage generating circuit comparator. Reference Voltage Generating Circuit This circuit generates reference voltage (slice voltage) using amplitude clock run-in pulse line specified data slice line specification circuit. Connect capacitor between VHOLD pin, make length wiring short possible that leakage current generated. Comparator comparator compares voltage composite video signal with voltage (reference voltage) generated reference voltage generating circuit, converts composite video signal into digital value.
8.10.8 Start Detecting Circuit
This circuit detects start line decided data slice line specification circuit. detection start described below. sampling clock generated dividing reference clock timing signal. clock run-in pulse detected sampling clock. After detection pulse, start pattern detected from comparator output.
8.10.9 Clock Run-in Determination Circuit
This circuit determinates clock run-in counting number pulses window composite video signal. reference clock count value pulse cycle stored bits clock run-in detect register (address 00EA16). Read these bits after occurrence data slicer interrupt (refer "8.10.12 Interrupt Request Generating Circuit"). Figure 8.10.10 shows structure clock run-in detect register.
Clock Run-in Detect Register
Clock run-in detect register (CRD) [Address 00EA16]
Test bits
Name Read-only
Functions
After reset
Clock run-in detection bit(CRD3 CRD7)
Number reference clocks counted clock run-in pulse period.
Fig. 8.10.10 Clock Run-in Detect Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.10.10 Data Clock Generating Circuit
This circuit generates data clock synchronized with start detected start detecting circuit. data clock stores caption data 16-bit shift register. When 16-bit data been stored clock run-in determination circuit determines clock run-in, caption data latch completion flag set. This flag reset falling vertical synchronous signal (Vsep).
Data Clock Position Register
Data clock position register (DPS) [Address 00EB16]
Name these bits "1."
Functions
After reset
this "0." Data clock position bits (DPS3 DPS7)
Fig. 8.10.11 Data Clock Position Register
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.10.11 16-bit Shift Register
caption data converted into digital value comparator stored into 16-bit shift register synchronization with data clock. contents high-order bits stored caption data obtained reading data register (address 00E316) data register (address 00E516). contents low-order bits obtained reading data register (address 00E216) data register (address 00E416), respectively. These registers reset falling Vsep. Read data registers after occurrence data slicer interrupt (refer "8.10.12 Interrupt Request Generating Circuit").
8.10.12 Interrupt Request Generating Circuit
interrupt requests shown Table 8.10.3 generated combination following bits; bits caption position register (address 00E616). Read contents data registers contents bits clock run-in detect register after occurrence data slicer interrupt request.
Table 8.10.2 Contents Caption Data Latch Completion Flag 16-bit Shift Register Slice Line Specification Mode Contents Caption Data Latch Completion Flag Completion Flag (bit DSC2) Line line specified bits Line Line Completion Flag (bit CPS) line specified bits Invalid Invalid line specified bits Contents 16-bit Shift Register Caption Data Registers 16-bit data line 16-bit data line specified bits 16-bit data line 16-bit data line Caption Data Registers 16-bit data line specified bits Invalid Invalid 16-bit data line specified bits
CPS: Caption position register DSC2: Data slicer control register
Table 8.10.3 Occurence Sources Interrupt Request Caption position register Occurence Souces Interrupt Request Data Slice Line After slicing line After line specified bits After slicing line After slicing line
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.10.13 Synchronous Signal Counter
synchronous signal counter counts composite sync signal taken from video signal data slicer circuit vertical synchronous signal Vsep count source. count value certain time time) generated f(XIN)/213 f(XIN)/213 stored into 5-bit latch. Accordingly, latch value changes cycle time. When count value exceeds "1F16," "1F16" stored into latch.
latch value obtained reading sync pulse counter register (address 00E916). count source selected sync pulse counter register. synchronous signal counter used when mode register (address 020816). Figure 8.10.12 shows structure sync pulse counter Figure 8.10.13 shows synchronous signal counter block diagram.
Sync Pulse Counter Register
Sync pulse counter register (HC) [Address 00E916]
Name Count value (HC0 HC4)
Functions
After reset
Indeterminate
Count source (HC5)
SYNC signal Composite sync signal
Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.10.12 Sync Pulse Counter Register
f(XIN)/213
Composite sync signal HSYNC signal
Reset 5-bit counter Counter
Latch bits)
Sync pulse counter register
Selection gate connected black side when reset.
Data
Fig. 8.10.13 Synchronous Signal Counter Block Diagram
Rev.
M37281MAH-XXXSP,M37281MFH-XXXSP M37281MKH-XXXSP,M37281EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER ON-SCREEN DISPLAY CONTROLLER
8.11 FUNCTIONS
Table 8.11.1 outlines functions. This function display following: block display characters lines), SPRITE display. besides, function display both display same time. There display modes they selected block unit. display modes selected block control register 16). features each mode described below.
Table.8.11.1 Features Each Display Style
Block display mode (Closed caption mode) mode (On-screem display mode) characters lines dots (Character display area: dots) kinds kinds kinds
1/2H, 1.5TC 1/2H, 1.5TC
Display style Parameter
Number display characters
CDOSD mode (Color on-screen display mode)
SPRITE display
character dots dots
structure
dots
Kinds characters Font memory Kinds character Pre-divide sizes size
kinds
kind kinds 1/2H,
ratio (Note
1/2H,
Attribute
Smooth italic, under l
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