Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater

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Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater

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19-2098; 1/02
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater
MAX3754/MAX3755 quad-port bypass circuits (PBCs) designed Fibre Channel Arbitrated Loop applications. Each consists four serially connected port bypass circuits repeater that provides clock data recovery. quad-PBC allows connection four Fibre Channel L-ports; each enabled bypassed individual logic inputs. reduce external parts count, signal inputs outputs have internal termination resistors. MAX3754/MAX3755 comply with Fibre Channel jitter tolerance requirements recover data signals with unit intervals (UIs) high-frequency jitter. These devices operate from single +3.3V supply.
Features
Selectable 1.0625Gbps/2.125Gbps Dual-Rate Operation Meets Fibre Channel Jitter Tolerance 1400mV Typical Differential Output Swing 3.0V 3.6V Operation Reference Clock Required Frequency Lock Indication Power Consumption (MAX3754) +3.3V Differential L-Port Impedance Available
MAX3754/MAX3755
Applications
LOUT2+ LOUT2-
Configuration
LOUT3+ LOUT3GND LIN3+
1.0625Gbps/2.125Gbps Dual-Rate Fibre Channel Fibre Channel Data Storage Systems Storage Area Networks Fibre Channel Hubs
LIN1LIN1+ LOUT11
LIN2+ LIN2-
LIN3-
LOUT4+ LOUT4GND LIN4+ LIN4GND OUTOUT+ LOCK
Typical Operating Circuit appears data sheet.
LOUT1+ ININ+ CLKEN
MAX3754 MAX3755
CDREN RATESEL
SEL1 SEL2
SEL3 SEL4
TQFP-EP*
*EXPOSED MUST CONNECTED GROUND
Ordering Information
PART MAX3754CCM MAX3755CCM TEMP RANGE +70°C +70°C PIN-PACKAGE TQFP-EP TQFP-EP DIFFERENTIAL LOUT TERMINATION DIFFERENTIAL TERMINATION
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater MAX3754/MAX3755
ABSOLUTE MAXIMUM RATINGS
.-0.5V Current into OUT±, LOUT1±, LOUT2±, LOUT3±, LOUT4±. 22mA Voltage OUT±, LOUT1±, LOUT2±, LOUT3±, LOUT4± .(VCC 1.65V) (VCC 0.5V) Voltage IN±, LIN1±, LIN2±, LIN3±, LIN4±.-0.5V (VCC 0.5V) Voltage CLKEN, CF+, CF-, CDREN, RATESEL, SEL_, LOCK.-0.5V (VCC 0.5V) Current into LOCK.-1mA +10mA Continuous Power Dissipation +70°C) 48-Pin TQFP-EP (derate 30.0mW/°C above +70°C) Operating Junction Temperature Range .-55°C +150°C Operating Temperature Range .-55°C +110°C Storage Temperature Range .-55°C +150°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC +3.0V +3.6V, CLKEN GND, 8B/10B data coding, 0.047µF, +70°C, unless otherwise noted. Typical values +3.3V, +25°C.)
PARAMETER CDREN Supply Current (Note CDREN Input Data Rate Range Differential Input Voltage Swing Input Common-Mode Voltage Differential Output Voltage Swing Differential L-Port Input Resistance Differential L-Port Output Resistance Differential Input Resistance Differential Output Resistance OUT± Input Voltage High Input Voltage Input Current LOCK Output Voltage LOCK Output High Voltage Differential Voltage across Data Propagation Delay OUT±, SEL_ GND, CDREN LIN(n)± LOUT(n+1)±, LIN4± OUT± input voltages +1mA (sinking) -100µA (sourcing) RLOAD RSOURCE MAX3754 MAX3755 MAX3754 MAX3755 1000 CONDITIONS MAX3754 MAX3755 MAX3754 MAX3755 -100 -100 0.45 1400 1800 +100 +100 2200 mVP-P mVP-P UNITS
1.0625Gbps operation, RATESEL 2.125Gbps operation, RATESEL
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater
ELECTRICAL CHARACTERISTICS (continued)
(VCC +3.0V +3.6V, CLKEN GND, 8B/10B data coding, 0.047µF, +70°C, unless otherwise noted. Typical values +3.3V, +25°C.)
PARAMETER Channel Select Delay Data Valid Data Transition Time Supply Noise Tolerance (Note Lock Time OPERATION 2.125Gbps (Note Pattern K28.7, CDREN (Note Random Jitter OUT±, Pattern K28.7, CDREN L-Port Outputs± Pattern CRPAT, CDREN (Notes Pattern K28.5+, CDREN (Note Deterministic Jitter OUT±, L-Port Outputs± Total Jitter OUT±, LOUT_± Sinusoidal Component Jitter Tolerance (BER 10-12) Deterministic Jitter Tolerance Total High-Frequency Jitter Tolerance Jitter Transfer Bandwidth Jitter Transfer Peaking (Note psP-P psP-P psRMS OPERATION 1.0625Gbps (Note Pattern K28.7, CDREN (Note Random Jitter OUT±, Pattern K28.7, CDREN L-Port Outputs± Pattern CRPAT, CDREN (Notes Pattern K28.5+, CDREN (Note Deterministic Jitter OUT±, L-Port Outputs± Total Jitter OUT±, LOUT_± Sinusoidal Component Jitter Tolerance (BER 10-12) Pattern K28.5+, CDREN Pattern RPAT, CDREN (Notes Pattern RPAT, CDREN (Notes 42.5kHz sine wave Pattern CJTPAT (Notes 635kHz sine wave 5MHz sine wave Pattern K28.5+, CDREN Pattern RPAT, CDREN (Notes Pattern RPAT, CDREN (Notes 85kHz sine wave Pattern CJTPAT (Notes CJTPAT (Note Pattern CJTPAT (Notes 1.27MHz sine wave 10MHz sine wave 0.05 CONDITIONS SEL(n)± LOUT(n+1)± SEL4 OUT± 10Hz 100Hz 100Hz 1MHz 1MHz 2.5GHz psP-P psP-P psRMS mVP-P UNITS
MAX3754/MAX3755
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater MAX3754/MAX3755
ELECTRICAL CHARACTERISTICS (continued)
(VCC +3.0V +3.6V, CLKEN GND, 8B/10B data coding, 0.047µF, +70°C, unless otherwise noted. Typical values +3.3V, +25°C.)
PARAMETER Deterministic Jitter Tolerance Total High-Frequency Jitter Tolerance Jitter Transfer Bandwidth Jitter Transfer Peaking (Note CONDITIONS CJTPAT (Note Pattern CJTPAT (Notes 0.05 UNITS
Includes output currents. Meets jitter output specifications with noise applied. characteristics guaranteed design characterization. K28.7 Pattern: 1111 1000 Compliant Random Pattern (CRPAT): Pattern Sequence: Repetitions: 6C64 Note Parameter measured with 0.40UI deterministic 0.20UI random jitter (BER 10-12 applied input. ports bypassed, SEL_ low. Jitter compliance with inter-enclosure, Fibre Channel jitter tolerance compliance point jitter output compliance point specifications (FC-PI 10.0). Output jitter specified output total given non-zero jitter input. Note K28.5± Pattern: 1111 1010 0000 0101 Note Random Pattern (RPAT): 3EB0 5C67 85D3 172C A856 D84B B6A6 Note Using differential drive over entire input amplitude range. input signal bandwidth limited 0.75 (bit-rate) 4th-order Bessel-Thompson filter equivalent. Total jitter (TJ) range pattern where error rate exceeds 10-12. estimated RJ). deterministic jitter. sigma distribution (RMS) random jitter. Note Compliant Jitter Tolerance Pattern (CJTPAT): Pattern Sequence: Repetitions: Note Parameter measured with 0.1UI sinusoidal jitter 10MHz 2.125Gbps data rate, 5MHz 1.0625Gbps. Note Simulation shows peaking 0.01dBm max. Characterization results limited test equipment. Note Note Note Note Note
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater
Typical Operating Characteristics
(VCC +3.3V, 0.047µF, +25°C, unless otherwise noted.)
SUPPLY CURRENT TEMPERTURE (MAX3754)
MAX3754 toc01
MAX3754/MAX3755
OUTPUT DIAGRAM OUT± (1.0625Gbps CRPAT, ENABLED)
MAX3754 toc02
OUTPUT DIAGRAM OUT± (2.125Gbps CRPAT, ENABLED)
MAX3754 toc03
SUPPLY CURRENT (mA) ENABLED DISABLED
200mV/
INPUT 400mVP-P 0.4UI 0.2UI
200mV/
INPUT 400mVP-P 0.4UI 0.2UI
200ps/div
100ps/div
TEMPERATURE (°C)
OUTPUT JITTER BATHTUB PLOT (1.0625Gbps)
10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12
MAX3754 toc04
OUTPUT JITTER BATHTUB PLOT (2.125Gbps)
2.125Gbps CRPAT INPUT 0.4UI, 0.2UI)
MAX3754 toc05
ERROR RATE
1.0625Gbps CRPAT INPUT 0.4UI, 0.2UI)
ERROR RATE
DATA SAMPLING TIME RELATIVE FIRST ZERO CROSSING (UI)
DATA SAMPLING TIME RELATIVE FIRST ZERO CROSSING (UI)
JITTER TOLERANCE 1.0625Gbps
MAX3754 toc06
JITTER TOLERANCE 2.125Gbps
CJTPAT 0.4UI 0.2UI
MAX3754 toc07
CJTPAT 0.4UI 0.2UI
SINUSOIDAL JITTER (UIP-P)
FIBRE CHANNEL MASK
SINUSOIDAL JITTER (UIP-P)
FIBRE CHANNEL MASK
0.01 100k FREQUENCY (Hz)
0.01 100k FREQUENCY (Hz)
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater MAX3754/MAX3755
Description
NAME LIN1LIN1+ LOUT1LOUT1+ ININ+ CLKEN CFSEL1 SEL2 SEL3 SEL4 CDREN RATESEL LOCK OUT+ OUTLIN4LIN4+ LOUT4LOUT4+ LIN3LIN3+ LOUT3LOUT3+ LIN2LIN2+ LOUT2LOUT2+ Exposed Electrical Ground Inverted Data Input L-Port Noninverted Data Input L-Port Inverted Data Output L-Port Noninverted Data Output L-Port Inverted Data Input Noninverted Data Input Clock Enable. high level enables clock output L-Port Supply Voltage Filter Capacitor Positive Connection. 0.047µF. Filter Capacitor Negative Connection. 0.047µF. Select SEL1 selects data from high SEL1 selects data from LIN1. Select SEL2 selects data from previous port bypass circuit. high SEL2 selects data from LIN2. Select SEL3 selects data from previous port bypass circuit. high SEL3 selects data from LIN3. Select SEL4 selects data from previous port bypass circuit. high SEL4 selects data from LIN4. Enable Input (TTL). high input enables data recovery. input disables data recovery). Rate Select Pin. selects 1.0625Gbps operation. high selects 2.125Gbps operation. Frequency Lock Indicator. When data present, high level indicates frequencylocked. output LOCK chatter when large jitter applied input. Noninverted Data Output Inverted Data Output Inverted Data Input L-Port Noninverted Data Input L-Port Inverted Data Output L-Port Noninverted Data Output L-Port Inverted Data Input L-Port Noninverted Data Input L-Port Inverted Data Output L-Port Noninverted Data Output L-Port Inverted Data Input L-Port Noninverted Data Input L-Port Inverted Data Output L-Port Noninverted Data Output L-Port exposed must soldered circuit board ground proper thermal performance. DESCRIPTION
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater MAX3754/MAX3755
0.047µF
RATESEL
CFLOCK
INCDREN CLKEN
PHASE/FREQ DETECTOR
LOOP FILTER
OUT+ OUT-
LOUT1+ LOUT1-
LOUT2+ LOUT2-
LOUT3+ LOUT3-
LOUT4+ LOUT4-
LIN1+ LIN1-
LIN2+ LIN2-
LIN3+ LIN3-
LIN4+ LIN4-
SEL1
SEL2
SEL3
Figure MAX3754/MAX3755 Functional Diagram
Detailed Description
MAX3754/MAX3755 quad port bypass circuits (PBCs) consist input buffer, rate-selectable clock data recovery (CDR) circuit (for optional jitter attenuation), four serially connected port bypass circuits, output buffer (Figure circuit design optimized both 1.0625Gbps 2.125Gbps operation 3.3V.
Input Buffer
input buffer provides line termination level conversion. accepts differential input voltage 200mV 2200mV IN±. Internal resistors terminate inputs differentially eliminating need external resistors.
input buffer drives circuit, well input multiplexer. high CDREN enables connects data output port bypass circuits. recovered clock signal available test purposes LOUT1 when CLKEN asserted high. CDREN disables connects output input buffer directly port bypass circuits. RATESEL included switch between data rates. output divide-by-2 block that switched into when RATESEL 1.0625Gbps operation (see Figure Phase Frequency Detector frequency difference between clock received data derived sampling in-phase quadrature outputs edges input data signal. frequency detector drives until frequency difference reduced zero. Once frequency acquisition complete, phase detector produces voltage proportional phase difference between incoming data internal clock. drives this error voltage zero, aligning recovered clock center incoming eye.
Clock Data Recovery
purpose improve jitter transfer performance attenuating jitter that present input data. recover 1.0625Gpbs 2.125Gbps data signals that corrupted 0.7UI high-frequency jitter (BER 10-12 When jitter attenuation needed, disabled order save power.
SEL4
OPTIONAL TERMINATION LOUT
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater MAX3754/MAX3755
Loop Filter, VCO, Latch phase detector frequency detector outputs summed into loop filter. external capacitor (between CF-) required damping factor. fully integrated contains internal current reference filter circuitry minimize influence noise. creates clock output with frequency proportional control voltage applied loop filter. Data recovery accomplished using recovered clock signal latch incoming data output buffers, significantly reducing output jitter. LOCK Output active high LOCK output monitor derived from frequency detector indicates that frequency locked onto input data. Without input data, LOCK signal settle High Low. low-pass filter recommended reduce effects chatter that could caused high input jitter content. RATESEL Input RATESEL input used select between input data rates 2.125Gbps 1.0625Gbps. This function allows repeater sample data correct data rate selecting optional divide-by-2 network. RATESEL selects between tuned frequency half that frequency, allowing maximum jitter tolerance both data rates. loop bandwidth repeater scales with selected frequency; i.e., loop-bandwidth input rate 1.0625Gbps half that input rate 2.125Gbps.
Output Buffer
output signal last drives differential high-power output buffer. output buffer drives output port (OUT±). Internal resistors terminate each output with (100 differentially), eliminating need external termination resistors. output buffer produces differential peak-to-peak output voltage 1.8V when driving differential load.
Applications Information
MAX3754/MAX3755 quad-PBC designed hard-disk array applications using Fibre Channel Arbitrated Loop network protocol. applications where data storage reliability critical, desirable create disk array where data stored redundantly more than physical drive. Fibre Channel Arbitrated Loop protocol enables multiple physical drives connected loop topology. Each physical drive connected Fibre Channel loop through L-port that individually addressed controlled create array logical drives. Data transmitted over loop encoded serial stream. Using Fibre Channel Arbitrated Loop protocol, configuration disk array rearranged under software control achieve desired objectives (such data reliability fast access). port bypass circuit allows L-port enabled (connected loop) bypassed (disconnected from loop) while loop operating. This enables swapping physical drives (inserting removing physical drives while loop operating) that drives replaced with minimal disruption disk array system. Figure shows disk array.
Port Bypass Circuits
output input multiplexer drives cascaded series four PBCs. Each consists differential output buffer, differential input buffer, multiplexer. multiplexer select input (SEL_) controls whether port included loop. multiplexer select routes data signal from previous stage multiplexer output (port bypass mode). high multiplexer select routes data signal from input buffer multiplexer output (port enable mode). output last drives output buffer. MAX3754 differential termination inputs single-ended terminations outputs (see Input/Output Structures specifics) L-ports match Fibre Channel Arbitrated Loop specifications. MAX3755 terminated with respectively. Testing MAX3754 using standard test equipment requires impedance matching network
Filter Capacitor Requirements
MAX3754/MAX3755 phase lock loop's (PLL) filter capacitor required supplied port bypass design. This capacitor sets damping factor device. also determines fast acquire initial lock. This device specified tested with recommended filter capacitor value 0.047µF that limits transfer peaking.
Input/Output Structures
Figures show models MAX3754/ MAX3755 inputs outputs, modeling package parasitics, diodes.
Cascading Port Bypass Circuits
more MAX3754/MAX3755 quad-PBCs cascaded directly connecting OUT± pins
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater MAX3754/MAX3755
FC-AL DRIVES PORT CONTROL PORT CONTROL
Figure Disk Array Implemented with Port Bypass Circuits
FAIL-OVER LOOP MAX3750 OUT±
PRIMARY LOOP
REPEATER
REPEATER MAX375x REPEATER MAX375x REPEATER MAX375x
MAX377x
MAX377x
MAX377x
MAX377x
MAX375x
MAX377x
MAX377x
REPEATER
MAX377x
MAX377x
MAX375x
MAX377x
MAX377x
MAX377x
MAX377x
REPEATER
MAX377x
MAX377x
MAX375x
MAX377x
MAX377x
MAX377x
MAX377x
MAX3750
MAX377x
MAX377x OUT±
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater MAX3754/MAX3755
PACKAGE PARASITICS
STRUCTURES
1.2k
2.2nH 0.2pF 0.4pF
2.2nH 0.2pF 0.4pF
*(75)
*(75)
0.45V
*MAX3754 LIN_ INPUTS
Figure MAX3754/MAX3755 Input Structure
quad-PBC pins next quad-PBC. Typical Operating Circuit.
PACKAGE PARASITICS STRUCTURES 2.2nH OUT+ 0.4pF 2.2nH OUT0.4pF 0.2pF 0.2pF
Layout Considerations
best performance, carefully board using high-frequency techniques. Filter voltage supplies, keep ground connections short with multiple vias where possible. controlled impedance transmission lines interface with MAX3754/MAX3755 high-speed inputs outputs. Power-supply decoupling capacitors should placed very close pins. Isolate input signals from output signals much possible.
*(75)
*(75)
*MAX3754 LOUT_ OUTPUTS
Figure MAX3754/MAX3755 Output Structure
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater MAX3754/MAX3755
Typical Operating Circuit
DISK DRIVE L_PORT DISK DRIVE L_PORT DISK DRIVE L_PORT DISK DRIVE L_PORT
LOUT1±
LOUT2±
LOUT1±
LIN1±
LIN2±
LIN1±
LOUT2±
LIN2±
SEL1
SEL2
SEL1
UPSTREAM L_PORT INCF 0.047µF
SEL2
0.047µF INCF+
DOWNSTREAM L_PORT
CDREN LOCK OUT+
CDREN LOCK OUT+
MAX3754 MAX3755
OUTCLKEN
MAX3754 MAX3755
OUTCLKEN
LOUT3±
LOUT4±
LOUT3±
LOUT4±
RATESEL LIN4± SEL4
RATESEL LIN4± DISK DRIVE SEL4
LIN3±
LIN3±
SEL3
L_PORT DISK DRIVE
L_PORT DISK DRIVE
SEL3
L_PORT DISK DRIVE
L_PORT
NOTE: HIGH-SPEED INPUTS OUTPUTS (IN±, OUT±, LIN±, LOUT±) SHOULD CONNECTED USING CONTROLLEDIMPEDANCE TRANSMISSION LINES. AC-COUPLING ALSO REQUIRED. CAPACITORS 0.1µF UNLESS OTHERWISE INDICATED. FIGURE SHOWS 1.0625Gbps OPERATION. 2.125Gbps OPERATION, CONNECT RATESEL VCC.
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater MAX3754/MAX3755
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
48L,TQFP.EPS
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater
Package Information (continued)
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
MAX3754/MAX3755
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2002 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass with Repeater

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