NUAL ATION SHEE EVALU OLLOW High-Speed, Digitally Adjusted Step-D

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NUAL ATION SHEE EVALU OLLOW High-Speed, Digitally Adjusted Step-D

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19-4781; 11/98
NUAL ATION SHEE EVALU OLLOW
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs
Ultra-High Efficiency Current-Sense Resistor (Lossless ILIMIT) QUICK-PWM with 100ns Load-Step Response VOUT Accuracy over Line Load 4-Bit On-Board (MAX1710) 5-Bit On-Board (MAX1711) 0.925V Output Adjust Range (MAX1711) Battery Input Range 200/300/400/550kHz Switching Frequency Remote VOUT Sensing Over/Undervoltage Protection 1.7ms Digital Soft-Start Drives Large Synchronous-Rectifier FETs Reference Output Power-Good Indicator Small 24-Pin QSOP Package
MAX1710/MAX1711
MAX1710/MAX1711 step-down controllers intended core DC-DC converters notebook computers. They feature triple-threat combination ultra-fast transient response, high accuracy, high efficiency needed leading-edge core power supplies. Maxim's proprietary QUICK-PWMquick-response, constant-on-time control scheme handles wide input/output voltage ratios with ease provides 100ns "instant-on" response load transients while maintaining relatively constant switching frequency. High precision ensured 2-wire remote-sensing scheme that compensates voltage drops both ground supply rail. on-board, digital-toanalog converter (DAC) sets output voltage compliance with Mobile Pentium specifications. MAX1710 achieves high efficiency reduced cost eliminating current-sense resistor found traditional current-mode PWMs. Efficiency further enhanced ability drive very large synchronousrectifier MOSFETs. Single-stage buck conversion allows these devices directly step down high-voltage batteries highest possible efficiency. Alternatively, 2-stage conversion (stepping down system supply instead battery) higher switching frequency allows minimum possible physical size. MAX1710 MAX1711 identical except that MAX1711 5-bit rather than 4-bit DAC. Also, MAX1711 fixed overvoltage protection threshold VOUT 2.25V undervoltage protection VOUT 0.8V, whereas MAX1710 variable thresholds that track VOUT. MAX1711 intended applications where code change dynamically.
Ordering Information
PART MAX1710EEG MAX1711EEG TEMP. RANGE -40°C +85°C -40°C +85°C PIN-PACKAGE QSOP QSOP
Minimal Operating Circuit
INPUT SHDN ILIM GNDS OVP* OUTPUT 0.925V (MAX1711) PGND SKIP BATTERY 4.5V
Applications
Notebook Computers Docking Stations Core DC-DC Converters Single-Stage (BATT VCORE) Converters Two-Stage (+5V VCORE) Converters
QUICK-PWM trademark Maxim Integrated Products. Mobile Pentium registered trademark Intel Corp. Configuration appears data sheet.
INPUTS *MAX1710 ONLY **MAX1711 ONLY
MAX1710 MAX1711
D4**
Maxim Integrated Products
free samples latest literature: http://www.maxim-ic.com, phone 1-800-998-8800 small orders, phone 1-800-835-8769.
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
ABSOLUTE MAXIMUM RATINGS
BST.-6V +0.3V .-0.3V +30V Short Circuit .Continuous VCC, .-0.3V PGND GND.±0.3V Continuous Power Dissipation +70°C) SHDN, PGOOD .-0.3V 24-Pin QSOP (derate 9.5mW/°C above +70°C).762mW OVP, ILIM, FBS, REF, D0-D4, Operating Temperature Range .-40°C +85°C GNDS, .-0.3V (VCC 0.3V) Junction Temperature .+150°C SKIP (Note 1).-0.3V (VCC 0.3V) Storage Temperature Range .-65°C +165°C PGND.-0.3V (VDD 0.3V) Lead Temperature (soldering, 10sec) .+300°C .-0.3V +36V .-0.3V (BST 0.3V) Note SKIP forced below -0.3V, temporarily exceeding absolute maximum rating, purpose debugging prototype breadboards using no-fault test mode. Limit current drawn -5mA maximum.
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit Figure VBATT 15V, SKIP GND, +85°C, unless otherwise noted.) PARAMETER Input Voltage Range Battery voltage, VCC, codes from 1.3V VBATT 4.5V 28V, includes codes from 0.925V load regulation error 1.275V ILOAD FB-FBS GNDS-GND 25mV 4.5V 5.5V, VBATT 4.5V (MAX1710 only) -0.2 Rising edge SHDN full ILIM (550kHz) VBATT 24V, (400kHz) open (300kHz) (Note (200kHz) (Note Measured VCC, forced above regulation point Measured VDD, forced above regulation point SHDN SHDN SHDN measured 28V, 4.5V 5.5V, external load IREF 50µA regulation Falling edge, hysteresis 40mV 1.98 2.02 0.01 CONDITIONS -1.2 UNIT
Output Voltage Accuracy Load Regulation Error Remote Sense Voltage Error Line Regulation Error Input Bias Current Input Resistance (MAX1711) GNDS Input Bias Current Soft-Start Ramp Time
On-Time
Minimum Off-Time Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) Shutdown Battery Supply Current Reference Voltage Reference Load Regulation Sink Current Fault Lockout Voltage
Quiescent Battery Supply Current Measured
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs
ELECTRICAL CHARACTERISTICS (continued)
(Circuit Figure VBATT 15V, SKIP GND, +85°C, unless otherwise noted.) PARAMETER Overvoltage Trip Threshold Overvoltage Fault Propagation Delay Output Undervoltage Protection Threshold Output Undervoltage Protection Time Current-Limit Threshold (Positive Direction, Fixed) Current-Limit Threshold (Positive Direction, Adjustable) Current-Limit Threshold (Negative Direction) Current-Limit Threshold (Zero Crossing) PGOOD Propagation Delay PGOOD Output Voltage PGOOD Leakage Current Thermal Shutdown Threshold Undervoltage Lockout Threshold Gate-Driver On-Resistance Gate-Driver On-Resistance (Pull-Up) Gate-Driver On-Resistance (Pull-Down) Gate-Driver Source/Sink Current Gate-Driver Sink Current Gate-Driver Source Current Dead Time SKIP Input Current Logic Threshold PGOOD Trip Threshold Logic Input High Voltage Logic Input Voltage Logic Input Current Logic Input Pull-Up Current (MAX1711) forced above trip threshold With respect unloaded output voltage (MAX1710) (MAX1711) From SHDN signal going high PGND, ILIM tied PGND RLIM 100k RLIM 400k 0.76 -150 -120 -1.5 -0.1 CONDITIONS With respect unloaded output voltage (MAX1710) 10.5 2.21 12.5 2.25 0.84 14.5 2.29 UNIT
MAX1710/MAX1711
PGND, +25°C PGND forced below PGOOD trip threshold, falling edge ISINK High state, forced 5.5V Hysteresis 10°C Rising edge, hysteresis 20mV, disabled below this level BST-LX forced high state state forced 2.5V, BST-LX forced forced 2.5V forced 2.5V rising rising enable no-fault mode, +25°C Measured with respect unloaded output voltage, falling edge, hysteresis D0-D4, SHDN, SKIP, D0-D4, SHDN, SKIP, SHDN, SKIP, D0-D4, each forced
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
ELECTRICAL CHARACTERISTICS (continued)
(Circuit Figure VBATT 15V, SKIP GND, +85°C, unless otherwise noted.) PARAMETER Level Float Voltage Reference Level Level Logic Input Current CONDITIONS logic input high level logic input upper-mid-range level logic input lower-mid-range level logic input level only, forced 3.15 1.65 3.85 2.35 UNIT
ELECTRICAL CHARACTERISTICS
(Circuit Figure VBATT=15V, SKIP GND, -40°C +85°C, unless otherwise noted.) (Note PARAMETER Input Voltage Range Battery voltage, VCC, VBATT 4.5V 28V, codes, includes load regulation error codes from 1.32V codes from 0.925V 1.275V CONDITIONS -1.5 -1.7 1.98 2.20 0.75 2.02 2.30 0.85 UNIT
Output Voltage Accuracy
On-Time
(550kHz) VBATT 24V, (400kHz) open (300kHz) (Note (200kHz) (Note Measured VCC, forced above regulation point 4.5V 5.5V, external load With respect unloaded output voltage (MAX1710) (MAX1711) With respect unloaded output voltage (MAX1710) (MAX1711) PGND, ILIM tied PGND RLIM 100k RLIM 400k
Minimum Off-Time Quiescent Supply Current (VCC) Reference Voltage Overvoltage Trip Threshold Output Undervoltage Protection Threshold Current-Limit Threshold (Positive Direction, Fixed) Current-Limit Threshold (Positive Direction, Adjustable) Undervoltage Lockout Threshold Logic Input High Voltage Logic Input Voltage Logic Input Current Logic Input Pull-Up Current
Rising edge, hysteresis 20mV, disabled below this level D0-D4, SHDN, SKIP, D0-D4, SHDN, SKIP, SHDN, SKIP, D0-D4, each forced
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
ELECTRICAL CHARACTERISTICS (continued)
(Circuit Figure VBATT=15V, SKIP GND, -40°C +85°C, unless otherwise noted.) (Note PARAMETER PGOOD Trip Threshold PGOOD Output Voltage PGOOD Leakage Current CONDITIONS Measured with respect unloaded output voltage, falling edge, hysteresis ISINK High state, forced 5.5V -8.5 -2.5 UNIT
Note On-Time Off-Time specifications measured from point point with forced forced 250pF capacitor connected from Actual in-circuit times differ MOSFET switching speeds. Note Specifications from -40°C guaranteed production tested.
_Typical Operating Characteristics
supply circuit Figure +25°C, unless otherwise noted.)
EFFICIENCY LOAD CURRENT 2.0V, 300kHz)
MAX1710-01
EFFICIENCY LOAD CURRENT 1.6V, 300kHz)
MAX1710-02
EFFICIENCY LOAD CURRENT 1.3V, 300kHz)
4.5V EFFICIENCY
MAX1710-03
4.5V EFFICIENCY 0.01
4.5V EFFICIENCY
0.01
0.01
LOAD CURRENT
LOAD CURRENT
LOAD CURRENT
EFFICIENCY LOAD CURRENT 1.6V, 550kHz)
MAX1710-04
FREQUENCY LOAD CURRENT 1.6V)
MAX1710-05
4.5V EFFICIENCY 0.01
FREQUENCY (kHz)
FREQUENCY (kHz) 1.6V 2.0V
15V, MODE
4.5V, SKIP MODE
15V, SKIP MODE
OPEN 0.01
OPEN
LOAD CURRENT
LOAD CURRENT
INPUT VOLTAGE
MAX1710-06
FREQUENCY INPUT VOLTAGE
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
_Typical Operating Characteristics (continued)
supply circuit Figure +25°C, unless otherwise noted.)
FREQUENCY TEMPERATURE (VIN 15V, 2.0V)
MAX1710-07
ON-TIME TEMPERATURE
TIME (ns)
MAX1710-08
CURRENT-LIMIT TRIP POINT TEMPERATURE
MAX1710-09
FREQUENCY (kHz) OPEN
CURRENT TRIP POINT ILIM
ILIM 400k
ILIM 100k
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
CONTINUOUS DISCONTINUOUS INDUCTOR CURRENT POINT INPUT VOLTAGE
MAX1710-10
INDUCTOR CURRENT PEAKS VALLEYS INPUT VOLTAGE CURRENT-LIMIT POINT)
MAX1710-11
NO-LOAD SUPPLY CURRENTS INPUT VOLTAGE (SKIP MODE, 300kHz)
MAX1710-12
LOAD CURRENT 1.3V 2.0V 1.6V
14.0 13.5 IPEAK INDUCTOR CURRENT 13.0 12.5 12.0 11.5 11.0 10.5 10.0 IVALLEY
SUPPLY CURRENT (mA) IBATT
INPUT VOLTAGE
INPUT VOLTAGE
INPUT VOLTAGE
NO-LOAD SUPPLY CURRENTS INPUT VOLTAGE (SKIP MODE, 550kHz)
MAX1710-13
NO-LOAD SUPPLY CURRENTS INPUT VOLTAGE (PWM MODE, 300kHz)
MAX1710-14
NO-LOAD SUPPLY CURRENTS INPUT VOLTAGE (PWM MODE, 550kHz)
SUPPLY CURRENT (mA) IBAT
MAX1710-15
SUPPLY CURRENT (mA) IBATT
SUPPLY CURRENT (mA)
IBAT
INPUT VOLTAGE
INPUT VOLTAGE
INPUT VOLTAGE
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs
_Typical Operating Characteristics (continued)
supply circuit Figure +25°C, unless otherwise noted.)
MAX1710/MAX1711
LOAD-TRANSIENT RESPONSE (WITH INTEGRATOR)
MAX1710-16
LOAD-TRANSIENT RESPONSE (WITH INTEGRATOR)
MAX1710-17
LOAD-TRANSIENT RESPONSE (WITHOUT INTEGRATOR)
MAX1710-18
10µs/div 15V, 1.6V, VOUT, COUPLED, 50mV/div INDUCTOR CURRENT, 5A/div
10µs/div 15V, 1.6V, 30mA, VOUT, COUPLED, 50mV/div INDUCTOR CURRENT, 5A/div
10µs/div 15V, 1.6V, 30mA VOUT, COUPLED, 50mV/div INDUCTOR CURRENT, 5A/div
LOAD-TRANSIENT RESPONSE (WITH INTEGRATOR)
MAX1710-19
LOAD-TRANSIENT RESPONSE (WITH INTEGRATOR)
MAX1710-20
START-UP WAVEFORM
MAX1710-21
20µs/div 4.5V, 30mA VOUT, COUPLED, 50mV/div INDUCTOR CURRENT, 5A/div 10V/div
20µs/div 4.5V, 1.3V, 30mA VOUT, COUPLED, 50mV/div INDUCTOR CURRENT, 5A/div 10V/div
500µs/div SHDN VOUT, 0.5V/div INDUCTOR CURRENT, 5A/div
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
_Typical Operating Characteristics (continued)
supply circuit Figure +25°C, unless otherwise noted.)
OUTPUT OVERLOAD WAVEFORM
MAX1710-22
LOAD-TRANSIENT RESPONSE
CERAMIC COUT
MAX1710-23
SHUTDOWN WAVEFORM
MAX1710-24
50µs/div VOUT 1.6V VIN, COUPLED, 2V/div VOUT, 0.5V/div INDUCTOR CURRENT, 5A/div 5µs/div 0.7µH, VOUT 1.6V, 15V, COUT 47µF (x4), 550kHz VOUT, COUPLED, 100mV/div INDUCTOR CURRENT, 5A/div 5V/div 5µs/div 15V, 1.6V, VOUT, 0.5V/div INDUCTOR CURRENT, 5A/div SHDN, 2V/div 5V/div
Description
NAME SHDN FUNCTION Battery Voltage Sense Connection. used only one-shot timing. on-time inversely proportional input voltage over range 28V. Shutdown Control Input, active low. SHDN cannot withstand battery voltage. shutdown mode, forced order enforce overvoltage protection, even when powered down (unless high). Fast Feedback Input, normally connected VOUT. connected bulk output filter capacitors locally power supply. external resistor-divider optionally output voltage. Feedback Remote-Sense Input, normally connected VOUT directly load. internally connects integrator that fine-tunes output voltage. disable three integrator amplifiers. disable integrators) when externally adjusting output voltage with resistor-divider. Integrator Capacitor Connection. Connect 100pF 1000pF (470pF typical) capacitor integration time constant. Current-Limit Threshold Adjustment. Connects external resistor GND. LX-PGND current-limit threshold defaults +100mV ILIM tied VCC. current-limit threshold 1/10 voltage forced ILIM. adjustable mode threshold RLIM 5µA/10. Analog Supply Voltage Input Core, 4.5V 5.5V. Bypass with 0.1µF minimum capacitor. On-Time Selection Control Input. This four-level input that sets factor determine on-time. 550kHz, 400kHz, open 300kHz, 200kHz. 2.0V Reference Output. Bypass with 0.22µF minimum capacitor. source 50µA external loads. Loading degrades accuracy according load-regulation error (see Electrical Characteristics).
ILIM
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
Description (continued)
(MAX1710) (MAX1711) NAME GNDS PGOOD PGND Analog Ground Ground Remote-Sense Input, normally connected ground directly load. GNDS internally connects integrator that fine-tunes ground offset voltage. Open-Drain Power-Good Output. Low-Side Gate-Driver Output, swings VDD. Power Ground. Also used inverting input current-limit comparator. Supply Voltage Input gate driver, 4.5V 5.5V Overvoltage-Protection Disable Control Input (Table normal operation overvoltage protection active, overvoltage protection disabled. Code Input, MSB, internal pull-up (Tables Code Input. internal pull-up VCC. Code Input. internal pull-up. Code Input. internal pull-up. Code Input LSB. internal pull-up. Low-Noise-Mode Selection Control Input. Low-noise forced-PWM mode causes inductor current recirculation light loads suppresses pulse-skipping operation. Normal operation prevents current recirculation. SKIP also used disable both overvoltage undervoltage protection circuits clear fault latch (Figure normal operation, low-noise mode. leave SKIP floating. Boost Flying-Capacitor Connection. optional resistor series with allows pull-up current adjusted (Figure This technique slowing rise time used prevent accidental turn-on low-side MOSFET excessive gate-drain capacitance. Inductor Connection. serves lower supply rail high-side gate driver. Also used noninverting input current-limit comparator well skip-mode zero-crossing comparator. High-Side Gate-Driver Output. Swings BST. FUNCTION
SKIP
Standard Application Circuit
standard application circuit (Figure generates low-voltage, high-power rail supplying core notebook computer. This DC-DC converter steps down battery adapter voltage sub-2V levels with high efficiency accuracy, represents good compromise between size, efficiency, cost. MAX1710 manual list components suppliers.
Detailed Description
MAX1710/MAX1711 buck controllers targeted low-voltage, high-current power supplies notebook computers. cores typically exhibit greater load steps when clock throttled. proprietary QUICK-PWM pulse-width modulator MAX1710/MAX1711 specifically designed handling these fast load steps while maintaining relatively constant operating frequency inductor operating point over wide range input voltages. QUICKPWM architecture circumvents poor load-transient timing problems fixed-frequency current-mode PWMs
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
VBATT 4.5V BIAS SUPPLY 10µF/30V ON/OFF CONTROL LOW-NOISE CONTROL INPUTS 470pF SHDN SKIP D4** GNDS 100k OVP* PGOOD POWER-GOOD INDICATOR IRF7807 IRF7805 MBRS130T3 (OPTIONAL) Sanyo OS-CON (30SC10M) 0.1µF PANASONIC ETQP6F2R0HFA 470µF KEMET T510
CMPSH-3
MAX1710 MAX1711
VOUT 1.25V (MAX1710) 0.925V (MAX1711) (OPTIONAL REVERSE-POLARITY CLAMP)
PGND
ILIM
MAX1710 ONLY MAX1711 ONLY
(OPTIONAL)
Figure Standard Application Circuit
while also avoiding problems caused widely varying switching frequencies conventional constant-ontime constant-off-time schemes.
Bias Supply (VCC VDD)
MAX1710/MAX1711 requires external bias supply addition battery. Typically, this bias supply notebook's efficient system supply. Keeping bias supply external improves efficiency eliminates cost associated with linear regulator that would otherwise needed supply circuit gate drivers. stand-alone
capability needed, supply generated with external linear regulator such MAX1615. battery bias inputs tied together input source fixed 4.5V 5.5V supply. bias supply powered prior battery supply, enable signal (SHDN) must delayed until battery voltage present order ensure start-up. bias supply must provide gate-drive power, maximum current drawn IBIAS (QG1 QG2) 15mA 30mA (typ)
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
VBATT RLIM
ILIM
TOFF ON-TIME COMPUTE FROM 1-SHOT TRIG
MAX1710
TRIG 1-SHOT SKIP SHDN GNDS +12% -30%
CURRENT LIMIT OUTPUT
ERROR ZERO CROSSING PGND
CHIP SUPPLY
PGOOD OVP/UVLO LATCH TIMER
R-2R CONVERTER
Figure MAX1710 Functional Diagram
where 600µA typical, switching frequency, MOSFET data sheet total gate-charge specification limits
Free-Running, Constant-On-Time Controller with Input Feed-Forward
QUICK-PWM control architecture almost fixedfrequency, constant-on-time current-mode type with voltage feed-forward (Figure This architecture relies
filter capacitor's current-sense resistor, output ripple voltage provides ramp signal. control algorithm simple: highside switch on-time determined solely one-shot whose period inversely proportional input voltage directly proportional output voltage. Another oneshot sets minimum off-time (400ns typical). on-time one-shot triggered error comparator low,
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
Table MAX1710 Output Voltage Codes
OUTPUT VOLTAGE 2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.25
Table MAX1711 Output Voltage Codes
OUTPUT VOLTAGE 2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 Shutdown 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 Shutdown
low-side switch current below current-limit threshold, minimum off-time one-shot timed out.
On-Time One-Shot (TON)
heart core one-shot that sets high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies on-time response battery output voltage. high-side switch on-time inversely proportional battery voltage measured input, directly proportional output voltage code. This algorithm results nearly constant switching frequency despite lack fixed-frequency clock generator. benefits constant switching frequency twofold: first, frequency selected avoid noise-sensitive regions such 455kHz band; second, inductor ripple-current operating point remains relatively constant, resulting easy design methodology predictable output voltage ripple. On-Time (VOUT 0.075V) where pin-strap connection 0.075V approximation accommodate expected drop across low-side MOSFET switch. One-shot timing error increases shorter on-time
Table
settings fixed propagation delays approximately ±12.5% 550kHz 400kHz, ±10% slower settings. This translates reduced switching-frequency accuracy higher frequencies. (see Table Switching frequency increases function load current increasing drop across low-
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
side MOSFET, which causes faster inductor-current discharge ramp. on-times guaranteed Electrical Characteristics influenced switching delays external high-side power MOSFET. exact switching frequency will depend gate charge, internal gate resistance, source inductance, output drive characteristics. external factors that influence switching-frequency accuracy resistive drops conduction loops (including inductor board resistance) dead-time effect. These effects largest contributors change frequency with changing load current. dead-time effect notable discontinuity switching frequency load current varied (see Typical Operating Characteristics). occurs whenever inductor current reverses, most commonly light loads with SKIP high. With reversed inductor current, inductor's causes high earlier than normal, extending on-time period equal low-to-high dead time. loads above critical conduction point, actual switching frequency VOUT VDROP1 (VIN VDROP2 where VDROP1 parasitic voltage drops inductor discharge path, including synchronous rectifier, inductor, board resistances; VDROP2 resistances charging path, on-time calculated MAX1710/MAX1711. average value output ripple waveform. integrator amplifiers disabled, VOUT regulated valleys output ripple waveform. This creates slight load-regulation characteristic which output voltage rises approximately peak amplitude ripple waveform limit) when under light loads. Integrators have both beneficial detrimental characteristics. While they correct drops resistance tighten output voltage tolerance limits averaging peak-to-peak output ripple, they interfere with achieving fastest possible load-transient response. fastest transient response achieved when three integrators disabled. This works very well when MAX1710/ MAX1711 circuit placed very close CPU. There often connector, least many milliohms board trace resistance, between DC-DC converter CPU. these cases, best strategy place most bulk bypass capacitors close CPU, with just capacitor other side connector near MAX1710/MAX1711 control ripple card unplugged. this situation, remote-sense lines integrators provide real benefit. When both GNDS tied that three integrators disabled, left unconnected, which eliminates component.
Automatic Pulse-Skipping Switchover
light loads, inherent automatic switchover takes place. This switchover effected comparator that truncates low-side switch on-time inductor current's zero crossing. This mechanism causes threshold between pulse-skipping non-skipping operation coincide with boundary between continuous discontinuous inductor-current operation (also known "critical conduction" point; Continuous Discontinuous Inductor Current Point Input Voltage graphs Typical Operating Characteristics). battery range this threshold relatively constant, with only minor dependence battery voltage. LOAD(SKIP)
Integrator Amplifiers (CC)
There three integrator amplifiers that provide fine adjustment output regulation point. amplifier monitors difference between GNDS GND, while another monitors difference between third amplifier integrates difference between output. These three transconductance amplifiers' outputs directly summed inside chip, integration time constant easily with capacitor. each amplifier 160µmho (typical). integrator block ability move correct output voltage about -2%, +4%. each amplifier, differential input voltage range about ±50mV total, including offset ripple. voltage gain each integrator about 80V/V. amplifier corrects voltage drops board traces connectors output path between DC-DC converter load. GNDS amplifier performs similar correction task output ground bus. third amplifier provides averaging function that forces VOUT regulated
where On-Time Scale factor (see Table load-current level which PFM/PWM crossover occurs, ILOAD(SKIP), equal peak-to-peak ripple current, which function inductor value (Figure example, standard application circuit with 300ns 24V, VOUT 2µH, switchover pulse-skipping operation occurs ILOAD 1.65A
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
VBATT -VOUT INDUCTOR CURRENT
-IPEAK
-IPEAK
ILOAD INDUCTOR CURRENT
ILOAD IPEAK/2
ILIMIT LX-PGND ILIMIT THRESHOLD 100mV (NOMINAL, DEFAULT) VOLTAGE DROP ACROSS
ON-TIME
TIME
TIME
Figure Pulse-Skipping/Discontinuous Crossover Point
Figure ``Valley'' Current-Limit Threshold Point
about full load. crossover point occurs even lower value swinging (soft-saturation) inductor used. switching waveforms appear noisy asynchronous when light loading causes pulse-skipping operation, this normal operating condition that results high light-load efficiency. Trade-offs noise light-load efficiency made varying inductor value. Generally, inductor values produce broader efficiency load curve, while higher values result higher full-load efficiency (assuming that coil resistance remains fixed) less output voltage ripple. Penalties using higher inductor values include larger physical size degraded load-transient response (especially input voltage levels).
current-sense signal above current-limit threshold, allowed initiate cycle (Figure actual peak current greater than current-limit threshold amount equal inductor ripple current. Therefore exact current-limit characteristic maximum load capability function MOSFET on-resistance, inductor value, battery voltage. reward this uncertainty robust, lossless overcurrent sensing. When combined with protection circuit, this current-limit method effective almost every circumstance. There also negative current limit that prevents excessive reverse inductor currents when VOUT sinking current. negative current-limit threshold approximately 120% positive current limit, therefore tracks positive current limit when ILIM adjusted. current-limit threshold adjusted with external resistor (RLIM) ILIM. precision pull-up current source ILIM sets voltage drop this resistor, adjusting current-limit threshold from 50mV 200mV. adjustable mode, current-limit threshold voltage precisely 1/10th voltage seen ILIM. Therefore, choose RLIM equal 2k/mV currentlimit threshold. threshold defaults 100mV when ILIM tied VCC. logic threshold switchover 100mV default value approximately adjustable current limit accommodate MOSFETs with atypical on-resistance characteristics (see Design Procedure). capacitor parallel with RLIM provide variable soft-start function. Carefully observe board layout guidelines ensure that noise errors don't corrupt current-sense signals seen PGND. must mounted close low-side MOSFET with short,
Forced-PWM Mode (SKIP High)
low-noise, forced-PWM mode (SKIP driven high) disables zero-crossing comparator, which controls low-side switch on-time. This causes low-side gatedrive waveform become complement highside gate-drive waveform. This turn causes inductor current reverse light loads, loop strives maintain duty ratio VOUT/VIN. benefit forced-PWM mode keep switching frequency fairly constant, comes cost: noload battery current high 40mA more. Forced-PWM mode most useful reducing audio-frequency noise, improving load-transient response, providing sink-current capability dynamic output voltage adjustment, improving cross-regulation multiple-output applications that flyback transformer coupled inductor.
Current-Limit Circuit (ILIM)
current-limit circuit employs unique "valley" current-sensing algorithm that uses on-state resistance low-side MOSFET current-sensing element.
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
direct traces making Kelvin sense connection source drain terminals.
MOSFET Gate Drivers (DH,
drivers optimized driving moderate-size, high-side larger, low-side power MOSFETs. This consistent with duty factor seen notebook environment, where large VBATT VOUT differential exists. adaptive dead-time circuit monitors output prevents high-side from turning until fully off. There must low-resistance, low-inductance path from driver MOSFET gate order adaptive dead-time circuit work properly. Otherwise, sense circuitry MAX1710/MAX1711 will interpret MOSFET gate "off" while there actually still charge left gate. very short, wide traces measuring squares mils wide MOSFET inch from MAX1710/MAX1711). dead time other edge turning off) determined fixed 35ns (typical) internal delay. internal pull-down transistor that drives robust, with typical on-resistance. This helps prevent from being pulled during fast rise-time inductor node, capacitive coupling from drain gate massive low-side synchronousrectifier MOSFET. However, might still encounter some combinations high- low-side FETs that will cause excessive gate-drain coupling, which lead efficiency-killing, EMI-producing shoot-through currents. This often remedied adding resistor series with BST, which increases turn-on time highside without degrading turn-off time.
forces gate driver high order enforce output overvoltage protection) until rises above 4.2V, whereupon internal digital soft-start timer begins ramp maximum allowed current limit. ramp occurs five steps: 20%, 40%, 60%, 80%, 100%, with 100% current available after 1.7ms ±50%. continuously adjustable, analog soft-start function realized adding capacitor parallel with RLIM ILIM. This soft-start method requires minimum interval between power-down power-up allow RLIM discharge capacitor.
Power-Good Output (PGOOD)
output (FB) continuously monitored undervoltage PGOOD comparator, except shutdown standby mode. undervoltage trip threshold measured with respect nominal unloaded output voltage, DAC. code increases steps greater than 1LSB, likely that PGOOD will momentarily low. shutdown standby modes, PGOOD actively held low. PGOOD output true open-drain type with parasitic diodes. Note that PGOOD undervoltage detector completely independent output fault detector.
Output Overvoltage Protection (OVP)
overvoltage protection circuit designed protect against shorted high-side MOSFET drawing high current blowing battery fuse. node continuously monitored overvoltage. overvoltage trip threshold tracks code setting. output more than 12.5% above nominal regulation point MAX1710 (2.25V absolute MAX1711), overvoltage protection (OVP) triggered circuit shuts down. low-side gate-driver output then latched high until SHDN toggled power cycled below This action turns synchronousrectifier MOSFET with 100% duty and, turn, rapidly discharges output filter capacitor forces output ground. condition that caused overvoltage (such shorted high-side MOSFET) persists, battery fuse will blow. Note that going high have effect causing output polarity reversal, energy stored output instant activates. load can't tolerate being forced negative voltage, desirable place power Schottky diode across output reverse-polarity clamp (Figure MAX1710/MAX1711 itself affected going below ground, with negative voltage coupling into SHDN. necessary resistors series with (Figure
Converter (D0-D4)
digital-to-analog converter (DAC) programs output voltage. receives digital code from pins module that either hard-wired left open-circuit. Note that codes don't match desktop codes. MAX1710/MAX1711 contain weak internal pull-ups each input order eliminate external resistors. When changing MAX1710 codes while powered over/undervoltage protection features activated code changed more than 1LSB time. applications needing capability changing codes "on-the-fly," MAX1711.
POR, UVLO, Soft-Start
Power-on reset (POR) occurs when rises above approximately resetting fault latch soft-start counter, preparing operation. undervoltage lockout (UVLO) circuitry inhibits switching
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
Table Operating Mode Truth Table
SHDN SKIP High MODE Shutdown1 Shutdown2 Shutdown3 (MAX1711 only) Fault COMMENTS Low-power shutdown state. forced VDD, enforcing OVP. typ. Low-power shutdown state. forced GND, disabling OVP. typ. Exiting shutdown triggers soft-start cycle. code X1111 (see Table forced PGND, forced MAX1711 eventually goes into fault mode load current discharges output. Test mode with OVP, UVP, thermal faults disabled latches cleared. Otherwise normal operation, with automatic PWM/PFM switchover pulse skipping light loads (Figure faults disabled latch cleared. Otherwise normal operation, with SKIP controlling PWM/PFM switchover. Low-noise operation with automatic switchover. Fixed-frequency action forced regardless load. Inductor current reverses light load levels. draw 750µA typ. draw 15mA typ. Normal operation with automatic PWM/PFM switchover pulse skipping light loads. 600µA typ. draw load dependent. Fault latch been OVP, output UVLO, thermal shutdown. Device will remain FAULT mode until power cycled, SKIP forced below ground, SHDN toggled.
Below
Switching
Switching
(PWM), Noise (PFM/PWM) Fault
Switching
Switching
High
Table Frequency Selection Guidelines
FREQUENCY (kHz) TYPICAL COMMENT APPLICATION 4-cell notebook absolute best core efficiency. 4-cell notebook Considered mainstream core current standards. Useful 4-cell systems 3-cell notebook lighter loads than core where size key. Good operating point +5V-input notebook compound buck designs core desktop circuits.
variable current limit. MAX1710 output (FB) under nominal value 20ms after coming shutdown, latched won't restart until power cycled SHDN toggled. MAX1711, nominal trip threshold fixed 0.8V.
No-Fault Test Mode
over/undervoltage protection features complicate process debugging prototype breadboards, since there most) milliseconds which determine what went wrong. Therefore, test mode provided totally disable OVP, UVP, thermal shutdown features, clear fault latch been previously set. operates SKIP were grounded (PFM/PWM mode). no-fault test mode entered sinking 1.5mA from SKIP external negative voltage source series with resistor (Figure SKIP clamped with silicon diode, choose resistor value equal (VFORCE 0.65V) 1.5mA.
also kept high continuously when UVLO active well Shutdown1 mode (Table Overvoltage protection defeated input (MAX1710 only) SKIP test mode (see Description).
Design Procedure
Firmly establish input voltage range maximum load current before choosing switching frequency inductor operating point (ripple current ratio). prima-
Output Undervoltage Protection (UVP)
output undervoltage protection function similar foldback current limiting, employs timer rather than
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
VBATT
MAX1710 MAX1711
SKIP
APPROXIMATELY -0.65V
1.5mA VFORCE
MAX1710 MAX1711
Figure Reducing Switching-Node Rise Time
Figure Disabling Over/Undervoltage Protection (Test Mode)
design trade-off lies choosing good switching frequency inductor operating point, following four factors dictate rest design: Input voltage range. maximum value (VBATT(MAX)) must accommodate worst-case high adapter voltage. minimum value (VBATT(MIN)) must account lowest battery voltage after drops connectors, fuses, battery selector switches. there choice all, lower input voltages result better efficiency. Maximum load current. There values consider. peak load current (ILOAD(MAX)) determines instantaneous component stresses filtering requirements, thus drives output capacitor selection, inductor saturation rating, design current-limit circuit. continuous load current (ILOAD) determines thermal stresses thus drives selection input capacitors, MOSFETs, other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD ILOAD(MAX) 80%. Switching frequency. This choice determines basic trade-off between size efficiency. optimal frequency largely function maximum input voltage, MOSFET switching losses that proportional frequency VBATT2. optimum frequency also moving target, rapid improvements MOSFET technology that making higher frequencies more practical (Table Inductor operating point. This choice provides trade-offs between size efficiency. inductor values cause large ripple currents, resulting smallest size, poor efficiency high output noise. minimum practical inductor value that causes circuit operate edge critical conduction (where inductor current just touch-
zero with every cycle maximum load). Inductor values lower than this grant further size-reduction benefit. MAX1710/MAX1711's pulse-skipping algorithm initiates skip mode critical-conduction point. inductor operating point also determines loadcurrent value which PFM/PWM switchover occurs. optimum point usually found between ripple current. inductor ripple current also impacts transientresponse performance, especially VBATT VOUT differentials. inductor values allow inductor current slew faster, replenishing charge removed from output filter capacitors sudden load step. amount output also function maximum duty factor, which calculated from on-time minimum off-time: LOAD(MAX) VSAG DUTY (VBATT(MIN) VOUT
Inductor Selection
switching frequency (on-time) operating point ripple LIR) determine inductor value follows: VOUT LOAD(MAX)
Example: ILOAD(MAX) VOUT 300kHz, ripple current 0.5. 1.9µH (2µH) 300kHz
Find low-loss inductor having lowest possible resistance that fits allotted dimensions. Ferrite cores often best choice, although powdered iron
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
cheap work well 200kHz. core must large enough saturate peak inductor current (IPEAK). IPEAK ILOAD(MAX) (LIR ILOAD(MAX) RESR LOAD(MAX)
Setting Current Limit
minimum current-limit threshold must great enough support maximum load current when current limit minimum tolerance value. valley inductor current occurs ILOAD(MAX) minus half ripple current, therefore: ILIMIT(LOW) ILOAD(MAX) (LIR ILOAD(MAX) where ILIMIT(LOW) minimum current-limit threshold voltage divided RDS(ON) MAX1710, minimum current-limit threshold (100mV default setting) 90mV. worst-case maximum value RDS(ON) from MOSFET data sheet, some margin rise RDS(ON) with temperature. good general rule allow 0.5% additional resistance each temperature rise. Examining notebook circuit example with maximum RDS(ON) high temperature reveals following: ILIMIT(LOW) 90mV greater than valley current 5.25A, circuit easily deliver full rated using default 100mV nominal ILIM threshold. When adjusting current limit, tolerance RLIM resistor prevent significant increase errors current-limit tolerance.
actual microfarad capacitance value required relates physical size needed achieve ESR, well chemistry capacitor technology. Thus, capacitor usually selected voltage rating rather than capacitance value (this true tantalums, OS-CONs, other electrolytics). When using low-capacity filter capacitors such ceramic polymer types, capacitor size usually determined capacity needed prevent overvoltage protection circuit from being tripped when transitioning from full-load no-load condition. capacitor must large enough prevent inductor's stored energy from launching output above overvoltage protection threshold. Generally, once enough capacitance added meet overshoot requirement, undershoot rising load edge longer problem (see also VSAG equation under Design Procedure). With integrators disabled, amount overshoot stored inductor energy calculated
IPEAK VOUT COUT
where IPEAK peak inductor current. absolutely minimize overshoot, disable integrator first, since inherent delay integrator cause extra "runon" switching cycles occur after load change.
Output Capacitor Selection
output filter capacitor must have enough effective series resistance (ESR) meet output ripple loadtransient requirements, have high enough satisfy stability requirements. Also, capacitance value must high enough absorb inductor energy going from full-load no-load condition without tripping overvoltage protection circuit. VCORE converters other applications where output subject violent load transients, output capacitor's size depends much needed prevent output from dipping under load transient. Ignoring finite capacitance: VDIP RESR LOAD(MAX) non-CPU applications, output capacitor's size depends much needed maintain acceptable level output voltage ripple:
Output Capacitor Stability Considerations
Stability determined value zero relative switching frequency. point instability given following equation: where RESR typical 300kHz application, zero frequency must well below 95kHz, preferably below 50kHz. Tantalum OS-CON capacitors widespread time publication have typical zero frequencies 15kHz. design example used inductor selection, needed support 50mVp-p ripple 50mV/3.5A 14.2m. Three 470µF/4V Kemet T510 lowESR tantalum capacitors parallel provide ESR. Their typical combined results zero 14.1kHz, well within bounds stability.
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs
Don't high-value ceramic capacitors directly across fast feedback inputs GND) without taking precautions ensure stability. Large ceramic capacitors have high zero frequency cause erratic, unstable operation. However, it's easy enough series resistance simply placing capacitors couple inches downstream from junction inductor (see All-Ceramic-Capacitor Application section). Unstable operation manifests itself related distinctly different ways: double-pulsing fast-feedback loop instability. Double-pulsing occurs noise because that there isn't enough voltage ramp output voltage (FB) signal. This "fools" error comparator into triggering cycle immediately after 400ns minimum off-time period expired. Doublepulsing more annoying than harmful, resulting nothing worse than increased output ripple. However, indicate possible presence loop instability, which caused insufficient ESR. Loop instability result oscillations output after line load perturbations that trip overvoltage protection latch cause output voltage fall below tolerance limit. easiest method checking stability apply very fast zero-to-max load transient (see MAX1710 Evaluation manual) carefully observe output voltage ripple envelope overshoot ringing. help simultaneously monitor inductor current with current probe. Don't allow more than cycle ringing after initial step-response under- overshoot. ensure that conduction losses minimum input voltage don't exceed package thermal limits violate overall thermal budget. Check ensure that conduction losses plus switching losses maximum input voltage don't exceed package ratings violate overall thermal budget. Choose low-side MOSFET (Q2) that lowest possible RDS(ON), comes moderate small package (i.e., SO-8), reasonably priced. Ensure that MAX1710/MAX1711 gate driver drive other words, check that gate isn't pulled high-side switch turning parasitic drain-to-gate capacitance, causing cross-conduction problems. Switching losses aren't issue low-side MOSFET, since it's zero-voltage switched device when used buck topology.
MAX1710/MAX1711
MOSFET Power Dissipation
Worst-case conduction losses occur duty factor extremes. high-side MOSFET, worst-case power dissipation resistance occurs minimum battery voltage: PD(Q1) (VOUT VBATT(MIN)) ILOAD2 RDS(ON) Generally, small high-side MOSFET desired order reduce switching losses high input voltages. However, RDS(ON) required stay within package power-dissipation limits often limits small MOSFET Again, optimum occurs when switching (AC) losses equal conduction (RDS(ON)) losses. High-side switching losses don't usually become issue until input greater than approximately 15V. Switching losses high-side MOSFET become insidious heat problem when maximum adapter voltages applied, squared term CV2F switching loss equation. high-side MOSFET you've chosen adequate RDS(ON) battery voltages becomes extraordinarily when subjected VBATT(MAX), must reconsider your choice MOSFET. Calculating power dissipation switching losses difficult, since must allow difficult quantify factors that influence turn-on turn-off times. These factors include internal gate resistance, gate charge, threshold voltage, source inductance, board layout characteristics. following switching loss calculation provides only very rough estimate substitute breadboard evaluation, preferably including sanity check using thermocouple mounted
Input Capacitor Selection
input capacitor must meet ripple current requirement (IRMS) imposed switching currents. Non-tantalum chemistries (ceramic, aluminum, OSCON) preferred their resistance power-up surge currents. VOUT LOAD BATT VBATT
Power MOSFET Selection
Most following MOSFET guidelines focus challenge obtaining high load-current capability (>5A) when using high-voltage (>20V) adapters. Low-current applications usually require less attention. maximum efficiency, choose high-side MOSFET (Q1) that conduction losses equal switching losses optimum battery voltage (15V). Check
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
24V* 0.1µF
ON/OFF SHDN SKIP
0.5µH 0.1µF
1.6V
MAX1711
INPUTS
PGND
0.22µF 470pF
GNDS 4.7µF/25V TAIYO YUDEN (TMK325BJ475K) 47µF/10V TAIYO YUDEN (LMK550BJ476KM) MINIMUM TRACE RESISTANCE (TOTAL)
HIGHER MINIMUM INPUT VOLTAGE, LESS OUTPUT CAPACITANCE REQUIRED.
Figure All-Ceramic-Capacitor Application
Table Approximate K-Factors Errors
SETTING FACTOR (kHz) (µs-V) APPROXIMATE K-FACTOR ERROR ±12.5 ±12.5 VBATT VOUT
current limit cause fault latch trip. protect against this possibility, must "overdesign" circuit tolerate ILOAD ILIMIT(HIGH) (LIR ILOAD(MAX), where ILIMIT(HIGH) maximum valley current allowed current-limit circuit, including threshold tolerance on-resistance variation. This means that MOSFETs must very well heatsinked. short-circuit protection without overload protection enough, normal ILOAD value used calculating component stresses. Choose Schottky diode having forward voltage enough prevent MOSFET body diode from turning during dead time. general rule, diode having current rating equal load current sufficient. This diode optional, efficiency isn't critical removed.
PD(switching)
CRSS VBATT(MAX) ILOAD IGATE
where CRSS reverse transfer capacitance IGATE peak gate-drive source/sink current typical). low-side MOSFET, worst-case power dissipation always occurs maximum battery voltage: PD(Q2) VOUT VBATT(MAX)) ILOAD2 RDS(ON) absolute worst case MOSFET power dissipation occurs under heavy overloads that greater than ILOAD(MAX) quite high enough exceed
Application Issues
Dropout Performance
output voltage adjust range continuous-conduction operation restricted non-adjustable 500ns (max) minimum off-time one-shot. best dropout performance, slowest (200kHz) on-time setting. When working with input voltages, duty-factor limit must calculated using worst-case values off-times. Manufacturing tolerances internal
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs
VBATT VOUT
MAX1710
GNDS
Figure Setting VOUT with Resistor-Divider
propagation delays introduce error K-factor. This error higher higher frequencies (Table Also, keep mind that transient response performance buck regulators operated close dropout poor, bulk output capacitance must often added (see VSAG equation Design Procedure). Dropout Design Example: VBATT min, VOUT 300kHz. required duty (VOUT VSW) (VBATT VSW) 0.1V) (3.0V 0.1V) 72.4%. worst-case on-time 0.075) BATT 2.075V 3.35µs-V 2.08µs. duty-factor limitation
DUTY ON(MIN) ON(MIN) OFF(MAX) 2.08µs 500ns 80.6%
which meets required duty. Remember include inductor resistance MOSFET on-state voltage drops (VSW) when doing worst-case dropout duty-factor calculations.
tor. some cases, there room electrolytics, creating need DC-DC design that uses nothing ceramics. all-ceramic-capacitor application Figure same basic performance Standard Application Circuit, replaces tantalum output capacitors with ceramics. This design relies having minimum parasitic board trace resistance series with capacitor order reduce zero frequency. This small amount resistance easily obtained locating MAX1710/MAX1711 circuit three inches away from CPU, placing ceramic capacitors close CPU. Resistance values higher than just improve stability (which observed examining load-transient response characteristic shown Typical Operating Characteristics). Avoid adding excess board trace resistance, there's efficiency penalty. sufficient circuit. Output overshoot determines minimum output capacitance requirement. this example, switching frequency been increased 550kHz inductor value been reduced 0.5µH (compared 300kHz standard circuit) order minimize energy transferred from inductor capacitor during load-step recovery. Even amount overshoot high enough (80mV) that MAX1710, it's wise disable MAX1711 with fixed 2.25V overvoltage protection threshold avoid tripping fault latch (see overshoot equation Output Capacitor Selection section). efficiency penalty operating 550kHz about depending input voltage. optional resistors placed series with FBS. These resistors prevent negative output voltage spike (that results from tripping OVP) from pulling SHDN internal diode, which tends clear fault latch, causing "hiccup" restarts.
MAX1710/MAX1711
All-Ceramic-Capacitor Application
Ceramic capacitors have advantages disadvantages. They have ultra-low ESR, non-combustible, relatively small, nonpolarized. other hand, they're expensive brittle, their ultra-low characteristic result excessively high zero frequencies (affecting stability). addition, they cause output overshoot when going abruptly from full-load no-load conditions, unless there some bulk tantalum electrolytic capacitors parallel absorb stored energy induc-
Setting VOUT with Resistor-Divider output voltage adjusted with resistordivider rather than desired (Figure drawback this practice that on-time doesn't automatically receive correct compensation changing output voltage levels. This result variable switching frequency resistor ratio changed and/or excessive switching frequency. equation adjusting output voltage
VOUT
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
4.5V 5.5V 10µF/25V
ILIM ON/OFF SHDN INPUTS D4** 0.22µF 470pF
0.1µF IRF7805 VOUT 1.6V 470µF KEMET T510
0.5µH
MAX1710 MAX1711
PGND REMOTE LOAD GNDS IRF7805
100k PGOOD MAX1710 ONLY MAX1711 ONLY
SKIP
OVP*
Figure 5V-Powered, Buck Regulator
where currently selected value. When using external resistors, remote sensing recommended, GNDS remote sensing still possible. Connect GNDS remote ground location. resistor-adjusted circuits, code should close possible actual output voltage that switching frequency doesn't become excessive. highest accuracy, MAX1710 when adjusting VOUT with external resistors. MAX1710 node very high impedance, while MAX1711 180k ±35% impedance, which degrades VOUT accuracy.
decreases isn't compensated change ontime. 3.3V about maximum limit practical adjustment range; even slowest setting with switching rate will exceed 600kHz. trip threshold output overvoltage protection scales with nominal output voltage setting.
2-Stage (5V-Powered) Notebook Buck Regulator
most efficient overall cost-effective solution stepping down high-voltage battery very output voltage single-stage buck regulator that's powered directly from battery. However, there situations where battery can't routed near CPU, where space constraints dictate smallest possible local DC-DC converter. such cases, 5Vpowered circuit Figure appropriate. reduced input voltage allows higher switching frequency much smaller inductor value.
Adjusting VOUT Above feed-forward circuit that makes on-time dependent battery voltage maintains nearly constant switching frequency VIN, ILOAD, code changed. This works extremely well long connected directly output. When output adjusted higher than with resistor-divider, switching frequency increased relatively unreasonable levels actual off-time
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs
Dynamic Code Changes (MAX1711)
Changing output voltage dynamically switching codes "on-the-fly" used help make power-savings/performance trade-offs host system. Several important design issues arise from this practice. First, know that attempting slew output upward quickly causes large current surges battery goes into output current limiting during transition. Surge currents controlled either counting code slowly (50kHz slower rate suggested), modulating ILIM current-limit threshold. inputs must driven quickly value device doesn't wrongly interpret disallowed code from transitory value. 100ns maximum rise fall times. Selecting output capacitors dynamically adjusted CORE applications tricky trade-offs between capacitor capacity ESR. other words, capacitor sufficiently meet loadtransient response specification, large capacity cause excessive input surge currents. other hand, purely ceramic capacitor have enough capacity prevent overvoltage during transition from full- no-load condition (see overshoot equation under Output Capacitor Selection). necessary capacitor types specialized capacitors such those shown Figure order achieve required while staying within min/max capacitance value window. minimum load very light, necessary assert forced mode (via SKIP) during transition period guarantee some output sink current capability. Otherwise, output voltage won't ramp downwards until pulled down external load current. Using forced mode repeatedly ensure sink current capability have side effects, however. energy taken from output synchronous rectifier isn't lost, instead returned input. frequency high-to-low output voltage transition high enough, efficiency will degraded resistive "friction" losses associated with shuttling energy between input output capacitors. Also, output being overdriven external source (such external docking-station power supply), forced mode cause battery voltage become pumped possibly overvoltaging battery.
High-Power, Dynamically Adjustable Application
MAX1711 VCORE regulator Figure designed have output voltage switched between 1.3V 1.45V less than 100µs, while causing minimum level input surge current. this end, output capacitors were selected having correct value support needed ESR, prevent excess load-recovery overshoot, minimize input surge currents. optional 74HC86 exclusive-OR gate detects code transitions each four most-significant inputs. transition detector output goes precision pulse stretcher, timer which extends pulse 75µs (nominal). This signal then feeds three circuits: power-good detector, SKIP input, ILIM current-limit control input, thus reducing current-limit threshold during transition interval order reduce battery current surges). Likewise, SKIP going high asserts forced mode order drag output voltage down value. Forced mode incompatible with good light-load efficiency inductor-current recirculation losses gate-drive losses. Therefore, SKIP driven high only during 100µs transition interval. power-good output signal logical 75µs timer signal MAX1711 PGOOD signal. internal PGOOD detector circuit monitors only output undervoltage; PGOOD will probably during upward transitions, downward. final powergood output will always least 75µs timer signal. Load current capability peak continuous over input range. three MOSFETs require good heatsinking. MAX1711 Manual complete bill materials.
MAX1710/MAX1711
Board Layout Guidelines
Careful board layout critical achieving switching losses clean, stable operation. switching power stage requires particular attention (Figure 11). possible, mount power components side board with their ground terminals flush against another. Follow these guidelines good board layout: Keep high-current paths short, especially ground terminals. This practice essential stable, jitter-free operation. PGND together close Carefully follow grounding instructions under step Layout Procedure.
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
INPUT VBATT 10µF/25V CERAMIC 0.1µF 0.22µF 470pF ON/OFF INPUTS 0.1µF 1µH/20A 220µF OS-CON OUTPUT +1.5V 20µF CERAMIC CMPSH3
IRF7805
MAX1711
SHDN
PGND
IRF7805
N.C.
GNDS PGOOD SKIP ILIM
2N7002
POWERGOOD
200k
2N7002
+3.3V TRANSITION DETECTOR 1000pF 1000pF 1000pF 1000pF 1N4148 2N7002 TIMER BLOCK 100k 100k 2N7002 1N4148 100k 0.1µF 100k 49.9k
74HC86
1N4148
MAX986
+3.3V 820pF 2N7002
1N4148
Figure Dynamically Adjustable Notebook Supply with Battery-Surge Current Limiting
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
VBATT ANALOG GROUNDS CONNECT ONLY
PGND NEAR SOURCE
MAX1710 MAX1711
ILIM COUT
GNDS
VOUT SOURCE NEAR COUT+
CONNECT PGND BENEATH POINT ONLY. SPLIT ANALOG PLANE SHOWN.
NOTES: "STAR" GROUND USED. DIRECTLY ACROSS
INDUCTOR DISCHARGE PATH RESISTANCE
Figure Power-Stage Board Layout Example
Keep power traces load connections short. This practice essential high efficiency. thick copper boards oz.) enhance full-load efficiency more. Correctly routing board traces difficult task that must approached terms fractions centimeters, where single milliohm excess trace resistance causes measurable efficiency penalty. PGND connections current limiting must made using Kelvin sense connections order guarantee current-limit accuracy. With SO-8 MOSFETs, this best done routing power MOSFETs from outside using copper layer, while tying PGND inside (underneath) SO-8 package. When trade-offs trace lengths must made, it's preferable allow inductor charging path
made longer than discharge path. example, it's better allow some extra distance between input capacitors high-side MOSFET than allow distance between inductor low-side MOSFET between inductor output filter capacitor. Ensure that connection COUT short direct. However, some cases desirable deliberately introduce some trace length between inductor node output filter capacitor (see All-Ceramic-Capacitor Application section). Route high-speed switching nodes away from sensitive analog areas (CC, REF, ILIM). Make pin-strap control input connections (SKIP, ILIM, etc.) rather than PGND VDD.
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
Layout Procedure
Place power components first, with ground terminals adjacent source, CIN-, COUT-, anode). possible, make these connections layer with wide, copper-filled areas. Mount controller adjacent MOSFET preferably back side opposite order keep LX-PGND current-sense lines gatedrive line short wide. gate trace must short wide, measuring squares mils wide MOSFET inch from controller IC). Group gate-drive components (BST diode capacitor, bypass capacitor) together near controller Make DC-DC controller ground connections shown Figure This diagram viewed having three separate ground planes: output ground, where high-power components PGND plane, where PGND bypass capacitor analog plane, where sensitive analog components analog ground plane PGND plane must meet only single point directly beneath These planes then connected high-power output ground with short connection from cap/PGND source low-side MOSFET, (the middle star ground). This point must also very close output capacitor ground terminal. Connect output power planes (VCORE system ground planes) directly output filter capacitor positive negative terminals with multiple vias. Place entire DC-DC converter circuit close practical.
Configurations
VIEW
SHDN ILIM GNDS PGOOD SKIP
VIEW
SHDN ILIM GNDS PGOOD SKIP
MAX1710
PGND
MAX1711
PGND
QSOP
QSOP
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
Package Information
QSOP.EPS
High-Speed, Digitally Adjusted Step-Down Controllers Notebook CPUs MAX1710/MAX1711
NOTES

NUAL ATION SHEE EVALU OLLOW High-Speed, Digitally Adjusted Step-D

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