IND: -7/10/12/14/18 MACH®111-5/7/10/12/15 High-Performance C

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IND: -7/10/12/14/18 MACH®111-5/7/10/12/15 High-Performance C

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COM'L: -5/7/10/12/15
IND: -7/10/12/14/18
MACH®111-5/7/10/12/15
High-Performance CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
Pins PLCC TQFP Macrocells Commercial, Industrial fCNT I/Os; dedicated inputs/clocks; dedicated inputs Flip-flops; clock choices "PALCE26V16" blocks SpeedLockingfor guaranteed fixed timing Bus-FriendlyInputs I/Os Peripheral Component Interconnect (PCI) compliant (-5/-7/-10/-12) Programmable power-down mode Safe mixed supply voltage system designs Pin-compatible with MACH211
GENERAL DESCRIPTION
MACH111 member Vantis' high-performance CMOS MACH families. This device approximately three times logic macrocell capability popular PALCE22V10 without loss speed. MACH111 consists PAL® blocks interconnected programmable switch matrix. blocks essentially "PALCE26V16" structures complete with product-term arrays programmable macrocells, which programmed high speed power. switch matrix connects blocks each other input pins, providing high degree connectivity between fully connected blocks. This allows designs placed routed efficiently. MACH111 macrocell provides either registered combinatorial outputs with programmable polarity. registered configuration chosen, register configured D-type Ttype help reduce number product terms. register type decision made designer software. macrocells connected cell. buried macrocell desired, internal feedback path from macrocell used, which frees input. Vantis offers software design support MACH devices through development system device fitters integrated into third-party tools. Platform support extends across PCs, workstations under advanced operating systems such Windows 3.1, Windows SunOS Solaris, HPUX.
Publication# 20420 Amendment/+1
Rev: Issue Date: June 1998
MACHXL® software complete development system supporting Vantis' MACH devices. supports design entry with Boolean behavioral syntax, state machine syntax truth tables. Functional simulation static timing analysis also included this easy-touse system. This development system includes high-performance device fitters MACH devices. same fitter technology included MACHXL software seamlessly incorporated into third-party tools from leading vendors such Synario, Viewlogic, Mentor Graphics, Cadence MINC. Interface kits MACHXL configurations also available support design entry verification with other leading vendors such Synopsys, Exemplar, OrCAD, Synplicity Model Technology. These MACHXL configurations interfaces accept EDIF 2.0.0 netlists, generate JEDEC files MACH devices, create industry-standard SDF, VITAL-compliant VHDL Verilog output files design simulation. Vantis offers in-system programming support MACH devices through MACHPRO® software enabling MACH device programmability through JTAG compliant ports easy-to-use interface. Additionally, MACHPRO generated vectors work seamlessly with HP3070, GenRad Teradyne testers program MACH devices test them connectivity. MACH devices supported industry standard programmers available from number vendors. These programmer vendors include Advin Systems, Microsystems, Data Corporation, Hi-Lo Systems, GmbH, Stag House, System General.
MACH111-5/7/10/12/15
BLOCK DIAGRAM
Block I/O0 I/O15 I0-I1/CLK0 I3-I4/CLK2
Cells Macrocells
Logic Array Logic Allocator
Switch Matrix Logic Array Logic Allocator
Macrocells
Cells
I/O16 I/O31 Block
CLK3/I5 CLK1/I2
20420B-1
MACH111-5/7/10/12/15
CONNECTION DIAGRAM
View
44-Pin PLCC
I/O31
I/O30
I/O29
I/O5 I/O6 I/O7 Block CLK0/I1 CLK1/I2 I/O8 I/O9 I/O10 I/O11
I/O27 I/O26 I/O25 I/O24 Block CLK3/I5 CLK2/I4 I/O23 I/O22 I/O21
I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 I/O19 I/O20
I/O28
I/O4
I/O3
I/O2
I/O1
I/O0
20420B-2
Note: Pin-compatible with MACH211SP MACH211.
DESIGNATIONS
CLK/I Clock Input Ground Input Input/Output Supply Voltage
MACH111-5/7/10/12/15
CONNECTION DIAGRAM
View
44-Pin TQFP
I/O5 I/O6 I/O7 CLK0/I1 CLK1/I2 I/O8 I/O9 I/O10 I/O11
I/O4 I/O3 I/O2 I/O1 I/O0 I/O31 I/O30 I/O29 I/O28
I/O27 I/O26 I/O25 I/O24 CLK3/I5 CLK2/I4 I/O23 I/O22 I/O21
Block
Block
I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 I/O19 I/O20
20420B-3
Note: Pin-compatible with MACH211SP.
DESIGNATIONS
CLK/I Clock Input Ground Input Input/Output Supply Voltage
MACH111-5/7/10/12/15
ORDERING INFORMATION
Commercial Products
Vantis programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed
OPERATING CONDITIONS Commercial (0°C +70°C)
DEVICE NUMBER Macrocells, Pins, Power-Down option, Bus-Friendly Inputs SPEED
PACKAGE TYPE 44-Pin Plastic Leaded Chip Carrier 044) 44-Pin Thin Quad Flat Pack (PQT044)
Valid Combinations MACH111-5 MACH111-7 MACH111-10 MACH111-12 MACH111-15
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult local Vantis sales office confirm availability specific valid combinations check newly released combinations.
MACH111-5/7/10/12/15 (Com'l)
ORDERING INFORMATION
Industrial Products
Vantis programmable logic products industrial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed
OPERATING CONDITIONS Industrial (-40°C +85°C)
DEVICE NUMBER Macrocells, Pins, Power-Down option, Bus-Friendly Inputs SPEED
PACKAGE TYPE 44-Pin Plastic Leaded Chip Carrier 044)
Valid Combinations MACH111-7 MACH111-10 MACH111-12 MACH111-14 MACH111-18
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult local Vantis sales office confirm availability specific valid combinations check newly released combinations.
MACH111-7/10/12/14/18 (Ind)
FUNCTIONAL DESCRIPTION
MACH111 consists blocks connected switch matrix. There pins dedicated input pins feeding switch matrix. These signals distributed blocks efficient design implementation. There four clock pins that also used dedicated inputs. Blocks Each block MACH111 (Figure contains 64-product-term logic array, logic allocator, macrocells, cells. switch matrix feeds each block with inputs. This makes block look effectively like independent "PALCE26V16." There four additional output enable product terms each block. purposes output enable, cells divided into banks macrocells. Each bank allocated output enable product terms. asynchronous reset product term asynchronous preset product term provided flip-flop initialization. flip-flops within block initialized together. Switch Matrix MACH111 switch matrix inputs feedback signals from blocks. Each block provides internal feedback signals feedback signals. switch matrix distributes these signals back blocks efficient manner that also provides high performance. design software automatically configures switch matrix when fitting design into device. Product-term Array MACH111 product-term array consists product terms logic use, special-purpose product terms. Four special-purpose product terms provide programmable output enable; provides asynchronous reset, provides asynchronous preset. output enable product terms used first eight cells; other control last eight macrocells. Logic Allocator logic allocator MACH111 takes logic product terms allocates them macrocells needed. Each macrocell driven product terms. design software automatically configures logic allocator when fitting design into device. Table illustrates which product term clusters available each macrocell within block. Refer Figure cluster macrocell numbers.
Table
Output Macrocell Available Clusters
Logic Allocation
Output Macrocell Available Clusters C10, C10, C11, C11, C12, C12, C13, C13, C14, C14,
MACH111-5/7/10/12/15
Macrocell MACH111 macrocells configured either registered combinatorial, with programmable polarity. macrocell provides internal feedback whether configured registered combinatorial. flip-flops configured D-type T-type, allowing product-term optimization. flip-flops individually select four clock pins, which also available data inputs. registers clocked LOW-to-HIGH transition clock signal. flip-flops also asynchronously initialized with common asynchronous reset preset product terms. Cell cell MACH111 consists three-state output buffer. three-state buffer configured three ways: always enabled, always disabled, controlled product term. product term control chosen, product terms used provide control. product terms that available common eight cells. Within each block, product terms available selection first eight three-state outputs; other product terms available selection last eight three-state outputs. SpeedLocking Guaranteed Fixed Timing unique MACH architecture designed high performance-a metric that both speed, even more importantly, guaranteed fixed speed. Using design central switch matrix, MACH111 product offers SpeedLocking feature, which allows stable fixed pin-to-pin delay, independent logic paths, routing resources design refits product terms output. Other non-Vantis CPLDs incur serious timing delays product terms expand beyond their typical product-term limits. Speed SpeedLocking combine continuous, high performance required today's demanding designs. Bus-Friendly Inputs I/Os MACH111 inputs I/Os include inverters series which loop back input. This double inversion reinforces state input pulls voltage away from input threshold voltage. Unlike pull-up, this configuration cannot cause contention bus. illustration this configuration, please turn Input/Output Equivalent Schematics section. Compliant MACH111-5/7/10/12 fully compliant with Local Specification published Special Interest Group. MACH111-5/7/10/12's predictable timing ensures compliance with specifications independent design. Power-Down Mode MACH111 features programmable low-power mode which individual signal paths programmed power. These low-power speed paths will slightly slower than non-low-power paths. This feature allows speed critical paths maximum frequency while rest paths operate low-power mode, resulting power savings 50%. Safe Mixed Supply Voltage System Designs MACH111 safe mixed supply voltage system designs. device will overdrive 3.3-V devices above output voltage while accepts inputs from other 3.3-V devices. Thus, MACH111 provides easy-to-use mixed-voltage design compatibility.
MACH111-5/7/10/12/15
Output Enable Output Enable Asynchronous Reset Asynchronous Preset
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Logic Allocator
Cell
Output Macro Cell
Output Macro Cell
Cell
Cell
Output Macro Cell
Switch Matrix
Cell
Output Macro Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Cell
Output Macro Cell
Cell Output Macro Cell Cell Output Macro Cell
Output Enable Output Enable
20420B-4
Figure
MACH111 Block
MACH111-5/7/10/12/15
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Device Junction Temperature +150°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage .-0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 70°C)
esses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability.
OPERATING RANGES
Commercial Devices
Ambient Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Test Conditions -3.2 Min, Min, Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note -160 Unit
Off-State Output Leakage Current VOUT 5.25 HIGH (Note Off-State Output Leakage Current VOUT (Note Output Short-Circuit Current Supply Current (Static) Supply Current (Active) VOUT (Note 25°C, (Note 25°C, (Note
Notes: These absolute values with respect device ground overshoots system and/or tester noise included.
leakage worst case IOZL IOZH). more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 16-bit up/down counter program low-power mode. This pattern programmed each block capable being enabled reset.
MACH111-5/7/10/12/15 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance -0.5 VOUT Test Conditions 25°C Unit
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Paramete Symbol Parameter Description Input, I/O, Feedback Combinatorial Output Setup Time from Input, I/O, Feedback Clock Register Data Hold Time Clock Output Clock Width External Feedback fMAX 1/(tS tCO) HIGH D-type T-type D-type T-type D-type T-type 166.7 66.7 62.5 76.9 71.4 83.3 47.6 66.6 55.5 83.3 Unit
Maximum Frequency Internal Feedback (fCNT) (Note Feedback
1/(tWL tWH)
tARW tARR tAPW tAPR tLPS tLPCO tLPEA
Asynchronous Reset Registered Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time Asynchronous Preset Registered Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable Input, I/O, Feedback Output Disable Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note
Notes: These parameters 100% tested, evaluated initial characterization time design modified where frequency affected.
Switching Test Circuit test conditions. signal powered-down, this parameter must added respective high-speed parameter.
MACH111-5/7/10/12/15 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Device Junction Temperature +150°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage .-0.5 Output Voltage. -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
esses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability.
OPERATING RANGES
Industrial Devices
Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over INDUSTRIAL operating ranges
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions -3.2 Min, Min, Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note 25°C, (Note 25°C, (Note -160 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included.
leakage worst case IOZL IOZH). more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 16-bit up/down counter program low-power mode. This pattern programmed each block capable being enabled reset.
MACH111-7/10/12/14/18 (Ind)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance -0.5 VOUT Test Conditions 25°C Unit
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output Setup Time from Input, I/O, Feedback Clock Register Data Hold Time Clock Output Clock Width External Feedback fMAX 1/(tS tCO) HIGH D-type T-type D-type T-type 166.7 D-type T-type 14.5 14.5 14.5 66.7 62.5 76.9 71.4 83.3 14.5 19.5 Unit 61.5 83.3 19.5 61.5 13.5
Maximum Frequency Internal Feedback (fCNT) (Note Feedback
1/(tWL tWH)
tARW tARR tAPW tAPR tLPS tLPCO tLPEA
Asynchronous Reset Registered Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time Asynchronous Preset Registered Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note
Notes: These parameters 100% tested, evaluated initial characterization time design modified where frequency affected.
Switching Test Circuit test conditions. signal powered-down, this parameter must added respective high-speed parameter.
MACH111-7/10/12/14/18 (Ind)
TYPICAL CURRENT VOLTAGE (I-V) CHARACTERISTICS
25°C
(mA) -1.0 -0.8 -0.6 -0.4 -0.2 Output,
20420B-5
(mA) -100 -125 -150 Output, HIGH
20420B-6
(mA) -100 Input
20420B-7
MACH111-5/7/10/12/15
TYPICAL CHARACTERISTICS
25°C
High Speed
Power
(mA)
Frequency (MHz)
20420B-6
selected "typical" pattern 16-bit up/down counter. This pattern programmed each block capable being loaded, enabled, reset. Maximum frequency shown uses internal feedback D-type register.
MACH111-5/7/10/12/15
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient lfpm Thermal impedance, junction ambient with flow lfpm lfpm lfpm TQFP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment. thermal measurements taken with components six-layer printed circuit board.
SWITCHING WAVEFORMS
Input, I/O, Feedback Combinatorial Output Combinatorial Output Input, I/O, Feedback Clock Registered Output Registered Output
20420B-8 20420B-9
20420B-7
Clock
Clock Width
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH111-5/7/10/12/15
SWITCHING WAVEFORMS
tARW Input, I/O, Feedback Registered Output
tARR Clock
20420B-10
Asynchronous Reset tAPW Input, I/O, Feedback Registered Output tAPR Clock
20420B-11
Asynchronous Preset
Input, I/O, Feedback Outputs
20420B-12
Output Disable/Enable
Notes:
Input pulse amplitude Input rise fall times ns-4 typical.
MACH111-5/7/10/12/15
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT*
Output Test Point
20420B-13
Commercial Specification tPD, Closed Open Closed Open Closed Measured Output Value
Switching several outputs simultaneously should avoided accurate measurement.
MACH111-5/7/10/12/15
fMAX PARAMETERS
parameter fMAX maximum clock rate which device guaranteed operate. Because flexibility inherent programmable logic devices offers choice clocked flip-flop designs, fMAX specified three types synchronous designs. first type design state machine with feedback signals sent off-chip. This external feedback could back device inputs, second device multi-chip state machine. slowest path defining period clock-to-output time input setup time external signals tCO). reciprocal, fMAX, maximum frequency with external feedback conjunction with equivalent speed device. This fMAX designated "fMAX external." second type design single-chip state machine with internal feedback only. this case, flip-flop inputs defined device inputs flip-flop outputs. Under these conditions, period limited internal delay from flip-flop outputs through internal feedback logic flip-flop inputs. This fMAX designated "fMAX internal". simple internal counter good example this type design; therefore, this parameter sometimes called "fCNT." third type design simple data path application. this case, input data presented flip-flop clocked through; feedback employed. Under these conditions, period limited data setup time data hold time tH). However, lower limit period each fMAX type minimum clock period (tWH tWL). Usually, this minimum clock period determines period third fMAX, designated "fMAX feedback." frequencies except fMAX internal calculated from other measured parameters. fMAX internal measured directly.
(SECOND CHIP)
LOGIC
REGISTER
LOGIC
REGISTER
fMAX Internal (fCNT)
fMAX External 1/(ts tCO)
LOGIC
REGISTER
fMAX Feedback; 1/(ts 1/(tWH tWL)
20420B-14
MACH111-5/7/10/12/15
ENDURANCE CHARACTERISTICS
MACH families manufactured using Vantis' advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar parts. result, device erased reprogrammed, feature which allows 100% testing factory. Endurance Characteristics
Parameter Symbol Parameter Description Pattern Data Retention Time Reprogramming Cycles Units Years Years Cycles Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Protection Input
Preload Circuitry
Feedback Input
20420B-15
MACH111-5/7/10/12/15
POWER-UP RESET
MACH devices have been designed with capability reset during system power-up. Following power-up, flip-flops will reset LOW. output state will depend logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
Parameter Symbol Parameter Descriptions Power-Up Reset Time Input Feedback Setup Time Switching Characteristics Clock Width Unit
Power Registered Output Clock
20420B-16
Power-Up Reset Waveform
MACH111-5/7/10/12/15
DEVELOPMENT SYSTEMS (subject change)
more information products listed below, please consult local Vantis sales office.
MANUFACTURER Vantis Corporation P.O. 3755 DeGuigne Drive Sunnyvale, 94088 (408) 732-0555 1(888) 826-8472 (VANTIS2) http://www.vantis.com Aldec, Inc. Sunset Way, Suite Henderson, 89014 (702) 456-1222 (800) 487-8743 Cadence Design Systems River Oaks Pkwy Jose, 95134 (408) 943-1234 (800) 746-6223 Exemplar Logic, Inc. Atlantic Avenue, Suite Alameda, 94501 (510) 337-3700 Logic Modeling 19500 Gibbs P.O. Beaverton, 97075 (800) 346-6335 Mentor Graphics Corp. 8005 S.W. Boeckman Wilsonville, 97070-7777 (800) 547-3000 (503) 685-7000 MicroSim Corp. Fairbanks Irvine, 92718 (714) 770-3022 MINC Inc. 6755 Earl Drive, Suite Colorado Springs, 80918 (800) 755-FPGA (719) 590-1155 Model Technology 8905 S.W. Nimbus Avenue, Suite Beaverton, 97008 (503) 641-1340 OrCAD, Inc. 9300 S.W. Nimbus Avenue Beaverton, 97008 (503) 671-9500 (800) 671-9505 Synario® Design Automation 10525 Willows Road N.E. P.O. 97046 Redmond, 98073-9746 (800) 332-8246 (206) 881-6444 SOFTWARE DEVELOPMENT SYSTEMS
MACHXL Software Vantis-ABEL Software Vantis-Synario Software
ACTIVE-CAD
Designer Concept/Composer Synergy Leapfrog/Verilog-XL LeonardoGalileo
SmartModel® Library
Design Architect, PLDSynthesisII Autologic Synthesizer, QuickSim Simulator, QuickHDL Simulator
MicroSim Design PLogic, PLSyn
PLDesigner-XLSoftware
V-System/VHDL
OrCAD Express
ABELSynarioSoftware
MACH111-5/7/10/12/15
MANUFACTURER Synopsys Middlefield Mountain View, 94040 (415) 962-5000 (800) 388-9125 Synplicity, Inc. East Evelyn Ave. Sunnyvale, 94086 (408) 617-6000 Teradyne Harrison Ave. Boston, 02118 (800) 777-2432 (617) 422-2793 VeriBest, Inc. 6101 Lookout Road, Suite Boulder, 80301 (800) 837-4237 Viewlogic Systems, Inc. Boston Post Road West Marlboro, 01752 (800) 873-8439 (508) 480-0881 MANUFACTURER Acugen Software, Inc. 427-3 Amherst St., Suite Nashua, 03063 (603) 881-8821 GmbH Busenstrasse D-8033 Martinsried, Munich, Germany (87) 857-6667
SOFTWARE DEVELOPMENT SYSTEMS FPGA Design Compiler (Requires MINC PLDesigner-XLTM) Simulator
Synplify
MultiSIM Interactive Simulator LASAR
VeriBest
Viewdraw, ViewPLD, Viewsynthesis Speedwave Simulator, ViewSim Simulator, Simulator TEST GENERATION SYSTEM
ATGENTest Generation Software
PLDCheck
Vantis responsible information relating products third parties. inclusion such information representation endorsement Vantis these products.
MACH111-5/7/10/12/15
APPROVED PROGRAMMERS (SUBJECT CHANGE)
more information products listed below, please consult local Vantis sales office.
MANUFACTURER Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, (408) 243-7000 (800) 627-2456 (408) 737-9200 (408) 736-2503 Microsystems 1000 Post Rd., Suite Houston, 77055-7237 (800) 225-2102 (713) 688-4600 (713) 688-9283 (713) 688-0920 Data Corporation 10525 Willows Road N.E. P.O. 97046 Redmond, 98073-9746 (800) 426-1045 (206) 881-6444 (206) 882-3211 (206) 882-1043 Hi-Lo Systems Sec. Ming Shoh Road Taipei, Taiwan (886) 2-764-0215 (886) 2-756-6403 Tribal Microsystems Hi-Lo Systems 44388 South Grimmer Blvd. Fremont, 94538 (510) 623-8859 (510) 623-0430 (510) 623-9925 GmbH Grund 88239 Wangen Germany (49) 7522-97280 (49) 7522-972850 Weddell Suite Sunnyvale, 94089 (408) 542-0388 Stag House Silver Court Watchmead, Welwyn Garden City Herfordshire 44-1-707-332148 44-1-707-371503 PROGRAMMER CONFIGURATION
Pilot-U40
Pilot-U84
BP1200
BP1400
BP2100
BP2200
UniSite
Model 2900
Model 3900
AutoSite
ALL-07
FLEX-700
Sprint Expert
Sprint Optima
Multisite
Stag Quazar
MACH111-5/7/10/12/15
MANUFACTURER System General 1603A South Main Street Milpitas, 95035 (408) 263-6667 (408) 262-6438 (408) 262-9220 Alley Lane Shing Road, Shin Diau Taipei, Taiwan (886) 2-917-3005 (886) 2-911-1283
PROGRAMMER CONFIGURATION
Turpro-1
Turpro-1/FX
Turpro-1/TX
APPROVED ADAPTER MANUFACTURERS
MANUFACTURER California Integration Coordinators, Inc. Main Street Placerville, 95667 (916) 626-6168 (916) 626-7740 Emulation Technology, Inc. 2344 Walsh Ave., Bldg. Santa Clara, 95051 (408) 982-0660 (408) 982-0664 PROGRAMMER CONFIGURATION
MACH/PAL Programming Adapters
Adapt-A-Socket® Programming Adapters
APPROVED ON-BOARD PROGRAMMING TOOLS
MANUFACTURER Corelis, Inc. 12607 Hidden Creek Way, Suite Cerritos, California 70703 (310) 926-6727 Vantis Corporation P.O. 3755 DeGuigne Drive Sunnyvale, 94088 (408) 732-0555 1(888) 826-8472 (VANTIS2) http://www.vantis.com PROGRAMMER CONFIGURATION
JTAGPROG
MACHPRO®
MACH111-5/7/10/12/15
PHYSICAL DIMENSIONS
44-Pin Plastic Leaded Chip Carrier (measured inches)
.685 .695
.650 .656
.042 .056
.062 .083
I.D. .685 .695 .650 .656 .500 .590 .630
.013 .021
.026 .032
.050
.009 .015
.090 .120 .165 .180
SEATING PLANE
VIEW
SIDE VIEW
16-038-SQ DA78 6-28-94
MACH111-5/7/10/12/15
PHYSICAL DIMENSIONS
PQT044 44-Pin Thin Quad Flat Pack (measured millimeters)
11.80 12.20 9.80 10.20
9.80 10.20 11.80 12.20
0.95 1.05 1.20
16-038-PQT-2 7-11-95
1.00 REF.
0.30 0.45
0.80
Trademarks Copyright 1998 Vantis Corporation. rights reserved. registered trademark Advanced Micro Devices, Inc. Vantis, Vantis logo combinations thereof, SpeedLocking Bus-Friendly trademarks, MACH, MACHXL, MACHPRO registered trademarks Vantis Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
MACH111-5/7/10/12/15

IND: -7/10/12/14/18 MACH®111-5/7/10/12/15 High-Performance C

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