communication. Serial EEPROM devices available variety densities, oper

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AN668
communication. Serial EEPROM devices available variety densities, operational voltage ranges, packaging options. This application note provides assistance source code ease design process interfacing Microchip PIC16C92x microcontroller Microchip serial EEPROM. hardware port microcontroller provides simple three-wire connection EEPROM external "glue" logic required Figure describes hardware schematic interface between Microchip's devices Microchip PIC16C92x Microcontroller. schematic shows connections necessary between microcontroller serial EEPROM, software written assuming these connections. Appendix contains listing source code.
Interfacing Microchip PIC16C92x Microchip SPISerial EEPROMs
INTRODUCTION
There many different microcontrollers market today that being used embedded control applications. Many these embedded control systems need non-volatile memory. Because their small footprint, byte level flexibility, requirement, power consumption, cost, serial EEPROMs popular choice non-volatile storage. Microchip addresses these needs offering full line serial EEPROMs covering industry standard serial communication protocols two-wire, three-wire,
FIGURE
CIRCUIT PIC16C92X
RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR/VPP COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 RA4/T0CKI RA5/AN4/SS RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO VLCD2 VLCD3 AVDD OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI
PIC16C924
RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RG7/SEG28 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12
T1OSI CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 RD4/SEG04 RE7/SEG27 RE0/SEG05 RE1/SEG06 RE2/SEG07 RE3/SEG08 RE4/SEG09 RE5/SEG10 RE6/SEG11
25xxXXX
HOLD
1997 Microchip Technology Inc.
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Please check Microchip latest version source code. Microchip's Worldwide Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership required).
APPENDIX
SOURCE CODE
ANXXX.ASM 4-7-1997 14:04:01 PAGE
MPASM 01.40.01 Intermediate
OBJECT CODE VALUE
LINE SOURCE TEXT
00000020 00000021 00000022 00000023 00000024 00000025 00000026
0000 0000 2801
0001 1283 0002 0187 0003 1683 0004 3010 Message[302]: 0005 0087 Message[302]: 0006 0186 Message[302]: 0007 1394 Message[302]: 0008 1314 0009 1283 000A 1606 000B 1486
00001 LIST P=16C924 00002 00003 Port descriptions 00004 00005 00006 00007 00008 00009 10MHz crystal being used, thus each instruction cycle 400nS 00010 00011 ;*******************RAM register 00012 rxdata 00013 txdata 00014 addr 00015 loops 00016 outbyte 00017 temp1 00018 temp2 00019 ;*******************Bit 00020 00021 #define 00022 #define SSPSTAT register definition 00023 #define SSPSTAT register definition 00024 #define SPI_HOLD PORTB,4 Hold definition 00025 #define SPI_WP PORTB,1 Write Protect definition 00026 #define SPI_CS PORTB,3 Chip Select definition 00027 00028 ;*******************Include 00029 include "p16c924.inc" 00001 LIST 00002 P16C924.INC Standard Header File, Version 1.00 Microchip Technology, Inc. 00288 LIST 00030 00031 0x000 reset vector 00032 goto start beginning main 00033 00034 ;!!!!!!!!!!!!!!!!!!!!!!Begin Main 00035 start STATUS,RP0 bank 00036 clrf PORTC initialize portc 00037 STATUS,RP0 bank 00038 movlw 0x10 bits outputs except Register operand bank Ensure that bank bits correct. 00039 movwf TRISC move value TRIS portc 00040 ;*** Register operand bank Ensure that bank bits correct. 00041 clrf TRISB Register operand bank Ensure that bank bits correct. 00042 SSPSTAT,SMP Register operand bank Ensure that bank bits correct. 00043 SSPSTAT,CKE 00044 STATUS,RP0 bank0 00045 ;*** 00046 SPI_HOLD 00047 SPI_WP
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00048 SPI_CS 00049 Message[302]: Register operand bank Ensure that bank bits correct. 000D 018C 00050 clrf PIE1 disable peripheral interrupts 000E 018B 00051 clrf INTCON disables interrupts 000F 1283 00052 STATUS,RP0 bank 0010 0194 00053 clrf SSPCON clear control register 0011 3031 00054 movlw 0x31 port, master, 0012 0094 00055 movwf SSPCON clk/16, ckp=1 (mode 1,1) 0013 1587 00056 PORTC,3 ;bug workaround 0014 3055 00057 movlw 0x55 starting address 0015 00A2 00058 movwf addr addr later 00059 ;Send write enable sequence (WREN) 0016 1186 00060 SPI_CS clear chip select line 0017 3006 00061 movlw 0x06 load WREN sequence 0018 00A4 00062 movwf outbyte store location outbyte 0019 2065 00063 call output call output routine 001A 1586 00064 SPI_CS chip select line 00065 ;Send write status register sequence (WRSR) 001B 1186 00066 SPI_CS clear chip select line 001C 3001 00067 movlw 0x01 clear status register 001D 00A4 00068 movwf outbyte store location outbyte 001E 2065 00069 call output call output routine 001F 3000 00070 movlw 0x00 load zero send 0020 00A4 00071 movwf outbyte store location outbyte 0021 2065 00072 call output call output routine 0022 1586 00073 SPI_CS chip select line 00074 ;Wait required write cycle timer 0023 2070 00075 call delay call delay subroutine 00076 ;Send write enable sequence (WREN) 0024 1186 00077 SPI_CS clear chip select line 0025 3006 00078 movlw 0x06 load WREN sequence 0026 00A4 00079 movwf outbyte store location outbyte 0027 2065 00080 call output call output routine 0028 1586 00081 SPI_CS chip select line 00082 ;Send read status register sequence (RDSR) 0029 1186 00083 SPI_CS clear chip select line 002A 3005 00084 movlw 0x05 load RDSR sequence 002B 00A4 00085 movwf outbyte store location outbyte 002C 2065 00086 call output call output routine 002D 2065 00087 call output read data status reg. 002E 1586 00088 SPI_CS chip select line 00089 ;Send write sequence (WRITE) 002F 1186 00090 SPI_CS clear chip select line 0030 3002 00091 movlw 0x02 load WRITE sequence 0031 00A4 00092 movwf outbyte store location outbyte 0032 2065 00093 call output call output routine 00094 ;****Comment with 25xx010, 25xx020 25xx040******** 0033 3000 00095 movlw 0x00 load high address byte 0034 00A4 00096 movwf outbyte store location outbyte 0035 2065 00097 call output call output routine 00098 0036 0822 00099 movf addr,W move address into 0037 00A4 00100 movwf outbyte store location outbyte 0038 2065 00101 call output call output routine 0039 30AA 00102 movlw 0xAA load data into 003A 00A4 00103 movwf outbyte store location outbyte 003B 2065 00104 call output call output routine 003C 1586 00105 SPI_CS chip select line 00106 ;Perform data polling (RDSR 003D 1186 00107 SPI_CS clear chip select line 003E 3005 00108 movlw 0x05 load RDSR sequence 003F 00A4 00109 movwf outbyte store location outbyte 0040 2065 00110 call output call output routine 00111 0041 3030 00112 movlw 0x30 give device time 000C 1586
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0042 00A3 Message[305]: 0043 0BA3 0044 2843 00113 movwf loops Using default destination (file). 00114 wait decfsz loops status register before coming 00115 goto wait back doing data polling 00116 0045 2065 00117 polling call output read data status reg. 0046 1820 00118 btfsc rxdata,0 test status reg. 0047 2845 00119 goto polling clear, loop until 0048 1586 00120 SPI_CS chip select line 00121 ;Send read sequence (READ), read address 0x55 0049 1186 00122 SPI_CS clear chip select line 004A 3003 00123 movlw 0x03 load READ sequence 004B 00A4 00124 movwf outbyte store location outbyte 004C 2065 00125 call output call output routine 00126 ;****Comment with 25xx010, 25xx020 25xx040******** 004D 3000 00127 movlw 0x00 load high address byte 004E 00A4 00128 movwf outbyte store location outbyte 004F 2065 00129 call output call output routine 00130 0050 0822 00131 movf addr,W move address into 0051 00A4 00132 movwf outbyte store location outbyte 0052 2065 00133 call output call output routine 0053 2065 00134 call output call output read byte 0054 1586 00135 SPI_CS chip select line 00136 ;Send write enable sequence (WREN) 0055 1186 00137 SPI_CS clear chip select line 0056 3006 00138 movlw 0x06 load WREN sequence 0057 00A4 00139 movwf outbyte store location outbyte 0058 2065 00140 call output call output routine 0059 1586 00141 SPI_CS chip select line 00142 ;Send write disable sequence (WRDI) 005A 1186 00143 SPI_CS clear chip select line 005B 3004 00144 movlw 0x04 load WRDI sequence 005C 00A4 00145 movwf outbyte store location outbyte 005D 2065 00146 call output call output routine 005E 1586 00147 SPI_CS chip select line 00148 ;Send read status register sequence (RDSR) 005F 1186 00149 SPI_CS clear chip select line 0060 3005 00150 movlw 0x05 load RDSR sequence 0061 00A4 00151 movwf outbyte store location outbyte 0062 2065 00152 call output call output routine 0063 2065 00153 call output read data status reg. 00154 ;*******Go back main 0064 2801 00155 goto start 00156 00157 ;*******************SPI output 0065 0824 00158 output movf outbyte,W move outbyte into 0066 0093 00159 movwf SSPBUF place data send buffer 0067 1683 00160 loop1 STATUS,RP0 bank Message[302]: Register operand bank Ensure that bank bits correct. 0068 1C14 00161 btfss SSPSTAT,BF data been received? 0069 2867 00162 goto loop1 loop received 006A 1283 00163 STATUS,RP0 bank 006B 0813 00164 movf SSPBUF,W empty receive buffer 00165 006C 1294 00166 SSPCON,SSPEN disable peripheral 006D 1694 00167 SSPCON,SSPEN enable peripheral 00168 previous instructions 00169 required device errata. 006E 00A0 00170 movwf rxdata received byte into rxdata 006F 3400 00171 retlw return from subroutine 00172 00173 400nS (plus overhead) 0070 3032 00174 delay movlw 0x32 move decimal into 0071 00A5 00175 movwf temp1 move decimal into temp1 0072 30FA 00176 dec1 movlw 0xFA move decimal into
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0073 0074 0075 0076 0077 0078 00A6 0BA6 2874 0BA5 2872 3400 00177 00178 dec2 00179 00180 00181 00182 00183 00184 movwf decfsz goto decfsz goto retlw temp2 temp2,1 dec2 temp1,1 dec1 move decimal into temp2 decrement temp2, skip zero goto decrement zero decrement temp1, skip zero goto decrement zero return both locations
MEMORY USAGE (`X' Used,
Unused)
0000 XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX 0040 XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXX-All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: 3975
Errors Warnings Messages
reported, reported,
suppressed suppressed
1997 Microchip Technology Inc.
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NOTES:
DS00668A-page
1997 Microchip Technology Inc.
AN668
NOTES:
1997 Microchip Technology Inc.
DS00668A-page
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United Kingdom
Arizona Microchip Technology Ltd. Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 Tel: 5858 Fax: 44-118 921-5835
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11/15/99
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Microchip Technology Inc. 2107 North First Street, Suite Jose, 95131 Tel: 408-436-7950 Fax: 408-436-7955
Microchip received QS-9000 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona July 1999. Company's quality system processes procedures QS-9000 compliant PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs microperipheral products. addition, Microchip's quality system design manufacture development systems 9001 certified.
rights reserved. 1999 Microchip Technology Incorporated. Printed USA. 11/99
Printed recycled paper.
Information contained this publication regarding device applications like intended suggestion only superseded updates. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights. Microchip logo name registered trademarks Microchip Technology Inc. U.S.A. other countries. rights reserved. other trademarks mentioned herein property their respective companies.
1999 Microchip Technology Inc.

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