DESCRIPTIO Sample Rate: 400ksps Power Dissipation: 70mW Guarantee
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LTC1416 Power 14-Bit, 400ksps Sampling FEATURES
DESCRIPTIO
Sample Rate: 400ksps Power Dissipation: 70mW Guaranteed 1.5LSB DNL, 2LSB (Max) 80.5dB S/(N 93dB 100kHz 80dB S/(N 90dB Nyquist Sleep Shutdown Modes Operates with Internal External Reference True Differential Inputs Reject Common Mode Noise 15MHz Full Power Bandwidth Sampling ±2.5V Bipolar Input Range 28-Pin SSOP Package
®1416 2.2µs, 400ksps, 14-bit sampling converter that draws only 70mW from supplies. This easy-to-use device includes high dynamic range sampleand-hold precision reference. digitally selectable power shutdown modes provide flexibility power systems. LTC1416's full-scale input range ±2.5V. Maximum specifications include ±2LSB INL, ±1.5LSB over temperature. Outstanding performance includes 80.5dB S/(N 93dB with 100kHz input, 80dB S/(N 90dB Nyquist input frequency 200kHz. unique differential input sample-and-hold acquire single-ended differential input signals 15MHz bandwidth. 60dB common mode rejection allows users eliminate ground loops common mode noise measuring signals differentially from source. compatible, 14-bit parallel output port. There pipeline delay conversion results. separate convert start input data ready signal (BUSY) ease connections FIFOs, DSPs microprocessors.
APPLICATI
Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems
registered trademarks Linear Technology Corporation.
TYPICAL APPLICATI
10µF AVDD DVDD
Complete, 70mW, 14-Bit with 80.5dB S/(N
Effective Bits Signal-to-(Noise Distortion) Input Frequency
SIGNAL/(NOISE DISTORTION) (dB)
LTC1416 AIN+ AIN- REFCOMP 22µF VREF 10µF BUFFER 2.5V REFERENCE TIMING LOGIC 14-BIT
EFFECTIVE BITS
OUTPUT BUFFERS
(MSB) (LSB)
BUSY CONVST SHDN
fSAMPLE 400kHz 100k INPUT FREQUENCY (Hz)
1416 TA02
AGND
DGND
1416 TA01
NYQUIST FREQUENCY
LTC1416 ABSOLUTE RATI PACKAGE/ORDER ATIO
VIEW AIN+ AIN- VREF REFCOMP AGND D13(MSB) DGND AVDD DVDD BUSY CONVST SHDN
AVDD DVDD (Notes
Supply Voltage (VDD) Negative Supply Voltage (VSS). Total Supply Voltage (VDD VSS) Analog Input Voltage (Note (VSS 0.3V) (VDD 0.3V) Digital Input Voltage (Note .(VSS 0.3V) Digital Output Voltage (VSS 0.3V) (VDD 0.3V) Power Dissipation 500mW Operating Temperature Range Commercial 70°C Industrial 40°C 85°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
ORDER PART NUMBER LTC1416CG LTC1416IG
PACKAGE 28-LEAD PLASTIC SSOP
TJMAX 110°C, 95°C/W
Consult factory Military grade parts grade parts.
VERTER CHARACTERISTICS
PARAMETER Resolution Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note (Note CONDITIONS
With Internal Reference (Notes
±0.8 ±0.7
±1.5
UNITS Bits ppm/°C
Internal Reference External Reference 2.5V IOUT(REF)
ALOG
SYMBOL PARAMETER tjitter CMRR
(Note
CONDITIONS 4.75V 5.25V, 5.25V 4.75V High Between Conversions During Conversions (Note
±2.5
UNITS
Analog Input Range (Note Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio
-1.5
psRMS
2.5V (AIN-
AIN+ 2.5V
LTC1416
ACCURACY
SYMBOL S/(N SFDR PARAMETER
REFERE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance COMP Output Voltage CONDITIONS IOUT IOUT 4.75V 5.25V 5.25V 4.75V 0.1mA IOUT 0.1mA IOUT
DIGITAL PUTS DIGITAL OUTPUTS
SYMBOL PARAMETER High Level Input Voltage Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage 4.75V IOUT 10µA IOUT 200µA 4.75V IOUT 160µA IOUT 1.6mA VOUT VDD, High High (Note VOUT VOUT CONDITIONS 5.25V 4.75V
Level Output Voltage
ISOURCE ISINK
Hi-Z Output Leakage Hi-Z Output Capacitance Output Source Current Output Sink Current
POWER REQUIRE
SYMBOL PARAMETER Positive Supply Voltage Negative Supply Voltage Positive Supply Current Mode Sleep Mode Negative Supply Current Mode Sleep Mode
(Note
CONDITIONS 100kHz Input Signal 200kHz Input Signal 100kHz Input Signal, First Harmonics 200kHz Input Signal, First Harmonics 100kHz Input Signal fIN1 87.01172kHz, fIN2 113.18359kHz (S/(N 77dB)
80.5
UNITS
Signal-to-(Noise Distortion) Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth
(Note
2.480 2.500 0.05 0.05 4.06 2.520 UNITS ppm/°C LSB/V LSB/V
(Note
UNITS
0.05 0.10
(Note
CONDITIONS (Note (Note
4.75 4.75
5.25 5.25
UNITS
SHDN SHDN
SHDN SHDN
LTC1416
POWER REQUIRE
SYMBOL PDISS PARAMETER Power Dissipation Power Dissipation, Mode Power Dissipation, Sleep Mode
CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ tACQ+CONV PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Acquisition Conversion Time Setup Time CONVST Setup Time SHDN Setup Time SHDN CONVST Wake-Up Time CONVST Time CONVST BUSY Delay Data Ready Before BUSY
Delay Between Conversions Wait Time After BUSY Data Access Time After
Relinquish Time
Time CONVST High Time
denotes specifications which apply over full operating temperature range; other limits typicals 25°C. Note Absolute Maximum Ratings those values beyond which life device impaired. Note voltage values with respect ground with DGND AGND wired together unless otherwise noted. Note When these voltages taken below above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA below above without latchup. Note When these voltages taken below VSS, they will clamped internal diodes. This product handle input currents greater than 100mA below without latchup. These pins clamped VDD. Note fSAMPLE 400kHz, unless otherwise specified.
(Note
CONDITIONS
UNITS
SHDN SHDN
(Note Figures
CONDITIONS
UNITS
(Note (Notes (Notes (Notes (Note (Notes 25pF
(Note 25pF
100pF
70°C 40°C 85°C
Note Linearity, offset full-scale specifications apply singleended AIN+ input with AIN- grounded. Note Integral nonlinearity defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Note Bipolar offset offset voltage measured from 0.5LSB when output code flickers between 0000 0000 0000 1111 1111 1111 Note Guaranteed design, subject test. Note Recommended operating conditions. Note falling CONVST edge starts conversion. CONVST returns high critical point during conversion create small errors. best results ensure that CONVST returns high either within 900ns after start conversion after BUSY rises.
LTC1416 TYPICAL PERFORMANCE CHARACTERISTICS
S/(N Input Frequency Amplitude
SIGNAL-TO-NOISE RATIO (dB)
AMPLITUDE BELOW FUNDAMENTAL)
SIGNAL/(NOISE DISTORTION) (dB)
100k INPUT FREQUENCY (Hz)
1416
-20dB
-60dB
Spurious-Free Dynamic Range Input Frequency
SPURIOUS-FREE DYNAMIC RANGE (dB)
AMPLITUDE (dB) 100k INPUT FREQUENCY (Hz)
1416
ERROR (LSB)
-100
Integral Nonlinearity Output Code
AMPLITUDE POWER SUPPLY FEEDTHROUGH (dB)
DGND (VIN 100mV) (VIN 10mV) (VIN 10mV) 100k RIPPLE FREQUENCY (Hz)
1416
COMMON MODE REJECTION (dB)
VOUT ±2.5V VREF 2.5V
ERROR (LSB)
-0.5
-1.0
4096
8192 OUTPUT CODE
12288
1416
Signal-to-Noise Ratio Input Frequency
100k INPUT FREQUENCY (Hz)
1416
Distortion Input Frequency
-100 -110 100k INPUT FREQUENCY (Hz)
1416
Intermodulation Distortion Plot
fSAMPLE 400kHz fa=87.01171876kHz fb=113.1835938kHz
Differential Nonlinearity Output Code
VOUT ±2.5V VREF 2.5V
-100 -120 -140 FREQUENCY (Hz)
1416
-0.5
-1.0
4096
8192 OUTPUT CODE
12288
16384
1416
Power Supply Feedthrough Ripple Frequency
Input Common Mode Rejection Input Frequency
-100
16384
100k INPUT FREQUENCY (Hz)
1416
LTC1416
CTIO
AIN+ (Pin ±2.5V Positive Analog Input. AIN- (Pin ±2.5V Negative Analog Input. VREF (Pin 2.5V Reference Output. Bypass AGND with 1µF. REFCOMP (Pin 4.06V Reference Output. Bypass AGND with 22µF tantalum parallel with 0.1µF ceramic, 22µF ceramic. AGND (Pin Analog Ground. (Pins 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground Internal Logic. AGND. (Pins 20): Three-State Data Outputs. SHDN (Pin 21): Power Shutdown Input. selects shutdown. Shutdown mode selected mode sleep mode. (Pin 22): Read Input. This enables output drivers when low. CONVST (Pin 23): Conversion Start Signal. This active signal starts conversion falling edge. (Pin 24): Chip Select input must recognize CONVST inputs. also sets shutdown mode when SHDN goes low. SHDN select quick wake-up mode. high SHDN select sleep mode. BUSY (Pin 25): BUSY output shows converter status. when conversion progress. Data valid rising edge BUSY. (Pin 26): Negative Supply. Bypass AGND with 10µF tantalum parallel with 0.1µF ceramic, 10µF ceramic. DVDD (Pin 27): Positive Supply. AVDD (Pin 28): Positive Supply. Bypass AGND with 10µF tantalum parallel with 0.1µF ceramic, 10µF ceramic.
CTIO BLOCK DIAGRA
AIN+ CSAMPLE AIN- VREF 2.5V ZEROING SWITCHES
REFCOMP (4.06V) AGND DGND INTERNAL CLOCK
CSAMPLE AVDD DVDD
14-BIT CAPACITIVE COMP
OUTPUT LATCHES
SUCCESSIVE APPROXIMATION REGISTER
CONTROL LOGIC
SHDN CONVST
BUSY
1416
LTC1416
TEST CIRCUITS
Load Circuits Access Timing
100pF 100pF
Load Circuits Output Float Delay
Hi-Z
Hi-Z
1416 TC01
Hi-Z
Hi-Z
1416 TC02
APPLICATIONS INFORMATION
CONVERSION DETAILS LTC1416 uses successive approximation algorithm internal sample-and-hold circuit convert analog signal 14-bit parallel output. complete with precision reference internal clock. control logic provides easy interface microprocessors DSPs. (Please refer Digital Interface section data format.)
CSAMPLE+ HOLD AIN- SAMPLE HOLD CDAC+ CSAMPLE- HOLD ZEROING SWITCHES HOLD
AIN+
SAMPLE
VDAC+ CDAC- COMP
VDAC-
OUTPUT LATCH
Figure Simplified Block Diagram
Conversion start controlled CONVST inputs. start conversion successive approximation register (SAR) reset. Once conversion cycle begun, cannot restarted. During conversion, internal differential 14-bit capacitive output sequenced from most significant (MSB) least significant (LSB). Referring Figure AIN+ AIN- inputs connected sample-and-hold capacitors (CSAMPLE) during acquire phase comparator offset nulled zeroing switches. this acquire phase, minimum delay 400ns will provide enough time sample-and-hold capacitors acquire analog signal. During convert phase comparator zeroing switches open, putting comparator into compare mode. input switches connect CSAMPLE capacitors ground, transferring differential analog input charge onto summing junction. This input charge successively compared with binary-weighted charges supplied differential capacitive DAC. decisions made high speed comparator. conversion, differential output balances AIN+ AIN- input charges. contents 14-bit data word) which represents difference AIN+ AIN- loaded into 14-bit output latches.
1416
LTC1416
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE LTC1416 excellent high speed sampling capability. (Fast Fourier Transform) test techniques used test ADC's frequency response, distortion noise rated throughput. applying distortion sine wave analyzing digital output using algorithm, ADC's spectral content examined frequencies outside fundamental. Figure shows typical LTC1416 plot.
AMPLITUDE (dB)) -100 -120 -140 fSAMPLE 400kHz 101.5625kHz SFDR 95.2dB SINAD 80.5dB
1416 F02a
FREQUENCY (kHz)
Figure LTC1416 Nonaveraged, 4096 Point FFT, Input Frequency 100kHz
EFFECTIVE BITS -100 -120 -140 fSAMPLE 400kHz 189.9414kHz SFDR 94.8dB SINAD 80.2dB
AMPLITUDE (dB))
FREQUENCY (kHz)
1416 F02b
Figure LTC1416 Nonaveraged, 4096 Point FFT, Input Frequency 190kHz
Signal-to-Noise Ratio Signal-to-Noise plus Distortion Ratio [S/(N ratio between amplitude fundamental input frequency amplitude other frequency components output. output band limited frequencies from above below half sampling frequency. Figure shows typical spectral content with 400kHz sampling rate 100kHz input. dynamic performance excellent input frequencies beyond Nyquist limit 200kHz, Figure Effective Number Bits Effective Number Bits (ENOBs) measurement resolution directly related S/(N equation: ENOB [S/(N 1.76]/6.02 where ENOB Effective Number Bits resolution S/(N expressed maximum sampling rate 400kHz LTC1416 maintains near ideal ENOBs Nyquist input frequency 200kHz (refer Figure
SIGNAL/(NOISE DISTORTION) (dB)
NYQUIST FREQUENCY
fSAMPLE 400kHz 100k INPUT FREQUENCY (Hz)
1416 TA02
Figure Effective Bits Signal/(Noise Distortion) Input Frequency
LTC1416
APPLICATIONS INFORMATION
Total Harmonic Distortion Total Harmonic Distortion (THD) ratio harmonics input signal fundamental itself. out-of-band harmonics alias into frequency band between half sampling frequency. expressed
.Vn2
AMPLITUDE (dB)
where amplitude fundamental frequency through amplitudes second through harmonics. versus input frequency shown Figure LTC1416 good distortion performance Nyquist frequency beyond.
AMPLITUDE BELOW FUNDAMENTAL)
-100 -110 100k INPUT FREQUENCY (Hz)
1416
Figure Distortion Input Frequency
Intermodulation Distortion input signal consists more than spectral component, transfer function nonlinearity produce intermodulation distortion (IMD) addition THD. change sinusoidal input caused presence another sinusoidal input different frequency. pure sine waves frequencies applied input, nonlinearities transfer function create distortion products differ-
ence frequencies nfb, where etc. example, order terms include fb). input sine waves equal magnitude, value decibels) order products expressed following formula:
fSAMPLE 400kHz fa=87.01171876kHz fb=113.1835938kHz
Amplitude Amplitude
-100 -120 -140 FREQUENCY (Hz)
1416
Figure Intermodulation Distortion Plot
Peak Harmonic Spurious Noise peak harmonic spurious noise largest spectral component excluding input signal This value expressed decibels relative value full-scale input signal. Full-Power Full-Linear Bandwidth full-power bandwidth that input frequency which amplitude reconstructed fundamental reduced full-scale input signal. full-linear bandwidth input frequency which S/(N dropped 77dB (12.5 effective bits). LTC1416 been designed optimize input bandwidth, allowing undersample input signals with frequencies above converter's Nyquist frequency. noise floor stays very high frequencies; S/(N becomes dominated distortion frequencies beyond Nyquist.
LTC1416
APPLICATIONS INFORMATION
Driving Analog Input differential analog inputs LTC1416 easy drive. inputs driven differentially singleended input (i.e., AIN- input grounded). AIN+ AIN- inputs sampled same instant. unwanted signal that common mode both inputs will reduced common mode rejection sampleand-hold circuit. inputs draw only small current spike while charging sample-and-hold capacitors conversion. During conversion analog inputs draw only small leakage current. source impedance driving circuit low, then LTC1416 inputs driven directly. source impedance increases will acquisition time (see Figure minimum acquisition time, with high source impedance, buffer amplifier should used. only requirement that amplifier driving analog input(s) must settle after small current spike before next conversion starts (settling time must 400ns full throughput rate).
ACQUISITION TIME (µs)
0.01
SOURCE RESISTANCE
100k
1416
Figure Acquisition Time Source Resistance
Choosing Input Amplifier Choosing input amplifier easy requirements taken into consideration. First, limit magnitude voltage spike seen amplifier from charging sampling capacitor, choose amplifier that output impedance (<100) closed-loop bandwidth
frequency. example, amplifier used gain unity-gain bandwidth 50MHz, then output impedance 50MHz should less than 100. second requirement that closed-loop bandwidth must greater than 10MHz ensure adequate smallsignal settling full throughput rate. slower amps used, more settling time provided increasing time between conversions. best choice drive LTC1416 will depend application. Generally, applications fall into categories: applications where dynamic specifications most critical time domain applications where accuracy settling time most critical. following list summary amps that suitable driving LTC1416. More detailed information available Linear Technology Databooks LinearViewCD-ROM. ®1220: 30MHz unity-gain bandwidth voltage feedback amplifier. ±15V supplies, excellent specifications. LT1223: 100MHz video current feedback amplifier. supply current, ±15V supplies, distortion frequencies above 400kHz, noise, good applications. LT1227: 140MHz video current feedback amplifier. 10mA supply current, ±15V supplies, lowest distortion frequencies above 400kHz, noise, best applications. LT1229/LT1230: Dual quad 100MHz current feedback amplifiers. ±15V supplies, noise, good specs, supply current each amplifier. LT1360: 50MHz voltage feedback amplifier. 3.8mA supply current, good specs, ±15V supplies. LT1363: 70MHz, 1000V/µs amps. 6.3mA supply current, good specs. LT1364/LT1365: Dual quad 70MHz, 100V/µs amps. 6.3mA supply current amplifier.
LinearView trademark Linear Technology Corporation.
LTC1416
APPLICATIONS INFORMATION
Input Filtering noise distortion input amplifier other circuitry must considered since they will LTC1416 noise distortion. small-signal bandwidth sample-and-hold circuit 15MHz. noise distortion products that present analog inputs will summed over this entire bandwidth. Noisy input circuitry should filtered prior analog inputs minimize noise. simple 1-pole filter sufficient many applications. example, Figure shows 1000pF capacitor from AIN+ ground source resistor limit input bandwidth 800kHz. 1000pF capacitor also acts charge reservoir input sample-and-hold isolates input from sampling glitch sensitive circuitry. High quality capacitors resistors should used since these components distortion. silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors also generate distortion from self-heating from damage that occur during soldering. Metal film surface mount resistors much less susceptible both problems.
ANALOG INPUT 1000pF 22µF AIN+ AIN- LTC1416 VREF REFCOMP AGND
1416
Figure Input Filter
Input Range ±2.5V input range LTC1416 optimized noise distortion. Most amps also perform best over this same range, allowing direct coupling analog inputs eliminating need special translation circuitry. Some applications require other input ranges. LTC1416 differential inputs reference circuitry
accommodate other input ranges often with little additional circuitry. following sections describe reference input circuitry they affect input range. Internal Reference LTC1416 on-chip, temperature compensated, curvature corrected, bandgap reference that factory trimmed 2.500V. connected internally reference amplifier available VREF (Pin Figure resistor series with output that easily overdriven external reference other circuitry (see Figure 8b). reference amplifier gains voltage VREF 1.625 create required internal reference voltage. This provides buffering between VREF high speed capacitive DAC.
2.5V
VREF
BANDGAP REFERENCE
4.0625V
REFCOMP
22µF AGND
LTC1416 128k
1416 F08a
Figure LTC1416 Reference Circuit
LT1019A-2.5 VOUT ANALOG INPUT
22µF
AIN+ AIN- LTC1416 VREF REFCOMP AGND
1416 F08b
Figure Using LT1019-2.5 External Reference
LTC1416
APPLICATIONS INFORMATION
COMMON MODE REJECTION (dB)
reference amplifier compensation pin, REFCOMP (Pin must bypassed with capacitor ground. reference amplifier stable with capacitors greater. best noise performance, 22µF ceramic 22µF tantalum parallel with 0.1µF ceramic recommended. VREF driven with other means shown Figure This useful applications where peak input signal amplitude vary. input span then adjusted match peak input signal, maximizing signal-to-noise ratio. filtering internal LTC1416 reference amplifier will limit bandwidth settling time this circuit. settling time should allowed after reference adjustment.
ANALOG INPUT 1.25V 22µF AIN+ AIN- LTC1416 VREF REFCOMP
LTC1450
AGND
1416
Figure Driving VREF with
Differential Inputs LTC1416 unique differential sample-and-hold circuit that allows rail-to-rail inputs. will always convert difference AIN+ AIN- independent common mode voltage. common mode rejection holds extremely high frequencies (see Figure 10a). only requirement that both inputs cannot exceed AVDD AVSS power supply voltages. Integral nonlinearity errors (INL) differential nonlinearity errors (DNL) independent common mode voltage, however, bipolar zero error (BZE) will vary. change typically less than 0.1% common mode voltage. Dynamic performance also affected common mode voltage. will degrade inputs approach either power supply rail, from 90dB with common mode 79dB with common mode 2.5V 2.5V. Differential inputs allow greater flexibility accepting different input ranges. Figure shows circuit that
100k INPUT FREQUENCY (Hz)
1416
Figure 10a. CMRR Input Frequency
±2.5V 22µF
ANALOG INPUT
AIN+ AIN- VREF LTC1416
REFCOMP AGND
1416 F10b
Figure 10b. Selectable ±2.5V Input Range
converts analog input signal with additional translation circuitry. Full-Scale Offset Adjustment Figure shows ideal input/output characteristics LTC1416. code transitions occur midway between successive integer values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, 1.5LSB, 0.5LSB). output two's complement binary with 1LSB FS)/16384 5V/16384 305.2µV. applications where absolute accuracy important, offset full-scale errors adjusted zero. Offset error must adjusted before full-scale error. Figure shows extra components required full-scale error adjustment. Zero offset achieved adjusting offset applied AIN- input. zero offset error, apply 152µV (i.e., 0.5LSB) AIN+ adjust offset AIN- input until output code flickers between 0000
LTC1416
APPLICATIONS INFORMATION
0000 0000 1111 1111 1111 full-scale adjustment, input voltage 2.499544V (FS/2 1.5LSB) applied adjusted until output code flickers between 0111 1111 1111 0111 1111 1111
011.111 011.110 OUTPUT CODE
000.001 000.000 111.111 111.110 100.001 100.000 1LSB) 1LSB
1416 F11a
INPUT VOLTAGE (AIN+ AIN-)
Figure 11a. LTC1416 Transfer Characteristics
ANALOG INPUT
AIN+ AIN- LTC1416 VREF REFCOMP AGND
1416 F11b
22µF
Figure 11b. Offset Full-Scale Adjust Circuit
Generating Supply There several advantages using supplies rather than single supply. larger signal magnitude possible which increases dynamic range improves signal-to-noise ratio. Operating supplies also offers increased headroom which eases requirements signal conditioning circuitry, avoids limitations rail-to-rail operation widens selection high performance operational amplifiers. Some
applications, however, have supply readily available most ADCs have inadequate PSRR sufficiently attenuate noise created switching charge pump supply. LTC1416's excellent PSRR makes possible achieve good performance, even bits, using switch based regulator supply. Figure shows circuit using LT1373 configured converter creating from supply. circuit shown Figure uses LT1054 regulated charge pump provide -5V. This circuit advantage reduced board space fewer passive components. (For further details refer Linear Technology Magazine, June 1997, Page 29.) BOARD LAYOUT BYPASSING Wire wrap boards recommended high resolution high speed converters. obtain best performance from LTC1416, printed circuit board with ground plane required. Layout printed circuit board should ensure that digital analog signal lines separated much possible. particular, care should taken digital track alongside analog signal track underneath ADC. analog input should screened AGND. analog ground plane separate from logic system ground should established under around (see Figure 13). (AGND), Pins (ADC's DGND) other analog grounds should connected this single analog ground point. REFCOMP bypass capacitor DVDD bypass capacitor should also connected this analog ground plane. other digital grounds should connected this analog ground plane. impedance analog digital power supply common returns essential noise operation foil width these tracks should wide possible. applications where data outputs control signals connected continuously active microprocessor bus, possible errors conversion results. These errors feedthrough from microprocessor successive approximation comparator. problem eliminated forcing microprocessor into Wait state during conversion using three-state buffers isolate data bus.
LTC1416
APPLICATIONS INFORMATION
ANALOG INPUT AIN+ AIN- VREF COMP AGND (MSB) DGND LTC1416 AVDD DVDD BUSY CONVST SHDN CERAMIC CERAMIC =OCTAPAC CTX-100-1 =1N5818 0.01µF MICROPROCESSOR/ MICROCONTROLLER INTERFACE 22µF TANT CUK* CONVERTER 100µF TANT 4.99k 4.99k 4.99k
1416 F12a
10µF
LT1373
Figure 12a. Using LT1373 Generate Supply
ANALOG INPUT AIN+ AIN- VREF COMP AGND (MSB) LTC1416 DGND AVDD DVDD BUSY CONVST SHDN CERAMIC CERAMIC 10µF TANT MICROPROCESSOR/ MICROCONTROLLER INTERFACE FB/SHDN CAP+ LT1054 VREF VOUT
100µF TANT
30.1k 120k
1416 F12b
0.002µF
Figure 12b. Using LT1054 Generate Supply
0.1µF
LTC1416
APPLICATIONS INFORMATION
AIN+ AIN- ANALOG INPUT CIRCUITRY REFCOMP 22µF AGND 10µF LTC1416 AVDD 10µF DVDD DGND DIGITAL SYSTEM
Figure Power Supply Grounding Practice.
traces connecting pins bypass capacitors must kept short should made wide possible. LTC1416 differential inputs minimize noise coupling. Common mode noise AIN+ AIN- leads will rejected input CMRR. AIN- input used ground sense AIN+ input; LTC1416 will hold convert difference voltage between AIN+ AIN- leads AIN+ (Pin AIN- (Pin should kept short possible. applications where this possible, AIN+ AIN- traces should side side equalize coupling. Supply Bypassing High quality, series resistance ceramic, bypass capacitors should used (10µF) REFCOMP (22µF) pins shown Typical Application first page this data sheet. Surface mount ceramic capacitors such Murata GRM235Y5V106Z016 provide excellent bypassing small board space. Alternatively tantalum capacitors parallel with 0.1µF ceramic capacitors used. Bypass capacitors must located close pins possible. traces connecting pins bypass capacitors must kept short should made wide possible. Example Layout Figures 14a, 14b, show schematic layout evaluation board. layout demonstrates proper decoupling capacitors ground plane with 2-layer printed circuit board.
1416
DIGITAL INTERFACE converter designed interface with microprocessors memory mapped device. control inputs common peripheral memory interfacing. separate CONVST used initiate conversion. Internal Clock converter internal clock that eliminates need synchronization between external clock signals found other ADCs. internal clock factory trimmed achieve typical conversion time 1.8µs, maximum conversion time over full operating temperature range 2.2µs. external adjustments required. guaranteed maximum acquisition time 400ns. addition, throughput time 2.5µs minimum sampling rate 400ksps guaranteed. Power Shutdown LTC1416 provides power shutdown modes-nap mode sleep mode save power during inactive periods. mode reduces power leaves only digital logic reference powered wake-up time from active 200ns. sleep mode reference shut down only small current 120µA remains. Wake-up time from sleep mode much slower since reference circuit must power settle 0.005% full 14-bit accuracy. Sleep mode wake-up time dependent value capacitor connected REFCOMP (Pin wake-up time 20ms with recommended 22µF capacitor.
VLOGIC D[00:13] 1.2k 1.2k 1.2k R10, 1.2k R11, 1.2k R12, 1.2k R13, 1.2k HC14 DATA READY 0.1µF VLOGIC HC14 15pF HC14
1416 F14a
-VIN VOUT 1.2k 1.2k 1.2k 1.2k 1.2k 1.2k 1.2k
LT1121-5
79L05
LTC1416
22µF
10µF
B[00:13] 74HC574 J6-13 J6-14 J6-11 J6-12 J6-9 J6-10 J6-7 J6-8 J6-5 J6-6 HC14 J6-3 J6-4 J6-1 J6-2 J6-15 J6-16 J6-17 J6-18 HC14 LTC1416 VREF DGND AGND DVDD AVDD SHDN CONVST BUSY REFCOMP 22µF VREF AIN- AIN+ VOUT 0.1µF
74HC574
LT1363 0.1µF
1000pF
APPLICATIONS INFORMATION
DGND DGND HEADER 18-PIN
HC14
HC14
VLOGIC
JP5C
JP5B
10µF 10µF
JP5A
SHDN
NOTES: UNLESS OTHERWISE SPECIFIED RESISTOR VALUES OHMS,
Figure 14a. Suggested Evaluation Circuit Schematic
AGND
DGND
-15V
+VIN
0.1µF 0.1µF
VOUT
TABGND
SS12
SS12
22µF
LTC1416
APPLICATIONS INFORMATION
Figure 14b. Suggested Evaluation Circuit Board- Component Side Silkscreen
Figure 14d. Suggested Evaluation Circuit Board- Solder Side Layout
Figure 14c. Suggested Evaluation Circuit Board- Component Side Layout
SHDN
1416 F15a
Figure 15a. SHDN Timing
SHDN CONVST
1416 F15b
Figure 15b. SHDN CONVST Wake-Up Timing
LTC1416
APPLICATIONS INFORMATION
Shutdown controlled (SHDN), shutdown when low. shutdown mode selected with (CS), selects nap. Timing Control Conversion start data read operations controlled three digital inputs: CONVST, logic applied CONVST will start conversion after been selected (i.e., low). Once initiated, cannot restarted until conversion complete. Converter status indicated BUSY output. BUSY during conversion. Figures through show several different modes operation. modes (Figures both tied low. falling edge CONVST starts conversion. data outputs always enabled data latched with BUSY rising edge. Mode shows operation with narrow logic CONVST pulse. Mode shows narrow logic high CONVST pulse. mode (Figure tied low. falling edge CONVST signal again starts conversion. Data outputs three-state until read with signal. Mode used operation with shared data bus. slow memory modes (Figures 21), tied CONVST tied together. starts conversion reads output with signal. Conversions started external sample clock). slow memory mode processor applies logic CONVST), starting conversion. BUSY goes low, forcing processor into Wait state. previous conversion result appears data outputs. When conversion complete, conversion results appear data outputs; BUSY goes high releasing processor, processor takes CONVST) back high reads conversion data. mode, processor takes CONVST) low, starting conversion reading previous conversion result. After conversion complete, processor read result initiate another conversion.
(SAMPLE CONVST BUSY DATA DATA DB13 DATA DB13 DATA DB13
1416
Figure Mode CONVST Starts Conversion. Data Outputs Always Enabled
(CONVST
CONVST
1416
Figure CONVST Setup Timing
CONV
LTC1416
APPLICATIONS INFORMATION
CONVST BUSY DATA DATA DB13 DATA DB13 DATA DB13
1416
tCONV
Figure Mode CONVST Starts Conversion. Data Outputs Always Enabled
(CONVST
(SAMPLE tCONV
CONVST BUSY DATA DATA DB13
1416
Figure Mode CONVST Starts Conversion. Data Read
(SAMPLE CONVST BUSY DATA
CONV
DATA DB13
Figure Slow Memory Mode Timing
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
DATA DB13 DATA DB13 DATA DB13
1416
LTC1416
APPLICATIONS INFORMATION
(SAMPLE CONVST BUSY DATA DATA DB13 DATA DB13
1416
CONV
PACKAGE DESCRIPTIO
Dimensions inches (millimeters) unless otherwise noted. Package 28-Lead Plastic SSOP (0.209)
(LTC 05-08-1640)
0.397 0.407* (10.07 10.33)
0.205 0.212** (5.20 5.38)
0.301 0.311 (7.65 7.90) 0.002 0.008 (0.05 0.21)
0.005 0.009 (0.13 0.22)
0.022 0.037 (0.55 0.95)
0.0256 (0.65)
*DIMENSIONS INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE **DIMENSIONS INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE
0.010 0.015 (0.25 0.38)
RELATED PARTS
PART NUMBER LTC1278/LTC1279 LTC1400 LTC1409 LTC1410 LTC1412 LTC1415 LTC1418 LTC1419 LTC1604 LTC1605 DESCRIPTION Single Supply, 12-Bit, 500ksps/600ksps ADCs High Speed Serial 12-Bit Power, 12-Bit, 800ksps Sampling 12-Bit, 1.25Msps Sampling with Shutdown 12-Bit, 3Msps Sampling Single 12-Bit, 1.25Msps 14-Bit, 200ksps Sampling 14-Bit, 800ksps Sampling with Shutdown 16-Bit, 333ksps Sampling Single 16-Bit, 100ksps COMMENTS Power, Supply 400ksps, Complete with VREF, CLK, Sample-and-Hold SO-8 Best Dynamic Performance, fSAMPLE 800ksps, 80mW Dissipation Best Dynamic Performance, 84dB SINAD 71dB Nyquist Best Dynamic Performance, SINAD 72dB Nyquist Single Supply, 55mW Dissipation 16mW Dissipation, Serial Parallel Outputs 81.5dB SINAD, 150mW from Supplies ±2.5V Input, SINAD 90dB, 100dB Power, ±10V Inputs
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417
(408)432-1900 FAX: (408) 434-0507 www.linear-tech.com
Figure Mode Timing
0.068 0.078 (1.73 1.99)
SSOP 0694
1416f LT/TP 0598 PRINTED
LINEAR TECHNOLOGY CORPORATION 1997
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