DESCRIPTIO Sample Rate: 2.2Msps Outstanding Spectral Purity: 80dB

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DESCRIPTIO Sample Rate: 2.2Msps Outstanding Spectral Purity: 80dB

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LTC1414 14-Bit, 2.2Msps, Sampling Converter
DESCRIPTIO
Sample Rate: 2.2Msps Outstanding Spectral Purity: 80dB S/(N 95dB SFDR 100kHz 78dB S/(N 84dB SFDR Nyquist Ultralow Distortion with Single-Ended Differential Inputs ±2.5V Bipolar Input Range Eliminates Level Shifting Rail-to-Rail Requirements Easy Hookup External Internal Reference Pipeline Delay Power Dissipation: 175mW Supplies 28-Pin Narrow SSOP Package
®1414 14-bit, 2.2Msps, sampling converter which draws only 175mW from supplies. This high performance includes high dynamic range sample-and-hold, precision reference requires external components. LTC1414's high performance sample-and-hold full-scale input range ±2.5V. Outstanding performance includes 80dB S/(N 95dB SFDR with 100kHz input. performance remains high Nyquist input frequency 1.1MHz with 78dB S/(N 84dB SFDR. unique differential input sample-and-hold acquire single-ended differential input signals 40MHz bandwidth. 70dB common mode rejection eliminate ground loops common mode noise measuring signal differentially from source microprocessor compatible, 14-bit parallel output port. There pipline delay conversion results.
registered trademarks Linear Technology Corporation.
APPLICATIO
Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems
TYPICAL APPLICATIO
10µF AVDD LTC1414 DVDD
OPTIONAL LOGIC SUPPLY
Effective Bits Signal-to-Noise Distortion Input Frequency
S/(N (dB)
OVDD
4.0625V COMP 10µF VREF 10µF BUFFER
14-BIT
OUTPUT BUFFERS
EFFECTIVE BITS
(MSB)
(LSB)
2.5V REFERENCE AGND
TIMING LOGIC DGND OGND
BUSY CONVST
fSAMPLE 2.2MHz 100k INPUT FREQUENCY (Hz)
1414 TA02
1414 TA01
LTC1414
ABSOLUTE MAXIMUM RATINGS
AVDD OVDD DVDD (Notes
PACKAGE/ORDER INFORMATION
VIEW AIN+ AIN- VREF REFCOMP AGND (MSB) AVDD AGND BUSY CONVST DGND DVDD OVDD
Supply Voltage (VDD) Negative Supply Voltage (VSS) Total Supply Voltage (VDD VSS) Analog Input Voltage (Note (VSS 0.3V) (VDD 0.3V) Digital Input Voltage (Note .(VSS 0.3V) Digital Output Voltage (VSS 0.3V) (VDD 0.3V) Power Dissipation. 500mW Operating Temperature Range 70°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
ORDER PART NUMBER LTC1414CGN
OGND
PACKAGE 28-LEAD PLASTIC SSOP
TJMAX 110°C, 110°C/
Consult factory Industrial, Military grade parts.
VERTER CHARACTERISTICS
PARAMETER Resolution Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note (Note CONDITIONS
With internal reference (Notes
LTC1414 ±0.75 ±0.75
±2.0 1.75
UNITS Bits ppm/°C ppm/°C
Internal Reference External Reference 2.5V Internal Reference External Reference 2.5V
ALOG
SYMBOL PARAMETER tACQ tjitter CMRR Analog Input Range
(Note
CONDITIONS 4.75V 5.25V, 5.25V 4.75V Between Conversions Between Conversions During Conversions
±2.5
UNITS
Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio
psRMS
2.5V (AIN- AIN+) 2.5V
LTC1414
ACCURACY
SYMBOL PARAMETER S/(N Signal-to-Noise Plus Distortion Ratio SFDR Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth
REFERE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance COMP Output Voltage CONDITIONS IOUT IOUT 4.75V 5.25V 5.25V 4.75V
IOUT 0.1mA
DIGITAL PUTS OUTPUTS
SYMBOL PARAMETER ISOURCE ISINK High Level Input Voltage Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Level Output Voltage Output Source Current Output Sink Current
POWER REQUIRE
SYMBOL PARAMETER Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation
(Note
CONDITIONS 100kHz Input Signal 1.1MHz Input Signal 100kHz Input Signal, First Harmonics 1.1MHz Input Signal, First Harmonics 100kHz Input Signal, First Harmonics 1.1MHz Input Signal, First Harmonics fIN1 29.37kHz, fIN2 32.446kHz S/(N 74dB UNITS
(Note
2.480 2.500 0.01 0.01 4.06 2.520 UNITS ppm/°C LSB/ LSB/
IOUT
(Note
CONDITIONS 5.25V 4.75V 4.75V, 10µA 4.75V, 200µA 4.75V, 160µA 4.75V, 1.6mA VOUT VOUT
UNITS
4.74
0.05 0.10
(Note
CONDITIONS (Note (Note High High
4.75 4.75
5.25 5.25
UNITS
LTC1414
CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ tTHROUGHPUT PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Throughput Time (Acquisition Conversion) CONVST BUSY Delay Data Ready Before BUSY Delay Between Conversions CONVST Time CONVST High Time Aperture Delay Sample-and-Hold (Note (Note (Note
denotes specifications which apply over full operating temperature range; other limits typicals 25°C. Note Absolute Maximum Ratings those values beyond which life device impaired. Note voltage values with respect ground with DGND AGND wired together (unless otherwise noted). Note When these voltages taken below above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA below above without latchup. Note When these voltages taken below VSS, they will clamped internal diodes. This product handle input currents greater than 100mA below without latchup. These pins clamped VDD. Note fSAMPLE 2.2MHz unless otherwise specified.
TYPICAL PERFOR CHARACTERISTICS
Signal-to-Noise Ratio Input Frequency
S/(N (dB)
S/(N Input Frequency
EFFECTIVE BITS fSAMPLE 2.2MHz 100k INPUT FREQUENCY (Hz)
1414 TA02
SIGNAL-TO-NOISE RATIO (dB)
100k INPUT FREQUENCY (Hz)
1414
DISTORTION (dB)
(Note
CONDITIONS
UNITS
25pF
Note Linearity, offset full-scale specifications apply singleended AIN+ input with AIN- grounded. Note Integral nonlinearity defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Note Bipolar offset offset voltage measured from 0.5LSB when output code flickers between 0000 0000 0000 1111 1111 1111 Note Recommended operating conditions. Note falling CONVST edge starts conversion. CONVST returns high critical point during conversion create small errors. best results ensure that CONVST returns high either within 225ns after start conversion after BUSY rises.
Distortion Input Frequency
-100 100k INPUT FREQUENCY (Hz)
1414
LTC1414 TYPICAL PERFOR CHARACTERISTICS
Spurious-Free Dynamic Range Input Frequency
SPURIOUS-FREE DYNAMIC RANGE (dB)
(LSBs)
AMPLITUDE (dB)
-100
100k INPUT FREQUENCY (Hz)
Integral Nonlinearity Output Code
(LSBs)
AMPLITUDE POWER SUPPLY FEEDTHROUGH (dB)
COMMON MODE REJECTION (dB)
-1.0
-2.0 4096 8192 12288 OUTPUT CODE 16384
1414
FUNCTIONS
(Pin Positive Analog Input. ±2.5V input range when AIN- grounded. ±2.5V differential AIN- driven differentially with AIN+. AIN- (Pin Negative Analog Input. grounded driven differentially with AIN+. VREF (Pin 2.5V Reference Output. REFCOMP (Pin 4.06V Reference Bypass Pin. Bypass AGND with 10µF ceramic 10µF tantalum parallel with 0.1µF ceramic. AGND (Pin Analog Ground. (Pins 13): Data Outputs. OGND (Pin 14): Digital Ground Output Drivers. AGND (Pins 20): Data Outputs. OVDD (Pin 21): Positive Supply Output Drivers. when driving logic. logic, supply logic being driven. DVDD (Pin 22): Positive Supply. DGND (Pin 23): Digital Ground. AGND. CONVST (Pin 24): Conversion Start Signal. This active signal starts conversion falling edge.
Intermodulation Distortion Plot
-1.0
Differential Nonlinearity Output Code
fSAMPLE 2.2MHz fIN1 80.566kHz fIN2 97.753kHz
-100 -120
1414
-2.0
FREQUENCY (kHz)
1000
1414 F05a
4096
8192 12288 OUTPUT CODE
16384
1414
Power Supply Feedthrough Ripple Frequency
Input Common Mode Rejection Input Frequency
100k INPUT FREQUENCY (Hz)
LTC1414
(VRIPPLE 0.02V) (VRIPPLE 0.2V) OGND (VRIPPLE 0.5V) OVDD (VRIPPLE 0.5V)
-100 -120 RIPPLE FREQUENCY (Hz)
1414
LTC1414
FUNCTIONS
BUSY (Pin 25): BUSY Output Shows Converter Status. when conversion progress. (Pin 26): Negative Supply. Bypass AGND with 10µF ceramic 10µF tantalum parallel with 0.1µF ceramic. AGND (Pin 27): Analog Ground. AVDD (Pin 28): Positive Supply. Bypass AGND with 10µF ceramic 10µF tantalum parallel with 0.1µF ceramic.
FUNCTIONAL BLOCK DIAGRA
AIN+
AIN- VREF 2.5V ZEROING SWITCHES
REFCOMP (4.06V) AGND DGND INTERNAL CLOCK SUCCESSIVE APPROXIMATION REGISTER
DIAGRA
tCONV CONVST BUSY DATA DATA DB13 DATA DB13 DATA DB13
CSAMPLE
CSAMPLE
AVDD DVDD
14-BIT CAPACITIVE COMP
OVDD OUTPUT LATCHES OGND CONTROL LOGIC
1414
CONVST
BUSY
1414
LTC1414
APPLICATIONS INFORMATION
CONVERSION DETAILS LTC1414 uses successive approximation algorithm internal sample-and-hold circuit convert analog signal 14-bit parallel output. complete with precision reference internal clock. device easy interface with microprocessors DSPs. (Please refer Digital Interface section data format.) Conversion start controlled CONVST input. start conversion successive approximation register (SAR) reset. Once conversion cycle begun cannot restarted. During conversion, internal differential 14-bit capacitive output sequenced from most significant (MSB) least significant (LSB). Referring Figure AIN+ AIN- inputs connected sample-and-hold capacitors (CSAMPLE) during acquire phase, comparator offset nulled zeroing switches. this acquire phase, minimum delay 70ns will provide enough time sample-and-hold capacitors acquire analog signal. During convert phase comparator zeroing switches open, putting comparator into compare mode. input switches connect CSAMPLE capacitors ground, transferring differential analog input charge onto summing junction. This input charge successively compared with binary-weighted charges supplied differential capacitive DAC. decisions made high speed comparator. conversion, differential output balances AIN+ AIN- input charges. contents 14-bit data word) which represents difference AIN+ AIN- loaded into 14-bit output latches. DYNAMIC PERFORMANCE LTC1414 excellent high speed sampling capability. (Fast Four Transform) test techniques used test ADC's frequency response, distortion noise rated throughput. applying distortion sine wave analyzing digital output using algorithm, ADC's spectral content examined frequencies outside fundamental. Figure shows typical LTC1414 plot.
AIN+ SAMPLE CSAMPLE+ HOLD SAMPLE CSAMPLE- HOLD CDAC+ ZEROING SWITCHES HOLD HOLD
AMPLITUDE (dB)
AIN-
VDAC+ CDAC- COMP
VDAC- OUTPUT LATCH
1414
Figure Simplified Block Diagram
Signal-to-Noise Ratio signal-to-(noise distortion) ratio [S/(N ratio between amplitude fundamental input frequency amplitude other frequency components output. output band limited frequencies from above below half sampling frequency. Figure shows typical spectral content with 2.2MHz sampling rate 100kHz input. dynamic performance excellent input frequencies beyond Nyquist limit 1.1MHz. (See Figure
-100 -120 FREQUENCY (kHz) 1000
1414 F02a
SINAD 80dB SFDR 96dB fSAMPLE 2.2MHz 97.753kHz
Figure LTC1414 Nonaveraged, 2048 Point FFT, Input Frequency 100kHz
LTC1414
APPLICATIONS INFORMATION
SINAD 78dB SFDR 84dB fSAMPLE 2.2MHz 997.949kHz
AMPLITUDE (dB)
-100 -120
EFFECTIVE BITS
FREQUENCY (kHz)
1000
1414 F02b
Figure LTC1414 2048 Point FFT, Input Frequency 1MHz
Effective Number Bits
DISTORTION (dB)
effective number bits (ENOBs) measurement resolution directly related S/(N equation: ENOBS [S/(N 1.76]/6.02 where S/(N expressed maximum sampling rate 2.2MHz LTC1414 maintains near ideal ENOBs Nyquist input frequency 1.1MHz. Refer Figure Total Harmonic Distortion Total harmonic distortion (THD) ratio harmonics input signal fundamental itself. out-of-band harmonics alias into frequency band between half sampling frequency. expressed
where amplitude fundamental frequency through amplitudes second through harmonics. input frequency shown Figure LTC1414 good distortion performance Nyquist frequency beyond.
fSAMPLE 2.2MHz 100k INPUT FREQUENCY (Hz)
S/(N (dB)
1414 TA02
Figure Effective Bits Signal/(Noise Distortion) Input Frequency
-100 100k INPUT FREQUENCY (Hz)
1414
Figure Distortion Input Frequency
Intermodulation Distortion input signal consists more than spectral component, transfer function nonlinearity produce intermodulation distortion (IMD) addition THD. change sinusoidal input caused presence another sinusoidal input different frequency. pure sine waves frequencies applied input, nonlinearities transfer function create distortion products difference frequencies nfb, where etc. example, order terms include fb). input sine waves equal magnitude, value order products expressed following formula:
LTC1414
APPLICATIONS INFORMATION
amplitude 20log amplitude
AMPLITUDE (dB)
fSAMPLE 2.2MHz fIN1 80.566kHz fIN2 97.753kHz
-100 -120 FREQUENCY (kHz) 1000
1414 F05a
Figure Intermodulation Distortion Plot with Inputs 80kHz 97kHz
AMPLITUDE (dB)
fSAMPLE 2.2MHz fIN1 970.019kHz fIN2 1.492MHz
-100 -120 FREQUENCY (kHz) 1000
1414 F05b
ACQUISITION TIME (µs)
Figure Intermodulation Distortion Plot with Input Signals 1MHz 1.5MHz
Peak Harmonic Spurious Noise peak harmonic spurious noise largest spectral component excluding input signal This value expressed relative value fullscale input signal. Full-Power Full-Linear Bandwidth full-power bandwidth that input frequency which amplitude reconstructed fundamental reduced full-scale input signal.
full-linear bandwidth input frequency which S/(N dropped 74dB effective bits). LTC1414 been designed optimize input bandwidth, allowing undersample input signals with frequencies above converter's Nyquist frequency. noise floor stays very high frequencies; S/(N becomes dominated distortion frequencies beyond Nyquist. Driving Analog Input differential analog inputs LTC1414 easy drive. inputs driven differentially singleended input (i.e., AIN- input grounded). AIN- inputs sampled same instant. unwanted signal that common mode both inputs will reduced common mode rejection sampleand-hold circuit. inputs draw only small current spike while charging sample-and-hold capacitors conversion. During conversion, analog inputs draw only small leakage current. source impedance driving circuit then LTC1414 inputs driven directly. source impedance increases will acquisition time (see Figure minimum acquisition time, with high source impedance, buffer amplifier should used. only requirement that amplifier driving analog input(s) must settle after small current spike before next conversion starts (settling time must 70ns full throughput rate).
0.01 SOURCE RESISTANCE 100k
1414
Figure Acquisition Time Source Resistance
LTC1414
APPLICATIONS INFORMATION
Choosing Input Amplifier Choosing input amplifier easy requirements taken into consideration. First, limit magnitude voltage spike seen amplifier from charging sampling capacitor, choose amplifier that output impedance (<100) closed-loop bandwidth frequency. example, amplifier used gain unity-gain bandwidth 50MHz, then output impedance 50MHz must less than 100. second requirement that closed-loop bandwidth must greater than 40MHz ensure adequate smallsignal settling full throughput rate. slower amps used, more settling time provided increasing time between conversions. best choice drive LTC1414 will depend application. Generally applications fall into categories: applications where dynamic specifications most critical time domain applications where accuracy settling time most critical. following list summary amps that suitable driving LTC1414. More detailed information available Linear Technology Databooks LinearViewCD-ROM. LT®1223: 100MHz Video Current Feedback Amplifier. supply current. ±15V supplies. noise. Good applications. LT1227: 140MHz Video Current Feedback Amplifier. 10mA supply current. ±15V supplies. noise. Best applications. LT1229/LT1230: Dual Quad 100MHz Current Feedback Amplifiers. ±15V supplies. noise. Good specifications, supply current each amplifier. LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA supply current. Good specs. ±15V supplies. 70ns settling 0.5LSB. LT1363: 70MHz, 1000V/µs Amps. 6.3mA supply current. Good specifications. 60ns settling 0.5LSB. LT1364/LT1365: Dual Quad 70MHz, 1000V/µs Amps. 6.3mA supply current amplifier. 60ns settling 0.5LSB.
LinearView trademark Linear Technology Corporation.
Coupled Inputs applications where only component analog input important, desirable couple input. This easily accomplished biasing LTC1414 analog input with resistor ground using coupling capacitor input. Figure shows simple coupled input circuit LTC1414 using only additional components. 10µF ceramic capacitor 1000 resistor ground. form highpass filter with lower frequency 1/2(C1)R1 15.9Hz.
10µF ANALOG INPUT 10µF AGND
LTC1414
AIN+ LTC1414 VREF REFCOMP
Figure Coupled Input
Differential Drive some applications drive circuitry differential. differential drive applied directly LTC1414 without special translation circuitry. Differential drive advantageous high frequencies (>1MHz) since provides improved SFDR. Transformers used provide coupling, input scaling single ended differential conversion shown Figure resistor across secondary will determine input impedance primary. input impedance primary will related secondary load resistor equation RS/n2 example, Minicircuits T4-6T transformer used, turns ratio then equal center secondary will common mode voltage should grounded optimal performance.
LTC1414
APPLICATIONS INFORMATION
ANALOG INPUT 10µF AGND
LTC1414
500pF
AIN+ LTC1414 VREF
REFCOMP
Figure Transformer Coupled Input Required, this Circuit Provides Simple Solution
Input Filtering noise distortion input amplifier other circuitry must considered since they will LTC1414 noise distortion. small-signal bandwidth sample-and-hold circuit 40MHz. noise distortion products that present analog inputs will summed over this entire bandwidth. Noisy input circuitry should filtered prior analog inputs minimize noise. simple 1-pole filter sufficient many applications. example, Figure shows 500pF capacitor from AIN+ ground source resistor limit input bandwidth 3.2MHz. 500pF capacitor also acts charge reservoir input sample-and-hold isolates input from sampling glitch-sensitive circuitry. High quality capacitors resistors should used since poor quality components distortion. silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors also generate distortion from self heating from damage that occur during soldering. Metal film surface mount resistors much less susceptible both problems.
INPUT 500pF 10µF AGND
LTC1414
AIN+ LTC1414 VREF
REFCOMP
Figure Filter Reduces ADC's 40MHz Bandwidth 3.2MHz Filters Wideband Noise Which Present Input Signal
Input Range ±2.5V input range LTC1414 optimized noise distortion. Most amps also perform best over this same range, allowing direct coupling analog inputs eliminating need special translation circuitry. Some applications require other input ranges. LTC1414 differential inputs reference circuitry accommodate other input ranges often with little additional circuitry. following sections describe reference input circuitry they affect input range. Internal Reference LTC1414 on-chip, temperature compensated, curvature corrected, bandgap reference that factory trimmed 2.500V. connected internally reference amplifier available VREF (Pin Figure resistor series with output that easily overdriven external reference other circuitry. reference amplifier multiplies voltage VREF 1.625 create required internal reference voltage. This provides buffering between VREF high speed capacitive DAC. reference amplifier compensation pin, REFCOMP (Pin must bypassed with capacitor ground. reference amplifier stable with capacitors greater. best noise performance, 10µF ceramic 10µF tantalum parallel with 0.1µF ceramic recommended.
VREF
2.500V
BANDGAP REFERENCE
4.0625V REFCOMP REFERENCE
10µF
AGND
LTC1414
1414
Figure LTC1414 Reference Circuit
LTC1414
APPLICATIONS INFORMATION
COMMON MODE REJECTION (dB)
VREF driven with other means shown Figure This useful applications where peak input signal amplitude vary. input span then adjusted match peak input signal, maximizing signal-to-noise ratio. filtering internal LTC1414 reference amplifier will limit bandwidth settling time this circuit. settling time should allowed after reference adjustment.
ANALOG INPUT DIFFERENTIAL AIN+ AIN- LTC1414 LTC1450 VREF
10µF
REFCOMP
AGND
1414
Figure Driving VREF with
Differential Inputs LTC1414 unique differential sample-and-hold circuit that allows rail-to-rail inputs. will always convert difference AIN+ (AIN-) independent common mode voltage. common mode rejection holds extremely high frequencies, Figure only requirement that neither input exceed AVDD AVSS power supply voltages. Integral nonlinearity errors (INL) differential nonlinearity errors (DNL) independent common mode voltage, however, bipolar zero error (BZE) will vary. change typically less than 0.1% common mode voltage. Dynamic performance also affected common mode voltage. will degrade inputs approach either power supply rail, from -84dB with common mode -75dB with common mode 2.5V -2.5V. Full-Scale Offset Adjustment Figure shows ideal input/output characteristics LTC1414. code transitions occur midway between successive integer values (i.e., 0.5LSB, 1.5LSB, 2.5LSB,.FS 2.5LSB, 1.5LSB).
OUTPUT CODE
100k INPUT FREQUENCY (Hz)
LTC1414
Figure CMRR Input Frequency
output two's complement binary with 1LSB FS)/16384 5V/16384 305.2µV. applications where absolute accuracy important, offset full-scale errors adjusted zero. Offset error must adjusted before full-scale error. Figure shows extra components required full-scale error adjustment. Zero offset achieved adjusting offset applied AIN- input. zero offset error apply 152µV (i.e., 0.5LSB) AIN+ adjust offset AIN- input until output code flickers between 0000 0000 0000 1111 1111 1111 full-scale adjustment, input voltage 2.499544V 1.5LSBs) applied AIN+ adjusted until output code flickers between 0111 1111 1111 0111 1111 1111
011.111 011.110 011.101 000.000 111.111
100.010 100.001 100.000 -(FS 1LSB) INPUT RANGE
LTC1414
1LSB
Figure LTC1414 Transfer Characteristics
LTC1414
APPLICATIONS INFORMATION
ANALOG INPUT 10µF AGND
LTC1414
AIN+ LTC1414
VREF
REFCOMP
Figure Offset Full-Scale Adjust Circuit
Board Layout Bypassing obtain best performance from LTC1414, printed circuit board with ground plane required. Layout printed circuit board should ensure that digital analog signal lines separated much possible. particular, care should taken digital line alongside analog signal line underneath ADC. analog input should screened AGND. High quality tantalum ceramic bypass capacitors should used VDD, VREF pins. Bypass capacitors must located close pins possible. traces connecting pins bypass capacitors must kept short should made wide possible.
AIN+ AIN- REFCOMP 10µF AGND
ANALOG INPUT CIRCUITRY
Figure Power Supply Grounding Practice
LTC1414 differential inputs minimize noise coupling. Common mode noise AIN+ AIN- inputs will reflected input CMRR. AIN- input used ground sense AIN+ input; LTC1414 will hold convert difference voltage between AIN+ AIN-. leads AIN+ (Pin AIN- (Pin should kept short possible. applications where this possible, AIN+ AIN- traces should side side equalize coupling. single point analog ground separate from logic system ground should established with analog ground plane AGND (Pin close possible (see Figure ADC's DGND (Pin other analog grounds should connected this single analog ground point. other digital grounds should connected this analog ground point. impedance analog digital power supply common returns essential noise operation these traces should wide possible. Excessive capacitive loading ADC's data output lines generate large transient currents supplies which affect conversion results. these cases, digital buffers recommended isolate from excessive loading. EXAMPLE LAYOUT Figures 16a, 16b, show schematic layout evaluation board. layout demonstrates proper decoupling capacitors ground plane with layer printed circuit board.
LTC1414 10µF AVDD 10µF DVDD OVDD DGND OGND
DIGITAL SYSTEM
ANALOG GROUND PLANE
1414
LTC1414
APPLICATIONS INFORMATION
AGND DGND
SS12
DGND 470pF 0.1µF VOUT LT1363 SO-8 LT1363 DIP-8 (OPTIONAL)
0.1µF
VREF
4.7µF
DGND
VLOGIC
DATA READY NOTES: UNLESS OTHERWISE SPECIFIED RESISTOR VALUES OHMS, 1/10W, CAPACITOR VALUES 25V, 50V,
Figure 16a. Evaluation Circuit Schematic
22µF SS12
0.125W
VLOGIC
22µF
10µF
0.1µF
0.1µF
0.1µF
74HC574 B[00:13] D[00:13]
LTC1414CGN AIN+ (MSB)D13 AIN- VREF REFCOMP BUSY CONVST DGND OVDD OVDD AVDD AGND AGND OGND
74HC574 DGND U7F, HC14 15pF U7E, HC14 J6-13 J6-14 J6-11 J6-12 J6-9 J6-10 J6-7 J6-8 J6-5 J6-6 J6-3 J6-4 J6-1 J6-2 J6-15 J6-16 J6-17 J6-18 DGND DGND
U7G, HC14
U7D, HC14
1414 F16a
HEADER 18-PIN
LTC1414
APPLICATIONS INFORMATION
Figure 16b. Evaluation Circuit Board Component Side Silkscreen
LTC1414
APPLICATIONS INFORMATION
Figure 16c. Evaluation Circuit Board Component Side Layout
LTC1414
APPLICATIONS INFORMATION
Figure 16d. Evaluation Circuit Board Solder Side Layout
LTC1414
APPLICATIONS INFORMATION
Digital Interface converter just control input CONVST. Data output 14-bit parallel bus. additional output BUSY indicates converter status. DIGITAL OUTPUTS parallel digital outputs LTC1414 designed interface CMOS logic. output data two's complement coded. output drivers have separate power (OVDD) ground (OGND). This allows relatively noisy output ground output supply bypass ground separated from other grounds. Additionally, OVDD driven supply logic that being driven. example, OVDD supply while LTC1414 DVDD AVDD pins allowing logic driven directly. Care should taken load digital outputs with excessive capacitance. Large capacitive loads result large charging currents which cause conversion errors. recommended that capacitive loading kept under 20pF. possible keep capacitance low, buffer latch used isolate LTC1414 from capacitive load. Timing Control conversion start controlled CONVST input. falling edge CONVST will start conversion. Once initiated, cannot restarted until conversion complete. Converter status indicated BUSY output. BUSY during conversion.
tCONV CONVST BUSY DATA DATA DB13 DATA DB13 DATA DB13
output data updated conversion BUSY rises. Output data updated coincident with rising edge BUSY. Data will valid, latched, 20ns after rising edge BUSY. Valid data also latched with falling edge BUSY with rising edge CONVST. latter cases data latched will previous conversion. CONVST Drive Considerations Timing jitter CONVST signal adversely affect noise performance LTC1414 when input signal contains high slew rate components. falling edge CONVST determines sampling instant. uncertainty this sampling instant will translate voltage noise when fast changing input signal being sampled. full amplitude sinusoidal input, relationship between timing jitter (tjitter) SNRj SNRj 20log(1/2 tjitter) where SNRj signal-to-jitter noise ratio. internal circuitry LTC1414 been optimized ultralow jitter (typically RMS). external clock drive circuitry equally important must also have jitter achieve noise. Internal Clock internal clock factory trimmed achieve typical conversion time 330ns maximum conversion time over full operating temperature range 400ns. external adjustments required. guaranteed maximum acquisition time 100ns. addition, throughput time (acquisition conversion) 454ns minimum sampling rate 2.2Msps guaranteed.
1414
Figure Timing Diagram
LTC1414
PACKAGE DESCRIPTION
0.015 0.004 (0.38 0.10) 0.0075 0.0098 (0.191 0.249) 0.016 0.050 (0.406 1.270) DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE DIMENSION DOES INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
Dimensions inches (millimeters) unless otherwise noted.
Package 28-Lead Plastic SSOP Narrow (0.150)
(LTC 05-08-1641)
0.386 0.393* (9.804 9.982) 1615
0.033 (0.838)
0.229 0.244 (5.817 6.198)
0.150 0.157** (3.810 3.988)
0.053 0.069 (1.351 1.748)
0.004 0.009 (0.102 0.249)
0.008 0.012 (0.203 0.305)
0.025 (0.635)
GN28 (SSOP) 0398
LTC1414
TYPICAL APPLICATIO
DIFFERENTIAL ANALOG INPUT -2.5V 2.5V
VREF 2.5V 10µF
RELATED PARTS
PART NUMBER LTC1412 LTC1415 LTC1416 LTC1417 LTC1418 LTC1419 LTC1604 LT1460 DESCRIPTION Power, 12-Bit ,3Msps, Single 12-Bit, 1.25Msps, Power, 14-Bit, 400ksps, Very Power, 14-Bit, 400ksps, Very Power, 14-Bit, 200ksps, Power, 14-Bit, 800ksps, High Speed, 16-Bit, 333ksps, Micropower Precision Series Reference COMMENTS Nyquist Sampling, 150mW, 72dB SINAD Single Supply, 55mW Dissipation Supplies, 75mW Dissipation 20mW, Supply, Serial 16-Pin SSOP 15mW, Supply, Serial Parallel True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation 90dB SINAD, -100dB THD, 220mW Dissipation 0.075% Accuracy, 10ppm/°C Drift
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417
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2.2MHz, 14-Bit Sampling
AIN+ AIN- VREF REFCOMP AGND AVDD AGND LTC1414 BUSY CONVST DGND (MSB) 14-BIT PARALLEL OGND DVDD OVDD 0.1µF 10µF 10µF
1414 TA03
1414f LT/TP 0399 PRINTED
LINEAR TECHNOLOGY CORPORATION 1998

DESCRIPTIO Sample Rate: 2.2Msps Outstanding Spectral Purity: 80dB

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